JP2014013520A - Signal transmission circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmission circuit for reducing the roundness of a signal waveform by reducing the reflection of a memory chip output waveform close to a memory controller without deteriorating amplitude, and for increasing a timing margin by quickening the rise/fall time of a signal.SOLUTION: In a signal transmission circuit in which one end of a transmission line is connected to a memory controller, and a plurality of memory chips are connected via a bus to the transmission line, the second characteristic impedance of the transmission line for connecting a first memory chip connected to the closest position to the memory controller and a second memory chip connected to the closest position next to the first memory chip is set to be higher than the first characteristic impedance of the transmission line for connecting the memory controller to the first memory chip.

Description

  The present invention relates to a signal transmission circuit having a bus connection configuration.

  In recent years, memory interfaces have been increasing in signal transmission speed and voltage. For example, in DDR SDRAM (Double-Data-Rate Synchronous Random Access Memory), which is established by JEDEC (Semiconductor Technology Association), the maximum signal transmission speed is 1066 Mbps in the previous generation DDR2 The current mainstream DDR3 is 2133 Mbps, and the next generation standard DDR4 is planned to be 3200 Mbps. Regarding the operating voltage, DDR3 is 1.8V, DDR3 is 1.5V, the low voltage version DDR3 is 1.35V, and DDR4 is 1.2V.

  In order to realize such high signal transmission speed and low voltage, the rising speed and falling speed of the signal waveform are accelerated, and the influence on the signal quality degradation due to reflection due to impedance mismatch is further increased. ing. Therefore, it is particularly important to design a transmission system with impedance matching in order to ensure signal quality.

  As a conventional technique for impedance matching, for example, a technique described in Japanese Patent Laid-Open No. 2003-133945 (Patent Document 1) is known.

  In the impedance matching method described in Japanese Patent Laid-Open No. 2003-133945 (Patent Document 1), an apparent printed circuit board viewed from a branch point is provided by providing a series resistor at a location where the wiring branches and impedance decreases. The impedance is matched.

JP 2003-133945 A

  In Japanese Patent Laid-Open No. 2003-133945, series resistance is provided on a transmission line, so that impedance is matched, and at the same time, signal amplitude decreases in proportion to the resistance value. For this reason, since the output voltage of the DDR3 memory interface has been lowered, the resistance value cannot be increased. In the DDR3 example, a technique using a series resistance of about 15Ω is common.

  The decrease in the resistance value of the series resistor increases the impedance mismatch when data is transferred from the memory chip to the memory controller, and the influence is increased particularly in the memory chip close to the memory controller.

  As an example, FIG. 2 shows a perspective view of a bus connection configuration in which two memory chips are mounted per same bus. In FIG. 2, the memory controller 2 mounted on the printed circuit board 100 is connected to two memory chips per bus, and is assumed to be 3d and 3e from the memory chip in front of the memory controller 2. The connection point L from the memory controller 2 to the near-end memory chip 3d is connected by the wiring 20, and the connection point M from the point L to the connection point M of the far-end memory chip 3e is connected by the wiring 21.

  An equivalent circuit in the connection configuration of FIG. 2 is shown in FIG. In FIG. 3, the wirings 4d and 4e in the memory chips 3d and 3e and the wirings 20 and 21 in the printed circuit board 100 are connected via the series resistors 5d and 5e, so that the memory chips 3d and 3e and the memory controller 2 are printed. A bus connection is made via the substrate 100.

  In this configuration, the reflection coefficient of the characteristic impedance from the memory chip side is obtained. As an example, when the characteristic impedance of the wirings 4d and 4e on the memory chips 3d and 3e is 50Ω, and the characteristic impedance of the wirings 20 and 21 is 35Ω, the change in the characteristic impedance when data is transferred from the memory chip 3d Since the path is branched into two lines of the wiring 20 and the wiring 21, it becomes 17.5Ω, which is half of the original characteristic impedance of 35Ω, which is caused by impedance mismatch at the series resistance input point P including the resistance value 15Ω of the series resistance 5d. When the reflection coefficient is obtained, the following Equation 1 is obtained.

(Formula 1)
{50- (17.5 + 15)} / {50+ (17.5 + 15)} = 0.21
Therefore, the energy transmitted from the memory chip 3d and transmitted to the printed circuit board 100 is 79%, and the energy corresponding to 21% is reflected at the point P. When energy is lost due to reflection, the transmission signal becomes dull at the rise / fall time. As a result, the rise / fall time is delayed and the timing margin is reduced.

  On the other hand, the change in characteristic impedance when data is transferred from the memory chip 3e is 35Ω, which is the original characteristic impedance value because the wiring does not diverge, so the series resistance input point Q including the resistance value 15Ω of the series resistor 5e When the reflection coefficient due to impedance mismatch is obtained, the following formula 2 is obtained.

(Formula 2)
{50- (35 + 15)} / {50+ (35 + 15)} = 0
Therefore, all energy is transmitted from the memory chip 3e and transmitted to the printed circuit board 100, and there is no reflection at the Q point.

  As described above, when a signal is output from a memory chip in a bus configuration in which a plurality of memory chips are connected, the output from the memory chip close to the memory controller is greatly affected by reflection at the bus connection point, and the energy that can be transmitted on the bus Decrease. On the other hand, the output from the memory chip far from the memory controller is less affected by reflection at the bus connection point, and the energy that can be transmitted on the bus increases. This phenomenon causes a difference in signal quality between the outputs of both memory chips.

  An object of the present invention is to provide a signal transmission circuit in which timing margin is increased by suppressing reflection of an output signal from a memory chip close to a memory controller and bringing the signal quality close to the output signal of a far-end memory chip. .

  According to the present invention, in a configuration in which a plurality of memory chips are bus-connected to one memory controller, the characteristic impedance of the wiring between the memory chip and the memory chip is higher than the characteristic impedance of the wiring between the memory controller and the memory chip. Doing is the main feature.

  According to the present invention, by reducing the reflection of the memory chip output waveform close to the memory controller, the signal waveform dullness that occurs when the reflection occurs is reduced. As a result, the rise / fall time of the signal becomes faster and the timing margin increases.

It is the perspective view which showed the implementation method of this invention. Example 1 It is the perspective view which showed the prior art. It is explanatory drawing of the equivalent circuit of FIG. It is explanatory drawing of the equivalent circuit of FIG. It is explanatory drawing of the relationship between characteristic impedance and a reflection coefficient. It is explanatory drawing of the relationship between characteristic impedance and a reflection coefficient. It is explanatory drawing of the signal waveform at the time of Example 1 application. It is explanatory drawing of the effect at the time of Example 1 application. It is explanatory drawing of the effect at the time of Example 1 application. It is explanatory drawing of the effect at the time of Example 1 application. It is explanatory drawing which showed the implementation method of this invention. (Example 2) It is the perspective view which showed the implementation method of this invention. (Example 3) It is explanatory drawing of the signal waveform at the time of Example 3 application. It is explanatory drawing of the effect at the time of Example 3 application. It is explanatory drawing which showed the implementation method of this invention. Example 4 It is the perspective view which showed the implementation method of this invention. (Example 5) It is explanatory drawing of the signal waveform at the time of Example 5 application. It is explanatory drawing of the effect at the time of Example 5 application.

  The best mode for carrying out the present invention will be described using the following examples. Although an example in which three memory chips are connected to one memory controller is shown here, the present invention can be applied if the number of memory chips is two or more. Further, although the device is exemplified by a memory controller and a memory chip, the present invention can be applied to any device provided with a transmission circuit and a reception circuit.

FIG. 1 shows a perspective view to which the present invention is applied, in a bus connection configuration in which three memory chips are mounted on the same bus. In FIG. 1, the memory controller 2 mounted on the printed circuit board 1 is connected to three memory chips per bus, and the memory chips closest to the memory controller 2 are denoted by 3a, 3b, and 3c. The connection from the memory controller 2 to the connection point A of the memory chip 3a is connected by the wiring 10, the wiring 11 from the point A to the connection point B of the memory chip 3b, and the wiring 12 from the point B to the connection point C of the memory chip 3c. Connected by.
In this embodiment, the thickness of the wiring 11 and the wiring 12 is made thinner than that of the wiring 10 to increase the impedance, and the present invention is applied. Assuming that the wiring width of the wiring 10 is W0, the wiring width of the wiring 11 is W1, and the wiring width of the wiring 12 is W2, the relationship between W0, W1, and W2 in the present embodiment is as shown in Equation 3 below.

(Formula 3)
W0> W1 = W2
Further, assuming that the characteristic impedance of the wiring 10 is Z0, the characteristic impedance of the wiring 11 is Z1, and the characteristic impedance of the wiring 12 is Z2, the relationship between Z0, Z1, and Z2 in this embodiment is as shown in the following Expression 4.

(Formula 4)
Z0 <Z1 = Z2
In this configuration, the reflection coefficient from the memory chip side is obtained. FIG. 4 shows an equivalent circuit when a signal is output from the memory chip 3a in the connection configuration of FIG. In FIG. 4, the wirings 4a, 4b and 4c in the memory chips 3a, 3b and 3c and the wirings 10 and 11 in the printed circuit board 1 are connected via the series resistors 5a, 5b and 5c, so that the memory chips 4a and 4b are connected. 4c and the memory controller 2 are connected by bus via the printed circuit board 1. Other circuit elements will be described later. As an example, when the characteristic impedance of the wirings 4a, 4b, and 4c on the memory chips 3a, 3b, and 3c is 50Ω, the characteristic impedance of the wiring 10 is 35Ω, and the characteristic impedance of the wirings 11 and 12 is 50Ω, data is transferred from the memory chip 3a. The change in characteristic impedance in the case of transfer is 20.6Ω corresponding to the combined characteristic impedance of the wirings 10 and 11 because the transmission path branches into two hands of the wirings 10 and 11, so that the resistance value of the series resistor 5a When the reflection coefficient due to impedance mismatch at the series resistance input point E including 15Ω is obtained, the following formula 5 is obtained.

(Formula 5)
{50- (20.6 + 15)} / {50+ (20.6 + 15)} = 0.16
Therefore, the energy transmitted from the memory chip 3a and transmitted to the printed circuit board 1 is 84%, and the energy corresponding to 16% is reflected at the point E.

  Since the reflection coefficient in the case of not implementing the present invention was 0.21 from Equation 1, it can be seen that the energy transmitted to the printed circuit board increased by 5%.

  FIG. 5 shows the relationship between the characteristic impedance of the wirings 11 and 12 and the reflection coefficient at the point E when the characteristic impedance of the wiring 10 is 35Ω. It should be noted that, in a general printed circuit board, the characteristic impedance that can exist is limited to about 100Ω due to restrictions on the wiring width that can be manufactured and the layer configuration, and thus this range was set as a calculation target. As shown in FIG. 5, in any case where the characteristic impedance of the wiring 4a changes in the range of 35Ω to 100Ω, the reflection coefficient decreases as the characteristic impedance of the wirings 11 and 12 increases. It can be seen that the reflection coefficient is reduced by about 0.1 when the value is set to 100Ω compared to 35Ω.

  FIG. 6 shows the relationship between the characteristic impedance of the wirings 11 and 12 and the reflection coefficient at the point E when the characteristic impedance of the wiring 10 is 50Ω. As shown in FIG. 6, in any case where the characteristic impedance of the wiring 4a changes in the range of 50Ω to 100Ω, the reflection coefficient decreases as the characteristic impedance of the wirings 11 and 12 increases. When 100 is set to 100Ω, it can be seen that the reflection coefficient is reduced by about 0.1 compared to 50Ω.

  Here, the effect of the present invention was calculated by circuit simulation. The equivalent circuit of FIG. 4 was used for the calculation model. For each parameter in the circuit, the following values were used as an example.

  The characteristic impedance of the wirings 4a, 4b, and 4c in the memory chip is 50Ω, the wiring length is 14mm, the on-resistance value of the transmission circuit 8 is 30Ω, the resistance values of the series resistors 5a, 5b, and 5c are 15Ω, and the termination resistors 6b and 6c The resistance value is 30Ω, the input capacitors 7b and 7c are 2 pF, the characteristic impedance of the wiring 32 in the memory controller is 35Ω, the wiring length is 15 mm, the resistance value of the termination resistor 33 is 50Ω, the input capacitance is 5 pF, and the wiring 10 on the printed circuit board The effect of the present invention was confirmed by changing the characteristic impedance value with the characteristic impedance of 35Ω, the wiring length of 97 mm, and the wiring length of the wirings 11 and 12 being 9 mm. In this calculation model, the speed of the electric signal transmitted through the wiring was 6.8 ns / m.

4, the waveform at the input point D of the reception circuit 30 in the memory controller 2 when a pulse wave rising from 0 V to 1.5 V at 200 ps is output from the transmission circuit 8 in the memory chip 3a at time 10 ns. Shown in From FIG. 7, it can be seen that the rise of the waveform becomes faster as the characteristic impedance of the wirings 11 and 12 increases.
FIG. 8 is a graph showing the relationship between the reflection coefficient R and the waveform Slew Rate at point E, which has changed as the characteristic impedance of the wirings 11 and 12 increases with respect to the change in waveform. Slew Rate represents a voltage increase per unit time during a period in which the signal voltage changes from 20% to 80% of the amplitude. From FIG. 8, assuming that the reflection coefficient R and the Slew Rate (S) at the point E are in a proportional relationship under the simulation conditions, an approximate expression of the following Expression 6 is obtained.

(Formula 6)
S = −4.315R + 2.468 [V / ns]
Next, assuming a range in which the characteristic impedance of each wiring can be actually taken, a simulation is performed when the characteristic impedance of the wiring 4a, 4b, and 4c changes in the range from 35Ω to 100Ω when the characteristic impedance of the wiring 10 is 35Ω. Carried out. A similar simulation was performed when the characteristic impedance of the wiring 10 was 50Ω and the characteristic impedance of the wirings 4a, 4b, and 4c changed in the range from 50Ω to 100Ω.

  A graph showing the relationship between the reflection coefficient R at the point E and the Slew Rate of the waveform is shown in FIG. From FIG. 9, it can be seen that, under this simulation condition, the reflection coefficient R and the Slew Rate (S) at point E are in a proportional relationship. FIG. 10 shows the relationship between the reflection coefficient change ΔR and the Slew Rate change ΔS at the point E when the input capacitance of the memory controller is 5 pF and 2 pF under each simulation condition shown in FIG. . FIG. 10 shows that when the reflection coefficient decreases by 0.1, the Slew Rate increases from 0.35 V / ns to about 0.70 V / ns. Therefore, even when the characteristic impedance of the wiring 10 and the wirings 4a, 4b, and 4c and the input capacity of the memory controller are changed, it is understood that the Slew Rate at the receiving point is improved by reducing the reflection coefficient at the point E.

  From the above, it can be seen that when the characteristic impedance of the wirings 11 and 12 is increased, the reflection coefficient at the point E is decreased and the Slew Rate is increased, so that the effect of increasing the timing margin can be obtained.

  The figure which looked at embodiment of the modification of Example 1 from the cross section in FIG. 11 is shown. In FIG. 11, the memory controller 2 mounted on the printed circuit board 1 is connected to three memory chips per same bus, and the memory chips closest to the memory controller 2 are designated as 3 a, 3 b, and 3 c. The connection point A of the memory controller 2 to the memory chip 3a is connected by the wiring 10 of the inner layer wiring, and the connection point B of the memory chip 3b from the point A to the wiring 11 of the surface layer wiring, and from the point B to the memory chip 3c. The connection point C is connected by the wiring 12 of the surface layer wiring.

  In this embodiment, the present invention is applied by changing the means for increasing the impedance of the wiring 11 and the wiring 12 from the inner layer wiring to the surface layer wiring. As a result, the same effect as in the first embodiment can be obtained.

  In this embodiment, the example in which the inner layer wiring is changed to the surface layer wiring is shown as a means for increasing the impedance. However, the present invention is not limited to this example. The present invention can be applied to any case where the wiring is changed to the wiring of another inner layer.

FIG. 12 is a perspective view to which the present invention is applied, in a bus connection configuration in which three memory chips are mounted on the same bus. In FIG. 13, the memory controller 2 mounted on the printed circuit board 1 is connected to three memory chips per bus, and the memory chips closest to the memory controller 2 are denoted by 3 a, 3 b, and 3 c. The connection from the memory controller 2 to the connection point A of the memory chip 3a is connected by the wiring 10, the wiring 11 from the point A to the connection point B of the memory chip 3b, and the wiring 12 from the point B to the connection point C of the memory chip 3c. Connected by.
In this embodiment, the thickness of the wiring 11 is made thinner than that of the wirings 10 and 12 to increase the impedance, and the present invention is applied. Assuming that the wiring width of the wiring 10 is W0, the wiring width of the wiring 11 is W1, and the wiring width of the wiring 12 is W2, the relationship between W0, W1, and W2 in this embodiment is as shown in Equation 7 below.

(Formula 7)
W0 = W2> W1
Further, assuming that the characteristic impedance of the wiring 10 is Z0, the characteristic impedance of the wiring 11 is Z1, and the characteristic impedance of the wiring 12 is Z2, the relationship between Z0, Z1, and Z2 in this embodiment is as shown in the following Expression 8.

(Formula 8)
Z0 = Z2 <Z1
Here, the effect of the present invention was calculated by circuit simulation. FIG. 4 was used for the calculation model. Each parameter in the circuit uses the same value as in the first embodiment, the input capacitance of the memory controller is 5 pF, the characteristic impedance of the wirings 10 and 12 is 35Ω, and the characteristic impedance value of the wiring 11 is changed to change the effect of the present invention. It was confirmed.

4, the waveform at the input point D of the receiving circuit 30 in the memory controller 2 when a pulse wave rising from 0 V to 1.5 V at 200 ps is output from the transmitting circuit 8 in the memory chip 3a at time 10ns is shown in FIG. Shown in From FIG. 13, it can be seen that the rise of the waveform becomes faster as the characteristic impedance of the wiring 11 increases.
FIG. 14 is a graph showing the relationship between the reflection coefficient R and the waveform Slew Rate at the point E, which has changed as the characteristic impedance of the wiring 11 increases, with respect to the change in the waveform. From FIG. 14, assuming that the reflection coefficient R and Slew Rate (S) at point E are in a proportional relationship under the simulation conditions, an approximate expression of the following Expression 9 is obtained.

(Formula 9)
S = −4.024R + 2.395 [V / ns]
From Equation 10, it can be seen that the Slew Rate decreases as the reflection coefficient at point E increases.

  From the above, it can be seen that when the characteristic impedance of the wiring 11 is increased, the reflection coefficient at the point E is decreased and the Slew Rate is increased, so that the effect of increasing the timing margin can be obtained.

  The figure which looked at embodiment of the modification of Example 3 from the cross section in FIG. 15 is shown. In FIG. 15, the memory controller 2 mounted on the printed circuit board 1 is connected to three memory chips per bus, and the memory chips closest to the memory controller 2 are denoted by 3 a, 3 b, and 3 c. The connection point A of the memory controller 2 to the memory chip 3a is connected by the wiring 10 of the inner layer wiring, and the connection point B of the memory chip 3b from the point A to the wiring 11 of the surface layer wiring, and from the point B to the memory chip 3c. The connection point C is connected by the wiring 12 of the inner layer wiring.

  In this embodiment, the present invention is applied by changing the means for increasing the characteristic impedance of the wiring 11 from the inner layer wiring to the surface layer wiring. As a result, the same effect as in the third embodiment can be obtained. In this embodiment, the example in which the inner layer wiring is changed to the surface layer wiring is shown as a means for increasing the impedance. However, the present invention is not limited to this example. The present invention can be applied to any case where the wiring is changed to the wiring of another inner layer.

FIG. 16 is a perspective view to which the present invention is applied, in a bus connection configuration in which three memory chips are mounted on the same bus. In FIG. 16, the memory controller 2 mounted on the printed circuit board 1 is connected to three memory chips per bus, and the memory chips closest to the memory controller 2 are denoted by 3 a, 3 b, and 3 c. The connection from the memory controller 2 to the connection point A of the memory chip 3a is connected by the wiring 10, the wiring 11 from the point A to the connection point B of the memory chip 3b, and the wiring 12 from the point B to the connection point C of the memory chip 3c. Connected by.
In this embodiment, the thickness of the wiring 11 is made thinner than that of the wiring 10 and is made thinner than that of the wiring 12 so that the impedance is increased, and the present invention is applied. Assuming that the wiring width of the wiring 10 is W0, the wiring width of the wiring 11 is W1, and the wiring width of the wiring 12 is W2, the relationship between W0, W1, and W2 in this embodiment is as shown in Equation 10 below.

(Formula 10)
W1 <W2 <W0
Further, assuming that the characteristic impedance of the wiring 10 is Z0, the characteristic impedance of the wiring 11 is Z1, and the characteristic impedance of the wiring 12 is Z2, the relationship between Z0, Z1, and Z2 in this embodiment is as shown in the following Expression 11.

(Formula 11)
Z1>Z2> Z0
Here, the effect of the present invention was calculated by circuit simulation. FIG. 4 was used for the calculation model. Each parameter in the circuit uses the same value as in the first embodiment, the input capacitance of the memory controller is 5 pF, the characteristic impedance of the wiring 10 is 35Ω, the characteristic impedance of the wiring 12 is 45Ω, and the characteristic impedance value of the wiring 11 is changed. The effect of the present invention was confirmed.

4, the waveform at the input point D of the receiving circuit 30 in the memory controller 2 when a pulse wave rising from 0 V to 1.5 V at 200 ps is output from the transmitting circuit 8 in the memory chip 3a at time 10 ns is shown in FIG. Shown in From FIG. 17, it can be seen that the rising of the waveform becomes faster as the characteristic impedance of the wiring 11 increases.
FIG. 18 is a graph showing the relationship between the reflection coefficient R and the waveform Slew Rate at the point E, which changes with the increase in the characteristic impedance of the wiring 11, with respect to the change in the waveform. From FIG. 18, assuming that the reflection coefficient R and the Slew Rate (S) at point E are in a proportional relationship under the simulation conditions, an approximate expression of the following Expression 12 is obtained.

(Formula 12)
S = −3.636R + 2.361 [V / ns]
From Equation 12, it can be seen that the Slew Rate decreases as the reflection coefficient at point E increases.

  From the above, it can be seen that when the characteristic impedance of the wiring 11 is increased, the reflection coefficient at the point E is decreased and the Slew Rate is increased, so that the effect of increasing the timing margin can be obtained.

1 Printed circuit board 2 Memory controller 3a Memory chip (mounted on the side closest to the memory controller 2)
3b Memory chip (mounted between the memory chips 3a and 3c)
3c Memory chip (mounted on the side farthest from the memory controller 2)
3d memory chip (mounted on the side closer to the memory controller 2)
3e Memory chip (mounted on the side far from the memory controller 2)
4a Wiring in the memory chip 3a 4b Wiring in the memory chip 3b 4c Wiring in the memory chip 3c 4d Wiring in the memory chip 3d 4e Wiring in the memory chip 3e 5a Series resistance in the memory chip 3a 5b Series in the memory chip 3b Resistance 5c Series resistance in the memory chip 3c 5d Series resistance in the memory chip 3d 5e Series resistance in the memory chip 3e 6b Termination resistance in the memory chip 3b 6c Termination resistance in the memory chip 3c 7b Input capacity in the memory chip 3b 7c Input capacity in the memory chip 3c 8 Transmission circuit in the memory chip 3a 10 Wiring for connecting the memory controller 2 and the memory chip 3a 11 Wiring for connecting the memory chip 3a and the memory chip 3b 12 Connecting the memory chip 3b and the memory chip 3c Wiring 20 Wiring for connecting the memory controller 2 and the memory chip 3d 21 Wiring for connecting the memory chip 3d and the memory chip 3e 30 Input circuit in the memory controller 2 32 Wiring in the memory controller 2 33 Termination resistance in the memory controller 2 A Memory chip 3a A point where the memory chip 3b is connected to the printed circuit board 1 C a point where the memory chip 3c is connected to the printed circuit board 1 D an input point of the receiving circuit 30 in the memory controller 2 E a point in the memory chip 3a Series resistor connection point on the transmission / reception circuit side L Point where the memory chip 3d is connected to the printed circuit board 100 M Point where the memory chip 3e is connected to the printed circuit board 100 P Series resistance connection point on the transmission / reception circuit side in the memory chip 3d Q Memory chip 3e In the transmitter / receiver circuit side 'S resistance connection point

Claims (6)

  In a signal transmission circuit in which one end of a transmission line is connected to a memory controller and a plurality of memory chips are bus-connected to the transmission line, a first memory chip connected to a position closest to the memory controller, and the first memory A second characteristic impedance of the transmission line connecting between the second memory chips connected to a position closest to the chip is the first characteristic of the transmission line connecting between the memory controller and the first memory chip; A signal transmission circuit characterized by being higher than the characteristic impedance of.   When three or more memory chips are bus-connected to the transmission line, the second characteristic impedance is connected to the second memory chip and connected to a position next to the second memory chip. The signal transmission circuit according to claim 1, wherein the signal transmission circuit is higher than a third characteristic impedance of a transmission line connecting the three memory chips.   A printed circuit board comprising the signal transmission circuit according to claim 1.   In a signal transmission circuit in which one end of a transmission line is connected to a master device and a plurality of slave devices are bus-connected to the transmission line, a first slave device connected to a position closest to the master device, and the first slave The second characteristic impedance of the transmission line connecting between the second slave devices connected to the next closest position of the device is the first characteristic of the transmission line connecting between the master device and the first slave device. A signal transmission circuit characterized by being higher than the characteristic impedance of.   When three or more slave devices are bus-connected to the transmission line, the second characteristic impedance is a third slave connected to the second slave device and a position closest to the second slave device. The signal transmission circuit according to claim 4, wherein the signal transmission circuit is higher than a third characteristic impedance of a transmission line connecting between the slave devices.   A printed circuit board comprising the signal transmission circuit according to claim 4.

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