JP2014011395A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a high breakdown voltage and superior reverse recovery characteristics.SOLUTION: In a semiconductor device having an SOI substrate of a first conductivity type with a buried oxide layer, a semiconductor region of the first conductivity type formed on the SOI substrate, a semiconductor region of a second conductivity type arranged having its long side in parallel with a long side of the semiconductor region of the first conductivity type formed on the SOI substrate, and an element isolation region surrounding the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type, the element isolation region is formed in a projection shape such that the distance between one end of the long side of the semiconductor region of the first conductivity type and the element isolation region adjoining it is longer than the distance between one end of the long side of the semiconductor region of the second conductivity type and the element isolation region adjoining it.

Description

  The present invention relates to a lateral diode and an insulated gate bipolar transistor (hereinafter referred to as IGBT) formed on an SOI substrate.

  In recent years, high-breakdown-voltage power ICs using an SOI (Silicon on Insulator) substrate have been actively developed because of their small device isolation region and parasitic transistor-free characteristics. In the development of a high voltage power IC, it is essential to improve the performance of a high voltage output device that directly drives a load from the viewpoint of output characteristics and chip size reduction.

  Patent Document 1 discloses an example of a lateral diode using an SOI substrate. This document describes the distance d between the end of the p-well layer in the anode region in the long side direction and the element isolation region formed so as to surround the diode, and the depletion layer performs element isolation when a reverse voltage is applied which is the maximum rating. It has been shown that by setting the area to 5 μm or less extending to the region, the electric field strength at the end of the p-well layer during reverse recovery is reduced, the hole current is suppressed, and the local temperature rise is suppressed.

  FIG. 12 is a diagram illustrating an example of a lateral diode disclosed in Patent Document 1. In FIG. 12A is a plan view, FIG. 12B is a cross-sectional view (A-A ′), and FIG. 12C is a cross-sectional view (B-B ′).

  In the anode region A18, a p-well layer A8 is selectively formed in the n-drift layer All, a p-contact layer A13 is formed on the surface of the p-well layer A8, and the anode electrode A16 is electrically connected to the p-contact layer A13. An anode plug A14 is provided as described above.

  In the cathode region A19, an n contact layer A9 is selectively formed in the n − drift layer A11, and a cathode plug A15 is provided so that the cathode electrode A17 is conductively connected to the contact layer A9.

  As shown in FIG. 12A, each of the anode region A18 and the cathode region A19 has a stripe shape, the long sides thereof are arranged to face each other, and the diode is surrounded by the element isolation region A10.

US Patent Publication No. 2011278669 (Japanese Patent Laid-Open No. 2011-238771)

  In the lateral diode, the distance d between the end in the long side direction of the p-well layer A8 in the anode region and the element isolation region A10 formed so as to surround the diode is set to a predetermined value or less.

  The distance d is equal to or less than the spread of the depletion layer formed in the vicinity of the p-well layer in the anode region when the reverse voltage VR which is the maximum rating of the diode is applied, that is, when the maximum rated reverse voltage VR is applied. The depletion layer is designed to be in contact with the element isolation region.

  During recovery, holes flow toward the end of the p-well layer 8 in the long side direction, but the amount of holes is reduced by designing the distance d to be smaller than when the distance d is large. The depletion layer extends from the boundary between the p-well layer A8 and the n-drift layer All toward the n-drift layer A11. The drift layer All is depleted, the potential gradient from the end in the long side direction of the P well layer A8 to the element isolation region A10 becomes gentle, and the electric field strength is reduced. As a result, the device has excellent reverse recovery tolerance.

  In the conventional diode, the distance f between the end of the cathode region in the long side direction and the element isolation region is preferably large in order to increase the breakdown voltage. For this reason, the difference between the distance d and the distance f must be set larger as the element has a higher breakdown voltage. However, when this difference becomes large, current may concentrate at the end of the cathode region A9 during on-conduction, leading to destruction. When the distance d is increased to prevent this, the reverse recovery current increases due to the deterioration of the reverse recovery tolerance and the excessive accumulation of holes around the edge of the anode region in the long side direction.

  The present invention has been made in view of these problems, and provides a semiconductor device having high breakdown voltage and excellent reverse recovery characteristics.

  In order to solve the above problems, the present invention employs the following means.

  A first conductivity type SOI substrate having a buried oxide layer, a first conductivity type semiconductor region formed on the SOI substrate, and a length of the first conductivity type semiconductor region formed on the SOI substrate In a semiconductor device comprising: a second conductive type semiconductor region arranged so that its long side is parallel to the side; and an element isolation region surrounding the first conductive type semiconductor region and the second conductive type semiconductor region; In the element isolation region, the distance between one end of the long side of the first conductivity type semiconductor region and the adjacent element isolation region is adjacent to one end of the long side of the second conductivity type semiconductor region. The convex shape was set to be longer than the distance between the element isolation regions.

  Since the present invention has the above-described configuration, it is possible to provide a semiconductor device with high breakdown voltage and excellent reverse recovery characteristics.

1 is a diagram illustrating a semiconductor device according to a first embodiment. It is a figure which shows the electric current and voltage waveform in the reverse recovery process of the conventional type and the horizontal type diode of this embodiment. It is a top view which shows the semiconductor device concerning 2nd embodiment. It is a top view which shows the semiconductor device concerning 3rd embodiment. It is a top view which shows the semiconductor device concerning 4th embodiment. It is a top view which shows the semiconductor device concerning 5th embodiment. It is a top view which shows the semiconductor device concerning 6th Embodiment. It is a top view which shows the semiconductor device concerning 7th Embodiment. It is a figure which shows the semiconductor device concerning 8th embodiment. It is a figure which shows the example of the inverter IC for motor drive using a horizontal IGBT and a horizontal diode. It is the figure which showed simply the example of the operation mode of inverter IC. It is a figure which shows the example of the conventional horizontal diode.

  Hereinafter, embodiments will be described with reference to the accompanying drawings.

(Embodiment 1)
1A and 1B are diagrams showing a diode according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. A p-type anode region 3 and an n-type cathode region 4 are formed on an n-type semiconductor substrate 2 which is an SOI substrate, and these are surrounded by an element isolation region 1. Here, the n-type semiconductor substrate 2 is made of single crystal silicon, and is formed on a support substrate (not shown) via a buried oxide layer that is an insulating layer. The p-type anode region 3 and the n-type cathode region 4 are formed by diffusing impurities into the n-type semiconductor substrate 2.

  The p-type anode region 3 and the n-type cathode region 4 have a stripe shape, and the long sides of the stripe are arranged to face each other. The distance bl of the element isolation region 1 adjacent to one end in the long side direction of the n-type cathode region 4 and the distance b3 of the element isolation region 1 adjacent to the other end in the long side direction of the n-type cathode region 4 are diodes, respectively. Is set to a distance satisfying the reverse voltage VR which is the maximum rating.

  The distance al between the element isolation region 1 adjacent to one end in the long side direction of the p-type anode region 3 and the distance a3 between the element isolation region 1 adjacent to the other end in the long side direction of the p-type anode region 3 are: Each is set below the spread of the depletion layer formed in the vicinity of the p-type anode region when the reverse voltage VR is applied. Further, the length a2 of the p-type anode region 3 in the long side direction and the length b2 of the n-type cathode region 4 in the long side direction are set to be approximately equal.

  As described above, the element isolation region 1 includes the length a2 in the long side direction of the p-type anode region 3, the sum a of the distance al and the distance a3, the length b2 in the long side direction of the n-type cathode region 4, and the distance bl. The sum b of the distance b3 is formed in a convex shape from the inside of the element toward the outside of the element so that a <b.

  FIG. 2 shows the current and voltage waveforms in the reverse recovery process of the conventional lateral diode and the lateral diode of this embodiment confirmed by device simulation.

  Note that the lateral diode according to this embodiment has a reduced distance (a1, a2) between the p-type anode region and the element isolation region in the planar structure shown in FIG. Only other conditions are the same.

  As shown in FIG. 2, it can be seen that the reverse recovery current and the reverse recovery charge amount are reduced by using the diode structure of the present embodiment as compared with the conventional diode structure.

(Embodiment 2)
FIG. 3 is a plan view showing a second embodiment of the present invention. In this structure, the element isolation regions 1 of the lateral diode shown in FIG. 1 are formed in multiple layers.

  By multiplexing the element isolation regions, the voltage that can be shared by the element isolation regions is increased, and a higher breakdown voltage can be obtained with respect to the structure of FIG. In FIG. 3, the element isolation region is shown as being triple, but the multiplexing number is not limited to three.

(Embodiment 3)
FIG. 4 is a plan view showing a third embodiment of the present invention. In this structure, the element isolation regions 1 of the lateral diode shown in FIG. 1 are formed in multiple layers, and only the innermost element isolation region is formed in a convex shape. As in the second embodiment, by dividing the element isolation region, the voltage that can be shared by the element isolation region is increased, and the voltage is also shared by the semiconductor substrate between the inner element isolation region and the outer element isolation region. Will do. For this reason, a higher breakdown voltage can be obtained with respect to the structure shown in Embodiment 1 (FIG. 1). In FIG. 4, the element isolation region is illustrated as being triple, but the multiplexing number is not limited to three.

(Embodiment 4)
FIG. 5 is a plan view showing a fourth embodiment of the present invention. In this structure, the element isolation regions 1 of the lateral diode shown in FIG. 1 are formed in multiple layers, and the outermost element isolation region is formed in a rectangular shape.

  Since the voltage that can be shared by the element isolation region is increased by multiplexing the element isolation regions, and the semiconductor substrate between the inner element isolation region and the outer element isolation region also shares the voltage, the structure of FIG. Higher withstand voltage can be obtained.

In FIG. 5, the element isolation region is illustrated as being triple, but the multiplexing number is not limited to three.

(Embodiment 5)
FIG. 6 is a plan view showing a fifth embodiment of the present invention. In the present embodiment, the element isolation region 1 is formed concentrically from the center of the end of the n-type cathode region. According to this structure, it is possible to further reduce the semiconductor substrate region inside the element while maintaining the element breakdown voltage according to the structure of FIG. Therefore, the reverse recovery current can be further reduced with respect to the structure of FIG. The element isolation region 1 can be multiplexed as in FIGS.

(Embodiment 6)
FIG. 7 is a plan view showing a sixth embodiment of the present invention. In this structure, a pair of p-type anode region and n-type cathode region is provided inside the device, and the device isolation region 1 is formed so that the distance a is shorter than the distance b, as in the structure of FIG. . Thereby, the same effect as FIG. 1 is acquired. The element isolation region 1 can be multiplexed as in FIGS.

(Embodiment 7)
FIG. 8 is a plan view showing a seventh embodiment of the present invention. In this structure, two or more sets of a p-type anode region and an n-type cathode region are provided in the element, and the element isolation region 1 is formed so that the distance a is shorter than the distance b as in the structure of FIG. Yes. Thereby, the same effect as FIG. 1 is acquired. The element isolation region 1 can be multiplexed as in FIGS.

(Embodiment 8)
FIG. 9 is a diagram showing an example in which the present invention is applied to an IGBT, in which FIG. 9A is a plan view and FIG. 9B is a cross-sectional view along BB ′. A p-type emitter region 5 and an n-type collector region 8 are formed in the n-type semiconductor substrate 2 and are surrounded by the element isolation region 1.

  The p-type emitter region 5 and the n-type collector region 8 have a stripe shape, and their long sides are arranged to face each other. An n-type emitter region 7 and a p-type contact region 6 are formed in the p-type emitter region 5. A p-type collector region 9 is formed in the n-type collector region 8. The p-type emitter region 5, the p-type contact region 6, the n-type emitter region 7 and the n-type collector region 8 are formed by diffusing impurities into the n-type semiconductor substrate 2.

  An emitter electrode is connected to the p-type contact region 6 and the n-type emitter region 7, a collector electrode is connected to the p-type collector region 9, and a gate electrode is disposed on the p-type emitter region 5.

  The distance dl of the element isolation region 1 adjacent to one end of the n-type collector region 8 in the long side direction and the distance d3 of the element isolation region 1 adjacent to the other end of the n-type collector region 8 in the long side direction are Set the distance to satisfy the reverse voltage VR which is the maximum rating. The distance cl between the element isolation region 1 adjacent to one end in the long side direction of the p-type emitter region 5 and the distance c3 between the element isolation region 1 adjacent to the other end in the long side direction of the p-type emitter region 5 are opposite. It is set below the spread of the depletion layer formed in the vicinity of the p-type emitter region when the voltage VR is applied. The length c2 of the p-type emitter region 5 in the long side direction and the length d2 of the n-type collector region 8 in the long side direction are set to be approximately the same.

  The element isolation region 1 includes the sum c of the length c2 of the p-type emitter region 5 in the long side direction, the distance cl and the distance c3, and the length d2, the distance dl and the distance d3 of the n-type collector region 8 in the long side direction. Is formed in a convex shape from the inside of the device toward the outside of the device so that c <d. Thereby, excessive carrier accumulation around the p-type emitter region is suppressed, and quick turn-off characteristics can be obtained.

  Note that the IGBT can be applied to the structures of FIGS. 3, 4, 5, 6, and 7 by the same structure as that of FIG.

(Embodiment 9)
FIG. 10 is a diagram showing an example of a motor drive inverter IC using a lateral IGBT and a lateral diode embodying the present invention.

  The inverter IC 10 is composed of an output stage circuit 11 and an output stage drive circuit 12, and the output stage circuit 11 is connected in parallel with three sets of totem pole connected IGBTs according to the present invention between the high voltage power supply VS and GND. Further, each IGBT is configured to be connected in parallel with a diode according to the present invention.

  Further, the connection points of the IGBTs connected to the totem pole are defined as output terminals MU, MV, and MW. The IGBT is ON / OFF controlled by the output stage control circuit 12, and the output terminal is set to a voltage level of VS or GND or a high impedance state. Hereinafter, the upper pair of totem pole-connected IGBTs and diodes is referred to as an upper arm, and the lower pair is referred to as a lower arm.

  FIG. 11 is a diagram schematically showing an example of the operation mode of the inverter IC. FIG. 11A shows a turn-off operation in which the lower arm IGBT is switched from the on state to the off state. The solid line is a current path that flows when the lower arm IGBT is on, and the broken line is a current path after the lower arm IGBT is off. is there. When the lower arm IGBT shifts to the OFF state, the current flowing through the inductor of the motor that is the load flows to the power supply side via the diode of the upper arm.

  FIG. 11B shows an operation in which the lower arm IGBT is turned on from the off state and the upper arm diode is turned off. A solid line is a current path through which the lower arm IGBT is turned off, and a broken line is a current path after the lower arm IGBT is turned on.

  When the IGBT is off, the upper arm diode is in a conducting state, and when the IGBT is switched on, current flows to the GND side via the lower arm IGBT. At this time, the upper arm diode is switched from the conductive state to the cut-off state, and a reverse recovery operation occurs in this process.

  In the inverter IC, the above-described IGBT on / off switching operation and diode reverse recovery operation are frequently performed. By applying the IGBT and the diode according to the present invention, the turn-off characteristic of the IGBT and the reverse recovery characteristic of the diode are improved, and the loss of the inverter IC can be reduced.

  As described above, in the diode of the present invention, the distance a and the distance b have different values as shown in FIG.

  The distance bl and the distance b3 are preferably larger in order to increase the breakdown voltage. On the other hand, it is desirable that the distance al and the distance a3 are small in order to improve recovery tolerance and prevent an increase in recovery current due to excessive carrier accumulation.

  Further, in order to suppress current concentration at the ends of the anode region and the cathode region, it is desirable that the length a2 in the long side direction of the anode region and the length b2 in the long side direction of the cathode region are equal.

  In the diode according to the present invention, by setting the distance a shorter than the distance b as described above, it is possible to obtain a diode that satisfies the desired form of the high breakdown voltage diode and has a high breakdown voltage and excellent reverse recovery characteristics.

  In addition, the conductivity type shown in the above description is an example, and the same effect can be expected even if each of the conductivity types (n-type and p-type) shown in each embodiment is a reverse conductivity type.

  In addition, the turn-off speed can be improved by similarly applying the shape of the element isolation region to the emitter region and the collector region of the IGBT.

  In addition, embodiment of this invention is not limited to the said embodiment, Various modifications are included. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to the one having all the configurations described.

Further, a part of the configuration of an embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of an embodiment. In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

1 element isolation region 2 n-type semiconductor substrate 3 p-type anode region 4 n-type cathode region 5 p-type emitter region 6 p-type contact region 7 n-type emitter region 8 n-type collector region 9 p-type collector region 10 inverter IC
11 Output stage circuit 12 Output stage drive circuit 13 IGBT
14 Diode

Claims (7)

A first conductivity type SOI substrate with a buried oxide layer;
A first conductivity type semiconductor region formed on the SOI substrate;
A second conductivity type semiconductor region arranged so that the long side thereof is parallel to the long side of the first conductivity type semiconductor region formed on the SOI substrate;
In a semiconductor device comprising an element isolation region surrounding the first conductivity type semiconductor region and the second conductivity type semiconductor region,
In the element isolation region, the distance between one end of the long side of the first conductivity type semiconductor region and the adjacent element isolation region is adjacent to one end of the long side of the second conductivity type semiconductor region. A semiconductor device characterized in that it is set in a convex shape that is longer than the distance between element isolation regions. The semiconductor device according to claim 1,
The distance between one end of the long side of the second conductivity type semiconductor region and the element isolation region adjacent thereto is equal to or less than the spread of the depletion layer formed in the vicinity of the second conductivity type semiconductor region when a reverse voltage is applied. A semiconductor device characterized by being set. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein a length of a long side of the first conductive type diffusion region is equal to a length of a long side of the second conductive type semiconductor region. A first conductivity type SOI substrate with a buried oxide layer;
A first conductivity type semiconductor region formed on the SOI substrate;
A second conductivity type semiconductor region arranged so that the long side thereof is parallel to the long side of the first conductivity type semiconductor region formed on the SOI substrate;
In a semiconductor device comprising an element isolation region surrounding the first conductivity type semiconductor region and the second conductivity type semiconductor region,
The length of the long side of the semiconductor region of the first conductivity type is b2, the distance b1 between one end of the long side and the element isolation region adjacent thereto, and the distance b3 between the other end of the long side and the element isolation region adjacent thereto. age,
The length of the long side of the semiconductor region of the second conductivity type is a2, the distance a1 between one end of the long side and the element isolation region adjacent thereto, the distance a3 between the other end of the long side and the element isolation region adjacent thereto. When
A semiconductor device, wherein a1 + a2 + a3 <b1 + b2 + b3 is set. The semiconductor device according to claim 1,
A semiconductor device characterized in that the first conductive type semiconductor region and the second conductive type semiconductor region are alternately and continuously arranged a plurality of times. The semiconductor device according to claim 1,
2. A semiconductor device according to claim 1, wherein the element isolation region is provided in a multiple number on the outer periphery of at least the convex element isolation region disposed on the innermost periphery. A first conductivity type SOI substrate with a buried oxide layer;
A first conductivity type semiconductor region formed on the SOI substrate;
A second conductivity type semiconductor region arranged so that the long side thereof is parallel to the long side of the first conductivity type semiconductor region formed on the SOI substrate;
A second conductivity type collector region formed in the first conductivity type semiconductor region, a first conductivity type emitter region formed in the second conductivity type semiconductor region, and a second conductivity type semiconductor region. An electrode functioning as a gate;
In a semiconductor device comprising an element isolation region surrounding the first conductivity type semiconductor region and the second conductivity type semiconductor region,
The length of the long side of the first conductivity type semiconductor region is d2, the distance d1 between one end of the long side and the adjacent element isolation region, and the distance d3 between the other end of the long side and the adjacent element isolation region. age,
The length of the long side of the second conductivity type semiconductor region is c2, the distance c1 between one end of the long side and the adjacent element isolation region, and the distance c3 between the other end of the long side and the adjacent element isolation region. When
c1 + c2 + c3 <d1 + d2 + d3.