JP2014011299A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce manufacturing cost by simultaneously performing formation of a contact hole in an interlayer insulation film on a first region and removal of the interlayer insulation film on a second region.SOLUTION: A semiconductor device manufacturing method comprises: a process of forming an interlayer insulation film on first and second regions of a semiconductor substrate; and a first process of simultaneously performing formation of a contact hole in the interlayer insulation film on the first region and removal of the interlayer insulation film on the second region.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, a transistor having a high dielectric constant insulating film (high-K film) as a gate insulating film and a stacked film of a metal film and a polysilicon film as a gate electrode has been proposed. In this type of transistor, a high-dielectric-constant insulating film that is a gate insulating film can reduce a leak current or reduce an equivalent oxide thickness (EOT) to suppress a short channel effect. In addition, by using a stacked film of a metal film and a polysilicon film as the gate electrode, depletion of the gate electrode can be prevented and gate electrode resistance can be reduced.

  Patent Document 1 (Japanese Patent Laid-Open No. 2007-329237) discloses an n-channel transistor and a p-channel transistor each having a silicide gate electrode and a high dielectric constant gate insulating film.

  In addition, the gate insulating film includes a high dielectric constant insulating film, and the gate electrode includes an n-channel transistor and a p-channel transistor each including a stacked film of a metal film and a polysilicon film. In order to change the element characteristics of p-channel transistors, semiconductor devices in which the configuration of the gate insulating film of these transistors is changed have been proposed. 1-4 and 24 show a method of manufacturing a DRAM (Dynamic Random Access Memory) as a semiconductor device having the above structure. 1-4 represents a cross-sectional structure corresponding to the A-A 'cross section of FIG. 24. In these drawings, X represents a memory cell region and Y represents a peripheral circuit region. In FIG. 24, the structure of the peripheral circuit region Y is omitted.

  As shown in FIG. 1, an element isolation region 9 is formed on the surface of the semiconductor substrate 4, and active regions 4a and 4b partitioned by the element isolation region 9 are formed in the memory cell region X and the peripheral circuit region Y, respectively. . In the active region 4a of the memory cell region X, a trench-type gate electrode 1 and a gate insulating film 2 are formed. A cap insulating film 10 is formed on the groove-type gate electrode 1. A bit-con interlayer insulating film 5 is formed on the semiconductor substrate 4 in the memory cell region X. Thereafter, a gate insulating film 6a, a metal film 7a, and a polysilicon film 8a for an n-channel transistor are formed in the peripheral circuit region Y. Thereafter, a gate insulating film 6b, a metal film 7b, and a polysilicon film 8b for a p-channel transistor are formed in the peripheral circuit region Y.

  As shown in FIG. 2, a contact hole 11 is formed in the bit-con interlayer insulating film 5 so as to expose the semiconductor substrate 4. Impurities are implanted into the memory cell region X using a photoresist (not shown) used for contact hole formation as a mask. As a result, an impurity region 3a serving as a source or drain is formed in the memory cell region X. Thereafter, the photoresist is removed.

  As shown in FIG. 3, a polysilicon film 13 is formed on the entire surface of the semiconductor substrate 4. Thereafter, impurities are implanted into the entire surface of the polysilicon film 13 without using a mask.

  As shown in FIG. 4, a metal film 14 and a silicon nitride film 15 are formed on the entire surface of the semiconductor substrate 4. The stacked films formed in the memory cell region X and the peripheral circuit region Y are respectively patterned by the lithography technique and the etching technique. As a result, a bit contact plug 16 made of the polysilicon film 13 and a bit line 17 made of the polysilicon film 13 and the metal film 14 are formed in the memory cell region X. In the peripheral circuit region Y, the gate insulating films 6a and 6b, the metal film 7a, the polysilicon films 8a and 13a, the gate electrode 18a made of the metal film 14a, the metal film 7b, the polysilicon films 8b and 13b, the metal A gate electrode 18b made of the film 14b is formed.

  Thereafter, a silicon nitride film (not shown) serving as an offset spacer is formed on the entire surface of the semiconductor substrate 4 in accordance with a conventional DRAM manufacturing method, and then a photoresist (not shown) is formed so as to cover the memory cell region X. Not formed). Using this photoresist as a mask, the silicon nitride film is dry etched back. Thereby, an offset spacer is formed on the side wall of the gate electrode of the transistor in the peripheral circuit region Y. Thereafter, the photoresist is removed.

  Next, in accordance with the characteristics of the n-channel transistor and the p-channel transistor in the peripheral circuit region Y, a photoresist mask (not shown) is formed at a necessary portion of the peripheral circuit region Y, impurities are implanted, Then, the photoresist mask is removed. A silicon oxide film (not shown) serving as a sidewall is formed on the sidewall of the gate electrode of the transistor in the peripheral circuit region Y. In accordance with the characteristics of the n-channel transistor and the p-channel transistor in the peripheral circuit region Y, a photoresist mask is formed, an impurity is implanted, and the photoresist mask is removed at a necessary portion of the peripheral circuit region Y, respectively. . Thereby, the source and drain 19a, 19b are formed in the peripheral circuit region Y. In this manner, the transistor Tr is formed in the memory cell region X, and the n-channel transistor TrA and the p-channel transistor TrB are formed in the peripheral circuit region Y.

JP 2007-329237 A

In the manufacturing method of the semiconductor device of FIGS.
(1) Lithography and wet etching process (process of FIG. 1) for removing the bit-con interlayer insulating film 5 on the peripheral circuit region Y,
(2) Lithography and etching process (process of FIG. 2) for forming the contact hole 11 in the bit-con interlayer insulating film 5 on the memory cell region X;
Two lithography and etching steps were required.

  For this reason, a manufacturing process increased and the manufacturing cost would increase.

One embodiment is:
Forming an interlayer insulating film on the first and second regions of the semiconductor substrate;
A first step of simultaneously forming a contact hole in the interlayer insulating film on the first region and removing the interlayer insulating film on the second region;
The present invention relates to a method for manufacturing a semiconductor device.

  By simultaneously forming the contact hole in the interlayer insulating film on the first region and removing the interlayer insulating film on the second region, the manufacturing cost can be reduced.

It is a figure showing 1 process of the manufacturing method of the conventional semiconductor device. It is a figure showing 1 process of the manufacturing method of the conventional semiconductor device. It is a figure showing 1 process of the manufacturing method of the conventional semiconductor device. It is a figure showing 1 process of the manufacturing method of the conventional semiconductor device. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a figure showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is a top view showing the semiconductor device of the prior art and 1st Example.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, these Examples are specific examples shown for a deeper understanding of the present invention, and the present invention is not limited to these specific examples.

(First embodiment)
The present embodiment relates to a method of manufacturing a semiconductor device having a DRAM (Dynamic Random Access Memory) to which the manufacturing method of the present invention is applied. In this embodiment, as will be described later, the contact hole 11 is formed in the bit-con interlayer insulating film 5 on the memory cell region (first region) X, and the bit con- figuration on the peripheral circuit region (second region) Y is formed. The interlayer insulating film 5 is removed at the same time. Accordingly, the number of steps can be reduced and the manufacturing cost can be reduced as compared with the case where the step of forming the contact hole 11 and the step of removing the bit-con interlayer insulating film 5 on the peripheral circuit region Y are performed separately. Can do.

  Hereinafter, with reference to FIGS. 5 to 24, a method of manufacturing the semiconductor device of this embodiment will be described. The memory cell region X in FIGS. 5 to 23 is a cross-sectional view corresponding to the direction A-A ′ in FIG. 24. FIG. 24 shows only main structures such as the groove-type gate electrode 1, the active region 4 a, the bit line 17, and the capacitor contact plug 20 in the memory cell region X. FIG. 24 does not show the peripheral circuit region Y.

  First, as shown in FIG. 5, element isolation regions 9 are formed in the memory cell region (first region) X and the peripheral circuit region (second region) Y of the semiconductor substrate 4 by the STI method. As a result, active regions 4 a and 4 b partitioned by the element isolation region 9 are formed in the semiconductor substrate 4 in the memory cell region X and the peripheral circuit region Y, respectively.

  Next, as shown in FIG. 6, the P well 24 is formed in the region where the n-channel transistor is formed in the peripheral circuit region Y, and the N well 25 is formed in the region where the p-channel transistor is formed. Further, impurities are implanted into the semiconductor substrate 4 using the resist mask 35 c to form the cell well 27.

  Subsequently, as shown in FIG. 7, impurities are doped to form impurity regions 3a and 3b to be source and drain regions. Subsequently, a groove-like trench 26 extending in a direction intersecting with the element isolation region 9 is formed in the memory cell region X. Then, the inner wall of the trench 26 is oxidized by an ISSG (in-situ steam generation) method to form the gate insulating film 2 made of a silicon oxide film. Next, the trench-type gate electrode 1 is formed by embedding the trench 26 with a conductor film. The gate electrode 1 forms a word line in the DRAM.

  Next, as shown in FIG. 8, a bit-con interlayer insulating film 5 made of a silicon nitride film is formed on the main surface on the semiconductor substrate 4. Subsequently, a resist mask 35d is formed.

  Next, as shown in FIG. 9, by using a wet etching technique using a resist mask 35d, the bit capacitor interlayer insulating film 5 on the peripheral circuit region Y is removed and the bit capacitor interlayer insulating film on the memory cell region X is removed. 5, a contact hole 11 is formed so as to expose the impurity region (first diffusion layer) 3a in the semiconductor substrate 4 (first step).

As shown in FIG. 10, a high dielectric constant insulating film 30 made of hafnium oxide (HfO ₂ ) is formed on the entire surface of the semiconductor substrate 4. Thereafter, a titanium nitride (TiN) film (first metal film) 31a, a polysilicon film 32a for a peripheral N-channel transistor, and a silicon oxide film 33 are formed on the entire surface of the semiconductor substrate 4. A resist mask 35a is formed on the P-well 24 by using a lithography technique.

  As shown in FIG. 11, after the silicon oxide film 33 is patterned by dry etching using the resist mask 35a as a mask to form a mask of the silicon oxide film 33, the polysilicon is formed by dry etching or wet etching using the mask 33. The silicon film 32a and the titanium nitride film 31a are sequentially patterned. As a result, a laminated structure is formed on the P well 24. Thereafter, the resist mask 35a is removed.

  As shown in FIG. 12, a titanium nitride (TiN) film (first metal film) 31b and a polysilicon film 32b are formed on the entire surface of the semiconductor substrate 4. A resist mask 35b is formed on the N well 25 by lithography.

  As shown in FIG. 13, dry etching of the polysilicon film 32b and the titanium nitride film 31b is sequentially performed using the resist mask 35b. Next, using the resist mask 35b as a mask, the high dielectric constant insulating film 30 is wet etched to form the high dielectric constant insulating film 30b. Thereby, a stacked structure is formed on the N well 25. Thereafter, the resist mask 35b is removed. In this step, since the silicon oxide film 33 is formed on the P well 24, the film under the silicon oxide film 33 remains without being removed, and the high dielectric constant insulating film 30a is formed.

  As shown in FIG. 14, after removing the silicon oxide film 33 on the P well 24, a peripheral P channel type transistor and a bit-comp plug polysilicon film (conductive film) 37 are formed on the entire surface of the semiconductor substrate 4. Form. At this time, the polysilicon film 37 is formed so as to fill the contact hole 11. The polysilicon film 37 is doped with a high concentration of impurities. This high-concentration impurity may be introduced at the same time as the polysilicon film 37 is formed, or may be introduced by injecting impurities into the entire surface after the polysilicon film 37 is formed.

  As shown in FIG. 15, heat treatment is performed to diffuse the impurities in the polysilicon film 37 into the semiconductor substrate 4 to form the contact impurity region 3a.

  As shown in FIG. 16, a silicon nitride film 38 is formed as a cap insulating film on the entire surface of the semiconductor substrate 4. Lithography technology and etching technology are applied to the stacked films on the memory cell region X and the peripheral circuit region Y, respectively. As a result, the bit contact plug 16 embedded in the contact hole 11 in the memory cell region X, the bit line 17 connected to the bit contact plug 16 and positioned on the bit-con interlayer insulating film 5, and the planar type in the peripheral circuit region Y. Gate electrodes 40a and 40b for the second transistor (second transistor) are formed at the same time. Through the above steps, the first transistor Tr1 is completed in one active region 4a in the memory cell region X. The first transistor Tr1 includes a gate insulating film 2, a groove-type gate electrode 1, and impurity regions 3a and 3b. In the present embodiment, two first transistors Tr1 are formed in one active region 4a, and the impurity region 3a serving as a source is shared between the two transistors Tr1. If the bias application state is reversed, the source and the drain are interchanged.

  Thereafter, a silicon nitride film (not shown) is formed on the entire surface of the semiconductor substrate 4 in accordance with a conventional DRAM manufacturing method, and then a photoresist (not shown) is formed on the memory cell region X. An offset spacer (not shown) is formed on the side wall of the gate electrode of the transistor in the peripheral circuit region Y by performing dry etching back of the silicon nitride film using the photoresist as a mask. Thereafter, the photoresist on the memory cell region X is removed. Next, in accordance with the characteristics of the n-channel transistor and the p-channel transistor in the peripheral circuit region Y, a photoresist mask (not shown) is formed at a necessary portion of the peripheral circuit region Y, impurities are implanted, Then, the photoresist mask is removed.

As shown in FIG. 17, a silicon oxide film 41 serving as a sidewall is formed on the sidewall of the gate electrode of the transistor in the peripheral circuit region Y and on the sidewall of the bit line 17. In accordance with the characteristics of the n-channel transistor and the p-channel transistor in the peripheral circuit region Y, formation of a photoresist mask (not shown), implantation of impurities, and photoresist in necessary portions of the peripheral circuit region Y, respectively. The mask is removed to form the source and drain 19a, 19b. Thus, an n-channel second transistor Tr2n and a p-channel second transistor Tr2p are formed in the peripheral circuit region Y. The transistor Tr2n includes a first gate insulating film 30a and a first gate electrode 40a provided in order on the semiconductor substrate 4, and an impurity region 19a provided in the semiconductor substrate 4. The first gate insulating film 30a is a high dielectric constant insulating film made of an HfO ₂ film. The first gate electrode 40a is composed of a titanium nitride film 31a provided in order on the first gate insulating film 30a, and impurities. The polysilicon films 32a and 37a are contained. The transistor Tr2p includes a second gate insulating film 30b and a second gate electrode 40b that are sequentially provided on the semiconductor substrate 4, and an impurity region 19b that is provided in the semiconductor substrate 4. The second gate insulating film 30b is a high dielectric constant insulating film made of an HfO ₂ film, and the second gate electrode 40b contains a titanium nitride film 31b provided in order on the second gate insulating film 30b and contains impurities. The polysilicon films 32b and 37b are provided.

  On the entire surface of the semiconductor substrate 4, an interlayer insulating film 42 made of a coating insulating film such as an SOD (Spin On Dielectrics) film is formed. Thereafter, the interlayer insulating film 42 is planarized by performing the CMP process using the cap insulating film 38 as a stopper. By the lithography technique and the etching technique, a capacitance contact hole (not shown) for exposing the impurity region 3b (second diffusion layer) of the first transistor and the impurity region 19a of the second transistor are exposed in the interlayer insulating film 42. , 19b is formed. Capacitive contact plugs (not shown) and contact plugs 46 are formed by embedding a conductive material in the capacitor contact holes and the contact holes 45.

  As shown in FIG. 18, a capacitor contact pad 48 electrically connected to the capacitor contact plug is formed in the memory cell region X, and a wiring 49 electrically connected to the contact plug 46 is formed in the peripheral circuit region Y. A silicon nitride film 47 is formed on the entire surface of the interlayer insulating film 42.

  As shown in FIG. 19, a BPSG film 50a and a silicon oxide film 50b are sequentially formed on the silicon nitride film 47 by a plasma CVD method using TEOS (Tetra Ethyl Ortho Silicate) as a source gas, and CMP is performed. These films 50a and 50b are planarized by the method. Next, a silicon nitride film 51 is formed on the silicon oxide film 50b. The silicon nitride film 51 functions as a support film that prevents the lower electrode of the capacitor to be formed in a later step from collapsing.

  As shown in FIG. 20, openings are sequentially formed in the films 51, 50b, 50a, and 47 using a lithography technique and a dry etching technique. As a result, a capacitor hole 52a is formed in the memory cell region X, and the contact pad 48 is exposed on the bottom surface thereof. A guard ring trench 52b is formed at the boundary between the peripheral circuit region Y and the memory cell region X. The capacitor hole 52a has a cylindrical shape with a substantially circular cross section, and the guard ring trench 52b is formed to surround the memory cell region X in a square shape. After a titanium nitride film is formed on the entire surface, the titanium nitride film on the silicon nitride film 51 is removed by etch back. Thereby, the lower electrode 53 is formed.

  As shown in FIG. 21, openings (not shown) for wet etching of the interlayer insulating films 50a and 50b are formed in the silicon nitride film 51 by using a lithography technique and a dry etching technique. The interlayer insulating films 50a and 50b in the memory cell region X are removed by wet etching using hydrofluoric acid (HF). At this time, since the peripheral circuit region Y is divided by the memory cell region X and the guard ring trench 52b, the HF aqueous solution does not enter the peripheral circuit region Y during wet etching. The interlayer insulating films 50a and 50b are not removed.

As shown in FIG. 22, a zirconium oxide (ZrO ₂ ) film (not shown) is formed on the entire surface as a capacitive insulating film. Thereafter, a titanium nitride film and an SiGe film doped with boron (B) are formed, and a tungsten film is further formed thereon. Hereinafter, these films are collectively referred to as the upper electrode 55. Thereafter, the upper electrode 55, the capacitor insulating film and the silicon nitride film 51 are dry-etched to leave these films in the vicinity of the memory cell region X. Thereby, a capacitor having a capacitance structure is formed on the inner wall surface and the outer wall side surface of the lower electrode 53, and a capacitor having a crown structure in which the upper electrode 55 is formed on the capacitance insulation film is completed.

  As shown in FIG. 23, after further forming an interlayer insulating film 56 on the interlayer insulating film 50b, a contact plug 57 is formed so as to be connected to the wiring 49 and the upper electrode 55. Thereafter, a wiring 60 is formed on the interlayer insulating film 56 so as to be connected to the contact plug 57. Further, by forming an upper layer contact plug and wiring (not shown), a DRAM having a plurality of memory cells each including a capacitor and a MOS transistor connected to the capacitor can be completed.

  In the present embodiment, as shown in FIG. 9, the contact hole 11 is formed in the bit-con interlayer insulating film 5 on the memory cell formation region X and the peripheral circuit formation region (peripheral circuit formation region ( (Second region) The bit-con interlayer insulating film 5 on Y is simultaneously removed. Therefore, the number of steps can be reduced as compared with the case where the contact hole 11 formation step and the bit-con interlayer insulating film 5 removal step on the peripheral circuit formation region Y are performed separately. As a result, the manufacturing cost can be reduced.

  In this embodiment, the high dielectric constant insulating film 30 is removed in the step of FIG. This embodiment is merely an example, and the timing for removing the high dielectric constant insulating film 30 is not limited to the process shown in FIG. 13, and the high dielectric constant insulating film 30 may be removed at least before forming the polysilicon film 37. .

  The present invention can also be applied to the case where three or more transistors are provided in the peripheral circuit region Y and the gate electrodes of the transistors are formed separately. In this case, the high-dielectric-constant insulating film 30 is removed after the final step of forming the stacked structure for the gate electrode individually for each transistor in the peripheral circuit region Y and before the polysilicon film 37 is formed. It is preferable.

  In the present embodiment, the polysilicon film 37 containing impurities is formed as a material for the gate electrode, the bit contact plug, and the bit line for the second transistor in the step of FIG. However, the film formed in the process of FIG. 14 is not limited to a polysilicon film containing impurities, and any film that can be formed in the manufacturing process may be used. For example, a metal film, a laminated film of a polysilicon film containing an impurity and a metal film, or the like can be formed.

  Furthermore, although the capacitor contact pad 48 is formed in the step of FIG. 18, the lower electrode 53 may be formed without forming the pad 48. In the process of FIG. 20, the guard ring trench 52b is formed to provide the guard ring, but the DRAM may be formed without forming the guard ring.

The high dielectric constant insulating film 30 used as the gate insulating film is not limited to a hafnium oxide (HfO ₂ ) film or an aluminum oxide (AlO ₂ ) film. The high dielectric constant insulating films 30a and 30b are made of a group consisting of a hafnium oxide (HfO ₂ ) film, an aluminum oxide (Al ₂ O ₃ ) film, a hafnium silicate (HfSiO) film, and a lanthanum oxide (La ₂ O ₃ ) film. At least one selected membrane can be used. Further, as the first metal film, at least one film selected from the group consisting of a titanium nitride (TiN) film and a tantalum nitride (TaN) film can be used. The “high dielectric constant insulating film” refers to an insulating film having a higher dielectric constant than silicon dioxide.

DESCRIPTION OF SYMBOLS 1 Groove type gate electrode 2 Gate insulating film 3a Contact impurity region 3b Impurity region 4 Semiconductor substrate 4a, 4b Active region 5 Bitcon interlayer insulating film 6a, 6b Gate insulating film 7a, 7b, 14 Metal film 8a, 8b, 12, 13 Polysilicon film 9 Element isolation region 10 Cap insulating film 11 Contact hole 15 Silicon nitride film 16 Bit contact plug 17 Bit lines 18a and 18b Gate electrodes 19a and 19b Impurity region 20 Capacitance contact plug 24 P well 25 N well 26 Groove-shaped trench 27 Cell well 30, 30a, 30b Hafnium oxide (HfO ₂ ) (high dielectric constant insulating film)
31a, 31b Titanium nitride films 32a, 32b Polysilicon film 33 Silicon oxide films 35a, 35b, 35c, 35d Resist masks 37, 37a, 37b Polysilicon films 38, 47, 51 containing impurities Silicon nitride films 40a, 40b Gate electrodes 41 Sidewalls 42, 56 Interlayer insulating film 45 Contact hole 46, 57 Contact plug 48 Capacitance contact pad 49, 60 Wiring 50a BPSG film 50b Silicon oxide film 52a Capacitor hole 52b Guard ring trench 53 Lower electrode 55 Upper electrode Tr Transistor TrAn Channel type transistor TrB p channel type transistor Tr1 first transistor Tr2n second transistor (n channel type transistor)
Tr2p second transistor (p-channel transistor)
X Memory cell area Y Peripheral circuit area

Claims (10)

Forming an interlayer insulating film on the first and second regions of the semiconductor substrate;
A first step of simultaneously forming a contact hole in the interlayer insulating film on the first region and removing the interlayer insulating film on the second region;
A method for manufacturing a semiconductor device, comprising: Further before the first step,
Forming a first transistor in a first region of the semiconductor substrate;
In the first step,
2. The method of manufacturing a semiconductor device according to claim 1, wherein a contact hole is formed in the interlayer insulating film so as to expose the first diffusion layer of the first transistor. After the step of forming the first transistor,
3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of forming a capacitor so as to be connected to the second diffusion layer of the first transistor. After the first step,
Forming a high dielectric constant insulating film on the first and second regions of the semiconductor substrate;
Removing the high dielectric constant insulating film on the first region of the semiconductor substrate;
Forming a conductive film on the first and second regions of the semiconductor substrate;
By patterning the conductive film, a contact plug and a bit line connected to the contact plug are formed in the contact hole, and at least a part of the gate electrode for the second transistor is formed in the second region. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the conductive film is a polysilicon film containing impurities. After the step of forming the high dielectric constant insulating film, and before the step of forming the conductive film,
Forming a first metal film on the high dielectric constant insulating film;
Forming a polysilicon film containing impurities on the first metal film;
The method of manufacturing a semiconductor device according to claim 4, wherein: The second region has an N well and a P well,
In the step of forming the high dielectric constant insulating film,
Forming first and second gate insulating films having a high dielectric constant insulating film on the N well and the P well, respectively;
In the step of forming the first metal film,
Forming the first metal film as a part of the first and second gate electrodes separately on the first and second gate insulating films, respectively;
In the step of forming the polysilicon film,
7. The method of manufacturing a semiconductor device according to claim 6, wherein the polysilicon film is formed separately as part of the first and second gate electrodes on the N well and the P well, respectively. The second transistor having the first gate insulating film and the first gate electrode constitutes an n-channel transistor,
8. The method of manufacturing a semiconductor device according to claim 7, wherein the second transistor having the second gate insulating film and the second gate electrode constitutes a p-channel transistor.   9. The method according to claim 6, wherein the first metal film is at least one film selected from the group consisting of a titanium nitride (TiN) film and a tantalum nitride (TaN) film. The manufacturing method of the semiconductor device of description. The high dielectric constant insulating film is selected from the group consisting of a hafnium oxide (HfO ₂ ) film, an aluminum oxide (Al ₂ O ₃ ) film, a hafnium silicate (HfSiO) film, and a lanthanum oxide (La ₂ O ₃ ) film. The method for manufacturing a semiconductor device according to claim 4, wherein the method is at least one kind of film.

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