JP2014006366A - Source driver and liquid crystal driving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a source driver capable of achieving a dot inversion driving method when used for driving a monochrome display liquid crystal panel in place of a color display liquid crystal panel.SOLUTION: When a potential output terminal i-th from an end is represented as a potential output terminal S, from continuous three potential output terminals S, S, and S(wherein n is an integer of 1 or more), the potential output terminal Sand the potential output terminal Sare short-circuited. The potential output terminal Sand the potential output terminal Soutput potentials common to each other. The adjacent potential output terminals output potentials having polarities opposite to each other.

Description

  The present invention relates to a source driver and a liquid crystal driving device for driving a liquid crystal panel.

  It can be considered that a color display source driver used for driving a color display liquid crystal panel is used for a monochrome display liquid crystal panel. As a configuration for driving a monochrome display liquid crystal panel using a color display source driver, the configuration illustrated in FIG. 7 can be considered. Hereinafter, the configuration illustrated in FIG. 7 will be described.

In FIG. 7, the pixels of the monochrome display liquid crystal panel are indicated by broken lines. Each pixel 50 is provided with a combination of a pixel electrode 22 and a TFT (Thin Film Transistor) 21. The pixel electrode 22 faces the common electrode 30, and a liquid crystal (not shown) is sandwiched between the pixel electrode 22 and the common electrode 30. The common electrode is kept at a predetermined electric potential _{V COM.}

The gate of the TFT 21 is connected to each gate line G ₁ , G ₂ ,..., And the source of the TFT 21 is connected to each source line C ₁ , C ₂ ,. The drain of the TFT 21 is connected to the pixel electrode 22 that is paired with the TFT.

The gate driver 71 sequentially selects the gate lines G ₁ , G ₂ ,.

  The source driver 72 is a color display source driver. However, in FIG. 7, it is used for driving a monochrome display liquid crystal panel.

The potential output terminals S ₁ , S ₂ ,... Of the source driver 72 are short-circuited every three consecutive potential output terminals. The three shorted potential output terminals are connected to one source line. For example, three consecutive potential output terminals S ₁ , S ₂ , S ₃ are short-circuited and connected to _one source line C ₁ . The same applies to the potential output terminals S ₄ , S ₅ , S _{6 and the} like.

The source driver 72 reads the image data of the row corresponding to the gate line before one gate line is selected. The image data for one row is a set of image data corresponding to each potential output terminal. However, the image data corresponding to three consecutive potential output terminals is monochrome image data showing the same gradation. Therefore, for example, common image data is supplied to the source driver 72 as the image data corresponding to the potential output terminals S ₁ , S ₂ , and S ₃ .

  The source driver 72 outputs a potential corresponding to each read image data from each potential output terminal when one gate line is selected.

  Further, the source driver 72 employs a line inversion driving method. That is, the source driver 72 inverts the polarity in each pixel for each row. There are positive and negative polarities. Positive polarity means that the potential of the pixel electrode is equal to or higher than the potential of the common electrode. The negative polarity means that the potential of the pixel electrode is made equal to or lower than the potential of the common electrode. An example of the polarity of each pixel in the line inversion driving method is shown in FIG. FIG. 8 illustrates a case where the pixels in the odd-numbered rows have positive polarity (“+”) and the pixels in the even-numbered rows have negative polarity (“−”). The source driver 72 inverts the polarity of each row for each frame.

In the line inversion driving method, the polarity of each pixel in one row is common. As described above, the image data corresponding to the three consecutive potential output terminals S _{1 to} S ₃ is image data indicating the same gradation. Therefore, the output potentials of the three consecutive potential output terminals S _{1 to} S ₃ are common. The potential output terminals S _{1 to} S ₃ that output a common potential are short-circuited and connected to _one source line C ₁ . Accordingly, the source line C ₁ is set to a potential corresponding to the gradation indicated by the image data corresponding to the potential output terminals S _{1 to} S ₃ . The same applies to the other source lines. As a result, each pixel electrode in the selected row has a potential corresponding to the image data in that row, and each pixel in that row has a gradation indicated by the image data.

  When the size of the color display liquid crystal panel and that of the monochrome display liquid crystal panel are approximately the same, the size of the pixel electrode of the monochrome display liquid crystal panel is three times that of the pixel electrode of the color display liquid crystal panel. As shown in FIG. 7, even when the pixel electrode is large, the response time can be shortened by short-circuiting three consecutive potential output terminals and connecting them to one source line.

  Patent Document 1 describes that the column terminals of the liquid crystal panel are short-circuited.

JP 2011-209632 A

  In order to reduce the lateral crosstalk, it is preferable to adopt the dot inversion driving method rather than the line inversion driving method.

When the dot inversion driving method is adopted, the color display source driver outputs potentials having different polarities at adjacent potential output terminals. Therefore, when the source driver 72 illustrated in FIG. 7 adopts the dot inversion driving method, even if the potential corresponding to the common gradation is output from three consecutive potential output terminals, the potential output terminal at the center thereof. Outputs a potential different from that of the other two potential output terminals. For example, when outputting a potential corresponding the potential output terminals S ₁ to S ₃ to a common gray scale (. To the x gradation), the positive electrode corresponding to the x gradation from the potential output terminals S _1, S ₃ when outputting sexual potential (a potential higher than V _COM) is from potential output terminals S ₂ and outputs a (potential lower than V _COM) negative potential corresponding to the x grayscale.

  However, in the source driver 72 illustrated in FIG. 7, since the three consecutive potential output terminals are short-circuited, the potentials of the three potential output terminals must be the same. Therefore, the color display source driver 72 having the configuration shown in FIG. 7 cannot adopt the dot inversion driving method.

  Therefore, an object of the present invention is to provide a source driver and a liquid crystal driving device that can realize a dot inversion driving method when used for driving a monochrome display liquid crystal panel instead of a color display liquid crystal panel.

The source driver according to the present invention is a source driver used to drive the liquid crystal panel, comprising a plurality of potential output terminals, when the i th potential output terminal representing the potential output terminals S _i from the end, continuous Of the three potential output terminals S _3n-2 , S _3n-1 , S _3n (where n is an integer equal to or greater than 1), the potential output terminal S _3n-2 and the potential output terminal S _3n are short-circuited and are continuous. Among the three potential output terminals S _3n-2 , S _3n-1 , S _3n , common image data is supplied as image data corresponding to at least the potential output terminal S _3n-2 and the potential output terminal S _3n , The potential output terminal S _3n-2 and the potential output terminal S _3n output a common potential corresponding to the gradation indicated by the common image data, and adjacent potential output terminals output potentials having opposite polarities. It is characterized by.

Of the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n , the potential output terminal S _3n-1 may output a potential corresponding to a predetermined gradation.

A source driver used for driving a normally black liquid crystal panel, and of the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n , the potential output terminal S _3n-1 is the lowest A potential corresponding to the tone may be output.

A source driver used for driving a normally white liquid crystal panel, and of the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n , the potential output terminal S _3n-1 is the highest A potential corresponding to the tone may be output.

Of the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n , the potential output terminal S _3n-1 may be grounded via a resistor.

Of the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n , the potential output terminal S _3n-1 may be grounded via a capacitor.

The liquid crystal drive device according to the present invention is a liquid crystal drive device that drives a liquid crystal panel having a common electrode and pixel electrodes arranged in a matrix and having a source line for each column of pixel electrodes, A gate driver that sequentially selects a source driver that sets a potential corresponding to image data of a row selected by the gate driver in each source line of the liquid crystal panel, and the source driver includes a plurality of potential output terminals, When the i-th potential output terminal from the end is expressed as a potential output terminal S _i , three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n (where n is an integer of 1 or more) among them, the short circuit and the potential output terminals _{S 3n-2} and potential output terminals _{S 3n} is connected to one source line, three potential output terminals _{S 3n-2 successive, S 3n-1, S 3n} At least, as image data corresponding to the potential output terminal _{S 3n-2} and potential output terminals _{S 3n,} common image data is supplied, the potential output terminals _{S 3n-2} and potential output terminals _{S 3n,} the common image A common potential corresponding to the gradation indicated by the data is output, and adjacent potential output terminals output potentials having opposite polarities.

  According to the present invention, a dot inversion driving method can be realized when a monochrome display liquid crystal panel is driven using a color display source driver.

The schematic diagram which shows the liquid crystal drive device of this invention, and the monochrome display liquid crystal panel driven by the liquid crystal drive device. 4 is a timing chart showing a situation in which the source driver 12 reads image data according to STH and CLK. The timing chart which shows the example of a change of STB, POL. Explanatory drawing which shows the polarity of each pixel in this invention. The schematic diagram which shows the state which earth | grounds potential output terminal _S3n-1 via a damping resistor. The schematic diagram which shows the state which earth | grounds electric potential output terminal _S3n-1 through a capacitor. The schematic diagram which shows the structural example in the case of driving a monochrome display liquid crystal panel using the source driver for color displays. Explanatory drawing which shows the example of the polarity of each pixel in a line inversion drive system.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram showing a liquid crystal driving device of the present invention and a monochrome display liquid crystal panel driven by the liquid crystal driving device. The liquid crystal driving device includes a source driver 12, a gate driver 11, and a control unit 10 according to the present invention.

  First, a monochrome display liquid crystal panel (hereinafter simply referred to as a liquid crystal panel) will be described. In FIG. 1, the pixels of the liquid crystal panel are indicated by broken lines. This liquid crystal panel is the same as the liquid crystal panel shown in FIG. Each pixel 50 is provided with a combination of the pixel electrode 22 and the TFT 21. Further, the liquid crystal panel is provided with a common electrode 30 facing each pixel electrode. A liquid crystal (not shown) is sandwiched between the pixel electrode 22 and the common electrode 30. In FIG. 1, the pixel electrode 22 and the common electrode 30 are schematically shown. For example, the common electrode 30 is disposed on one substrate (not shown) of the liquid crystal panel as one electrode facing each pixel electrode 22, and each pixel electrode 22 is another substrate facing the substrate. (Not shown). A liquid crystal (not shown) is sealed between the substrates.

Each pixel 50 is arranged in a matrix. That is, the combination of the pixel electrode 22 and the TFT 21 is arranged in a matrix. A source line is provided for each column of pixel electrodes 22, and a gate line is provided for each row of pixel electrodes 22. The kth source line from the left as viewed from the observer side is denoted as C _k . The k-th gate line is _denoted as Gk.

  The gate of the TFT 21 is connected to the gate line of the row where the TFT is arranged, and the source of the TFT 21 is connected to the source line of the column where the TFT is arranged. The drain of the TFT 21 is connected to the pixel electrode 22 that is paired with the TFT.

When the gate of the TFT 21 is set to a predetermined on potential via the gate line, the source and drain of the TFT are brought into conduction, and the pixel electrode 22 is set to the same potential as the source line. When the gate of the TFT 21 is set to a predetermined off potential, the source and drain of the TFT are in a non-conductive state, and the pixel electrode 22 and the source line are also in a non-conductive state. The predetermined on-potential is a predetermined potential of the gate for making the source and drain conductive. The predetermined off potential is a predetermined potential of the gate for making the source and drain non-conductive. Hereinafter, the predetermined on potential is represented as V _gH and the predetermined off potential is represented as V _gL .

The gate driver 11 is connected to each gate line. Then, the gate driver 11 sequentially selects individual gate lines by setting the potential to a predetermined on-potential _VgH sequentially from the gate line of the first row in the frame according to the control unit 10. The gate driver 11 sets the potential of each unselected gate line to a predetermined off potential _VgL . A row selected by the gate driver 11 is simply referred to as a selected row. A period during which the gate driver 11 selects one gate line is referred to as a selection period.

  The source driver 12 includes a plurality of potential output terminals. Then, the source driver 12 outputs a potential corresponding to the gradation indicated by the image data of the selected row from the potential output terminal according to the control unit 10.

In the source driver 12, the i-th potential output terminal from the end (here, the left end as viewed from the observer is taken as an example) is represented by a symbol “S _i ”. FIG. 1 illustrates the first to eighth potential output terminals S _{1 to} S ₈ from the end. Further, when a set of potential output terminals is determined in order from one end as one set of three consecutive potential output terminals, the potential output terminals S _3n-2 , S _3n-1 , and S _3n are included in an arbitrary group. become. However, n is an integer of 1 or more.

In each set of three consecutive potential output terminals, the potential output terminal S _3n-2 and the potential output terminal S _3n are short-circuited and connected to one source line C _n . The potential output terminal S _3n-1 is not connected to the source line. The potential output terminal S _3n-1 may be in a state where it is not connected anywhere (open state). For example, the set of potential output terminals _S 1 to S _3, the potential output terminals _S 1, _{S 3} are short-circuited, is connected to a source line _{C 1.} Potential output terminals S ₂ is in a state of not being connected to anything. Similarly, in the set of potential output terminals _S 4 to S _6, the potential output terminals _S 4, _{S 6} are shorted and connected to a source line _{C 2.} Potential output terminals S ₅ is in a state of not being connected to anything. The same applies to other groups.

  The control unit 10 supplies image data for one screen to the source driver 12 in order from the image data in the first row for each frame.

The image data for one row is a set of image data corresponding to each potential output terminal. However, the image data corresponding to three consecutive potential output terminals is monochrome image data showing the same gradation. Therefore, for example, common image data is supplied to the source driver 12 as each image data corresponding to the potential output terminals S ₁ , S ₂ , S ₃ .

The control unit 10 outputs, to the source driver 12 for each selected row, a potential corresponding to the gradation indicated by the individual image data included in the image data for one row, and a potential output corresponding to the individual image data. Output from the end. Since the image data corresponding to the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n are common, the source driver 12 is connected to the potential output terminals S _3n-2 , S _3n-1 , S _3n. To output a potential corresponding to the same gradation.

However, adjacent potential output terminals output opposite polarities. That is, the odd-numbered potential output terminal, when outputting potentials higher than V _COM, the even-numbered potential output terminals outputs potentials lower than V _COM. Also, the odd-numbered potential output terminal, when outputting potentials lower than V _COM, the even-numbered potential output terminals outputs potentials higher than V _COM.

Accordingly, any set of potential output terminals S _3n-2 , S _3n-1 , S _3n outputs a potential corresponding to the same gradation, but the central potential output terminal S of the three potential output terminals. _3n-1 outputs a potential having a polarity opposite to that of the potential output terminals _S3n-2 and _S3n . For example, when the potential output terminals S _3n-2 and S _3n output a potential higher than V _COM corresponding to the x-th gradation, the potential output terminal S _3n-1 corresponds to V _COM corresponding to the x-th gradation. Output a low potential. Further, for example, when the potential output terminals S _3n-2 and S _3n output a potential lower than V _COM corresponding to the xth gradation, the potential output terminal S _3n-1 corresponds to the Vth corresponding to the xth gradation. _A potential higher than _COM is output.

  The control unit 10 outputs to the source driver 12 a control signal (POL, which will be described later) that defines the level relationship between the output potentials of the common electrode and each potential output terminal.

  Further, the control unit 10 instructs the gate driver 11 to switch the selection of the gate line.

Further, the liquid crystal driving device of the present invention includes a common driver (not shown) that sets the potential of the common electrode 30 (see FIG. 1), and the common driver sets the potential of the common electrode 30 to a predetermined potential _VCOM . .

  Hereinafter, control signals output from the control unit 10 will be described.

  The control unit 10 gates a signal for instructing the start of each frame (hereinafter referred to as a frame start signal) and a control signal for instructing switching of a selected gate line (hereinafter referred to as a row switching signal). Output to the driver 11. The control unit 10 instructs the gate driver 11 to switch the gate line in a selection period cycle by a row switching signal. When the gate driver 11 is instructed to start a frame by the frame start signal and receives a gate line switching instruction for the first time, the gate driver 11 selects the gate line of the first row. Thereafter, each time the gate driver 11 receives a gate line switching instruction, the gate driver 11 sequentially switches the gate line to be selected.

  Further, the control unit 10 outputs a frame start signal, STH, CLK, STB, and POL as control signals to the source driver 12.

  STH is a control signal that instructs the source driver 12 to start reading image data for one row. The source driver 12 to which STH is input reads image data for one line from the control unit 10 and stores the image data for one line.

  CLK is a control signal that instructs the source driver 12 to read image data corresponding to three potential output terminals for each set of three consecutive potential output terminals.

  FIG. 2 is a timing chart showing a state in which the source driver 12 reads image data in accordance with STH and CLK. The control unit 10 switches CLK alternately between a high level and a low level so that the period of the rising edge becomes constant. Further, the control unit 10 raises STH to the high level at the same cycle as the length of the selection period, and then falls to the low level after a certain period.

When the source driver 12 detects the rising edge of CLK during the period when STH is at a high level, each time the rising edge is detected thereafter, one set of potential output terminals S _3n-2 , S _3n-1 , S Image data corresponding to _3n is read. Each image data corresponding to the potential output terminals S _3n-2 , S _3n-1 , S _3n is image data representing a common gradation. FIG. 2 shows an example in which each piece of image data is represented by 4 bits. D _{0 to} D ₃ shown in FIG. 2 indicate each bit of the image data. For example, assume that the rising edge of CLK is first detected after the rising edge of CLK is detected during a period in which STH is at a high level. If the values of D _{0 to} D ₃ supplied from the control unit 10 at this time are, for example, D ₀ = 1, D ₁ = 1, D ₂ = 1, and D ₃ = 1, respectively, the potential output terminal S _{3n −2} , S _3n−1 , S _3n , 4-bit image data “1111” is read and stored as each image data. Similarly, the source driver 12 reads and stores each image data corresponding to the three potential output terminals forming a set at every rising edge of CLK. As a result, the source driver 12 stores image data for one line. Then, the source driver 12 reads and stores the image data of each row sequentially by repeating the above-described operation according to STH and CLK.

  Note that the above 4 bits are examples, and the number of bits of image data is not limited to 4 bits.

  The STB outputs a potential corresponding to the gradation indicated by the image data from each potential output terminal corresponding to each image data to the source driver 12 based on the stored image data for one row. This is a control signal for instructing.

POL is a control signal that defines the level of the output potential of the common electrode and each potential output terminal. That POL is at a high level, the output potential of the odd-numbered potential output terminals from the left in the positive polarity potential (a potential higher than V _COM), the negative potential output potential of the even-numbered potential output terminals from the left ( to a lower potential) than V _COM, which means that instructs the source driver 12. Further, when POL is at a low level, it means that the output potential of the odd-numbered potential output terminal from the left is set to the negative potential, and the output potential of the even-numbered potential output terminal from the left is set to the positive potential. 12 is instructed.

The source driver 12 according to POL, the output potential from each potential output _terminal, a potential higher than _{V COM,} or the potentials lower than _{V COM.}

  The control unit 10 switches POL between a high level and a low level in the same period as the selection period.

  FIG. 3 is a timing chart showing an example of changes in STB and POL output from the control unit 10. The control unit 10 outputs the STB so that the period from the falling edge of the STB to the next falling edge is the same as the length of the selection period (T). Further, the control unit 10 alternately switches the POL level between the high level and the low level for each period T having the same length as the selection period. Therefore, the period of POL is 2T. Further, the control unit 10 outputs STB and POL so as to switch the level of POL before the falling edge of STB.

The source driver 12 displays the image data from each potential output terminal corresponding to each image data based on the image data for one row read before the falling edge to the rising edge of the STB. A potential corresponding to the gradation is output. However, if POL is at a high level, the source driver 12, the odd-numbered potential output terminals _{S 1, S 3, S 5} , S 7, the output potential from _..., and potentials higher than _{V COM,} the even The output potentials from the second potential output terminals S ₂ , S ₄ , S ₆ , S ₈ ,... _{Are set} lower than V _COM . On the other hand, when POL is at a low level, the source driver 12, the odd-numbered potential output terminals _{S 1, S 3, S 5} , S 7, the output potential from _..., and potentials lower than _{V COM,} the even The output potential from the second potential output terminals S ₂ , S ₄ , S ₆ , S ₈ ,... _{Is set} higher than V _COM .

  Further, when the source driver 12 outputs a potential from each potential output terminal according to each gradation indicated by the image data for one row, the image data for the next row is output in accordance with STH and CLK input from the control unit 10. And the image data for one line is stored. Then, the source driver 12 outputs a potential from each potential output terminal based on the image data and POL for one row from the falling edge to the rising edge of the next STB.

Prior to the falling edge of STB, the level of POL is switched. Therefore, at this time, the source driver 12, the height relation between the output potential of the odd-numbered potential output terminal and V _COM, and, respectively inverts the even the high and low relation between the output potential and V _COM potential output terminal.

  The source driver 12 repeats the same operation within the frame.

The polarity of each pixel in this embodiment will be described. The set potential of the source line in the selection period in which POL is at a high level will be described. In this case, the source driver 12, as described above, the output potential of the odd-numbered potential output terminals and potentials higher than V _COM, the output potential of the even-numbered potential output terminals and potentials lower than V _COM. Three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n output a potential corresponding to a common gradation. Therefore, the potential output terminals S _3n-2 and S _3n output the same potential, and the potential output terminal S _3n-1 has a common gradation potential, but the potential output terminals S _3n-2 and S _3n A potential having an opposite polarity to the output potential is output.

Here, the potential output terminals S _3n-2 and S _3n are short-circuited and connected to one source line C _n . Therefore, the potential of the source line C _n is set to a common potential output from the potential output terminals S _3n-2 and S _3n . Further, since the potential output terminals _{S 3n-1} for outputting a potential different from the potential output terminals _{S 3n-2, S} 3n is not connected to a source line _{C n,} does not affect the potential of the source line _{C n.}

At this time, when n is an odd number, the potential output terminals S _3n-2 and S _3n (for example, the potential output terminals S ₁ and S ₃ ) output a potential higher than V _COM , so the potential of the odd-numbered source line a higher than _{V COM} is also potential. When n is an even number, the potential output terminals S _3n-2 and S _3n (for example, the potential output terminals S ₄ and S ₆ ) output a potential lower than V _COM , so that the potential of the even-numbered source line is also V _COM. Lower potential. Therefore, as shown in the first row of FIG. 4, the polarities of the pixels in the selected row are alternately inverted from the left side in the order of positive polarity and negative polarity.

In the next selection period, POL is switched to a low level. In this case, the source driver 12, the output potential of the odd-numbered potential output terminals and potentials lower than V _COM, the output potential of the even-numbered potential output terminals and potentials higher than V _COM. Also in this case, the potential output terminals S _3n-2 and S _3n output the same potential, and the potential output terminal S _3n-1 has a common gradation potential, but the potential output terminals S _3n-2 , A potential having a polarity opposite to the output potential of _S3n is output.

The potential output terminals S _3n-2 and S _3n are short-circuited and connected to one source line C _n . Therefore, the potential of the source line C _n is set to a common potential output from the potential output terminals S _3n-2 and S _3n . Further, since the potential output terminals _{S 3n-1} for outputting a potential different from the potential output terminals _{S 3n-2, S} 3n is not connected to a source line _{C n,} does not affect the potential of the source line _{C n.}

At this time, when n is an odd number, the potential output terminals S _3n-2 and S _3n (for example, the potential output terminals S ₁ and S ₃ ) output a potential lower than V _COM , so the potential of the odd-numbered source line _Is also lower than VCOM. When n is an even number, the potential output terminals S _3n-2 and S _3n (for example, the potential output terminals S ₄ and S ₆ ) output a potential higher than V _COM , and therefore the potential of the even-numbered source line is also V _COM. Higher potential. Therefore, as shown in the second row of FIG. 4, the polarities of the pixels in the selected row are alternately inverted from the left in the order of negative polarity and positive polarity.

  Thereafter, since the POL level is alternately switched between the high level and the low level in the selection period, the polarity of each pixel is as shown in FIG.

Thus, in the present invention, among the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n , the potential output terminals S _3n-2 , S _3n-1 are short _- circuited, and the source line C _n Connect to. Among the three, the central potential output terminal S _3n-1 is not connected to the source line. Adjacent potential output terminals output potentials having opposite polarities. Therefore, short-circuit the potential output terminals _{S 3n-2, S 3n-} 1 for outputting a common potential, since is connected to a source line _{C n,} to the source line _{C n,} the potential output terminals _{S 3n-2,} The same potential as S _3n-1 is set. Further, the set of potential output terminal _S 3 of the adjacent the _{(n + 1) -2, S} 3 (n + 1) -1, but also applies to _{S 3 (n + 1),} the potential output terminals _{S 3 (n + 1) -2} , S3 _{(n + 1)} outputs a potential having a polarity opposite to that of the potential output terminals _S3n-2 and _S3n-1 . Accordingly, the potential of the source line C _{n + 1} has a polarity opposite to that of the source line C _n .

  Therefore, in the present invention, the pixels adjacent to the left and right are opposite in polarity. Further, since the POL level is alternately switched between the high level and the low level in the selection period cycle, the pixels adjacent to each other in the vertical direction have opposite polarities. Therefore, according to the present invention, it is possible to realize a dot inversion driving method using a color display source driver.

  In addition, since a color display source driver can be used to drive the monochrome display liquid crystal panel, the cost of the liquid crystal drive device can be reduced.

  The operation of the control unit 10 is a general operation when driving the color display liquid crystal panel by the dot inversion driving method. Therefore, the general-purpose control unit 10 can be used for controlling the source driver 12.

Next, a modification of the embodiment of the present invention will be described.
Among the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n , at least two potential output terminals S _3n-2 , S _3n on both sides should output a potential corresponding to a common gradation. The central potential output terminal S _3n-1 may output a potential corresponding to a predetermined gradation.

In this case, the image data corresponding to the central potential output terminal S _3n-1 in each set of three consecutive potential output terminals may not be supplied to the source driver 12. That is, the source driver 12 only needs to be supplied with image data corresponding to at least two potential output terminals S _3n-2 and S _3n on both sides in each set. In each group, each image data corresponding to the potential output terminals S _3n-2 and S _3n represents a common gradation.

An example of the output potential of the potential output terminal S _3n-1 in this case is shown. When the liquid crystal panel is normally black, it is preferable that the central potential output terminal S _{3n-1 in} each group outputs a potential corresponding to the lowest gradation. For example, when POL is at a high level, if the potential output terminal S _3n-1 is an odd _- numbered potential output terminal, a potential higher than V _COM corresponding to the lowest gradation is output, and the potential output terminal S _3n-1 if the even-numbered potential output terminals, it is preferable to output lower than V _COM corresponding to the lowest gradation voltage.

At this time, the output potential of the potential output terminal S _3n−1 is alternately changed into “a potential higher than V _COM corresponding to the lowest gradation” and “a potential lower than V _COM corresponding to the lowest gradation” for each selected row. Can be switched. In a normally black liquid crystal panel, since the difference between the two potentials is small, power consumption can be suppressed.

When the liquid crystal panel is normally white, it is preferable that the central potential output terminal _{S3n-1 in} each group outputs a potential corresponding to the highest gradation. For example, when POL is at a high level, if the potential output terminal S _3n-1 is an odd _- numbered potential output terminal, a potential higher than V _COM corresponding to the highest gradation is output, and the potential output terminal S _3n-1 if the even-numbered potential output terminals, it is preferable to output a potential lower than V _COM corresponding to the highest grayscale.

At this time, the output potential of the potential output terminal S _3n−1 is alternately changed into “a potential higher than V _COM corresponding to the highest gradation” and “a potential lower than V _COM corresponding to the highest gradation” for each selected row. Can be switched. In a normally black liquid crystal panel, since the difference between the two potentials is small, power consumption can be suppressed.

Further, in the above embodiment, although the case where the potential output terminals S _3n-1 are not connected to anything as an example, as illustrated in FIG. 5, the potential output terminals S _3n-1 in each set, a damping resistor It may be grounded through. The resistance value of the damping resistor is preferably a high resistance value such as 100 KΩ or 1 MΩ. By grounding the potential output terminal S _3n-1 via a damping resistor, oscillation at the potential output terminal S _3n-1 that is not connected to the source wiring can be suppressed.

Further, as illustrated in FIG. 6, the potential output terminal S _3n−1 in each set may be set via a capacitor. Also in this case, oscillation at the potential output terminal S _3n-1 can be suppressed.

  The present invention can also be applied to driving of a liquid crystal panel in which the common electrode is in the same plane as the TFT and the pixel electrode, such as an in-plane switching (IPS) liquid crystal panel. Furthermore, in the above embodiment, the case where the TFT liquid crystal panel is driven has been described as an example. However, the liquid crystal panel to be driven according to the present invention may be a liquid crystal panel having a switching element other than the TFT.

  The present invention can be suitably applied to driving a monochrome display liquid crystal panel.

DESCRIPTION _{OF SYMBOLS} 10 Control part 11 Gate driver 12 Source driver _S3n-2 , _S3n-1 , _S3n electric potential output terminal

Claims (7)

A source driver used for driving a liquid crystal panel,
With multiple potential output terminals,
When the i-th potential output terminal from the end is expressed as a potential output terminal S _i , three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n (where n is an integer of 1 or more) Among them, the potential output terminal S _3n-2 and the potential output terminal S _3n are short-circuited,
Among the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n , at least common image data is image data corresponding to the potential output terminal S _3n-2 and the potential output terminal S _3n. Supplied,
The potential output terminal S _3n-2 and the potential output terminal S _3n output a common potential corresponding to the gradation indicated by the common image data,
A source driver characterized in that adjacent potential output terminals output potentials having opposite polarities. The source driver according to claim 1, wherein among the three consecutive potential output terminals S _3n−2 , S _3n−1 , and S _3n , the potential output terminal S _3n−1 outputs a potential corresponding to a predetermined gradation. . A source driver used to drive a normally black liquid crystal panel,
Three potential output terminals successive _{S 3n-2, S 3n-} 1, of the _{S 3n,} the potential output terminals _{S 3n-1} is defined in claim 1 or claim 2 for outputting a potential corresponding to the lowest gradation Source driver. A source driver used to drive a normally white liquid crystal panel,
Three potential output terminals successive _{S 3n-2, S 3n-} 1, of the _{S 3n,} the potential output terminals _{S 3n-1} is defined in claim 1 or claim 2 for outputting a potential corresponding to the highest gradation Source driver. The potential output terminal S _3n-1 is grounded through a resistor among the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n . The source driver according to item 1. Three potential output terminals _{S 3n-2 successive, S 3n-1,} of the _{S 3n,} the potential output terminals _{S 3n-1} are any of claims 1 to be grounded via a capacitor of claim 4 The source driver according to item 1. A liquid crystal driving device having a common electrode and pixel electrodes arranged in a matrix and driving a liquid crystal panel having a source line for each column of the pixel electrodes,
A gate driver that sequentially selects each row;
Each source line of the liquid crystal panel includes a source driver that sets a potential according to image data of a row selected by the gate driver,
The source driver is
With multiple potential output terminals,
When the i-th potential output terminal from the end is expressed as a potential output terminal S _i , three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n (where n is an integer of 1 or more) Among them, the potential output terminal S _3n-2 and the potential output terminal S _3n are short-circuited and connected to one source line,
Among the three consecutive potential output terminals S _3n-2 , S _3n-1 , S _3n , at least common image data is image data corresponding to the potential output terminal S _3n-2 and the potential output terminal S _3n. Supplied,
The potential output terminal S _3n-2 and the potential output terminal S _3n output a common potential corresponding to the gradation indicated by the common image data,
An adjacent potential output terminal outputs potentials having opposite polarities to each other.

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