JP2013515306A5 - - Google Patents

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JP2013515306A5
JP2013515306A5 JP2012545216A JP2012545216A JP2013515306A5 JP 2013515306 A5 JP2013515306 A5 JP 2013515306A5 JP 2012545216 A JP2012545216 A JP 2012545216A JP 2012545216 A JP2012545216 A JP 2012545216A JP 2013515306 A5 JP2013515306 A5 JP 2013515306A5
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instruction
store
hazard
load
execution
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JP2012545216A
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JP5850532B2 (ja
JP2013515306A (ja
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Priority claimed from US12/644,923 external-priority patent/US8468325B2/en
Priority claimed from US12/822,960 external-priority patent/US8521992B2/en
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JP2012545216A 2009-12-22 2010-12-13 アウトオブオーダー型マイクロプロセッサにおけるオペランド・ストア比較ハザードの予測及び回避 Active JP5850532B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US12/644,923 2009-12-22
US12/644,923 US8468325B2 (en) 2009-12-22 2009-12-22 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
US12/822,960 2010-06-24
US12/822,960 US8521992B2 (en) 2009-12-22 2010-06-24 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
PCT/EP2010/069496 WO2011076602A1 (en) 2009-12-22 2010-12-13 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

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JP2015146076A Division JP6143306B2 (ja) 2009-12-22 2015-07-23 アウトオブオーダー型マイクロプロセッサにおけるオペランド・ストア比較ハザードの予測及び回避

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JP2013515306A JP2013515306A (ja) 2013-05-02
JP2013515306A5 true JP2013515306A5 (enExample) 2015-02-19
JP5850532B2 JP5850532B2 (ja) 2016-02-03

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JP2012545216A Active JP5850532B2 (ja) 2009-12-22 2010-12-13 アウトオブオーダー型マイクロプロセッサにおけるオペランド・ストア比較ハザードの予測及び回避
JP2015146076A Active JP6143306B2 (ja) 2009-12-22 2015-07-23 アウトオブオーダー型マイクロプロセッサにおけるオペランド・ストア比較ハザードの予測及び回避

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US (2) US8521992B2 (enExample)
JP (2) JP5850532B2 (enExample)
CN (1) CN102652304B (enExample)
DE (1) DE112010004322T5 (enExample)
GB (1) GB2486155B (enExample)
WO (1) WO2011076602A1 (enExample)

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