JP2013251960A - Multilevel power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate an interference between the control for a neutral-point voltage and the control for a capacitor voltage of each phase.SOLUTION: A multilevel power converter, including five-level power conversion parts for three phases and two capacitors serially connected between the positive and negative electrodes of a DC current, includes: a vector selection part 201 for prediction-calculating respective currents of the five-level power conversion parts for the individual phases, for each of six vectors moved from the present vector defined for two-axis coordinate system zone in spatial vector control, and selecting a vector whose deviation of the prediction-calculated current against a current instruction value is the smallest, to thereby calculate a phase voltage instruction; a Vc voltage constant-control part 202 for calculating a charge/discharge instruction with which a deviation of the capacitor voltage within the five-level power conversion parts against an instruction value is the smallest; and a Vdc voltage constant-control part 203 for calculating a neutral-point voltage when selecting a movement destination vector determined by the phase voltage instruction and selecting a vector with which the voltage deviation between the two capacitors is eliminated to thereby determine the charge/discharge instruction.

Description

  The present invention relates to a power conversion circuit that can output a five-level phase voltage and operates with a single DC voltage source, and converts an AC voltage obtained by converting a DC voltage between positive and negative electrodes of a DC voltage source into a plurality of voltage levels. The present invention relates to an output multilevel power converter and a control method thereof.

  Conventionally, for example, a three-level three-phase inverter device described in Patent Literatures 1 and 2 has been proposed as a power converter that outputs an AC voltage obtained by converting a DC voltage between positive and negative electrodes of a DC voltage source into a plurality of voltage levels. .

  Patent Document 1 describes controlling a neutral point voltage of a DC power supply in a three-level three-phase inverter. Patent Document 2 describes a method for stabilizing the neutral point potential using a space vector modulation method.

JP-A-5-292754 JP-A-8-107698

  In Patent Documents 1 and 2, the neutral point voltage in the three-phase inverter is controlled, but the voltage of the capacitor for generating a plurality of voltage levels by charging and discharging is provided for each of the three-phase inverters. Is not taken into consideration for control for maintaining the voltage constant or for maintaining the voltage within a certain voltage range.

  For this reason, in the techniques of Patent Documents 1 and 2, there is a possibility that the control of the neutral point voltage and the control of the capacitor voltage of each phase may interfere with each other, and this makes it impossible to control the optimum output voltage waveform with little distortion. There was a problem.

  SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object of the present invention is to provide a multilevel power converter in which neutral point voltage control and capacitor voltage control of each phase do not interfere with each other, and a control method therefor. is there.

  The multilevel power converter according to claim 1 for solving the above-mentioned problem is a multilevel power converter that outputs an AC voltage obtained by converting a DC voltage between positive and negative electrodes of a DC voltage source into a plurality of voltage levels. A switching element series circuit in which the first to fourth switching elements are sequentially connected in series, and a first series connection in series between the first switching element side end and the fourth switching element side end of the switching element series circuit. And a second capacitor, a first common connection point between the first switching element and the second switching element, and a second common connection point between the third switching element and the fourth switching element. A fifth switch having one end connected to a common connection point of the first and second diodes and the first capacitor and the first switching element One end connected to a common connection point of the switching element, a second connection point of the second capacitor and the fourth switching element, and a common connection point of the first and second capacitors. And a first switching means that can be controlled in the reverse withstand voltage directions, and is configured by connecting a common connection point of the first and second diodes and a common connection point of the first and second capacitors. A multi-level power converter is provided for each phase of the three-phase AC, and the other ends of the fifth switching elements of the multi-level power converter for each of the three-phase phases are connected to the positive electrode of the DC voltage source, The other end of the sixth switching element is connected to the negative electrode of the DC voltage source, and the other end of the first switching means is connected in series between the positive and negative electrodes of the DC voltage source. Connected to the common connection point of the sensor and the fourth capacitor as a neutral point, and the common connection point of the second and third switching elements of the multi-phase power conversion unit of the three-phase each phase is Each output terminal, the current command value of the multi-level power conversion unit of each of the three-phase each phase, the voltage detection value and the current detection value of each output terminal of the multi-phase power conversion unit of each of the three-phase each input, a space vector From the current vector defined in the two-axis coordinate system area in the control, each of the three-phase each phase for each of the six vectors when each vector moves in the positive direction and the negative direction by the unit vector in each direction of the three phases. Predicting and calculating the current of the multi-level power converter, and selecting the vector having the smallest deviation between the predicted and calculated current and the current command value of each of the three-phase phases from among the six vectors. A vector selection unit for obtaining a command, and the capacitor voltages of the first capacitor and the second capacitor of the three-phase each phase when the vector determined by the phase voltage command is selected, based on the predicted calculation current And a capacitor voltage constant control unit of the multi-level power conversion unit for each of the three-phase phases to obtain a charge / discharge command that minimizes the deviation between the estimated capacitor voltage and the capacitor voltage command, Current detection value of each phase of level power conversion unit, voltage detection value of third and fourth capacitors, phase voltage command obtained by vector selection unit, and charge / discharge command obtained by constant capacitor voltage control unit Is input, the current flowing through the neutral point when the destination vector determined by the phase voltage command of the vector selection unit is selected is calculated, and the destination vector is calculated. DC voltage constant is selected to select a vector in which the deviation between the third capacitor voltage and the fourth capacitor voltage is eliminated, and to determine a charge / discharge command, and to output the determined charge / discharge command and the phase voltage command. A control unit; and a gate transition unit that selects a gate transition direction based on the charge / discharge command and the phase voltage command output from the DC voltage constant control unit and outputs a gate signal in accordance with the gate transition direction. The first to sixth switching elements and the first switching means based on the gate signal are provided with control means for outputting a plurality of voltage levels by on / off control.

  According to a third aspect of the present invention, there is provided a multilevel power converter control method comprising: a switching element series circuit in which first to fourth switching elements are sequentially connected in series; a first switching element side end of the switching element series circuit; First and second capacitors sequentially connected in series with the fourth switching element side end; a common connection point of the first switching element and the second switching element; a third switching element and a second switching element; First and second diodes sequentially connected in series with a common connection point of the four switching elements, and a fifth terminal having one end connected to the common connection point of the first capacitor and the first switching element. A sixth switching element having one end connected to a common connection point of the switching element and the second capacitor and the fourth switching element; A first switching means having one end connected to a common connection point of the first and second capacitors and capable of controlling in a reverse withstand voltage direction, and a common connection point of the first and second diodes A multi-level power converter configured by connecting a common connection point of the first and second capacitors is provided in each phase of a three-phase AC, and the fifth multi-level power converter of the three-phase each phase The other ends of the switching elements are connected to the positive electrode of the DC voltage source, the other ends of the sixth switching elements are connected to the negative electrode of the DC voltage source, and the other ends of the first switching means are connected to each other, Connected as a neutral point to a common connection point of a third capacitor and a fourth capacitor connected in series between the positive and negative electrodes of the DC voltage source, and the second of the multi-level power converters of the three-phase each phase And third A control method for a multi-level power converter configured by using a common connection point of switching elements as output terminals of three-phase each phase, wherein the first to sixth switching elements and the first switching means are turned on / off The vector selection unit of the control means for outputting a plurality of voltage levels by control includes a current command value of the multi-level power conversion unit of the three-phase each phase, a voltage at each output terminal of the multi-level voltage conversion unit of the three-phase each phase Using the detection value and current detection value as input, each vector moves in the positive and negative directions by a unit vector in each direction of each of the three phases from the current vector defined in the two-axis coordinate system area in space vector control. The current of the multi-level power conversion unit of each of the three phases is predicted and calculated for each of the six vectors, and the prediction calculation of the six vectors is performed. Obtaining a phase voltage command by selecting a vector having the smallest deviation between the measured current and the current command value of each of the three-phase phases, and a constant capacitor voltage of the multi-level power converter of each of the three-phase phases of the control means The controller estimates each capacitor voltage of the first capacitor and the second capacitor of each phase of the three phases when the vector determined by the phase voltage command is selected based on the predicted calculation current, A step of obtaining a charge / discharge command in which a deviation between the estimated capacitor voltage and the capacitor voltage command is minimized; and a DC voltage constant control unit of the control unit includes a current of each phase of the multi-level power conversion unit of the three-phase each phase Detection value, voltage detection value of the third and fourth capacitors, phase voltage command obtained by the vector selection unit, and charge / discharge finger obtained by the capacitor voltage constant control unit Is input, the current flowing through the neutral point when the destination vector determined by the phase voltage command of the vector selection unit is selected, and the third capacitor voltage and the third capacitor voltage of the destination vector are calculated. A step of selecting a vector that eliminates the deviation of the capacitor voltage of 4 and determining a charge / discharge command, and outputting the determined charge / discharge command and the phase voltage command; and a gate transition unit of the control means includes the DC voltage And a step of selecting a gate transition direction based on a charge / discharge command and a phase voltage command output from the constant control unit, and outputting a gate signal in accordance with the gate transition direction.

  According to the above configuration, the voltage control of the first and second capacitors of the multi-level power conversion unit for each of the three phases is performed between the estimated capacitor voltages of the first capacitor and the second capacitor and the capacitor voltage command value. The neutral voltage of the DC voltage between the positive and negative electrodes of the DC voltage source (the voltage at the common connection point of the third and fourth capacitors) is controlled by the capacitor voltage constant control unit based on the deviation. This is performed by the DC voltage constant control unit based on the deviation between the capacitor voltage and the fourth capacitor voltage. For this reason, the control of the capacitor voltage of each of the three phases and the control of the neutral point voltage of the DC voltage between the positive and negative electrodes of the DC voltage source are performed independently, and the control of both does not interfere.

  The multi-level power converter according to claim 2 is characterized in that in claim 1, the on / off control of the control means charges the first capacitor or the second capacitor at the time of phase voltage command of the same voltage level. A control mode for discharging and a control mode for discharging, and a control mode for simultaneously discharging the first capacitor and the second capacitor. When the phase voltage command changes, the capacitor voltage constant control unit of the conversion unit has a positive deviation between the first capacitor voltage and the second capacitor voltage and the capacitor voltage command immediately before the change. Determining a charge / discharge command to shift to a control mode for discharging at least one of the first capacitor and the second capacitor; When a deviation between the capacitor voltage and the second capacitor voltage and the capacitor voltage command is negative, a charge / discharge command for shifting to a control mode for charging at least one of the first capacitor and the second capacitor is determined. It is characterized by that.

  According to a fourth aspect of the present invention, in the control method for a multilevel power converter according to the third aspect, the on / off control of the control means is performed when the first capacitor or the second A control mode for charging the capacitor and a control mode for discharging, and a control mode for simultaneously discharging the first capacitor and the second capacitor, and a control mode for discharging simultaneously with the three-phase each phase. The step of obtaining the charge / discharge command by the constant capacitor voltage control unit of the multi-level power conversion unit includes the first capacitor voltage, the second capacitor voltage, and the capacitor voltage immediately before the change when the phase voltage command is changed. When the deviation from the command is positive, the control mode is set to discharge at least one of the first capacitor and the second capacitor. A charge / discharge command to be performed is determined, and when a deviation between the first capacitor voltage and the second capacitor voltage and the capacitor voltage command is negative, at least one of the first capacitor and the second capacitor is A charge / discharge command for shifting to a control mode for charging is determined.

  According to the above configuration, when the deviation between the first capacitor voltage, the second capacitor voltage, and the capacitor voltage command is positive (that is, when the capacitor voltage is larger than the capacitor voltage command), the discharge can be performed. Can be charged when is negative (ie when the capacitor voltage is less than the capacitor voltage command).

  As a result, the capacitor voltage of each of the three-phase capacitors (the first capacitor and the second capacitor) can be controlled to be constant, the pulsation of the capacitor voltage is reduced, and the desired phase voltage is easily output. Control performance is improved.

  In addition, since it has a control mode in which the first capacitor and the second capacitor are charged at the same time and a control mode in which the capacitor is discharged at the same time, the pulsation of the capacitor voltage is reduced, and the desired phase voltage is easily output. Performance is improved.

(1) According to the first to fourth aspects of the present invention, the control of the capacitor voltage of each phase of the three phases and the control of the neutral point voltage of the DC voltage source are performed independently, so the control of both interferes. There is nothing. This makes it possible to control the optimal output voltage waveform with little distortion. In addition, a multilevel power converter can be realized with a small number of elements, and costs can be reduced.
(2) According to the second and fourth aspects of the invention, the capacitor voltage of each of the three-phase capacitors (the first capacitor and the second capacitor) can be controlled to be constant, and the pulsation of the capacitor voltage The desired phase voltage is easily output and the control performance is improved.

1 is a circuit diagram of a five-level power converter according to an embodiment of the present invention. The control block diagram of the control means in one embodiment of this invention. The vector transition diagram of the vector defined in the biaxial coordinate system area | region in space vector control utilized in one embodiment of this invention. The gate transition diagram which shows the mode of the gate transition by the charging / discharging instruction | command of the capacitor voltage constant control part of one embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments. Hereinafter, an embodiment in which the present invention is applied to a 5-level power converter (5-level inverter) will be described.

As shown in FIG. 1, the five-level power converter according to the embodiment of the present invention includes the switching elements S1 to S10, the diodes D1 and D2, and the capacitors C1 and C2 to form a five-level power converter 100. The converter 100 is provided for three phases (100 U, 100 V, 100 W), and is connected to the Y connection with reference to the neutral point NP of the capacitors C _U and C _L divided by two with respect to the DC power source V _DC .

  In FIG. 1, the configuration of a U-phase five-level power converter 100U is as follows. A switching element series circuit is configured by sequentially connecting the first to fourth switching elements S1 to S4 in series. Between the both ends of this switching element series circuit, the 1st and 2nd capacitor | condenser C1, C2 is connected in series.

V _DC is a DC power source, and third and fourth capacitors C _U and C _L are connected in series between the positive and negative ends of the DC power source V _DC . Switching elements S5 and S6 constituting the fifth switching element of the present invention are connected in series between the positive terminal of the DC power source V _DC and the common connection point of the switching element S1 and the capacitor C1. Switching elements S7 and S8 constituting the sixth switching element of the present invention are connected in series between the common connection point of the switching element S4 and the capacitor C2 and the negative end of the DC power source V _DC .

  Between the common connection point of the switching elements S1 and S2 and the common connection point of the switching elements S3 and S4, diodes D1 and D2 having the polarities shown are connected in series.

A common connection point of the diodes D1 and D2 is connected to a common connection point NP ′ (Floating NP; floating midpoint) of the capacitors C1 and C2. One end of a first switching means comprising switching elements S9 and S10 connected in series in opposite withstand voltage directions is connected to the floating midpoint NP ′, and the other end of the first switching means is connected to a capacitor C _U. And C _L are connected to a common connection point (neutral point NP).

  The common connection point of the switching elements S2 and S3 is a U-phase output terminal U.

  V-phase and W-phase 5-level power converters 100V and 100W are also configured similarly to the U-phase 5-level power converter 100U.

  The first switching means is not limited to the switching elements S9 and S10, and may be constituted by one bidirectional switch that can be controlled in the reverse withstand voltage direction.

  The switching elements S1 to S10 are composed of, for example, IGBTs as switching elements.

  The fifth switching element uses the two switching elements S5 and S6 in consideration of the withstand voltage. However, the fifth switching element is not limited to this and may be composed of one switching element having a double withstand voltage.

  The sixth switching element uses two switching elements S7 and S8 in consideration of the withstand voltage. However, the sixth switching element is not limited to this, and may be composed of one switching element having a double withstand voltage.

  The switching elements S1 to S10 of each phase are on / off controlled by a control unit (control means) (not shown) according to a switching pattern for outputting a voltage of five levels, and as a result, U phase, V phase, W phase A five-level voltage is output between each of the output terminals U, V, W and the neutral point NP.

The power source voltage of the DC power source V _DC may be fixed or variable. Moreover, AC power source may be a DC voltage obtained by rectifying an, the following description will be in the DC power supply V _DC.

In the above structure, when a voltage, for example, 4E of the DC power supply V _DC, capacitor C _U, the C _L is assumed that the voltage of 2E are respectively charged.

  The on / off of the switching elements S1 to S10 is controlled according to a switching pattern having mode 1 to mode 9 shown in Table 1, for example.

Table 1 shows the voltages (V _LN ) output to the output terminals U, V, and W of each phase according to the on / off modes 1 to 9 (indicated as Mode 1 to 9 in Table 1) of the switching elements S1 to S10. ) And whether the capacitors C1 and C2 are charged or discharged.

In Table 1, the charge / discharge state represents the charge / discharge state of the capacitors C1, C2 when the currents output from the output terminals U, V, W are positive and negative, + is charge,-is discharge, and 0 is charge / discharge. It indicates no, 1 neutral point current I _M represents the case with the current flowing from the neutral point NP to the floating midpoint NP', 0 represents the case of no.

When the voltage of the DC power source V _DC is 4E and the voltages of the capacitors C _U and C _L are 2E, the voltages between the output terminals U, V, W and the neutral point NP are 2E, E, 0, −E, − 5E voltage of 2E can be output.

Here, taking the U-phase five-level power converter 100U as an example, the path of the current I _L between the modes 1 to 9 of the switching pattern in Table 1 and the output terminal U and the neutral point NP (I _L > 0) Will be described below.

In the following description, the end of the positive electrode side of the DC power source V _DC at capacitor C _U P, expressed as N the end of the negative electrode side of the DC power source V _DC at capacitor C _L.

<Mode 1>
Switching elements S3, S4, S7 to S9 are each turned off, the switching element S1, S2, S5, S6, S10 are each turned on, current I _{L, NP → C U → P →} S5 → S6 → S1 → S2 → Output It flows through the path of terminal U. The voltage between the output terminal U and the neutral point NP is 2E. In this mode 1, the capacitors C1 and C2 are not charged / discharged.

<Mode 2>
The switching elements S1, S4, S7 to S9 are turned off, the switching elements S2, S3, S5, S6, and S10 are turned on, and the current I _L is NP → C _U → P → S5 → S6 → C1 → D1 → S2. → Flows along the path of the output terminal U. The voltage between the output terminal U and the neutral point NP is E. In this mode 2, the capacitor C1 is charged.

<Mode 3>
The switching elements S3 to S8 are turned off, the switching elements S1, S2, S9, and S10 are turned on, and the current I _L flows through a path of NP → S10 → S9 → C1 → S1 → S2 → output terminal U. The voltage between the output terminal U and the neutral point NP is E. In this mode 3, the capacitor C1 is discharged. Further, a neutral point current I _M flows between the neutral point NP and the floating neutral point NP ′.

<Mode 4>
Switching elements S1, S2, S7 to S8 are turned off, switching elements S3 to S6 and S10 are turned on, and current I _L is NP → C _U → S5 → S6 → C1 → C2 → S4 → S3 → output terminal U It flows in the route. The voltage between the output terminal U and the neutral point NP is zero. In this mode 4, the capacitors C1 and C2 are charged.

<Mode 5>
The switching elements S1, S4 to S8 are turned off, the switching elements S2, S3, S9, and S10 are turned on, and the current I _L flows through a path of NP → S10 → S9 → D1 → S2 → output terminal U. The voltage between the output terminal U and the neutral point NP is zero. In mode 5, there is no charge / discharge of the capacitors C1 and C2. Further, a neutral point current I _M flows between the neutral point NP and the floating neutral point NP ′.

<Mode 6>
The switching elements S3 to S6, S10 are turned off, the switching elements S1, S2, S7 to S9 are turned on, and the current I _L is output from NP → C _L → N → S8 → S7 → C2 → C1 → S1 → S2 → output. It flows through the path of terminal U. The voltage between the output terminal U and the neutral point NP is zero. In this mode 6, the capacitors C1 and C2 are discharged.

<Mode 7>
The switching elements S1, S2, S5, S6 to S8 are turned off, the switching elements S3, S4, S9, and S10 are turned on, and the current I _L is NP → S10 → S9 → C2 → S4 → S3 → output terminal U It flows along the route. The voltage between the output terminal U and the neutral point NP is -E. In this mode 7, the capacitor C2 is charged. Further, a neutral point current I _M flows between the neutral point NP and the floating neutral point NP ′.

<Mode 8>
The switching elements S1, S4 to S6, S10 are turned off, the switching elements S2, S3, S7 to S9 are turned on, and the current I _L is NP → C _L → S8 → S7 → C2 → D1 → S2 → output terminal U It flows in the route. The voltage between the output terminal U and the neutral point NP is -E. In this mode 8, the capacitor C2 is discharged.

<Mode 9>
The switching elements S1, S2, S5, S6, S10 are turned off, the switching elements S3, S4, S7 to S9 are turned on, and the current I _L is NP → C _L → S8 → S7 → S4 → S3 → output terminal U It flows in the route. The voltage between the output terminal U and the neutral point NP is −2E. In this mode 9, there is no charge / discharge of the capacitors C1 and C2.

The current paths of the modes 1 to 9, the charge / discharge states of the capacitors C 1 and C 2, and the presence / absence of the neutral point current I _M flowing out from the neutral point NP are determined by the V-phase 5-level power conversion unit 100 V and the W-phase 5 The same applies to the level power converter 100W.

In Table 1, since the output voltages of mode 2 and mode 3 are both + E and current flows through the capacitor C1, the voltage of the capacitor C1 can be adjusted. In mode 2, the capacitor C1 is charged when the current is positive (I _L > 0), and the capacitor C1 is discharged when the current is negative (I _L <0). In mode 3, the capacitor C1 is discharged when the current is positive, and the capacitor C1 is charged when the current is negative. By alternately selecting mode 2 and mode 3 via mode 1 or mode 5, the voltage of capacitor C1 can be kept constant.

  Since the output voltages of mode 7 and mode 8 are both -E, and a current flows through the capacitor C2, the voltage of the capacitor C2 can be adjusted. In mode 7, C2 is charged when the current is positive, and C2 is discharged when the current is negative. In mode 8, C2 is discharged when the current is positive, and C2 is charged when the current is negative. By alternately selecting the mode 7 and the mode 8 via the mode 5 or the mode 9, the voltage of the capacitor C2 can be kept constant.

  In this embodiment, as shown in mode 4 and mode 6 of Table 1, there are a control mode in which the capacitors C1 and C2 are charged simultaneously and a control mode in which the capacitors C1 and C2 are discharged simultaneously. This reduces the pulsation of the voltages of the capacitors C1 and C2, makes it easier to output the desired phase voltage, and improves the control performance.

In mode 3, mode 5 and mode 7, the neutral point current I _M flows out from the neutral point NP of the capacitors C _U and C _L connected in series between the positive and negative terminals of the DC power source V _DC. The balance between the voltages of the capacitors C _U and C _L is lost.

A control (Vdc voltage constant control) for improving the balance of the voltages of the capacitors C _U and C _L on the DC power source V _DC side to keep the voltage at the neutral point NP constant, and the capacitors C1, FIG. 2 shows an embodiment of a control unit (control means of the present invention) that executes control for maintaining C2 constant (Vc voltage constant control) without interfering with each other.

Control unit of FIG. 2, by using the spatial vector modulation, control of the three-phase AC component, the voltage constant control of the capacitor C _U and C _L, performs the three-phase phase of the capacitor C1 C2 the voltage control in the independent A vector selection unit 201 based on a current prediction method, a Vc voltage constant control unit (capacitor voltage constant control unit of the present invention) 202 for controlling the voltages of the capacitors C1 and C2 to a desired voltage, capacitors C _U and C The circuit includes a Vdc voltage constant control unit (a DC voltage constant control unit of the present invention) 203 that keeps the _L voltage constant, and a gate transition unit 204.

The vector selection unit 201 outputs U, V, W phase current command values I _uRef , I _vRef , I _wRef and U, V, W phase detected voltage values V _uac , V _vac , V _wac or UV, UW, WU. The line voltage detection values and U, V, and W phase current detection values I _uinv , I _vinv , and I _winv are input.

The vector selection unit 201 has six states when moving from the current vector defined in the biaxial coordinate system area in the space vector control to the unit vector in the u, v, and w directions in the plus and minus directions, respectively. The current of the five-level power converters 100U, 100V, 100W of each of the three-phase phases is predicted for each of the vectors, and the current command value I of each of the three-phase phases of the predicted current among the six vectors is calculated. _A vector having the smallest deviation from _URef , I _vRef , and I _wRef is selected to obtain phase voltage commands V _uN , V _vN , and V _wN (V _{LN in} Table 1).

  FIG. 3 shows the transition of the vector selected by the vector selection unit 201. From the current vector Vn, the unit vector in the u, v, and w directions in the α-β space is added in the plus direction (right direction in the figure). ) And the three previous state vectors moved in the negative direction (left direction in the figure).

  The current prediction method executed by the vector selection unit 201 is a kind of space vector control, and the following inverter calculated by the equivalent circuit of the five-level power converter of FIG. This is a method of moving to a position where current error is reduced by predicting and calculating an inverter value several steps ahead from one step in the control calculation cycle from the current estimation formula (formula (1)).

Iinv = L / s (Vinv−Vac) (1)
L: inductance of filter and motor s: Laplace operator Vinv: terminal voltage of the inverter, voltage at terminals u, v, w in FIG. 1 Vac: V _uac , V _vac , V _wac
Processing operations when the vector selection unit 201 selects an optimal vector from the six vectors are input signals I _URef , I _vRef , I _wRef , V _uac , V _vac , V _wac , I _uinv , I _vinv , I _{Using winv} , an inverter current estimation formula Iinv = L / s (Vinv−Vac) calculated from an equivalent circuit (an equivalent model of the circuit of FIG. 1) is used to predict and calculate the inverter current for each of the six state vectors. The vector having the smallest difference from the current command value I _Ref is selected from the six vectors, and this is output as the phase voltage command V _LN (V _UN , V _VN , V _WN ).

  Further, when the selected vector moves to the right from Vn (A, b, c) in FIG. 3 according to the switching direction, for example, (A + 1, B, C) and (A, B-1, C-1) Two states in which positions in the αβ space are equivalent are shown.

The Vc voltage constant control unit 202 converts the capacitor voltages of the capacitors C1 and C2 when the vector determined by the phase voltage command V _LN (V _UN , V _VN , V _WN ) is selected into the predicted current. The charge / discharge command GateDir having the smallest deviation between the estimated capacitor voltage and the capacitor voltage command (a voltage E that is ¼ of the DC power source V _{DC in} FIG. 1) is obtained based on FIG. The relationship between the discharge command GateDir, the phase voltage command V _LN and the gate transition is shown. The circled numbers in FIG. 4 correspond to modes 1 to 9 in Table 1.

In the constant Vc voltage control unit 202, every time the vector selection unit 201 _{obtains the} phase voltage command V _LN , it is necessary to lower the voltage when the polarity of the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is positive. Therefore, when the current polarity is positive (I _L > 0), the charge / discharge command is GateDir = n in FIG. 4, and when the current polarity is negative (I _L <0), the charge / discharge command is set to GateDir in FIG. = P.

Similarly, when the polarity of the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is negative, it is necessary to increase the voltage. Therefore, when the polarity of the current is positive (I _L > 0), the charge / discharge command 4 is set to GateDir = p, and when the current polarity is negative (I _L <0), the charge / discharge command is set to GateDir = n in FIG.

This process is performed regardless of whether the phase voltage command after the state change is in a state where the capacitors C1 and C2 can be controlled (V _LN = E, 0, -E). This is because the charge / discharge command GateDir is a variable independent of the phase voltage command V _LN .

The charge / discharge command GateDir is a flag for performing constant voltage control of the capacitors C1 and C2, and when there are two destinations for the phase voltage command V _LN when the gate state transitions, the charge / discharge command GateDir Gate transition is performed according to the direction.

Next, a specific example of the operation performed by the Vc voltage constant control unit 202 when the phase voltage command V _LN changes will be described with reference to FIG. 4 and Table 1.

<When phase voltage command V _LN changes from 2E to E during control in mode 1>
In this case, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is positive, the mode 3 in the arrow direction of the charge / discharge command GateDir = n is set when the current polarity is positive (I _L > 0). When selected, the capacitor C1 is discharged, and when the current polarity is negative (I _L <0), the capacitor C1 is discharged by selecting the mode 2 in the arrow direction of the charge / discharge command GateDir = p. As a result, the voltage of the capacitor C1 can be lowered.

Further, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is negative, when the current polarity is positive (I _L > 0), the mode 2 in the arrow direction of the charge / discharge command GateDir = p is selected. To charge the capacitor C1, and when the current polarity is negative (I _L <0), the capacitor C1 is charged by selecting the mode 3 in the arrow direction of the charge / discharge command GateDir = n. As a result, the voltage of the capacitor C1 can be increased.

<When phase voltage command V _LN changes from E to 0 during control in mode 2>
In this case, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is positive, when the current polarity is positive (I _L > 0), the mode 5 in the arrow direction of the charge / discharge command GateDir = n is set. When the capacitor C1 is not selected and the current polarity is negative (I _L <0), the mode 4 in the arrow direction of the charge / discharge command GateDir = p is selected to discharge not only the capacitor C1 but also the capacitor C2. As a result, the voltages of the capacitors C1 and C2 can be lowered.

If the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is negative, the mode 4 in the arrow direction of the charge / discharge command GateDir = p is selected when the current polarity is positive (I _L > 0). Then, not only the capacitor C1 but also the capacitor C2 is charged, and when the current polarity is negative (I _L <0), the mode 5 in the arrow direction of the charge / discharge command GateDir = n is selected to stop the discharge of the capacitor C1. As a result, the voltage of the capacitor C1 can be increased.

<When phase voltage command V _LN changes from E to 0 during control in mode 3>
In this case, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is positive, the mode 6 in the arrow direction of the charge / discharge command GateDir = n is set when the current polarity is positive (I _L > 0). The capacitor C2 is discharged as well as the capacitor C1, and when the current polarity is negative (I _L <0), the charging of the capacitor C1 is stopped by selecting the mode 5 in the arrow direction of the charge / discharge command GateDir = p. As a result, the voltage of the capacitor C1 can be lowered.

Further, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is negative, when the current polarity is positive (I _L > 0), the mode 5 in the arrow direction of the charge / discharge command GateDir = p is selected. Then, the discharge of the capacitor C1 is stopped, and when the current polarity is negative (I _L <0), the mode 6 in the arrow direction of the charge / discharge command GateDir = n is selected to charge not only the capacitor C1 but also the capacitor C2. As a result, the voltages of the capacitors C1 and C2 can be increased.

<When phase voltage command V _LN changes from 0 to E during control in mode 5>
In this case, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is positive, the mode 3 in the arrow direction of the charge / discharge command GateDir = n is set when the current polarity is positive (I _L > 0). When selected, the capacitor C1 is discharged, and when the current polarity is negative (I _L <0), the capacitor C1 is discharged by selecting the mode 2 in the arrow direction of the charge / discharge command GateDir = p. As a result, the voltage of the capacitor C1 can be lowered.

Further, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is negative, when the current polarity is positive (I _L > 0), the mode 2 in the arrow direction of the charge / discharge command GateDir = p is selected. To charge the capacitor C1, and when the current polarity is negative (I _L <0), the capacitor C1 is charged by selecting the mode 3 in the arrow direction of the charge / discharge command GateDir = n. As a result, the voltage of the capacitor C1 can be increased.

<When phase voltage command V _LN changes from 0 to -E during mode 1 control>
In this case, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is positive, the mode 8 in the arrow direction of the charge / discharge command GateDir = n is set when the current polarity is positive (I _L > 0). The capacitor C2 is selected and discharged, and when the current polarity is negative (I _L <0), the capacitor C2 is discharged by selecting the mode 7 in the arrow direction of the charge / discharge command GateDir = p. As a result, the voltage of the capacitor C2 can be lowered.

Further, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is negative, when the current polarity is positive (I _L > 0), the mode 7 in the arrow direction of the charge / discharge command GateDir = p is selected. To charge the capacitor C2, and when the current polarity is negative (I _L <0), the capacitor C2 is charged by selecting the mode 8 in the arrow direction of the charge / discharge command GateDir = n. As a result, the voltage of the capacitor C2 can be increased.

<When phase voltage command V _LN changes from -E to 0 during control in mode 7>
In this case, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is positive, when the current polarity is positive (I _L > 0), the mode 5 in the arrow direction of the charge / discharge command GateDir = n is set. When the current polarity is negative (I _L <0), the mode C4 in the direction of the arrow of the charge / discharge command GateDir = p is selected to discharge not only the capacitor C2 but also the capacitor C1. As a result, the voltages of the capacitors C1 and C2 can be lowered.

If the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is negative, the mode 4 in the arrow direction of the charge / discharge command GateDir = p is selected when the current polarity is positive (I _L > 0). Then, not only the capacitor C2 but also the capacitor C1 is charged, and when the current polarity is negative (I _L <0), the mode 5 in the arrow direction of the charge / discharge command GateDir = n is selected to stop the discharge of the capacitor C2. As a result, the voltages of the capacitors C1 and C2 can be increased.

<When phase voltage command V _LN changes from -E to 0 during control in mode 8>
In this case, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is positive, the mode 6 in the arrow direction of the charge / discharge command GateDir = n is set when the current polarity is positive (I _L > 0). The capacitor C1 is discharged as well as the capacitor C2, and when the current polarity is negative (I _L <0), the charging of the capacitor C2 is stopped by selecting the mode 5 in the arrow direction of the charge / discharge command GateDir = p. As a result, the voltages of the capacitors C1 and C2 can be lowered.

Further, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is negative, when the current polarity is positive (I _L > 0), the mode 5 in the arrow direction of the charge / discharge command GateDir = p is selected. Then, discharging of the capacitor C2 is stopped, and when the current polarity is negative (I _L <0), the mode 6 in the arrow direction of the charge / discharge command GateDir = n is selected to charge not only the capacitor C2 but also the capacitor C1. As a result, the voltages of the capacitors C1 and C2 can be increased.

<When phase voltage command V _LN changes from -2E to -E during control in mode 9>
In this case, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is positive, the mode 8 in the arrow direction of the charge / discharge command GateDir = n is set when the current polarity is positive (I _L > 0). The capacitor C2 is selected and discharged, and when the current polarity is negative (I _L <0), the capacitor C2 is discharged by selecting the mode 7 in the arrow direction of the charge / discharge command GateDir = p. As a result, the voltage of the capacitor C2 can be lowered.

Further, if the deviation between the estimated capacitor voltage of the capacitors C1 and C2 and the capacitor voltage command is negative, when the current polarity is positive (I _L > 0), the mode 7 in the arrow direction of the charge / discharge command GateDir = p is selected. To charge the capacitor C2, and when the current polarity is negative (I _L <0), the capacitor C2 is charged by selecting the mode 8 in the arrow direction of the charge / discharge command GateDir = n. As a result, the voltage of the capacitor C2 can be increased.

The Vdc voltage constant control unit 203 includes current detection values I _uinv , I _vinv , I _winv of each phase of the five-level power conversion units 100U, 100V, 100W of the three phases, positive and negative terminals of the DC power source V _DC The voltage detection values V _CU , V _{CL of} capacitors C _U , C _L connected in series between them, the phase voltage command V _LN (V _UN , V _VN , V _WN ) obtained by the vector selector 201 and the Vc voltage The neutral point current flowing through the neutral point NP when the charge / discharge command GateDir obtained by the constant control unit 202 is input and the destination vector determined by the phase voltage command V _LN of the vector selection unit 201 is selected. I _M is calculated, a charge / discharge command is determined by selecting a vector in which the deviation between V _CU and V _CL is eliminated from the destination vectors, and the determined charge / discharge command GateDir and the phase voltage command V _{UN are determined.} , V _VN And it outputs the V _WN.

The voltages V _CU and V _CL of the capacitors C _U and C _L are out of balance when the neutral point current I _M flows from the neutral point NP (that is, in the case of modes 3, 5, and 7 in Table 1) (I _M is a positive when V _CU large, negative if V _CL is large) Therefore, by always selecting the direction neutral point current I _M to improve the balance of the voltage, the balance of the V _CU and V _CL Can keep.

Therefore, the Vdc voltage constant control unit 203 calculates a neutral point current I _M and selects a vector that eliminates the deviation between V _CU and V _CL .

The gate transition unit 204 performs the following operation according to the phase voltage commands V _uN , V _vN , V _{wN of} the three phases obtained by the Vdc voltage constant control unit 203 and the Vc voltage constant control unit 202 and the charge / discharge commands GateDiru, GateDirv, GateDirw. The direction of transition is selected, and a gate signal matching that is output.

  When the state transitions, a dead time state is passed, and after the transition to each state, the movement is restricted so that the transition to the next state can be made only after the set minimum on-time has elapsed.

100U, 100V, 100W ... 5-level power conversion unit 201 ... vector selection unit 202 ... Vc voltage constant control unit 203 ... Vdc voltage constant control unit 204 ... gate transition unit S1-S10 ... switching element V _DC ... DC power supply C1, C2, C _U , C _L ... capacitor D1, D2 ... diode

Claims (4)

In a multi-level power converter that outputs an AC voltage obtained by converting a DC voltage between the positive and negative electrodes of a DC voltage source into a plurality of voltage levels,
A switching element series circuit in which the first to fourth switching elements are sequentially connected in series, and a first switching element side circuit of the switching element series circuit that is sequentially connected in series between the first switching element side end and the fourth switching element side end. The first and second capacitors, the common connection point of the first switching element and the second switching element, and the common connection point of the third switching element and the fourth switching element are sequentially connected in series. The first and second diodes, the fifth switching element having one end connected to a common connection point of the first capacitor and the first switching element, and the common of the second capacitor and the fourth switching element One end is connected to a common connection point of the sixth switching element, one end of which is connected to the connection point, and the first and second capacitors. And a first switching means that can be controlled in directions opposite to each other with a withstand voltage, and is configured by connecting a common connection point of the first and second diodes and a common connection point of the first and second capacitors. Multi-level power converters are provided for each phase of the three-phase AC,
The other end of the fifth switching element of the multi-phase power converter for each of the three phases is connected to the positive electrode of the DC voltage source, and the other end of the sixth switching element is connected to the DC voltage source. Connect to the negative electrode, and connect the other ends of the first switching means as a neutral point to the common connection point of the third capacitor and the fourth capacitor connected in series between the positive and negative electrodes of the DC voltage source. , The common connection point of the second and third switching elements of the multi-phase power conversion unit of each of the three-phase each phase as an output terminal of each of the three-phase each phase,
Two-axis coordinates in space vector control using as input the current command value of the multi-level power conversion unit for each of the three-phase phases and the voltage detection value and current detection value of each output terminal of the multi-level power conversion unit for each of the three phases A multi-level power conversion unit for each of the three phases for each of the six vectors when the respective vectors move in the positive direction and the negative direction for the unit vector in each direction of the three phases from the current vector defined in the system region A vector selection unit that obtains a phase voltage command by selecting a vector having the smallest deviation between the predicted current and the current command value of each of the three phases among the six vectors; When the vector determined by the phase voltage command is selected, the predicted voltage of each capacitor voltage of the first capacitor and the second capacitor of the three-phase each phase is calculated. Based on the capacitor voltage constant control unit of the multi-level power conversion unit of each of the three-phase each phase for obtaining a charge / discharge command that minimizes the deviation between the estimated capacitor voltage and the capacitor voltage command; and Current detection value of each phase of the multi-level power conversion unit, voltage detection value of the third and fourth capacitors, phase voltage command obtained by the vector selection unit, and charging / discharging obtained by the capacitor voltage constant control unit An instruction is input, a current flowing through the neutral point when the destination vector determined by the phase voltage command of the vector selection unit is selected, and the third capacitor voltage of the destination vector is calculated. A DC voltage for selecting a vector that eliminates the deviation of the fourth capacitor voltage, determining a charge / discharge command, and outputting the determined charge / discharge command and the phase voltage command. A constant control unit, and a gate transition unit that selects a gate transition direction based on the charge / discharge command and the phase voltage command output from the DC voltage constant control unit and outputs a gate signal in accordance with the gate transition direction. And a control means for outputting a plurality of voltage levels by on / off control of the first to sixth switching elements and the first switching means based on the gate signal,
A multi-level power converter characterized by that. The on / off control of the control means has a control mode in which the first capacitor or the second capacitor is charged and a control mode in which the first capacitor or the second capacitor is discharged at the time of a phase voltage command at the same voltage level. And a control mode for simultaneously discharging the second capacitor and a control mode for discharging simultaneously.
When the phase voltage command changes, the capacitor voltage constant control unit of the multi-phase power conversion unit for each of the three phases has the first capacitor voltage, the second capacitor voltage, and the capacitor voltage command immediately before the change. A charge / discharge command to shift to a control mode for discharging at least one of the first capacitor and the second capacitor is determined, and the first capacitor voltage and the second capacitor The charge / discharge command for shifting to a control mode for charging at least one of the first capacitor and the second capacitor when the deviation between the voltage and the capacitor voltage command is negative is determined. 2. The multilevel power converter according to 1. A switching element series circuit in which the first to fourth switching elements are sequentially connected in series, and a first switching element side circuit of the switching element series circuit that is sequentially connected in series between the first switching element side end and the fourth switching element side end. The first and second capacitors, the common connection point of the first switching element and the second switching element, and the common connection point of the third switching element and the fourth switching element are sequentially connected in series. The first and second diodes, the fifth switching element having one end connected to a common connection point of the first capacitor and the first switching element, and the common of the second capacitor and the fourth switching element One end is connected to a common connection point of the sixth switching element, one end of which is connected to the connection point, and the first and second capacitors. And a first switching means that can be controlled in directions opposite to each other with a withstand voltage, and is configured by connecting a common connection point of the first and second diodes and a common connection point of the first and second capacitors. Multi-level power converters are provided for each phase of the three-phase AC,
The other ends of the fifth switching elements of the multi-phase power converter for each of the three phases are connected to the positive electrode of the DC voltage source, and the other ends of the sixth switching elements are connected to the negative electrode of the DC voltage source. And the other ends of the first switching means are connected as a neutral point to a common connection point of a third capacitor and a fourth capacitor connected in series between the positive and negative electrodes of the DC voltage source, A control method of a multi-level power converter configured such that a common connection point of the second and third switching elements of the multi-phase power converter of each of the three-phase phases is used as each output terminal of each of the three-phase phases. ,
The vector selection unit of the control unit that outputs a plurality of voltage levels by on / off control of the first to sixth switching elements and the first switching unit is a current command of the multi-level power conversion unit of the three-phase each phase Value, a voltage detection value and a current detection value at each output end of the multi-phase voltage conversion unit of each of the three phases, and from the current vector defined in the two-axis coordinate system region in the space vector control, Predicting and calculating the current of the multi-level power conversion unit for each of the three phases for each of the six vectors when the vectors move in the positive direction and the negative direction by a unit vector in each direction of the phase, Among them, a step of obtaining a phase voltage command by selecting a vector having the smallest deviation between the predicted current and the current command value of each of the three-phase phases,
The first and second capacitors of the three-phase each phase when the constant voltage control unit of the multi-level power conversion unit of the three-phase each phase of the control unit selects the vector determined by the phase voltage command. Estimating each capacitor voltage of the capacitor based on the predicted and calculated current, obtaining a charge / discharge command with a minimum deviation between the estimated capacitor voltage and the capacitor voltage command;
The DC voltage constant control unit of the control means is obtained by the current detection value of each phase of the multi-level power conversion unit of the three-phase each phase, the voltage detection value of the third and fourth capacitors, and the vector selection unit. The current flowing through the neutral point when the phase vector command and the charge / discharge command obtained by the constant capacitor voltage control unit are input and the destination vector determined by the phase voltage command of the vector selection unit is selected. And calculating a charge / discharge command by selecting a vector in which a deviation between the third capacitor voltage and the fourth capacitor voltage is eliminated from the destination vector, and determining the determined charge / discharge command and the phase voltage command. A step of outputting
A step of selecting a gate transition direction based on a charge / discharge command and a phase voltage command output from the DC voltage constant control unit, and outputting a gate signal in accordance with the gate transition direction; A control method for a multi-level power converter, comprising: The on / off control of the control means has a control mode in which the first capacitor or the second capacitor is charged and a control mode in which the first capacitor or the second capacitor is discharged at the time of a phase voltage command at the same voltage level. And a control mode for simultaneously discharging the second capacitor and a control mode for discharging simultaneously.
The step of obtaining the charge / discharge command by the capacitor voltage constant control unit of the multi-level power conversion unit for each of the three-phase phases includes the first capacitor voltage, the second capacitor voltage immediately before the change, When the deviation between the capacitor voltage and the capacitor voltage command is positive, a charge / discharge command for shifting to a control mode for discharging at least one of the first capacitor and the second capacitor is determined, and the first When a deviation between the capacitor voltage and the second capacitor voltage and the capacitor voltage command is negative, a charge / discharge command for shifting to a control mode for charging at least one of the first capacitor and the second capacitor is determined. The control method of a multilevel power converter according to claim 3.

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