JP2013251587A - Capacitive load bias circuit - Google Patents

Capacitive load bias circuit Download PDF

Info

Publication number
JP2013251587A
JP2013251587A JP2012122649A JP2012122649A JP2013251587A JP 2013251587 A JP2013251587 A JP 2013251587A JP 2012122649 A JP2012122649 A JP 2012122649A JP 2012122649 A JP2012122649 A JP 2012122649A JP 2013251587 A JP2013251587 A JP 2013251587A
Authority
JP
Japan
Prior art keywords
low
pass filter
capacitive load
diode
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012122649A
Other languages
Japanese (ja)
Other versions
JP5970241B2 (en
Inventor
Ryuhei Nemoto
竜平 根本
Tadahiko Kuramochi
忠彦 倉持
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP2012122649A priority Critical patent/JP5970241B2/en
Publication of JP2013251587A publication Critical patent/JP2013251587A/en
Application granted granted Critical
Publication of JP5970241B2 publication Critical patent/JP5970241B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Electrostatic, Electromagnetic, Magneto- Strictive, And Variable-Resistance Transducers (AREA)
  • Circuit For Audible Band Transducer (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the cutoff frequency of a low-pass filter from changing even when a leakage current flows into an overvoltage protection element.SOLUTION: A capacitive load bias circuit comprises: a voltage output circuit 11 which outputs a bias voltage; an overvoltage protection element 12 which is connected between the output side of the voltage output circuit 11 and ground; and a low-pass filter 13 which includes a diode D1 having its anode connected to output side of the voltage output circuit 11 and a capacitor C1 connected between the cathode of the diode D1 and ground. A common connection point between the cathode of the diode D1 and the capacitor C1 of the low-pass filter 13 is connected to an output terminal 14 having a capacitive load connected thereto.

Description

本発明は、ＭＥＭＳマイクロフォン、タッチパネル等の容量性負荷にバイアス電圧を供給するための容量性負荷バイアス回路に関する。   The present invention relates to a capacitive load bias circuit for supplying a bias voltage to a capacitive load such as a MEMS microphone or a touch panel.

ＭＥＭＳマイクロフォンにバイアス電圧を供給する際は、そのバイアス電圧は音声帯域で低ノイズでなければならず、そのために一般的にはバイアス電圧の供給路にローパスフィルタが挿入される（例えば、特許文献１）。そして、そのローパスフィルタのカットオフ周波数は音声帯域の信号成分を完全にカットする必要から数Ｈｚに設定される。このカットオフ周波数を実現するためには、そのローパスフィルタを半導体集積回路に内蔵する場合は、ローパスフィルタを構成するキャパシタの容量値は最大でもｐＦのオーダーにならざるを得ないので、抵抗の値はＧΩのオーダーにする必要がある。そこで、この高い抵抗値を実現するために、通常の抵抗ではなく、ダイオードの平衡状態の抵抗が使用される。   When supplying a bias voltage to a MEMS microphone, the bias voltage must be low noise in the voice band, and for this purpose, a low-pass filter is generally inserted in the bias voltage supply path (for example, Patent Document 1). ). The cut-off frequency of the low-pass filter is set to several Hz because it is necessary to completely cut the signal component in the audio band. In order to realize this cut-off frequency, when the low-pass filter is built in the semiconductor integrated circuit, the capacitance value of the capacitor constituting the low-pass filter must be on the order of pF at the maximum. Needs to be on the order of GΩ. Therefore, in order to realize this high resistance value, not a normal resistance but a resistance in a balanced state of a diode is used.

図４に従来の容量性負荷バイアス回路１０Ｄを示す。１１はチャージポンプ等で構成された一定値のバイアス電圧を出力する電圧出力回路、１３は抵抗としてのダイオードＤ１とキャパシタＣ１とからなるカットオフ周波数が数Ｈｚのローパスフィルタ、１２は１又は複数個を並列接続したＭＯＳトランジスタ等からなるＥＳＤ（静電気放電）対策用の過電圧保護素子、１４は出力端子、１５は出力端子１４に接続されたＭＥＭＳマイクロフォン、１６は増幅器、Ｒ２は抵抗である。ダイオードＤ１は、図５に示すように、容量性負荷バイアス回路１０Ｄの通常動作時に流れる小電流で高抵抗を示すので、この抵抗をフィルタ抵抗として使用している。   FIG. 4 shows a conventional capacitive load bias circuit 10D. Reference numeral 11 denotes a voltage output circuit configured to output a bias voltage having a constant value constituted by a charge pump or the like. Reference numeral 13 denotes a low-pass filter having a cutoff frequency of several Hz composed of a diode D1 as a resistor and a capacitor C1. An overvoltage protection element for ESD (electrostatic discharge) countermeasures composed of MOS transistors connected in parallel, 14 is an output terminal, 15 is a MEMS microphone connected to the output terminal 14, 16 is an amplifier, and R2 is a resistor. As shown in FIG. 5, the diode D1 exhibits a high resistance with a small current that flows during the normal operation of the capacitive load bias circuit 10D, and this resistance is used as a filter resistance.

特開２００８−１５３９８１号公報JP 2008-153981 A

ところが、過電圧保護素子１２にはリーク電流が通常流れ、そのリーク電流は過電圧保護素子１２のＥＳＤ耐性が大きいほど大きくなる。この大きなリーク電流は電圧出力回路１１からローパスフィルタ１３のダイオードＤ１を流れるので、図５に示すように、そのダイオードＤ１の抵抗値が小さくなって、ローパスフィルタ１３のカットオフ周波数が高くなり、出力端子１４に電圧出力回路１１で発生した音声帯域のノイズ成分が出力し、ＭＥＭＳマイクロフォン１５の特性を悪化させる恐れがある。   However, a leakage current normally flows through the overvoltage protection element 12, and the leakage current increases as the ESD resistance of the overvoltage protection element 12 increases. Since this large leak current flows from the voltage output circuit 11 to the diode D1 of the low-pass filter 13, as shown in FIG. 5, the resistance value of the diode D1 decreases, the cutoff frequency of the low-pass filter 13 increases, and the output There is a possibility that the noise component of the voice band generated in the voltage output circuit 11 is output to the terminal 14 and the characteristics of the MEMS microphone 15 are deteriorated.

本発明の目的は、過電圧保護素子にリーク電流が流れても、そのリーク電流がダイオードを使用したローパスフィルタに流れないようにして、そのローパスフィルタのカットオフ周波数が変動しないようにした容量性負荷バイアス回路を提供することである。   An object of the present invention is to provide a capacitive load in which even if a leakage current flows through an overvoltage protection element, the leakage current does not flow into a low-pass filter using a diode so that the cutoff frequency of the low-pass filter does not fluctuate. A bias circuit is provided.

上記目的を達成するために、請求項１にかかる発明の容量性負荷バイアス回路は、バイアス電圧を出力する電圧出力回路と、該電圧出力回路の出力側と接地との間に接続した過電圧保護素子と、前記電圧出力回路の出力側にアノードを接続したダイオードおよび該ダイオードのカソードと接地間に接続したキャパシタを有するローパスフィルタとを備え、該ローパスフィルタの前記ダイオードのカソードと前記キャパシタとの共通接続点を容量性負荷が接続される出力端子に接続してなることを特徴とする。
請求項２にかかる発明は、請求項１に記載の容量性負荷バイアス回路において、前記キャパシタに直列に減流抵抗を接続したことを特徴とする。 In order to achieve the above object, a capacitive load bias circuit according to a first aspect of the present invention includes a voltage output circuit for outputting a bias voltage, and an overvoltage protection element connected between the output side of the voltage output circuit and the ground. And a low-pass filter having a diode having an anode connected to the output side of the voltage output circuit and a capacitor connected between the cathode of the diode and the ground, and a common connection between the cathode of the diode and the capacitor of the low-pass filter The point is connected to an output terminal to which a capacitive load is connected.
According to a second aspect of the present invention, in the capacitive load bias circuit according to the first aspect, a current reducing resistor is connected in series with the capacitor.

本発明によれば、電圧出力回路の出力側と接地との間に過電圧保護素子を接続しているので、その過電圧保護素子に電圧出力回路からリーク電流が流れても、そのリーク電流はローパスフィルタには流れないので、そのローパスフィルタのカットオフ周波数が変動することはなく、電圧出力回路で発生した不要なノイズ成分をそのローパスフィルタで完全にカットすることができる。また、過電圧保護素子のリーク電流がローパスフィルタのカットオフ周波数に影響を及ばさないことから、その過電圧保護素子の耐性を向上させるべくその面積を大きくする、つまり過電圧保護素子の並列接続数を多くすることができる。また、そのローパスフィルタのキャパシタに直列に減流抵抗を接続することで、出力端子に過電圧が印加した際にそのキャパシタに流れる過電流を減流させることができ、出力端子から離れた箇所に過電圧保護素子を接続したことによるキャパシタの破壊を防止することができる。   According to the present invention, since the overvoltage protection element is connected between the output side of the voltage output circuit and the ground, even if a leakage current flows from the voltage output circuit to the overvoltage protection element, the leakage current is low-pass filtered. Therefore, the cut-off frequency of the low-pass filter does not fluctuate, and unnecessary noise components generated in the voltage output circuit can be completely cut by the low-pass filter. Moreover, since the leakage current of the overvoltage protection element does not affect the cutoff frequency of the low-pass filter, the area is increased in order to improve the tolerance of the overvoltage protection element, that is, the number of overvoltage protection elements connected in parallel is increased. can do. Also, by connecting a current reducing resistor in series with the capacitor of the low-pass filter, it is possible to reduce the overcurrent that flows through the capacitor when an overvoltage is applied to the output terminal. The destruction of the capacitor due to the connection of the protective element can be prevented.

本発明の第１の実施例の容量性負荷バイアス回路の回路図である。1 is a circuit diagram of a capacitive load bias circuit according to a first embodiment of the present invention. FIG. 本発明の第２の実施例の容量性負荷バイアス回路の回路図である。It is a circuit diagram of the capacitive load bias circuit of the 2nd Example of this invention. 本発明の第３の実施例の容量性負荷バイアス回路の回路図である。FIG. 5 is a circuit diagram of a capacitive load bias circuit according to a third embodiment of the present invention. 従来の容量性負荷バイアス回路の回路図である。It is a circuit diagram of the conventional capacitive load bias circuit. ダイオードの電流／電圧特性図である。It is a current / voltage characteristic diagram of a diode.

＜第１の実施例＞
図１に本発明の第１の実施例の容量性負荷バイアス回路１０Ａを示す。本実施例では、過電圧保護素子１２を、電圧出力回路１１とローパスフィルタ１３の間、つまり電圧出力回路１１の出力側と接地との間に接続している。 <First embodiment>
FIG. 1 shows a capacitive load bias circuit 10A according to the first embodiment of the present invention. In this embodiment, the overvoltage protection element 12 is connected between the voltage output circuit 11 and the low-pass filter 13, that is, between the output side of the voltage output circuit 11 and the ground.

本実施例では、通常動作時に過電圧保護素子１２にリーク電流が流れる場合、そのリーク電流は電圧出力回路１１から過電圧保護素子１２に直接流れ、ローパスフィルタ１３には流れない。このため、ローパスフィルタ１３のダイオードＤ１に流れる電流はリーク電流の影響を受けることがないので、その抵抗値が低下することはなく、そのローパスフィルタ１３のカットオフ周波数が設定値から上昇することはない。   In this embodiment, when a leakage current flows through the overvoltage protection element 12 during normal operation, the leakage current flows directly from the voltage output circuit 11 to the overvoltage protection element 12 and does not flow through the low-pass filter 13. For this reason, since the current flowing through the diode D1 of the low-pass filter 13 is not affected by the leakage current, the resistance value does not decrease, and the cutoff frequency of the low-pass filter 13 increases from the set value. Absent.

なお、過電圧保護素子１２は、外部に晒される出力端子１４に静電気放電の過電圧が印加した際に導通し過電流を吸収して内部回路（この場合は電圧出力回路１１）を保護するものであり、従来では出力端子１４に直接接続されていたので、その機能を十分発揮できた。一方、本実施例は出力端子１４と過電圧保護素子１２との間にローパスフィルタ１３が介在することになるが、過電圧保護素子１２の導通電圧はローパスフィルタ１３のダイオードＤ１やキャパシタＣ１の耐圧に比べて十分低く設定されるので、出力端子１４に過電圧が印加した際でも、ローパスフィルタ１３が破壊される前に過電圧保護素子１２を動作させることが可能となる。   The overvoltage protection element 12 is conductive when an electrostatic discharge overvoltage is applied to the output terminal 14 exposed to the outside, and absorbs the overcurrent to protect the internal circuit (in this case, the voltage output circuit 11). Conventionally, since it was directly connected to the output terminal 14, its function could be sufficiently exhibited. On the other hand, in this embodiment, the low-pass filter 13 is interposed between the output terminal 14 and the overvoltage protection element 12, but the conduction voltage of the overvoltage protection element 12 is higher than the breakdown voltage of the diode D1 and the capacitor C1 of the low-pass filter 13. Therefore, even when an overvoltage is applied to the output terminal 14, the overvoltage protection element 12 can be operated before the low-pass filter 13 is destroyed.

また本実施例では、この過電圧保護素子１２のリーク電流が問題とならないので、その過電圧保護素子として多数のトランジスタを並列接続して過電流を分散させＥＳＤ耐性を向上させることができる。   In this embodiment, since the leakage current of the overvoltage protection element 12 does not become a problem, a large number of transistors can be connected in parallel as the overvoltage protection element to disperse the overcurrent and improve the ESD resistance.

＜第２の実施例＞
図２に本発明の第２の実施例の容量性負荷バイアス回路１０Ｂを示す。本実施例では、第１の実施例において、そのローパスフィルタ１３のキャパシタＣ１に直列に抵抗Ｒ１を接続している。このように抵抗Ｒ１を接続すると、出力端子１４に過電圧が印加してキャパシタＣ１に過電流が流れる場合、その過電流を制限してキャパシタＣ１の保護を向上させることができる。この抵抗Ｒ１の抵抗値は数ｋΩ程度で十分であり、ＧΩオーダーの抵抗値を示すダイオードＤ１の抵抗値に比べてほぼ無視できる程度であるので、ローパスフィルタ１３のカットオフ周波数が実質的に変動することはない。 <Second embodiment>
FIG. 2 shows a capacitive load bias circuit 10B according to the second embodiment of the present invention. In this embodiment, a resistor R1 is connected in series to the capacitor C1 of the low-pass filter 13 in the first embodiment. When the resistor R1 is connected in this way, when an overvoltage is applied to the output terminal 14 and an overcurrent flows through the capacitor C1, the overcurrent can be limited to improve the protection of the capacitor C1. The resistance value of the resistor R1 is about several kΩ, and is almost negligible as compared with the resistance value of the diode D1 having a resistance value on the order of GΩ. Therefore, the cut-off frequency of the low-pass filter 13 is substantially changed. Never do.

＜第３の実施例＞
図３に第３の実施例の容量性負荷バイアス回路１０Ｃを示す。本実施例では、ローパスフィルタ１３のダイオードＤ１に別ダイオードＤ２を逆並列接続している。このように、別のダイオードＤ２を逆並列接続すれば、ＭＥＭＳマイクロフォン１５やキャパシタＣ１から電圧出力回路１１の方向に流れる電流を吸収することができる。 <Third embodiment>
FIG. 3 shows a capacitive load bias circuit 10C of the third embodiment. In this embodiment, another diode D2 is connected in antiparallel to the diode D1 of the low-pass filter 13. Thus, if another diode D2 is connected in antiparallel, the current flowing from the MEMS microphone 15 or the capacitor C1 toward the voltage output circuit 11 can be absorbed.

＜その他の実施例＞
以上はＭＥＭＳマイクロフォン１５を負荷としてそこにバイアスを供給するバイアス回路１０Ａ〜１０Ｃについて説明したが、バイアスが必要な容量性負荷であれば、他の負荷についても同様に実施することができる。この場合、ローパスフィルタ１３のカットオフ周波数はその容量性負荷に応じて設定される。 <Other examples>
The bias circuits 10A to 10C that supply the bias to the MEMS microphone 15 as a load have been described above. However, other capacitive loads that require a bias can be similarly implemented. In this case, the cutoff frequency of the low-pass filter 13 is set according to the capacitive load.

１０Ａ〜１０Ｄ：容量性負荷バイアス回路、１１：電圧出力回路、１２：過電圧保護素子、１３：ローパスフィルタ、１４：出力端子、１５：ＭＥＭＳマイクロフォン、１６：増幅器   10A to 10D: capacitive load bias circuit, 11: voltage output circuit, 12: overvoltage protection element, 13: low-pass filter, 14: output terminal, 15: MEMS microphone, 16: amplifier

Claims (2)

バイアス電圧を出力する電圧出力回路と、該電圧出力回路の出力側と接地との間に接続した過電圧保護素子と、前記電圧出力回路の出力側にアノードを接続したダイオードおよび該ダイオードのカソードと接地間に接続したキャパシタを有するローパスフィルタとを備え、該ローパスフィルタの前記ダイオードのカソードと前記キャパシタとの共通接続点を容量性負荷が接続される出力端子に接続してなることを特徴とする容量性負荷バイアス回路。   A voltage output circuit for outputting a bias voltage, an overvoltage protection element connected between the output side of the voltage output circuit and the ground, a diode having an anode connected to the output side of the voltage output circuit, and a cathode and ground of the diode And a low-pass filter having a capacitor connected therebetween, wherein a common connection point between the cathode of the diode of the low-pass filter and the capacitor is connected to an output terminal to which a capacitive load is connected. Load bias circuit. 請求項１に記載の容量性負荷バイアス回路において、
前記キャパシタに直列に減流抵抗を接続したことを特徴とする容量性負荷バイアス回路。 The capacitive load bias circuit of claim 1,
A capacitive load bias circuit comprising a current reducing resistor connected in series to the capacitor.
JP2012122649A 2012-05-30 2012-05-30 Capacitive load bias circuit Active JP5970241B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012122649A JP5970241B2 (en) 2012-05-30 2012-05-30 Capacitive load bias circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012122649A JP5970241B2 (en) 2012-05-30 2012-05-30 Capacitive load bias circuit

Publications (2)

Publication Number Publication Date
JP2013251587A true JP2013251587A (en) 2013-12-12
JP5970241B2 JP5970241B2 (en) 2016-08-17

Family

ID=49849914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012122649A Active JP5970241B2 (en) 2012-05-30 2012-05-30 Capacitive load bias circuit

Country Status (1)

Country Link
JP (1) JP5970241B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015211355A (en) * 2014-04-25 2015-11-24 ローム株式会社 Bias circuit for microphone, audio interface circuit, and electronic apparatus
JP2019161337A (en) * 2018-03-09 2019-09-19 新日本無線株式会社 Capacitive load bias circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006514497A (en) * 2003-03-20 2006-04-27 ビーエスイー カンパニー リミテッド Condenser microphone with enhanced resistance to electrostatic discharge using a broadband blocking filter
JP2008153981A (en) * 2006-12-18 2008-07-03 Sanyo Electric Co Ltd Capacitance change detection circuit and condenser microphone device
JP2009290640A (en) * 2008-05-30 2009-12-10 Audio Technica Corp Power supply unit for capacitor microphone

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006514497A (en) * 2003-03-20 2006-04-27 ビーエスイー カンパニー リミテッド Condenser microphone with enhanced resistance to electrostatic discharge using a broadband blocking filter
JP2008153981A (en) * 2006-12-18 2008-07-03 Sanyo Electric Co Ltd Capacitance change detection circuit and condenser microphone device
JP2009290640A (en) * 2008-05-30 2009-12-10 Audio Technica Corp Power supply unit for capacitor microphone

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015211355A (en) * 2014-04-25 2015-11-24 ローム株式会社 Bias circuit for microphone, audio interface circuit, and electronic apparatus
JP2019161337A (en) * 2018-03-09 2019-09-19 新日本無線株式会社 Capacitive load bias circuit
JP7047229B2 (en) 2018-03-09 2022-04-05 日清紡マイクロデバイス株式会社 Capacitive load bias circuit

Also Published As

Publication number Publication date
JP5970241B2 (en) 2016-08-17

Similar Documents

Publication Publication Date Title
US20090086992A1 (en) Microphone circuit and charge amplifier thereof
JP2015211463A (en) Electrostatic discharge protection circuit
TWI517511B (en) Protecting circuit and electrical device using the same
JP2011519488A (en) Multi-voltage electrostatic discharge protection
JP2014207412A (en) ESD protection circuit
JP2015002510A (en) Electrostatic protection circuit
JP2005005705A (en) Technique for reducing esd load capacitance
JP2009239844A (en) Noise filter and amplifier circuit with built-in noise filter
JP2016167516A (en) Electrostatic protection circuit
JP2009087962A (en) Protection circuit and semiconductor integrated circuit
JP5970241B2 (en) Capacitive load bias circuit
CN101378056A (en) Semiconductor integrated circuit
KR101031655B1 (en) Semiconductor integrated circuit and condenser microphone
US20190373688A1 (en) Power supply device, lighting equipment, and method for manufacturing power supply device
JP2017034583A (en) Optical module
JP2010225930A (en) Esd protection circuit
TW201445866A (en) Power conversion circuit and electronic device
US20170287893A1 (en) Electrostatic discharge protection device having an adjustable triggering threshold
JP4822686B2 (en) Protection circuit and semiconductor integrated circuit equipped with the same
TWI596856B (en) Circuit system
TW201320292A (en) Electrostatic discharge protection apparatus
US20060209477A1 (en) Input protection circuit
JP2006115255A (en) Operational amplifier
JP6686259B2 (en) Microphone amplifier
US20130249044A1 (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150403

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160524

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160627

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160711

R150 Certificate of patent or registration of utility model

Ref document number: 5970241

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250