JP2013247129A - Method of manufacturing semiconductor substrate having isolation, method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor substrate which prevents generation of formation failures of an isolation film on a semiconductor substrate surface to avoid reduction in a yield.SOLUTION: A method includes the following steps of: forming a silicon nitride film 103 on a semiconductor substrate 101; thinning the silicon nitride film so that a film thickness in a first region for forming a logic circuit on the semiconductor substrate and that in a second region for forming a memory cell are different from each other; forming a trench pattern 105 in the semiconductor substrate to fill the trench pattern with the silicon oxide film 108; flattening the silicon oxide film 108 so as to match respective surfaces of the silicon nitride films 103 in the first and second regions; etching the entire flattened silicon oxide film 108 by a predetermined amount to expose the silicon nitride film 103; removing the exposed silicon nitride film 103; and adjusting a height of a surface of the silicon oxide film 108 in the first and second regions to a surface of the semiconductor substrate 101.

Description

  The present invention relates to a method for manufacturing a semiconductor substrate having an element isolation portion, a method for manufacturing a semiconductor device, and a semiconductor device, and in particular, element isolation that occurs when a memory portion, a logic portion, and the like are formed on the same semiconductor substrate. The present invention relates to a method for manufacturing a semiconductor substrate having an element isolation portion suitable for avoiding film formation defects, a method for manufacturing a semiconductor device, and a semiconductor device.

  In a semiconductor device, for example, a memory device and a logic device are formed on a single chip, so that downsizing, low power consumption, high speed, and EMI (Electro Magnetic Interference) noise are reduced.

  In order to form the memory portion and the logic portion on the same semiconductor substrate, for example, as described in Patent Document 1, a semiconductor element isolation portion called STI (Shallow Trench Isolation) is formed on the semiconductor substrate, and the memory portion And the logic part must be electrically separated.

  In order to form such an STI, various film forming steps and etching steps are repeatedly performed. Further, in manufacturing such a memory, a memory portion is formed and peripheral circuits such as a logic portion other than the memory formation region are formed on the same substrate.

  At this time, since the manufacturing process of the memory formation region and the logic part formation region is not necessarily the same, a process of forming only the memory formation area and a process of forming only the logic part formation region are mixed. Therefore, the number of processes increases in the process of forming the memory part and the peripheral circuit together as compared to the process of forming each part alone.

  When etching for forming the memory portion is performed, the surface of the STI is also reduced by the etching. As a result of repeated etching of the STI, when the decrease of the STI becomes more significant than that of the substrate, the junction portion is exposed, resulting in an increase in junction leakage current and a short circuit. Accompanying this, erroneous writing of the memory also occurs.

  Further, when the STI surface is higher than the substrate surface and the level difference is increased, the film at the level difference portion cannot be completely removed, and there is a possibility that it will become dust in a subsequent process. That is, a substance in process, for example, an oxide film or a nitride film on the sidewall, remains on the stepped part or the divot part, and there is a possibility that it will become dust if it is peeled off in a subsequent process.

  Further, as described above, when the memory portion and the peripheral circuit portion are formed, the total number of processes is increased, and the influence of the process is transferred to other parts during the process of forming only one of the parts. It also extends. This further increases the number of steps in which the STI is etched, and the above problems are further increased.

  Patent Document 2 discloses a technique for solving such a problem and preventing the STI oxide film from excessively decreasing.

  In Patent Document 2, as a method of manufacturing a split gate type MONOS type flash memory including a word gate and a control gate, a word gate sandwiching an oxide film is formed on an impurity diffusion layer of a semiconductor substrate separated by STI. A step of forming an ONO layer formed in the order of an oxide film, a nitride film, and an oxide film on the entire surface of the semiconductor substrate on which the STI and the word gate are formed, and a control gate conductive layer on the ONO layer. A manufacturing method including a step of forming a film and a step of forming a mask insulating film over the entire surface of the control gate conductive film is described. And in patent document 2, in adjusting the height of a STI oxide film, it adjusts by using dry etching in multiple times.

JP 2005-72578 A JP 2011-187562 A

  As described above, in Patent Document 2, adjustment of the height of the STI oxide film is performed by using dry etching a plurality of times. However, when the height of the STI oxide film is adjusted by dry etching, it is half-etched by time adjustment, and therefore it is not easy to control so as to reduce variations in height adjustment.

  The present invention has been made to solve the above-described problems, and makes it possible to easily adjust the height of an STI oxide film with little variation with a small number of man-hours. An object of the present invention is to prevent a decrease in yield by preventing the formation of an element isolation film from occurring even when forming a logic portion.

  In order to achieve the above object, a method of manufacturing a semiconductor substrate having an element isolation portion according to the present invention includes a first region for forming a first element group and a second element group for forming a second element group on the semiconductor substrate. Forming a first insulating film having a thickness different from that of the region, and forming a pattern for forming an element isolation portion on the semiconductor substrate with respect to the first insulating film. And forming an opening for forming a plurality of openings for forming the element isolation portion in the semiconductor substrate, and forming a second insulating film covering the first insulating film to form each of the openings. And embedding the second insulating film, planarizing the second insulating film in accordance with the surface of the first insulating film in the first region, and the second region in the second region. Flatten the second insulating film to the surface of the first insulating film Flattening step, flattening step of flattening the second insulating film in accordance with each surface of the first insulating film in the first region and the second region, and flattening An exposure step of uniformly removing the second insulating film from the surface side to expose the first insulating film; a removing step of removing the exposed first insulating film; and a surface of the semiconductor substrate. Adjusting the height of the second insulating film in each of the first region and the second region.

  On the other hand, in order to achieve the above object, a method of manufacturing a semiconductor device of the present invention includes a step of forming a semiconductor substrate having the element isolation portion by a method of manufacturing a semiconductor substrate having the element isolation portion, and the semiconductor substrate. Forming the first element group in the first region and forming the second element group in the second region.

  In order to achieve the above object, according to the method for manufacturing a semiconductor device of the present invention, the thickness of the second insulating film in the first region is determined by the method for manufacturing a semiconductor substrate having the element isolation portion. Forming a semiconductor substrate having the element isolation portion by making the film thinner than the thickness of the second insulating film in the second region; and a logic circuit in the first region on the semiconductor substrate. Forming a memory circuit in the second region.

On the other hand, in order to achieve the above object, the semiconductor device of the present invention is manufactured by the manufacturing method of the semiconductor device.
Manufactured.

  According to the present invention, in the step of forming the STI on the semiconductor substrate, it is possible to form the STI surface with respect to the semiconductor substrate surface at different heights for each region. As a result, for example, the height of the STI surface in the region where the logic portion where the man-hour such as the edging process is large is made higher than the height of the STI in the region where the memory portion is formed can be easily performed with a small man-hour. Therefore, it is possible to prevent a formation defect of the element isolation film when the memory portion and the logic portion are formed on the same semiconductor substrate, and it is possible to avoid a decrease in yield.

It is explanatory drawing which shows the process example of the first half of the manufacturing method of the semiconductor substrate provided with the element separation part which concerns on embodiment. It is explanatory drawing which shows the process example of the second half of the manufacturing method of the semiconductor substrate provided with the element isolation part which concerns on embodiment. It is explanatory drawing which shows the 1st-3rd process of the first half of the other process example of the manufacturing method of the semiconductor substrate provided with the element separation part which concerns on embodiment. It is explanatory drawing which shows the 4th-6th process of the first half of the other process example of the manufacturing method of the semiconductor substrate provided with the element separation part which concerns on embodiment. It is explanatory drawing which shows the second half of the other process example of the manufacturing method of the semiconductor substrate provided with the element isolation part which concerns on embodiment. It is sectional drawing which shows the structural example of the semiconductor device which concerns on embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 and 2 show a process example of a method for manufacturing a semiconductor substrate provided with an element isolation portion used in the semiconductor device according to the present embodiment.

  The semiconductor device according to this embodiment is formed by mixing a memory cell portion and a logic circuit portion on one semiconductor substrate. Hereinafter, a case where a silicon substrate is used as a semiconductor substrate will be described as an example.

  In the first step shown in FIG. 1, a silicon oxide film 102 is formed on the silicon substrate 101, and a silicon nitride film 103 is formed on the silicon oxide film 102.

  In the second step, a photoresist 104 is formed on the silicon nitride film 103 so as to cover only the logic circuit portion.

  In the third step, the silicon nitride film 103 is thinned by dry etching using the photoresist 104 as a mask. Thereafter, the photoresist 104 is stripped using a resist stripping solution.

  Here, the film thickness to be dry-etched is the amount of the step in the logic circuit region where the step between the silicon substrate surface and the STI surface becomes large after the formation of the memory cell portion or logic circuit portion, and the memory cell portion in which the step is small. The difference from the level difference of the area is.

  For example, if the step in the logic circuit region is 126 nm and the step in the memory cell region is 40 nm, the difference (126 nm−40 nm = 86 nm) is the film thickness for dry etching.

  Thus, in the third step, the film thickness of the silicon nitride film 103 is different between the first region for forming the logic circuit portion on the silicon substrate 101 and the second region for forming the memory cell portion. Thin film. Here, the thickness of the silicon nitride film 103 in the first region is made larger than the thickness of the silicon nitride film 103 in the second region.

  In the fourth step, a pattern for forming an STI (element isolation portion) is formed on the silicon substrate 101 on the silicon nitride film 103, and further, an STI (element isolation portion) is formed on the silicon substrate 101 according to the formed pattern. A plurality of openings for forming a trench pattern 105 is formed. Here, the silicon substrate 101 on which the trench pattern 105 is formed is described as a silicon substrate 106.

  In the fifth step, the trench pattern 105 portion of the silicon substrate 106 is oxidized to form a silicon oxide film 107 on the silicon substrate 106 and the silicon nitride film 103.

  Next, in the sixth step shown in FIG. 2, the silicon oxide film 108 is covered in the trench pattern by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) so as to cover the logic circuit portion and the memory cell portion. Embed. The hatched portion in FIG. 2 is the silicon oxide film 108 embedded in the trench pattern.

  In the seventh step, the silicon oxide film 108 on the silicon nitride film 103 is removed by a CMP (Chemical Mechanical Polishing) method. At this time, the silicon nitride film 103 is planarized using the stopper film.

  As a result of the processing in the seventh step, each STI surface filled with the silicon oxide film 108 in the memory cell portion and the logic circuit portion due to the difference in film thickness of the silicon nitride film 103 etched in the third step. There is a step in

  In the eighth step, the silicon nitride film 103 is exposed by etching the silicon oxide film 107 and the silicon oxide film 108 by HF treatment.

  In the ninth step, the exposed silicon nitride film 103 is subjected to thermal phosphoric acid treatment to remove the silicon nitride film 103. The silicon substrates 101 and 106 after removing the silicon nitride film 103 are referred to as a silicon substrate 109, and the silicon oxide film 108 is referred to as a silicon oxide film 110.

  In the tenth step, the silicon oxide film 110 is etched again by HF treatment, so that the surface of the silicon oxide film 110 in each of the first region and the second region is higher than the surface of the silicon substrate 109. Adjust the height. Here, the first region in which the surface 111 of the silicon oxide film 110 in the second region where the memory cell portion is formed is adjusted to be the same as the surface of the silicon substrate 109, and the logic circuit portion is formed. The surface 112 of the silicon oxide film 110 is adjusted to be higher than the surface of the silicon substrate 109.

  Through the above manufacturing process, an element isolation portion, that is, an STI filled with the silicon oxide film 110 is formed on the silicon substrate 109, and adjacent elements can be electrically isolated from each other.

  The surface 111 of the silicon oxide film 110 in the memory cell portion and the logic circuit portion are adjusted by adjusting the etching film thickness of the silicon nitride film 103 in the third step and by adjusting the HF processing time in the tenth step. The height of the surface 112 of the silicon oxide film 110 with respect to the surface of the silicon substrate 109 can be controlled.

  As described above, in the manufacturing process of the semiconductor element isolation portion of the present embodiment, the silicon nitride film 103 serving as a CMP stopper in each of the memory cell portion and the logic circuit portion can be etched to have a film thickness difference. In addition, the height of the STI surface filled with the oxide film with respect to the silicon substrate surface in the memory cell portion and the logic circuit portion can be controlled.

  In this manner, the silicon oxide film 110 in the second region where the memory cell portion is formed, that is, the surface 111 of the STI is equal to the surface of the silicon substrate 109, and the logic circuit portion is Memory cells and logic circuits are formed on the silicon substrate 109 in which the surface 112 of the silicon oxide film 110 (STI) in the first region to be formed is formed higher than the surface of the silicon substrate 109.

  Next, referring to FIGS. 3A, 3B, and 4, another example of the manufacturing method of the semiconductor substrate provided with the element isolation portion used in the semiconductor device according to the present embodiment will be described. Hereinafter, a case where a silicon substrate is used as a semiconductor substrate will be described as an example.

  The semiconductor device according to this embodiment is formed by mixing a memory cell portion and a logic circuit portion on one semiconductor substrate.

  In the first step shown in FIG. 3A, a silicon oxide film 302 is formed on the silicon substrate 301, and a silicon nitride film 303 is formed on the silicon oxide film 302.

  Note that the thickness of the silicon nitride film 303 has a large difference in level difference between the silicon substrate surface and the STI surface filled with the oxide film after elements such as memory cells and logic circuits are formed on the silicon substrate 301. (Here, the region for the logic circuit portion) and the step difference between the region where the difference in level between the silicon substrate surface and the STI surface filled with the oxide film after the element formation is small (here, the region for the memory cell portion) To do.

  In the next second step, a photoresist 304 is formed using a mask so as to cover only the first region for the logic circuit portion.

  In the third step, the silicon nitride film 303 in the second region for the memory cell circuit is removed by wet etching or dry etching using the photoresist 304 as a mask and the silicon oxide film 302 on the silicon substrate 301 as a stopper. Thereafter, the photoresist 304 is stripped using a resist stripping solution.

  In the next fourth step shown in FIG. 3B, a silicon nitride film 305 is formed again on the entire surface. At this time, the total thickness of the silicon nitride film 303 and the silicon nitride film 305 in the first region is set to a predetermined thickness.

  In the fifth step, a pattern for forming an STI (element isolation portion) is formed on the silicon substrate 301 on the silicon nitride films 303 and 305, and further, an STI (element) is formed on the silicon substrate 301 according to the formed pattern. A plurality of openings for forming a separation portion are formed to form a trench pattern 306. Here, the silicon substrate 301 on which the trench pattern 305 is formed is described as a silicon substrate 307.

  In the sixth step, the trench pattern 306 portion in the silicon substrate 307 is oxidized to form a silicon oxide film 308 on the silicon substrate 307 and the silicon nitride film 305.

  Next, in a seventh step shown in FIG. 4, a silicon oxide film 309 is embedded in the trench pattern by the HDP-CVD method so as to cover the logic circuit portion and the memory cell portion.

  In the eighth step, the silicon oxide film 309 on the silicon nitride films 303 and 305 is removed and planarized by CMP using the silicon nitride film 303 as a stopper film.

  At that time, due to the difference in film thickness between the area of only the silicon nitride film 303 (second region) and the combined area of the silicon nitride films 303 and 305 (first region), the memory cell portion (second region) Steps are formed on the STI surfaces filled with the silicon oxide film 309 in the region) and the logic circuit portion (first region).

  In the ninth step, the silicon oxide films 308 and 309 are exposed by etching the silicon oxide film 308 and the silicon oxide film 309 by HF treatment.

  In the tenth step, the exposed silicon oxide films 303 and 305 are subjected to hot phosphoric acid treatment to remove the silicon nitride films 303 and 305. The silicon substrates 301 and 307 after the removal of the silicon nitride films 303 and 305 are referred to as a silicon substrate 310, and the silicon oxide film 309 is referred to as a silicon oxide film 311.

  In the eleventh step, the silicon oxide film 311 is etched again by HF treatment, so that the height of the surface of the silicon oxide film 311 in each of the first region and the second region with respect to the surface of the silicon substrate 310 is increased. Adjust. Here, the first region in which the surface 312 of the silicon oxide film 311 in the second region where the memory cell portion is formed is adjusted to be the same as the surface of the silicon substrate 310 and the logic circuit portion is formed. The surface 313 of the silicon oxide film 311 is adjusted to be higher than the surface of the silicon substrate 310.

  Through the above manufacturing process, an element isolation portion (STI) filled with the silicon oxide film 311 is formed on the silicon substrate 310, and adjacent elements can be electrically isolated from each other.

  In FIGS. 3 and 4, the etching film thickness of the silicon nitride films 303 and 305 is adjusted by the second to fourth steps, and the HF processing time is adjusted in the eleventh step. The height of the surface 312 of the silicon oxide film 311 and the surface 313 of the silicon oxide film 311 in the logic circuit portion with respect to the surface of the silicon substrate 310 can be controlled.

  As described above, in the manufacturing process of the semiconductor element isolation portion according to the present embodiment shown in FIGS. 3 and 4, the silicon nitride films 303 and 305 serving as CMP stoppers in each of the memory cell portion and the logic circuit portion are formed. By forming the film separately, the first region and the second region can have different film thicknesses, and the STI surface filled with the oxide film with respect to the silicon substrate surface in the memory cell portion and the logic circuit portion can be provided. Each height can be controlled.

  In this way, the surface 312 of the silicon oxide film 311 (STI) in the second region where the memory cell portion is formed is equal to the surface of the silicon substrate 310 and the logic circuit portion is Memory cells and logic circuits are formed on the silicon substrate 310 in which the surface 313 of the silicon oxide film 311 (STI) in the first region to be formed is formed higher than the surface of the silicon substrate 310.

  FIG. 5 shows a configuration example of a semiconductor device in which logic circuits and memory cells are formed over the silicon substrate formed in the tenth step in FIG. 2 or the eleventh step in FIG.

  In the example of FIG. 5, a logic circuit 501c including a logic gate 501a and a sidewall 501b is formed in a first region 501 of a silicon substrate 500, and a word gate 502a, a control gate 502b, and a side region are formed in a second region 502. A structure of a semiconductor device 503 in which a memory cell 502d including a wall 502c is formed is shown. In FIG. 5, the STI (silicon oxide film) in the first region 501 of the silicon substrate 500 is removed and flattened.

  Hereinafter, a process of forming a logic circuit and a memory cell in the first region 501 and the second region 502 of the silicon substrate 500 formed by each process shown in FIGS.

  In this way, for the process of forming the logic circuit and the memory cell on the silicon substrate 500 as described above, for example, a known technique described in Patent Documents 1 and 2 described above can be used. Here, the technique described in Patent Document 2 will be described.

  First, a case where a split gate type flash memory is formed in a second region on a silicon substrate, in which elements are separated by STI, will be described. The split gate type flash memory is a type of flash memory in which a gate is divided into a word gate and a control gate.

  When the flash memory is formed in the second region on the silicon substrate separated by STI, first, an oxide film and polysilicon for word gate (WG) are formed on the entire surface of the silicon substrate separated by STI. Film and etch to form the word gate.

  Next, an ONO layer in which an oxide film, a nitride film, and an oxide film are sequentially stacked is formed on the entire surface, and a polysilicon film for a control gate (CG) is further formed. Thereafter, the polysilicon film is etched to form a control gate. Then, an oxide film for sidewall (SW) is formed and etched back to form a sidewall.

  Note that the STI is etched both when the polysilicon film is etched and when the sidewall (SW) oxide film is etched back.

  Next, a case where a logic circuit as a peripheral circuit is formed in the first region on the silicon substrate, which is element-isolated by the STI formed in the steps of FIGS.

  When the logic circuit is formed on a silicon substrate separated by STI, a resist for gate processing of the logic circuit is first formed and etched on the silicon substrate separated by STI.

  Next, after forming an oxide film for a side wall of the logic circuit, this is etched to form a side wall. In this step, the STI around the logic circuit is etched. Then, after forming an electrode silicide, a contact is formed to complete the structural portion. Thereafter, a wiring process is performed.

  Through such steps, the semiconductor device 505 shown in FIG. 5 is manufactured.

  As described above, in this embodiment, in the step of forming the STI on the semiconductor substrate, the silicon nitride film used as the CMP stop film is partially etched by dry etching using a photoresist as a mask when forming the STI structure. By making the film thinner, the height of the STI surface filled with the oxide film with respect to the silicon substrate surface can be controlled.

  In addition, in the step of forming the STI on the semiconductor substrate, the silicon nitride film used for the CMP stop film is formed twice at the time of forming the STI structure, so that the STI filled with the oxide film with respect to the silicon substrate surface is formed. The height of each surface can be controlled.

  That is, in the step of forming the STI on the semiconductor substrate, the silicon nitride film used as the CMP process stop film is partially thinned for each region, so that the height of the STI surface with respect to the semiconductor substrate surface is reduced. It is possible to form at different heights.

  As a result, for example, the height of the STI surface in the region where the logic part where the man-hours such as the edging process are formed is higher than the height of the STI in the area where the memory part is formed can be easily performed with less man-hours. Therefore, it is possible to prevent a formation defect of the element isolation film from occurring when the memory portion and the logic portion are formed on the same semiconductor substrate, and it is possible to avoid a decrease in yield.

  Then, by aligning the height of the STI surface with respect to the semiconductor substrate surface over the entire surface of the chip after element formation, the influence on the transistor characteristics due to the difference in level difference, for example, the memory mixed product in the NMOS CoreTr is a pure logic product The problem that the off-leak becomes higher by about one digit or more or the problem that the power consumption increases can be solved.

  The present invention is not limited to the embodiments described with reference to the drawings, and various modifications can be made without departing from the scope of the invention. For example, in this example, a silicon oxide film and a silicon nitride film are used as a mask film at the time of STI formation, but any type can be used as long as it can be a mask film at the time of STI formation.

  In the example shown in FIGS. 3 and 4, the silicon substrate film and the STI surface filled with the oxide film in the two areas (first region and second region) are formed by forming the silicon nitride film twice. However, by repeatedly performing the second to fourth steps, it is possible to provide three or more surfaces on which the step can be adjusted.

101, 301 Silicon substrate 102, 302 Silicon oxide film 103, 303, 305 Silicon nitride film 104, 304 Photo resist 105, 306 Trench pattern 106, 307 Silicon substrate 107, 308 Silicon oxide film 108, 309 Silicon oxide film 109, 310 Silicon substrate 110, 311 Silicon oxide films 111, 112, 312, 313 Surface 500 Silicon substrate 501 First region 501a Logic gate 501b Side wall 501c Logic circuit 502 Second region 502a Word gate 502b Control gate 502c Side wall 502d Memory cell 503 Semiconductor apparatus

Claims (8)

A film forming step of forming a first insulating film having a different thickness between a first region for forming a first element group and a second region for forming a second element group on a semiconductor substrate;
A pattern for forming an element isolation portion in the semiconductor substrate is formed in the first insulating film, and a plurality of openings for forming the element isolation portion in the semiconductor substrate are formed according to the formed pattern. An opening forming step,
Forming a second insulating film covering the first insulating film and embedding the second insulating film in each of the openings;
The second insulating film is planarized according to the surface of the first insulating film in the first region, and the second insulating film is aligned with the surface of the first insulating film in the second region. A planarization step of planarizing the insulating film;
A planarization step of planarizing the second insulating film in accordance with each surface of the first insulating film in the first region and the second region;
An exposing step of uniformly removing the planarized second insulating film from the surface side to expose the first insulating film;
A removing step of removing the exposed first insulating film;
An adjusting step of adjusting the height of the second insulating film in each of the first region and the second region with respect to the surface of the semiconductor substrate;
The manufacturing method of the semiconductor substrate provided with the element isolation part containing. The film forming step includes
Forming the first insulating film on the semiconductor substrate;
Forming a photoresist on the first insulating film in the first region and then etching to form different thicknesses of the first region and the second region;
The manufacturing method of the semiconductor substrate provided with the element separation part of Claim 1 containing this. The film forming step includes
Forming the first insulating film on the semiconductor substrate;
The first insulating film formed in the second region on the semiconductor substrate is etched by forming a photoresist on the first insulating film formed in the first region and then etching. Removing, and
The first insulating film is formed on the semiconductor substrate and the first insulating film, and the film thickness of the first insulating film is set so that the first region and the second region on the semiconductor substrate are formed. A process of making the area different,
The manufacturing method of the semiconductor substrate provided with the element separation part of Claim 1 containing this. The first insulating film is made of a silicon nitride film,
The second insulating film comprises a silicon oxide film;
In the planarization step, the second insulating film is planarized by removing the second insulating film by CMP using the first insulating film as a stopper film,
The method for manufacturing a semiconductor substrate having an element isolation portion according to any one of claims 1 to 3, wherein, in the removing step, the first insulating film is removed by a thermal phosphoric acid treatment. Forming a semiconductor substrate provided with the element isolation part by a method of manufacturing a semiconductor substrate provided with the element isolation part according to any one of claims 1 to 4,
Forming the first element group in the first region on the semiconductor substrate and forming the second element group in the second region;
A method of manufacturing a semiconductor device including: The film thickness of the second insulating film in the first region is the thickness of the second region in the second region by the method of manufacturing a semiconductor substrate having the element isolation portion according to any one of claims 1 to 4. Forming a semiconductor substrate having the element isolation portion by reducing the thickness to be thicker than the thickness of the second insulating film;
Forming a logic circuit in the first region on the semiconductor substrate and a memory circuit in the second region;
A method of manufacturing a semiconductor device including: The method for manufacturing a semiconductor device according to claim 6, further comprising: removing the second insulating film in the first region where the logic circuit is formed on the semiconductor substrate.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 5.

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