JP2013239625A - Semiconductor device manufacturing method and lead frame - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep a clearance between a punch and a die in a cut process of a suspension lead with high accuracy.SOLUTION: A semiconductor device manufacturing method comprises a process of cutting a suspension lead SL1. In the process of cutting the suspension lead SL1, the suspension lead SL1 is cut by a first edge EP1 of a punch P1 and a second edge EP2 of the punch P1, which is located on a side opposite to the first edge EP1 is caused to pass a slit ST1 of a lead frame LF1.

Description

  The present invention relates to a method for manufacturing a semiconductor device and a lead frame, and more particularly to a method for manufacturing a semiconductor device including a step of cutting a suspended lead and a lead frame used for manufacturing the semiconductor device.

  In the semiconductor device manufacturing process, when the semiconductor chip is sealed with a resin to form the main body of the semiconductor device, the main body and the frame of the lead frame are connected via the suspension leads. In a step subsequent to the step of forming the main body portion, the main body portion and the frame portion of the lead frame are cut and separated.

  As a method of cutting and separating the main body portion and the frame portion of the lead frame, a method of integrally punching the suspension lead and a portion in the vicinity of the suspension lead in the frame portion of the lead frame by pressing is often used. . In this method, as described in Patent Document 1, for example, a resin-sealed semiconductor device is placed on a lower mold of a press mold (hereinafter, a mold) and then the upper mold of the mold is lowered. . Thus, punching is performed with the upper punch and the lower die, and the main body portion and the frame portion of the lead frame are separated.

  Patent Documents 2 to 9 describe a lead frame having suspension leads. Among these, the lead frames described in Patent Documents 2 to 7 have slits formed on the extension of the suspension leads.

JP-A-8-316400 Japanese Patent Laid-Open No. 11-67974 JP 2005-50939 A JP 2003-46051 A JP 2002-373964 A Japanese Patent Laid-Open No. 3-165057 JP 2006-100312 A Japanese Patent Laid-Open No. 10-313090 JP-A-11-121680

With the above method of integrally punching the suspension lead and the portion of the lead frame in the vicinity of the suspension lead, it is difficult to maintain the clearance between the punch and the die at the time of cutting the suspension lead with high accuracy. It is. If the suspension lead is cut while the clearance is enlarged, various problems that lead to a decrease in the productivity and quality of the semiconductor device occur.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to the method of manufacturing a semiconductor device of one embodiment, in the step of cutting the suspension lead, the suspension lead is cut by the first edge portion of the punch, and the first of the punch located on the opposite side to the first edge portion is cut. Two edges are passed through the slit of the lead frame.

  According to the one embodiment, the clearance between the punch and the die when cutting the suspension lead can be maintained with high accuracy.

It is a schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment. It is a typical sectional side view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment. It is a mimetic diagram showing an example of a semiconductor device obtained by a manufacturing method of a semiconductor device concerning an embodiment. It is a figure which shows an example of the lead frame used for the manufacturing method of the semiconductor device which concerns on embodiment. FIG. 5 is a plan view showing a state in which a semiconductor chip is mounted on the lead frame of FIG. 4 and then resin-sealed. It is a typical top view for explaining a manufacturing method of a semiconductor device concerning a modification. It is a schematic diagram for demonstrating the manufacturing method of the semiconductor device which concerns on a comparative example. It is typical sectional drawing for demonstrating the problem in the manufacturing method of the semiconductor device which concerns on a comparative example. It is typical sectional drawing for demonstrating the problem in the manufacturing method of the semiconductor device which concerns on a comparative example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  FIG. 1 is a schematic view for explaining the method for manufacturing a semiconductor device according to the embodiment. 1A is a plan view, and FIGS. 1B and 1C are side sectional views taken along the line AA in FIG. 1A. FIG. 2 is a schematic cross-sectional side view for explaining the method for manufacturing the semiconductor device according to the embodiment. FIG. 3 is a schematic diagram illustrating an example of a semiconductor device SD1 obtained by the method for manufacturing a semiconductor device according to the embodiment. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line BB in FIG. 3A. FIG. 4 is a diagram illustrating an example of the lead frame LF1 used in the method for manufacturing a semiconductor device according to the embodiment. 4A is an overall plan view, FIG. 4B is an enlarged view of a portion C in FIG. 4A, and FIG. 4C is an enlarged view of a portion D in FIG. 4B. FIG. 5 is a plan view showing a state in which the semiconductor chip is mounted on the lead frame of FIG. 4 and then sealed with resin, and corresponds to the region shown in FIG.

  The method for manufacturing a semiconductor device according to the present embodiment includes a step of preparing a lead frame LF1 (FIG. 4). As shown in FIG. 4C, the lead frame LF1 has a chip connection part CCP1, a frame part FP1, and a suspension lead SL1. As shown in FIG. 3B, one surface of the semiconductor chip SC1 is connected to one surface of the chip connection portion CCP1. As shown in FIG. 4C, the frame part FP1 is arranged around the chip connection part CCP1. The suspension lead SL1 has one end connected to the frame part FP1 and the other end connected to the chip connection part CCP1. In the frame part FP1, a slit ST1 is formed at a position on the extension of the suspension lead SL1 with respect to the chip connection part CCP1. This manufacturing method further includes a step of connecting one surface of the semiconductor chip SC1 to one surface of the chip connection portion CCP1, and a step of resin-sealing the semiconductor chip SC1. As shown in FIG. 1, the manufacturing method further includes a step of cutting the suspension lead SL1 with the punch P1 while the frame portion FP1 is supported by the die D1 of the mold having the die D1 and the punch P1. Here, in the plane of the lead frame LF1, the width of the slit ST1 in the direction orthogonal to the extending direction of the suspension lead SL1 is wider than the width of the punch P1. Further, the edge on the semiconductor chip side of the punch P1 is referred to as a first edge EP1, and the edge of the punch P1 opposite to the first edge EP1 is referred to as a second edge EP2. Further, the edge from the one end of the first edge EP1 to the one end of the second edge EP2 in the punch P1 is the third edge EP3, and the other edge of the first edge EP1 in the punch P1 is the second edge EP2. The edge extending over the end will be referred to as a fourth edge EP4. In the step of cutting the suspension lead SL1, the suspension lead is cut by the first edge portion EP1, the frame portion FP1 is cut by the third edge portion EP3 and the fourth edge portion EP4, and the second edge portion EP2 is cut. The lead frame LF1 is passed from one surface side to the other surface side through the slit ST1. Details will be described below.

  As shown in FIG. 1B, the mold for cutting the suspension lead SL1 has a device receiving portion DSP1, a die D1, and a punch P1. The device receiver DSP1 supports the main body MP1 of the semiconductor device SD1. The die D1 supports the frame portion FP1 of the lead frame LF1. A discharge hole EH1 is formed between the die D1 and the device receiving portion DSP1 to discharge the cut waste CW1 (FIG. 1C). The discharge hole EH1 also serves as a movement area of the punch P1 after punching the lead frame LF1.

  In FIG. 1A, the outline of the punch P1 in plan view is indicated by a dotted line. Moreover, the outline in the planar view of die | dye D1 is shown with the broken line thicker than this dotted line.

  A concave portion CP1 that defines the shape of the discharge hole EH1 is formed on the side surface of the die D1 on the semiconductor device SD1 side (device receiving portion DSP1 side). The punch P1 is located in the recess CP1 (that is, in the discharge hole EH1) in plan view. Therefore, the die D1 does not have a cutting edge that cuts the lead frame LF1 in cooperation with the first edge EP1 of the punch P1. The reason for this is that there is no space for installing the die D1 having sufficient strength in the vicinity of the first edge EP1 in connection with the mold and the semiconductor device SD1, and even if it can be temporarily installed, the suspended lead after cutting This is because the problem that the base end portion of SL1 remains in a state of protruding from the side surface of the main body portion MP1 occurs.

  The punch P1 is held by a pressing device (not shown) and is moved up and down linearly by the pressing device.

  In addition, as shown in FIG. 2, it is preferable that the metal mold | die has stripper plate SP1. The stripper plate SP1 guides the punch P1 when the punch P1 moves up and down, and peels off the cutting waste CW1 generated by punching the lead frame LF1 from the punch P1.

  The lead frame LF1 is made of a metal such as copper or a copper alloy. As shown in FIG. 4A and FIG. 4B, the lead frame LF1 has a plurality of product components PSP1 each serving as a part of the semiconductor device SD1 in an array arrangement. As shown in FIG. 4C, each product component PSP1 has a chip connection part CCP1, a frame part FP1, a plurality of leads L1, and a suspension lead SL1.

  The slit ST1 is formed at a position on the extension of the suspension lead SL1 with the chip connection portion CCP1 as a reference. The planar shape of the slit ST1 is, for example, a rectangular shape. More specifically, for example, the slit ST1 has a long rectangular shape in a direction orthogonal to the extending direction of the suspension lead SL1. That is, in the plane of the lead frame LF1, the slit ST1 in the direction orthogonal to the extending direction of the suspension lead SL1 is longer than the length W2 (FIG. 1A) of the slit ST1 in the extending direction of the suspension lead SL1. Is longer (width W1 (FIG. 1A)).

  The semiconductor device SD1 includes a chip connection portion CCP1, a semiconductor chip SC1 having an electrode E1, a plurality of leads L1, a wire WR1 electrically connecting the electrode E1 and the lead L1 of the semiconductor chip SC1, and a sealing. Resin ER1. One surface of the semiconductor chip SC1 is connected to one surface of the chip connection portion CCP1 through an adhesive layer such as silver paste. The electrode E1 of the semiconductor chip SC1 is formed on the surface opposite to the one surface of the semiconductor chip SC1. The formation region of the sealing resin ER1 in the semiconductor device SD1 is the main body MP1 of the semiconductor device SD1.

  The sealing resin ER1 seals the chip connection portion CCP1, the semiconductor chip SC1, and the wire WR1. A part of the suspension lead SL1 (a part on the chip connection part CCP1 side) is embedded in the sealing resin ER1, and constitutes a part of the semiconductor device SD1. A part of the lead L1 (a part on the chip connection part CCP1 side: an inner lead) is embedded in the sealing resin ER1. The other part (outer lead) of the lead L1 protrudes outside the sealing resin ER1. For example, the lead L1 protrudes outward from the side surface of the sealing resin ER1. A dam bar portion DB1 is formed at the base end side portion of the outer lead. The sealing resin ER1 includes a dam resin portion DR1 (FIG. 1) formed to slightly protrude outward from the side surface.

  At the stage where the chip connection part CCP1, the semiconductor chip SC1, and the wire WR1 are sealed with the sealing resin ER1, the main body part MP1 is connected to the frame part FP1 of the lead frame LF1 via the suspension leads SL1 (for example, a pair). It is in a state. At this stage, the suspension lead SL1 protrudes outward from the side surface of the sealing resin ER1. After the resin sealing, the suspension lead SL1 is cut using the mold described above, and the main body MP1 and the frame part FP1 are separated.

  As shown in FIG. 1A, the punch P1 is a first edge EP1 that is an edge on the semiconductor chip side (semiconductor device SD1 side) and an edge that is opposite to the first edge EP1. 2 edges EP2. For example, the first edge portion EP1 and the second edge portion EP2 face each other in parallel. The first edge EP1 is provided with a recess CP2 for avoiding the punch P1 from interfering with the dam resin portion DR1.

  Further, the punch P1 includes a third edge EP3 that is an edge extending from one end of the first edge EP1 to one end of the second edge EP2, and other than the second edge EP2 from the other end of the first edge EP1. And a fourth edge EP4 which is an edge extending to the end.

  For example, the third edge portion EP3 and the fourth edge portion EP4 are flat surfaces, and the shapes of the third edge portion EP3 and the fourth edge portion EP4 in a plane orthogonal to the moving direction of the punch P1 are linear. It has become. For example, the third edge portion EP3 and the fourth edge portion EP4 face each other in parallel.

  The width W1 of the slit ST1 is longer than the width of the second edge EP2 in a plane orthogonal to the moving direction of the punch P1. Moreover, the second edge portion EP2 is disposed so as to be located in the slit ST1 in plan view.

  Here, in frame part FP1, it is preferable that the length of the part cut | disconnected by 3rd edge part EP3 and the length of the part cut | disconnected by 4th edge part EP4 are mutually equal. In order to make these lengths equal to each other, an edge EP5 on the semiconductor chip side (semiconductor device SD1 side) in the slit ST1, an inner peripheral edge IC1 on the semiconductor chip SC1 side (semiconductor device SD1 side) in the frame portion FP1, Need only be linear and parallel to each other in plan view.

  In the plane orthogonal to the movement direction of the punch P1, the lengths of the first edge portion EP1 and the second edge portion EP2 are preferably longer than the lengths of the third edge portion EP3 and the fourth edge portion EP4.

  Within the surface of the lead frame LF1, the length W2 of the slit ST1 in the extending direction of the suspension lead SL1 and the distance W3 from the sealing resin ER1 to the slit ST1 of the semiconductor device SD1 are the strength of the lead frame LF1, the lead It can be arbitrarily set according to the size of the region desired to be punched in the frame LF1. Specifically, for example, W2 is practically about 0.5 mm to 1 mm, and W3 is practically about 2 mm to 3 mm. Moreover, it is preferable that W1: W2: W3 = about 5: 1: 3. For example, W1 can be 4 to 6 times W2, and W3 can be 2 to 4 times W2. These dimensions are SSOP (semiconductor device SD1) in which the length of the sealing resin ER1 is 6.1 mm, the length of the longitudinal direction is 9.7 mm, and the thickness of the lead frame LF1 is 0.15 mm. This is an appropriate value when manufacturing a Shrink Small Outline Package), and the present embodiment is not limited to these values. For example, when the semiconductor device is a QFP (Quad Flat Package), although the details are omitted, the same effect can be obtained by forming the rectangular slit ST1 as shown in FIG.

  The method of forming the slit ST1 in the lead frame LF1 includes a method of forming the slit ST1 from the design and manufacturing stage of the lead frame LF1, and a method of forming the slit ST1 by punching with a press die in the manufacturing process of the semiconductor device. .

  In the step of cutting the suspension lead SL1 with the punch P1, the suspension lead SL1 is cut with the first edge portion EP1, and the frame portion FP1 is cut with the third edge portion EP3 and the fourth edge portion EP4. At this time, the second edge portion EP2 passes through the slit ST1 from one surface side (the upper side of FIGS. 1B and 1C) to the other surface side (FIGS. 1B and 1C). The shape, size and arrangement of the slit ST1 and the punch P1 are set so as to pass to the lower side.

  Thereby, since the second edge EP2 of the punch P1 does not contribute to the cutting process of the lead frame LF1, the clearance between the punch P1 and the die D1 can be sufficiently increased only in the second edge EP2. .

  For example, in the plane orthogonal to the moving direction of the punch P1, the third edge EP3 and the fourth edge EP4 have the same length, and the length of the second edge EP2 is, for example, the third edge. The length is set to about 1.2 to 2.0 times the length of EP3 and the fourth edge EP4. Thereby, the rigidity of the punch P1 can be sufficient with respect to the load received by the punch P1 from the lead frame LF1 when the lead frame LF1 is cut.

  Hereinafter, an example of a series of manufacturing steps of the present embodiment will be described.

First, for example, the semiconductor chip SC1 is manufactured by the following procedure.
First, an element isolation film is formed on a semiconductor substrate. Thereby, the element formation region is separated. The element isolation film is formed using, for example, the STI method, but may be formed using the LOCOS method. Next, a gate insulating film and a gate electrode are formed in a portion located in the element formation region in the semiconductor substrate. The gate insulating film may be a silicon oxide film or a high dielectric constant film (for example, a hafnium silicate film) having a higher dielectric constant than that of the silicon oxide film. When the gate insulating film is a silicon oxide film, the gate electrode is formed of a polysilicon film. When the gate insulating film is a high dielectric constant film, the gate electrode is formed of a laminated film of a metal film (for example, TiN) and a polysilicon film. When the gate electrode is formed of polysilicon, a polysilicon resistor may be formed on the element isolation film in the step of forming the gate electrode.

  Next, source and drain extension regions are formed in a portion of the semiconductor substrate located in the element formation region. Next, sidewalls are formed on the sidewalls of the gate electrode. Next, impurity regions serving as a source and a drain are formed in a portion located in the element formation region in the semiconductor substrate. In this way, a MOS transistor is formed on the semiconductor substrate.

  Next, a multilayer wiring layer is formed on the element isolation film and the MOS transistor. In the uppermost wiring layer, an electrode pad (that is, the electrode E1) is formed. Next, a protective insulating film (passivation film) is formed on the multilayer wiring layer. An opening located on the electrode pad is formed in the protective insulating film.

  Thereafter, the semiconductor chip SC1 is obtained by dividing the wafer into individual pieces.

  On the other hand, a lead frame LF1 in which the slit ST1 as described above is formed is prepared.

  Next, one surface of the semiconductor chip SC1 is bonded and fixed to one surface of the chip connection portion CCP1 of the lead frame LF1 using, for example, an adhesive such as Ag paste.

  Next, the electrode E1 and the lead L1 of the semiconductor chip SC1 are electrically connected to each other via the wire WR1 (wire bonding is performed).

  Next, the chip connection portion CCP1, the semiconductor chip SC1, and the wire WR1 are sealed with a sealing resin ER1 made of an insulating resin (FIG. 5). The sealing resin ER1 is formed such that the portion on the chip connection portion CCP1 side in the suspension lead SL1 and the portion on the chip connection portion CCP1 side in the lead L1 are embedded in the sealing resin ER1. At this time, the sealing resin ER1 is formed to include the dam resin portion DR1 (FIG. 1).

  Thereafter, the lead L1 is plated as necessary. Further, a portion (outer lead) protruding from the sealing resin ER1 in the lead L1 is bent into a desired shape such as a gull wing shape.

  Next, as shown in FIG. 1, the semiconductor device SD1 and the lead frame LF1 are set in a mold. That is, the main body portion MP1 of the semiconductor device SD1 is placed on the device receiving portion DSP1, and the frame portion FP1 is placed on the die D1. FIG. 5 shows a planar positional relationship between the lead frame LF1 and the punch P1.

Next, the punch P1 is lowered and the suspension lead SL1 is cut by the first edge EP1 of the punch P1. This cutting is performed by the first edge portion EP1 pushing down a portion in the vicinity of the suspension lead SL1 in the frame portion FP1. At this time, the suspension lead SL1 is sheared so as to be torn off starting from the front side and the back side of the base end portion of the portion protruding from the sealing resin ER1.
Further, the suspension lead SL1 is cut, and the portion between the inner peripheral edge IC1 and the slit ST1 in the frame portion FP1 is cut by the third edge portion EP3 and the fourth edge portion EP4 of the punch P1, respectively. This cutting is performed by the cooperation of the punch P1 and the die D1.
By these cuttings, the suspension lead SL1 and the portion in the vicinity of the suspension lead SL1 in the frame portion FP1 can be integrally punched. Thereby, the main body MP1 of the semiconductor device SD1 and the frame part FP1 of the lead frame LF1 can be separated.
The punch P1 is preferably provided with a shear angle so that the first edge portion EP1 first contacts the lead frame LF1.

  In this cutting process, the second edge EP2 of the punch P1 passes through the slit ST1 and passes from one side of the lead frame LF1 (the upper side of FIGS. 1B and 1C) to the other side ( 1 (b) and (c) lower side). That is, the second edge portion EP2 does not cut the lead frame LF1.

  Thus, the semiconductor device SD1 is obtained.

  The manufacturing process of the semiconductor device SD1 according to this embodiment is not limited to the above example. For example, the suspension lead SL1 may be cut before the main body MP1 and the frame FP1 are separated, and the main body MP1 may be held by the frame FP1 via the outer lead after the cutting. .

  Here, with reference to FIG. 7 thru | or FIG. 9, the manufacturing method of the semiconductor device which concerns on a comparative example is demonstrated. FIG. 7 is a schematic diagram for explaining a method of manufacturing a semiconductor device according to a comparative example. 7A is a plan view, and FIG. 7B and FIG. 7C are side sectional views taken along line AA in FIG. 7A. 8 and 9 are schematic cross-sectional side views for explaining problems in the method of manufacturing a semiconductor device according to the comparative example.

  The semiconductor device manufacturing method according to the comparative example is the semiconductor device according to this embodiment only in that the slit ST1 is not formed in the lead frame LF1, and the second edge EP2 of the punch P1 cuts the frame portion FP1. This is different from the manufacturing method.

  In the case of the comparative example, when the lead frame LF1 is cut including the suspension lead SL1, the punch P1 is bent toward the semiconductor device SD1, so that the clearance between the punch P1 and the die D1 is easily increased. As a result, as described below, various problems that lead to a decrease in productivity and quality of the semiconductor device occur.

First, when the lead frame LF1 is cut while the clearance between the punch P1 and the die D1 is enlarged, a large cutting beam is generated at the cut portion of the lead frame LF1, as shown in part E of FIG. Resulting in.
When the lead frame LF1 is appropriately cut, the cutting waste CW1 generated by the cutting smoothly passes through the discharge hole EH1 formed in the lower mold of the mold and is discharged to the outside of the mold. However, when a large cutting beam occurs, a phenomenon called so-called “cass clogging” occurs in which the cutting beam is caught in the discharge hole EH1 and the cutting waste CW1 remains in the discharge hole EH1. It is difficult to detect scum clogging. If the mold is operated in a state where the clogging occurs, the punch P1 and the die D1 may be damaged.

  Further, in a state where the clearance between the punch P1 and the die D1 is enlarged, a part of the lead frame LF1 cannot be cut, and a phenomenon of deforming the lead frame LF1 also occurs.

  Further, in a state where the lead frame LF1 is deformed, the semiconductor device SD1 is likely to be misaligned when the semiconductor device SD1 is placed on the device receiver DSP1. If cutting is performed in a state where the position of the semiconductor device SD1 is shifted, the punch P1 may come into contact with the sealing resin ER1, and the semiconductor device SD1 and the mold may be damaged.

  Further, as shown in FIG. 9, the punch P1 is bent toward the semiconductor device SD1 to cause an unintended contact between the punch P1 and the dam resin portion DR1, and as a result, resin scraps adhere to the semiconductor device SD1. There is also a case where it ends up. Even if the concave portion CP2 is formed on the punch P1 as described above in order to avoid contact between the punch P1 and the dam resin portion DR1, the generation of resin waste due to the contact between the punch P1 and the dam resin portion DR1 occurs. there is a possibility.

  Further, by cutting the lead frame LF1 with the clearance between the punch P1 and the die D1 enlarged, normal lead frame cutting cannot be performed, and the lead frame surface is formed by plating as shown in FIG. In some cases, the metal film MF1 is rubbed against the side surface of the dam resin portion DR1 during the cutting process. In this case, conductive foreign matter adheres to the semiconductor device SD1, which is a serious problem in terms of quality of the semiconductor device SD1.

  Further, when the lead frame LF1 is cut by the second edge portion EP2, as shown in FIG. 8, a thrust load that deflects the punch P1 toward the semiconductor device SD1 is generated.

It is known that this thrust load is a value obtained by multiplying the cutting load by a constant. Specifically, for example, the length of the second edge EP2 in a plane orthogonal to the traveling direction of the punch P1 is 4.0 mm, and the lead frame LF1 is made of a copper material having a plate thickness of 0.15 mm. The thrust load will be about 3.6 kgf. The material of the punch P1 is a super hard metal (longitudinal elastic modulus of about 54,000 kgf / mm ² ), and the third edge EP3 and the fourth edge EP4 in a plane orthogonal to the traveling direction of the punch P1. Assume that the length is 3.0 mm. Further, it is assumed that the punch P1 is inserted and fixed to a punch plate (not shown), and the protruding length of the punch P1 downward from the punch plate is 25.0 mm.
In this case, when a thrust load of 3.6 kgf is applied to the punch P1, the amount of displacement of the tip of the punch P1 due to bending is considered to be about 0.04 mm according to the cantilever calculation formula. Further, an appropriate value of the clearance between the punch P1 and the die D1 is 0.015 mm if it is 10% of the thickness of the lead frame LF1. Therefore, normal lead cutting is impossible under the situation where the above-described deflection due to the thrust load occurs.

  Therefore, generally, a method is employed in which the punch P1 is guided and the bending of the punch P1 is suppressed by providing the stripper plate SP1 (see FIG. 2) positioned with high accuracy. However, in this method, the punch P1 that has received a thrust load slides up and down with respect to the stripper plate SP1 every time processing is performed, so that the punch guide surface of the stripper plate SP1 is easily worn. As a result, the effect of suppressing the bending of the punch P1 is gradually lost.

  Further, in order to accurately position the stripper plate SP1, a method of installing a stripper guide post and a stripper guide bush in addition to a main post and a main bush for positioning the upper mold and the lower mold of the mold is the mainstream. However, there are also inconveniences that the cost of mold production rises due to an increase in the number of parts and difficulty in positioning and adjustment.

  As described above, in the semiconductor device manufacturing method according to the comparative example, the punch P1 is bent toward the semiconductor device SD1 due to the thrust load generated when the lead frame LF1 is cut, so that the punch P1 and the die at the second edge EP2 The clearance with D1 is easy to expand, and various problems as described above occur.

  On the other hand, in the present embodiment, as described above, in the step of cutting the suspension lead SL1, the suspension lead SL1 is cut by the first edge EP1 of the punch P1, and on the side opposite to the first edge EP1. The second edge EP2 that is positioned does not cut the lead frame LF1, but passes through the slit ST1. Thus, it is possible to suppress the generation of a thrust load that causes the punch P1 to bend toward the semiconductor device SD1 when the suspension lead SL1 is cut. As a result, the clearance between the punch P1 and the die D1 can be maintained with high accuracy. Therefore, generation | occurrence | production of the various problems in the comparative example mentioned above can be suppressed.

In this embodiment, since the bending of the punch P1 toward the semiconductor device SD1 can be suppressed, the guide of the punch P1 by the stripper plate SP1 is not so important. For this reason, wear of the stripper plate SP1 due to friction with the punch P1 can be suppressed, and also from this, the clearance between the punch P1 and the die D1 can be maintained with high accuracy for a long time.
In addition, since the guide of the punch P1 by the stripper plate SP1 is not important, the installation of the stripper guide post and the stripper guide bush can be omitted. Therefore, it is possible to simplify the structure of the mold.

  Moreover, since slit ST1 is rectangular shape, it can suppress that the cutting waste CW1 becomes an irregular shape. Therefore, the cutting waste CW1 can be smoothly discharged through the discharge hole EH1.

In the punch P1, the frame part FP1 of the lead frame LF1 is cut only at the third edge part EP3 and the fourth edge part EP4 that face each other.
Since the third edge portion EP3 and the fourth edge portion EP4 face each other in parallel, the thrust loads generated at the third edge portion EP3 and the fourth edge portion EP4 can be opposite to each other. Therefore, these thrust loads can be offset each other.
In particular, in the frame part FP1, since the length of the part cut by the third edge part EP3 and the length of the part cut by the fourth edge part EP4 are equal to each other, the third edge part EP3 and the fourth edge part EP4 The generated thrust loads are equal to each other. For this reason, these thrust loads are almost completely offset and can be ignored.
Note that the edge EP5 on the semiconductor chip SC1 side in the slit ST1 and the inner peripheral edge IC1 on the semiconductor chip SC1 side in the frame FP1 are parallel to each other, so that the frame FP1 is cut by the third edge EP3. The length of the portion and the length of the portion cut by the fourth edge EP4 can be made equal to each other.

  Further, in the plane orthogonal to the moving direction of the punch P1, the lengths of the first edge portion EP1 and the second edge portion EP2 are longer than the lengths of the third edge portion EP3 and the fourth edge portion EP4. Thereby, the rigidity of the punch P1 can be sufficient with respect to the load received by the punch P1 from the lead frame LF1 when the lead frame LF1 is cut.

  Further, in the plane of the lead frame LF1, the length W1 of the slit ST1 in the direction orthogonal to the extending direction of the suspension lead SL1 is larger than the length W2 of the slit ST1 in the extending direction of the suspension lead SL1. long. This facilitates the second edge EP2 of the punch P1 with the first edge EP1 and the second edge EP2 being longer than the third edge EP3 and the fourth edge EP4 through the slit ST1. Can be passed through.

<Modification>
FIG. 6 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to a modification.

  In the above embodiment, the example in which the semiconductor device SD1 is the SSOP has been described. However, in the modification, the semiconductor device SD1 is a QFP (Quad Flat Package). In this case, a slit ST1 is formed in the lead frame LF1 in an arrangement as shown in FIG. As a result, the same effects as those of the first embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

CCP1 Chip connection part CP1 Concave part CP2 Concave part CW1 Cutting waste D1 Die DB1 Dam bar part DR1 Dam resin part DSP1 Device receiving part E1 Electrode EH1 Discharge hole EP1 First edge part EP2 Second edge part EP3 Third edge part EP4 Fourth edge part EP5 Edge portion ER1 Sealing resin FP1 Frame portion IC1 Inner peripheral edge L1 Lead LF1 Lead frame MF1 Metal film MP1 Main body portion P1 Punch PSP1 Product component SC1 Semiconductor chip SD1 Semiconductor device SL1 Hanging lead SP1 Stripper plate ST1 Slit WR1 Wire

Claims (10)

A chip connection part in which one surface of the semiconductor chip is connected to one side; a frame part arranged around the chip connection part; one end connected to the frame part and the other end to the chip connection part A suspension lead connected to the frame, and preparing a lead frame in which a slit is formed at a position on the extension of the suspension lead with respect to the chip connection portion in the frame portion;
Connecting the one surface of the semiconductor chip to the one surface of the chip connecting portion;
A step of resin-sealing the semiconductor chip;
Cutting the suspension lead with the punch in a state where the frame portion is supported by the die of a die having a die and a punch;
Have
In the plane of the lead frame, the width of the slit in the direction orthogonal to the extending direction of the suspension lead is wider than the width of the punch,
The edge of the punch on the side of the semiconductor chip is a first edge, the edge of the punch opposite to the first edge is a second edge, and the first edge of the punch from one end of the first edge. When the edge extending from one end of the two edges is the third edge, and the edge extending from the other end of the first edge to the other end of the second edge in the punch is the fourth edge,
In the step of cutting the suspension lead, the suspension lead is cut by the first edge portion, the frame portion is cut by the third edge portion and the fourth edge portion, and the second edge portion is A method of manufacturing a semiconductor device, wherein the lead frame is passed from one surface side to the other surface side through the slit.   The method of manufacturing a semiconductor device according to claim 1, wherein the slit is rectangular.   The method for manufacturing a semiconductor device according to claim 1, wherein the third edge portion and the fourth edge portion face each other in parallel.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a length of a portion cut by the third edge portion and a length of a portion cut by the fourth edge portion are equal to each other in the frame portion.   The length of the first edge portion and the second edge portion is longer than the length of the third edge portion and the fourth edge portion in a plane perpendicular to the moving direction of the punch. The manufacturing method of the semiconductor device of description.   The length of the slit in the direction orthogonal to the extending direction of the suspension lead is longer in the plane of the lead frame than the length of the slit in the extending direction of the suspension lead. The manufacturing method of the semiconductor device of description. A chip connection part in which one side of the semiconductor chip is connected to one side;
A frame portion arranged around the chip connection portion;
A suspension lead having one end connected to the frame portion and the other end connected to the chip connection portion;
A slit formed at a position on the extension of the suspension lead with respect to the chip connection portion in the frame portion;
Have
The suspension lead is cut by the punch of a mold having a punch,
The width of the slit in the direction orthogonal to the extending direction of the suspension lead is wider than the width of the punch,
The edge of the punch on the side of the semiconductor chip is a first edge, the edge of the punch opposite to the first edge is a second edge, and the first edge of the punch from one end of the first edge. When the edge extending from one end of the two edges is the third edge, and the edge extending from the other end of the first edge to the other end of the second edge in the punch is the fourth edge,
The slit is arranged such that when the first edge portion cuts the suspension lead and the third edge portion and the fourth edge portion cut the frame portion, the second edge portion passes through the slit. The lead frame is arranged.   The lead frame according to claim 7, wherein the slit is rectangular.   The lead frame according to claim 7, wherein an edge of the slit on the semiconductor chip side and an inner peripheral edge of the frame on the semiconductor chip side are parallel to each other.   The length of the slit in the direction orthogonal to the extending direction of the suspension lead is longer in the plane of the lead frame than the length of the slit in the extending direction of the suspension lead. The described lead frame.

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