JP2013229722A - Load control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a load control device that prevents generation of radiation/conduction noise by avoiding turning on/off a switch via a pulse signal with such a duty ratio that fails in completely turning off the switch.SOLUTION: A first comparator 7 outputs a normally L level DC signal when a supply voltage VI is not more than a predetermined value, and if the predetermined value is exceeded, outputs a first pulse signal with a duty ratio increasing with increasing supply voltage VI. As the first comparator 7 outputs the first pulse signal, a second pulse signal output circuit 8 outputs a second pulse signal with a constant duty ratio. An OR gate 9 selects one of the first pulse signal and the second pulse signal which has the longer H level period, and uses the selected pulse signal for controlling on/off a FET.

Description

  The present invention relates to a load control device, and more particularly to a load control device that controls a load based on a duty.

  When an abnormality occurs due to a failure of an automobile power generation device or the like, the power supply voltage of a battery generally in the range of 12V to 14.5V may rise to 16V or more. At this time, since the power supply voltage supplied to the load also rises, there is a problem that the effective voltage with respect to the load rises and power is supplied to the load more than necessary. For example, when the effective voltage supplied to the lamp as a load increases, the life of the lamp is shortened, or when the lamp is irradiated with an illuminance that is more than necessary, the irradiated person feels very dazzling.

  Therefore, when the power supply voltage of the battery exceeds a predetermined value, the control of the switch for turning on / off the power supply to the load is switched from the DC signal to the pulse signal, and the duty ratio of the ON period of the switch is lowered as the power supply voltage increases. A load control device that outputs a pulse signal has been considered (Patent Document 1).

  As the load control device described above, for example, a power supply device as shown in FIG. 5 has been proposed. As shown in the figure, a power supply device 1 includes a lamp 2 as a load, a battery 3 as a power source for supplying power to the lamp 2, and a switch provided between the lamp 2 and the battery 3. A field effect transistor (hereinafter abbreviated as “FET”) 4, and a load control device 5 that controls the supply of power supply voltage from the battery 3 to the lamp 2 by controlling on / off of the FET 4.

  The load control device 5 compares a triangular wave generator 6 (periodic signal generator) for generating a triangular wave, a triangular wave VT generated by the triangular wave generator 6 and a voltage Vk1 corresponding to the power supply voltage VI of the power supply 3. 1 comparator 7 and an FET drive circuit 10 that shifts the output V1 of the first comparator 7 to a level at which the FET 4 can be turned on and off.

  According to the configuration described above, when the FET 4 is turned on / off using the output V1 of the first comparator 7, for example, as shown in FIG. 6, the FET 4 is always turned on when the power supply voltage VI is 12V or less (duty ratio 100). %). When the power supply voltage VI exceeds 12V, the FET 4 is intermittently turned on, and thereafter, the duty ratio of the ON period of the FET 4 gradually decreases as the power supply voltage VI rises. As a result, the effective voltage with respect to the lamp 2 can be suppressed even if the power supply voltage VI increases.

  As described above, since the on / off control of the FET 4 is performed using the output V1 from the first comparator 7, when the power supply voltage VI rises above a predetermined value, the duty ratio continuously decreases as the power supply voltage VI rises. For this reason, when the power supply voltage VI is slightly higher than the predetermined voltage, the FET 4 is turned on / off with a high duty ratio of 99% and 98%. While the FET 4 is turned on / off at this high duty ratio, the off-period of the FET 4 is very short, and the power supply voltage VI supplied to the lamp 2 is reduced by turning off the FET 4 as shown in FIG. 7B. There is a case where the ON period is reached before it becomes 0 completely, and the FET 4 is not completely turned off. When such a state occurs, there is a problem that radiation / conduction noise increases rapidly, and malfunction of other devices is a concern. When the power supply voltage VI is increased to some extent and the duty ratio is decreased, the power supply voltage supplied to the lamp 2 is completely zero by turning off the FET 4 as shown in FIG. 7A.

JP 2009-65246 A

  Accordingly, an object of the present invention is to provide a load control device that prevents radiation / conduction noise from occurring by preventing the switch from being turned on / off with a pulse signal having a duty ratio that does not completely turn off the switch. .

  The invention according to claim 1 for solving the above-mentioned problem is a load control device for controlling a switch provided between a load and a power supply, and periodically increases or decreases between an upper limit value and a lower limit value. A periodic signal generator for generating a periodic signal, and a first comparator for comparing the periodic signal generated by the periodic signal generator with a power supply voltage of the power supply or a voltage corresponding to the power supply voltage, In the load control device, wherein the first comparator outputs a DC signal while the power supply voltage is less than a predetermined value, and outputs a first pulse signal when the power supply voltage exceeds the predetermined value. A second pulse signal output means for outputting a second pulse signal having a constant duty ratio when the value is equal to or greater than the value, and when the first pulse signal and the second pulse signal are input, one of them is selected, and the selected pulse signal Using Selection means for performing on / off control of the switch, and the first pulse signal has a duty ratio of an on period of the switch according to an increase in the power supply voltage when the switch is on / off controlled using the signal. The one of the signals selected by the selecting means is turned on / off using the other signal that is not selected when the switch is turned on / off using the one signal. The load control apparatus is characterized in that the signal is such that the off-period of the switch is longer than in the case where the switch is off.

  According to a second aspect of the present invention, the second pulse signal output means compares the periodic signal generated by the periodic signal generator with a voltage that internally divides the upper limit value and lower limit value of the periodic signal. The load control device according to claim 1, comprising two comparators.

  According to a third aspect of the present invention, the second pulse signal output means includes a flip-flop in which an output of the first comparator is input to a set terminal, and an output of the flip-flop and an output of the second comparator are input. The load control apparatus according to claim 2, further comprising: a first logic gate that outputs the second pulse signal.

  The invention according to claim 4 is characterized in that the selection means comprises a second logic gate to which an output from the second pulse signal output means and an output of the first comparator are inputted. It exists in the load control apparatus of any one of Claims 1-3.

  As described above, according to the first aspect of the present invention, when the duty ratio is such that the first pulse signal does not completely turn off the switch, the switch is turned on / off using the second pulse signal rather than the first pulse signal. Since the switch off period becomes longer when the control is performed, the second pulse signal is selected by the selection means. On the other hand, when the duty ratio is such that the first pulse signal completely turns off the switch, the switch off period is longer when the switch is turned on / off using the first pulse signal than the second pulse signal. The first pulse signal is selected by the means. Therefore, the switch is not turned on / off by a pulse signal having a duty ratio that does not completely turn off the switch, and the generation of radiation / conduction noise can be prevented.

  According to the second aspect of the present invention, the second pulse signal output means compares the periodic signal generated by the periodic signal generator with a voltage that internally divides the upper limit value or lower limit value of the periodic signal. Since the comparator is provided, the second pulse signal having the same period as the first pulse signal can be easily output.

  According to the invention described in claim 3, the second pulse signal output means can be easily provided from the flip-flop and the first logic gate.

  According to the fourth aspect of the present invention, the selecting means can be easily provided from the second logic gate.

It is a circuit diagram showing one embodiment of a power supply device incorporating a load control device of the present invention. It is an electric circuit diagram which shows the detail of the load control apparatus shown in FIG. (A) to (G) are the power supply voltage VI, the triangular wave VT and the voltage Vk1, the output V1 of the first comparator, the output V2 of the second comparator, the output of the flip-flop, the output of the NOR gate, and the output of the OR gate. It is a time chart. 2 is a graph showing an effective voltage with respect to a power supply voltage and a duty ratio of an ON period of the FET shown in FIG. 1 according to the present embodiment. It is a circuit diagram which shows an example of the power supply device incorporating the conventional load control apparatus. It is a graph which shows the effective voltage with respect to the conventional power supply voltage, and the duty ratio of the ON period of FET shown in FIG. (A) And (B) is a graph for demonstrating the problem of the power supply device shown in FIG.

  Hereinafter, a power supply apparatus incorporating the load control apparatus of the present invention will be described with reference to FIGS. As shown in FIG. 1, a power supply device 1 is provided between a lamp 2 as a load, a battery 3 as a power source for supplying power to the lamp 2, and between the lamp 2 and the battery 3. FET 4 as a switch for turning on and off the power supply to 2, and a load control device 5 for controlling the supply of the power supply voltage VI from the battery 3 to the lamp 2 by controlling on and off of the FET 4.

  The FET 4 is a P-channel FET, the source of which is connected to the + side of the in-vehicle battery 3, the drain of which is connected to the lamp 2, and the gate of which is connected to the load control device 5. The FET 4 is turned on when the L level is supplied to the gate and the power is supplied to the lamp 2, and is turned off when the H level is output to the gate and the power supply to the lamp 2 is cut off. As shown in FIG. 2, the load control device 5 is made into an IC and includes a power input terminal TP, an output terminal TO, and a ground terminal TG. In the present embodiment, an example in which the entire load control device 5 is integrated will be described. However, the present invention is not limited to this, and only a part of the load control device 5 may be integrated.

  The power input terminal TP is connected to the positive side of the battery 3. The output terminal TO is connected to the gate of the FET 4. The ground terminal TG is connected to the negative side of the battery 3. Note that the negative side of the battery 3 is connected to the ground.

  The load control device 5 includes a triangular wave generator 6 as a periodic signal generator generated by generating a triangular wave VT from the power supply voltage VI supplied to the lamp 2, and the triangular wave VT generated by the triangular wave generator 6 and the power supply voltage. A first comparator 7 for comparing with a voltage Vk1 corresponding to VI.

  The triangular wave generator 6 includes, for example, a capacitor, a first current mirror circuit that charges the capacitor with a constant charge current, a second current mirror circuit that discharges the capacitor with a constant discharge current, and both ends of the capacitor have upper limit values. When it exceeds, the output is inverted from L level to H level, and when both ends of the capacitor are below the lower limit value, the output is inverted from H level to L level, and the capacitor is charged when the output of the hysteresis comparator is L level. This is a known triangular wave generator provided with a charge / discharge control circuit (none of which is shown) for discharging the capacitor when it is at the H level. Then, a triangular wave VT as a periodic signal that periodically increases and decreases between an upper limit value and a lower limit value is generated in a voltage across a capacitor (not shown) of the triangular wave generator 6. In the present embodiment, the upper limit value and the lower limit value are obtained by dividing the power supply voltage VI and supplying it to the hysteresis comparator, so that the upper limit value Va and the lower limit value Vb of the triangular wave are as shown in FIG. The power supply voltage VI rises as it rises.

In the first comparator 7, a voltage Vk1 corresponding to the power supply voltage VI is input to the + terminal, and a triangular wave VT is supplied to the-terminal. The voltage Vk1 is a voltage obtained by dividing the power supply voltage VI by the Zener diode ZD and the first resistor R1. Therefore, when the power supply voltage VI is equal to or lower than the breakdown voltage of the Zener diode ZD, almost no current flows through the Zener diode ZD, and the voltage Vk1 becomes zero. On the other hand, when the power supply voltage VI exceeds the breakdown voltage of the Zener diode ZD, the voltage Vk1 has a value represented by the following formula (1).
Vk1 = VI−VZD (1)

  The VZD is a Zener voltage and is constant regardless of the increase or decrease of the power supply voltage VI. As is apparent from the equation (1), when the power supply voltage VI becomes equal to or higher than the breakdown voltage of the Zener diode ZD, the voltage Vk1 becomes a value corresponding to the power supply voltage VI, and as shown in FIG. As the voltage rises, the voltage Vk1 also rises. The rate of increase of voltage Vk1 at this time is greater than the rate of increase of upper limit value Va and lower limit value Vb of triangular wave VT.

  As shown in FIGS. 3B and 3C, the first comparator 7 compares the voltage Vk1 with the triangular wave VT, and outputs an L level when the voltage Vk1 is lower than the triangular wave VT. When it exceeds the triangular wave VT, H level is output. Accordingly, as shown in FIGS. 3A to 3C, the first comparator 7 always outputs an L level DC signal while the power supply voltage VI is less than a predetermined value, and the power supply voltage VI is equal to or higher than the predetermined value. Then, the voltage Vk1 exceeds the lower limit value Vb of the triangular wave VT, and the first pulse signal whose duty ratio increases as the power supply voltage VI increases is output. As described above, the FET 4 is turned on when the L level is supplied to the gate, and is turned on when the H level is supplied. Therefore, the DC signal always at the L level output from the first comparator 7 always turns on the FET 4. The first pulse signal is a pulse signal that reduces the duty ratio of the on-period of the FET 4 as the power supply voltage VI increases.

  Further, as shown in FIG. 2, the load control device 5 includes a second pulse signal output circuit as second pulse signal output means for outputting a second pulse signal having a constant duty ratio when the power supply voltage VI becomes a predetermined value or more. 8, a selection means for selecting a pulse signal having a longer H level period when a first pulse signal and a second pulse signal are input, and performing on / off control of the FET 4 using the selected pulse signal; An OR gate 9 as a logic gate and an FET drive circuit 10 that shifts the output of the OR gate 9 to a level at which the FET 4 can be turned on and off are provided.

  The second pulse signal output circuit 8 compares the voltage dividing circuit 11 that outputs the voltage Vk2 obtained by dividing the power supply voltage VI with the triangular wave VT generated by the triangular wave generator 6 and the voltage Vk2, and compares the comparison result. The second comparator 12 to be output, the flip-flop 13 to which the output V1 of the first comparator 7 is input to the set terminal S, the output V3 of the flip-flop 13 and the output V2 of the second comparator 12 to be input And a NOR gate 14 as two logic gates.

  The voltage dividing circuit 11 includes a second resistor R2 and a third resistor R3 connected in series with each other between the power supply voltages VI, and a voltage Vk2 obtained by dividing the power supply voltage VI with the second resistors R2 and R3. Output as (= VI × R3 / (R2 + R3)). The voltage Vk2 increases as the power supply voltage VI increases, and becomes a voltage that internally divides the upper limit value Va and the lower limit value Vb of the triangular wave.

  As shown in FIG. 3D, the second comparator 12 compares the voltage Vk2 with the triangular wave VT, outputs an H level when the voltage Vk2 is lower than the triangular wave VT, and the voltage Vk2 exceeds the triangular wave VT. And L level are output. Therefore, as described above, the voltage Vk2 is a voltage that internally divides the upper limit value Va and the lower limit value Vb of the triangular wave VT, so that the third pulse signal having a constant duty ratio is output from the output V2 of the second comparator 12. Is output. Since the third pulse signal is obtained by inputting the triangular wave VT input to the + terminal of the first comparator 7 to the − terminal of the second comparator 12, the center of the L level is the H level of the first pulse signal. The same as the center of

  As shown in FIG. 3E, when the power supply voltage VI becomes equal to or higher than a predetermined value and the first pulse signal is output from the first comparator 7, the flip-flop 13 inverts the output V3 from the H level to the L level. And maintain the L level. As shown in FIG. 3F, the NOR gate 14 maintains the L level while the output V3 of the flip-flop 13 outputs the H level, and the third output when the output V3 of the flip-flop 13 becomes the L level. A second pulse signal obtained by inverting the pulse signal is output. Since the second pulse signal is obtained by inverting the third pulse signal, the center of the H level is the same as the center of the H level of the first pulse signal.

  Next, the operation of the power supply device 1 having the above-described configuration will be described with reference to the time chart of FIG. Since the voltage Vk1 is smaller than the lower limit value Vb of the triangular wave VT while the power supply voltage VI is equal to or lower than a predetermined value, an L level DC signal is always output from the output V1 of the first comparator 7 (FIG. 3C). . Therefore, the H level is always output from the output V3 of the flip-flop 13 (FIG. 3E). On the other hand, the third pulse signal is output from the output V2 of the second comparator 12 (FIG. 3D). However, since the output V3 of the flip-flop 13 is always at the H level as described above, the NOR gate The second pulse signal is not output from the output V4 of 14, and the L level is always output (FIG. 3F). As a result, since the OR gate 9 is always supplied to the two inputs of the L level signal, the output V5 always outputs the L level signal (FIG. 3G), and the FET 4 is always turned on. .

  On the other hand, when the power supply voltage VI exceeds a predetermined value, the voltage Vk1 rises according to the power supply voltage VI. Therefore, the first pulse signal having a duty ratio according to the power supply voltage VI is output from the output V1 of the first comparator 7. (FIG. 3C). In response to the output of the first pulse signal, the output V3 of the flip-flop 13 is inverted from the H level to the L level and maintained at the L level (FIG. 3E). Therefore, a second pulse signal obtained by inverting the third pulse signal is output from the output V4 of the NOR gate 14 (FIG. 3 (F)).

  As a result, the first pulse signal and the second pulse signal are input to the OR gate 9. The OR gate 9 selects a pulse signal having a longer H level period from the first pulse signal and the second pulse signal, and performs on / off control of the FET 4 using the selected pulse signal.

  The duty ratio of the second pulse signal is set to such a value that the FET 4 is completely turned off when the second pulse signal is supplied to the gate of the FET 4. For example, assume that the duty ratio of the second pulse signal is constant, for example, 5% (= the duty ratio of the on period is 95% when the second pulse signal is supplied to the gate of the FET 4). While the power supply voltage VI is slightly higher than the predetermined value, the OR gate 9 selects the second pulse signal while the duty ratio of the first pulse signal is less than 5% of the second pulse signal. Output. On the other hand, when the power supply voltage VI greatly exceeds a predetermined value and the duty ratio of the first pulse signal exceeds 5% of the second pulse signal, the OR gate 9 selects and outputs the first pulse signal.

  As a result, even when the power supply voltage VI exceeds a predetermined value (12.5 V), the FET 4 is turned on / off using the second pulse signal while the duty ratio of the first pulse signal is less than 5%, and the first pulse When the duty ratio of the signal exceeds 5%, the FET 4 is turned on / off using the first pulse signal. Therefore, as shown in FIG. 4, the on period of the FET 4 is not turned on / off when the duty ratio is 95% or more. .

  According to the embodiment described above, when the duty ratio is such that the first pulse signal does not completely turn off the FET 4, the FET 4 is turned off by using the second pulse signal rather than the first pulse signal. Since the period becomes longer, the second pulse signal is selected by the OR gate 9. On the other hand, when the duty ratio is such that the first pulse signal completely turns off the FET 4, the FET 4 is turned on / off using the first pulse signal rather than the second pulse signal, and the off period of the FET 4 becomes longer. The first pulse signal is selected by the gate 9. For this reason, the FET 4 is not turned on / off by a pulse signal having a duty ratio that does not completely turn off the FET 4, and the generation of radiation / conduction noise can be prevented.

  According to the embodiment described above, the second pulse signal output circuit 8 compares the triangular wave VT generated by the triangular wave generator 6 with the voltage that internally divides the upper limit value Va or the lower limit value Vb of the triangular wave VT. Since the second comparator 12 is provided, a second pulse signal having the same period as the first pulse signal can be easily output.

  According to the embodiment described above, since the second pulse signal output circuit 8 further includes the flip-flop 13 and the NOR gate 14, it can be easily provided.

  According to the above-described embodiment, the selection means is composed of the OR gate 9, so that it can be easily provided.

  In the above-described embodiment, the triangular wave generator 6 that generates the triangular wave VT is used as the periodic signal generator. However, the present invention is not limited to this. For example, the periodic signal may be a signal that periodically increases or decreases between the upper limit value Va and the lower limit value Vb, and may be, for example, a sawtooth wave.

  In the above-described embodiment, the second pulse signal output circuit 8 includes the flip-flop 13 and the NOR gate 14, but the present invention is not limited to this. For example, a voltage Vk2 that is equal to or higher than the upper limit value Va of the triangular wave VT or lower than the lower limit value Vb is output until the power supply voltage VI exceeds a predetermined value, and when the power supply voltage VI exceeds a predetermined value, the upper limit value Va of the triangular wave VT It is also conceivable that the voltage dividing circuit 11 is variably provided so as to output a voltage Vk2 that internally divides the lower limit value Vb.

  In the embodiment described above, the upper limit value Va and the lower limit value Vb of the triangular wave generator 6 are generated from the power supply voltage VI and fluctuate according to the fluctuation of the power supply voltage VI. However, the present invention is limited to this. is not. It is also conceivable that the upper limit value Va and the lower limit value Vb are generated from a constant voltage source and made constant. In this case, the voltage dividing circuit 11 also needs to divide the constant voltage from the constant voltage source and output it to the second comparator 12.

  Further, the above-described embodiments are merely representative forms of the present invention, and the present invention is not limited to the embodiments. That is, various modifications can be made without departing from the scope of the present invention.

2 Lamp (load)
3 Battery (Power)
4 FET (switch)
5 Load control device 6 Triangular wave generator (periodic signal generator)
7 first comparator 8 second pulse signal output circuit (second pulse signal output means)
9 OR gate (selection means, second logic gate)
12 Second comparator 13 Flip-flop 14 NOR gate (first logic gate)
VT Triangular wave (periodic signal)
VI Power supply voltage Vk1 Voltage according to the power supply voltage

Claims (4)

A load control device for controlling a switch provided between a load and a power supply, wherein the periodic signal generator generates a periodic signal that periodically increases and decreases between an upper limit value and a lower limit value, and the periodic signal generation A first comparator that compares a periodic signal generated by a power supply with a power supply voltage of the power supply or a voltage corresponding to the power supply voltage, and the first comparator has a power supply voltage that is less than a predetermined value. In a load control device that outputs a direct current signal and outputs a first pulse signal when the power supply voltage exceeds the predetermined value,
A second pulse signal output means for outputting a second pulse signal having a constant duty ratio when the power supply voltage is equal to or higher than a predetermined value;
Selection means for selecting one of the first pulse signal and the second pulse signal when the first pulse signal and the second pulse signal are input, and performing on / off control of the switch using the selected pulse signal;
The first pulse signal is a pulse signal such that when the switch is turned on / off using the signal, the duty ratio of the on period of the switch is reduced as the power supply voltage increases.
The one signal selected by the selection means is an off period of the switch when the on / off control of the switch is performed using one signal, compared to a case where the switch is on / off controlled using the other signal not selected. The load control device is characterized in that the signal is such that becomes longer. The second pulse signal output means includes a second comparator that compares the periodic signal generated by the periodic signal generator with a voltage that internally divides the upper limit value and the lower limit value of the periodic signal. The load control device according to claim 1. The second pulse signal output means includes a flip-flop in which an output of the first comparator is input to a set terminal, an output of the flip-flop and an output of the second comparator, and the second pulse signal The load control device according to claim 2, further comprising: a first logic gate that outputs. The said selection means is comprised from the 2nd logic gate into which the output from the said 2nd pulse signal output means and the output of the said 1st comparator are input. The any one of Claims 1-3 characterized by the above-mentioned. The load control device according to item.

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