JP2009053783A - Overshoot suppression circuit and voltage regulator using overshoot suppression circuit, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an overshoot suppression circuit for improving overshoot while reducing the size and power consumption, and to provide a voltage regulator using the overshoot circuit, and electronic equipment. <P>SOLUTION: This overshoot suppression circuit is provided with: error amplifier circuits (P1, P2, N1, N2) for amplifying a difference between a reference voltage (Vref) and an output voltage (Vout); an output transistor (P4) to be controlled according to the output of the error amplifier circuit; a bias current supply means (N3) for supplying bias currents to the error amplifier circuit; an auxiliary bias current supply means (N4) connected to the bias current supply means in parallel for increasing the bias currents; and auxiliary load means (N5, R1) for connecting a prescribed load to the output terminal (Vout). When the output voltage (Vout) is increased from a stationary state by a prescribed voltage, the auxiliary bias current supply means (N4) and the auxiliary load means (N5, R1) are operated, so that it is possible to suppress the overshoot of the output voltage. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for improving characteristics of a voltage regulator, and more particularly to an overshoot suppression circuit that suppresses overshoot of an output voltage that occurs during load fluctuation or input fluctuation, a voltage regulator that uses the overshoot suppression circuit, and an electronic device.

  A voltage regulator using a MOS transistor has been widely used because of its small size and low power consumption. In such a voltage regulator, when the output current is increased, a large output transistor is used. However, the large transistor has a gate capacity that increases in proportion to its area.

  When an output transistor having a large gate capacitance is driven by a conventional error amplifier circuit with low current consumption, it takes time to charge and discharge the gate capacitance of the output transistor, and output response characteristics deteriorate. If the bias current of the error amplifier circuit is increased, the output response characteristic can be improved, but the advantage of low power consumption is lost.

  FIG. 5 shows an overshoot improvement circuit (overshoot recovery circuit) of a voltage regulator disclosed in Japanese Patent Laid-Open No. 2005-165604.

  The conventional overshoot improvement circuit shown in FIG. 1 includes a comparator CMP, resistors R11 to R14, a capacitor C11, a diode D11, and switch means SW11, and is disposed after the output terminal Vout of the voltage regulator 10.

  The resistor R11 and the capacitor C11 and the resistors R12 and R13 are connected in series, and are connected between the output terminal Vout of the voltage regulator 10 and the ground. A connection node between the resistor R11 and the capacitor C11 is connected to a non-inverting input of the comparator CMP, and a connection node between the resistors R12 and R13 is connected to an inverting input of the comparator CMP. The output of the comparator CMP is connected to the output terminal Vo via the resistor R14, the diode D11, and the switch means SW11.

  In the overshoot improvement circuit of the voltage regulator having such a configuration, the switch means SW11 is on during normal operation. The voltage of the capacitor C11 is charged to the same voltage as the output voltage Vo. Since the voltage at the connection node of the resistors R12 and R13 is lower than the output voltage Vo, the output of the comparator CMP is at a high level and does not affect the output voltage Vo.

  When an overshoot occurs in the output voltage Vo, the voltage at the connection node between the resistors R12 and R13 increases immediately, but the voltage at the connection node between the resistor R11 and the capacitor C11 does not increase immediately because it takes time to charge the capacitor C11. . Therefore, when the voltage at the connection node between the resistors R12 and R13 becomes equal to or higher than the voltage at the connection node between the resistor R11 and the capacitor C11 due to the occurrence of overshoot, the output of the comparator CMP is inverted and becomes a low level.

  When the output of the comparator CMP becomes low level, current flows from the output terminal Vo through the switch means SW11, the diode D11, and the resistor R14, so the output current is increased to suppress overshoot.

  The switch means SW11 is turned off until the capacitor C11 is charged with the same voltage as the output voltage Vo so that the output of the overshoot improvement circuit does not affect the output voltage Vo.

JP 2005-165604 A

  However, the conventional overshoot improvement circuit disclosed in Patent Document 1 requires many parts for the overshoot improvement circuit such as the comparator CMP, and also requires extra power for operating these circuits. . Although not shown, a control circuit for controlling the switch means SW11 is also necessary.

  As a result, there is a problem that the small size and low power consumption which are the features of the voltage regulator using the MOS transistor cannot be achieved.

  The present invention has been made in consideration of the above-described circumstances, and it is possible to improve overshoot while maintaining small size and low power consumption by adding a few components without using a comparator. An object is to provide a shoot suppression circuit, a voltage regulator using the overshoot suppression circuit, and an electronic device.

The present invention employs the following configuration in order to achieve the above object.
a) The present invention includes an error amplification circuit that amplifies a difference between a reference voltage and an output voltage or a voltage proportional to the output voltage, and an output that is controlled by the output of the error amplification circuit and connected between an input terminal and an output terminal A bias current supply means for supplying a bias current to the error amplifier circuit; and an overshoot suppression circuit for suppressing an overshoot of the output voltage, wherein the bias current supply means is connected in parallel to the bias current supply means. Auxiliary bias current supply means for increasing and auxiliary load means for connecting a predetermined load to the output terminal are further provided, and when the output voltage rises by a predetermined voltage from a steady state, the auxiliary bias current supply means and the auxiliary load The load means is operated.

b) In the above, the auxiliary bias current supply means includes a first MOS transistor connected in parallel to the bias current supply means and a gate voltage setting means for setting a gate voltage of the first MOS transistor. The output terminal and the gate of the first MOS transistor are connected via a capacitor.

c) According to the present invention, in the above, the gate voltage setting means is constituted by a fixed resistor connected between the gate and source of the first MOS transistor, and a voltage drop due to a current flowing through the fixed resistor is used as a gate voltage. It is characterized by.

d) In the above, the present invention is characterized in that the gate voltage setting means uses a divided voltage obtained by dividing the output voltage by a plurality of resistors as a gate voltage.

e) Also, in the present invention, the auxiliary bias current supply means includes a first MOS transistor connected in parallel to the bias current supply means and a gate voltage setting means for setting a gate voltage of the first MOS transistor. The gate voltage setting means uses the divided voltage obtained by dividing the output voltage by a plurality of resistors as the gate voltage of the first MOS transistor.

f) Also, in the present invention, the auxiliary load means is composed of a second MOS transistor having the same conductivity type as the first MOS transistor, and a gate and a source of the second MOS transistor are commonly connected to the first MOS transistor, The drain is connected to the output terminal via a resistor.

g) Further, the present invention is any one of a voltage regulator using the overshoot suppression circuit and an electronic device using the voltage regulator, for example, a portable electronic device, an in-vehicle electrical component, and a home appliance.

  According to the present invention, only when an overshoot occurs, the bias current of the error amplifier circuit is increased, and the auxiliary load is connected to the output terminal, so that an increase in current consumption can be suppressed. .

  Also, MOS transistors of the same conductivity type are used for auxiliary bias current generation and auxiliary load connection, respectively, and the gate voltage setting circuit is composed of several resistors and one capacitor, so that an increase in circuit scale can be suppressed, and low It became possible to achieve current consumption and miniaturization.

Next, the effect of each claim will be described.
a) The present invention includes an error amplification circuit that amplifies a difference between a reference voltage and an output voltage or a voltage proportional to the output voltage, and an output that is controlled by the output of the error amplification circuit and connected between an input terminal and an output terminal In a voltage regulator comprising a transistor and a bias current supply means for supplying a bias current to the error amplifier circuit, an auxiliary bias current supply means connected in parallel to the bias current supply means for increasing the bias current, and the output terminal Further comprising auxiliary load means for connecting a predetermined load to the auxiliary bias current supply means and the auxiliary load means when the output voltage is increased by a predetermined voltage from a steady state. An increase in current consumption can be reduced.

b) In the present invention, the auxiliary bias current supply means includes a first MOS transistor connected in parallel to the bias current supply means, and a gate voltage setting means for setting a gate voltage of the first MOS transistor, and the output Since the terminal and the gate of the first MOS transistor are connected by a capacitor, the number of parts to be added is small and the size can be reduced.

c) In the present invention, the gate voltage setting means includes a fixed resistor connected between the gate and the source of the first MOS transistor, and a voltage drop due to a current flowing through the fixed resistor is used as a gate voltage. There are few and it can miniaturize.

d) In the present invention, since the gate voltage setting means uses the divided voltage obtained by dividing the output voltage by a plurality of resistors as the gate voltage, the overvoltage at which the overshoot suppression circuit starts operating can be arbitrarily set. It became so.

e) In the present invention, the auxiliary bias current supply means includes a first MOS transistor connected in parallel to the bias current supply means, and a gate voltage setting means for setting a gate voltage of the first MOS transistor. Since the voltage setting means uses the divided voltage obtained by dividing the output voltage by a plurality of resistors as the gate voltage of the first MOS transistor, the number of components to be added is small and the size can be reduced.

f) In the present invention, the auxiliary load means is composed of a second MOS transistor having the same conductivity type as the first MOS transistor, the gate and source of the second MOS transistor are connected in common with the first MOS transistor, and the drain is a resistor. Since it is connected to the output terminal via the connector, the increase in current consumption is small, and the number of additional components can be reduced.

g) In addition, the present invention can realize a voltage regulator and an electronic device in which an increase in current consumption is small and an overshoot is improved with few additional components.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram showing a voltage regulator using an overshoot suppression circuit according to a first embodiment of the present invention.

  As shown in the figure, a voltage regulator 10 having an overshoot suppressing circuit according to the present invention includes a reference voltage generating circuit 11, PMOS transistors P1 to P3 and NMOS transistors N1 to N6 constituting an error amplifier circuit, PMOS transistors An output transistor P4 using a transistor, resistors R1 to R3, and a capacitor C1 are provided, and includes an input terminal Vbat and an output terminal Vout. Although not shown, an input power supply is connected to the input terminal Vbat. A load 20 is connected to the output terminal Vout.

  NMOS transistors N1 and N2 are differential input transistors of the differential amplifier circuit. The reference voltage Vref generated by the reference voltage generation circuit 11 is applied to the gate of the NMOS transistor N1, the output terminal Vout is connected to the gate of the NMOS transistor N2, and the output voltage Vo is applied.

  The sources of the NMOS transistors N1 and N2 are connected in common and are connected to the drain of the NMOS transistor N3. Since the source of the NMOS transistor N3 is grounded and the reference voltage Vref is applied to the gate of the NMOS transistor N3, the drain current of the NMOS transistor N3 becomes a constant current, which becomes a bias current source of the differential amplifier circuit. Yes.

  The drains of the NMOS transistors N1 and N2 are connected to the drains of the PMOS transistors P1 and P2, respectively. The sources of the PMOS transistors P1 and P2 are connected to the input terminal Vbat, and the gates of the PMOS transistors P1 and P2 are connected in common and connected to the drain of the PMOS transistor P1, so that the PMOS transistors P1 and P2 form a current mirror circuit. This is a load for the differential input transistors N1 and N2.

  The output of the differential amplifier circuit is output from the drain of the NMOS transistor N2. The drain of the NMOS transistor N2 is connected to the gate of the PMOS transistor P3. The source of the PMOS transistor P3 is connected to the input terminal Vbat, and the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N6. Since the source of the NMOS transistor N6 is grounded and the reference voltage Vref is applied to the gate of the NMOS transistor N6, the drain current of the NMOS transistor N6 becomes a constant current and becomes a constant current load of the PMOS transistor P3. .

  The drain of the PMOS transistor P3 is further connected to the gate of the output transistor P4. The source of the output transistor P4 is connected to the input terminal Vbat. The drain is grounded via series resistors R1 and R2, and is connected to the output terminal Vout.

  The NMOS transistor N4 is connected in parallel with the NMOS transistor N3 which is a bias current source of the differential amplifier circuit. The gate of the NMOS transistor N4 is grounded via the resistor R3. Further, it is connected to the output terminal Vout through a capacitor C1.

  The source of the NMOS transistor N5 is grounded, and the gate is connected to the gate of the NMOS transistor N4. Further, the drain is connected to a connection node of series resistors R1 and R2.

  When the output voltage Vo is in a steady state, since the capacitor C1 is charged to the same voltage as the output voltage Vo, the gate voltages of the NMOS transistors N4 and N5 are 0V. Now, when the output voltage Vo rises rapidly under some condition and the raised voltage exceeds the gate threshold voltage of the NMOS transistors N4 and N5, the NMOS transistors N4 and N5 are turned on. When the NMOS transistor N4 is turned on, a drain current flows through the NMOS transistor N4. This current is added to the constant current bias current generated by the NMOS transistor N3 to increase the bias current of the differential amplifier circuit.

  When the output voltage Vo increases, the drain voltage of the NMOS transistor N2 decreases. Since the bias current increases at this time, the drain current of the NMOS transistor N2 also increases, and the gate capacitance of the PMOS transistor P3 connected to the drain of the NMOS transistor N2 can be rapidly charged. As compared with the case where only the NMOS transistor N3 is, the PMOS transistor P3 can be quickly turned on.

  As a result, the gate voltage of the output transistor M1 can be quickly raised, and the on-resistance of the output transistor M1 can be quickly increased, so that the current supplied from the input terminal Vbat can be quickly suppressed and overshoot can be prevented. Can be suppressed.

  Further, when the NMOS transistor N5 is turned on, a current flows from the output terminal Vout to the ground potential via the resistor R1 and the NMOS transistor N5, so that the electric charge stored in the output capacitor (not shown) can be discharged quickly and The shoot can be recovered quickly.

  FIG. 2 is a circuit diagram of a voltage regulator using an overshoot suppression circuit according to the second embodiment of the present invention. The difference from FIG. 1 is that one end of the resistor R2 is connected to the ground, the resistor R3 is removed, and one end of the resistor R2 is connected to the resistor R3 connected to the ground, and the NMOS transistor N4 This is a change to connect to the gate.

  As a result, when the output voltage Vo is in a steady state, a divided voltage obtained by dividing the output voltage Vo by the series resistors R1 + R2 and R3 is applied to the gates of the NMOS transistors N4 and N5. Overshooting is performed by setting the divided voltage lower than the gate threshold voltage of the NMOS transistors N4 and N5, and further setting the differential voltage between the gate threshold voltage of the NMOS transistors N4 and N5 and the divided voltage to the overshoot voltage to be suppressed. The overshoot voltage at which the suppression circuit operates can be set easily.

  FIG. 3 is a circuit diagram of a voltage regulator using an overshoot suppression circuit according to a third embodiment of the present invention. The difference from FIG. 2 showing the second embodiment is that the capacitor C1 is removed.

  In the first and second embodiments, only the AC component of the output voltage Vo is detected via the capacitor C1, so that it can be detected only in the case of a steep overshoot, and the output voltage Vo rises slowly. In such a case, even if there was a large overshoot, it could not be suppressed.

  However, in the third embodiment shown in FIG. 3, since the voltage obtained by directly dividing the output voltage is applied to the gates of the NMOS transistors N4 and N5 without passing through the capacitor C1, the output voltage Vo rises slowly. Can handle overshoot.

  Furthermore, in the second and third embodiments, the gate bias voltage of the NMOS transistors N4 and N5 in the normal state is set so that at least the drain current of the NMOS transistor N5 flows slightly, so that the output transistor at high temperatures can be obtained. Even when the leakage current of P4 increases, the leakage current is canceled by the drain current of the NMOS transistor N5, and the output voltage Vo can be prevented from rising.

  In the present invention, only when an overshoot occurs, the bias current of the differential amplifier circuit is increased and the resistor R1, which is an auxiliary load, is connected to the output terminal Vout, so that the increase in current consumption can be extremely reduced. . Furthermore, it is only necessary to add NMOS transistors N4 and N5, and one or two resistors and capacitors, and the increase in circuit scale can be suppressed.

  The above-described overshoot suppression circuit maintains small size and low power consumption by incorporating it into various electronic devices such as voltage regulators (voltage regulators), portable electronic devices such as mobile phones, in-vehicle electrical components, and various home appliances. In addition, an electronic device capable of improving overshoot can be realized.

  As described above, the overshoot suppression circuit according to the present invention can be used for electrical products in various fields. As an example, the overshoot suppression circuit according to the present invention is applied to a hybrid vehicle disclosed in Japanese Patent Laid-Open No. 2005-175439. An embodiment to which the voltage regulator used is applied is shown below.

  FIG. 4 is a diagram showing an embodiment of a hybrid vehicle using a voltage regulator using an overshoot suppression circuit according to the present invention.

  As shown in the figure, a hybrid vehicle 100 according to the present embodiment includes a battery 110, a voltage regulator 120 using an overshoot suppression circuit according to the present invention, a power output device 130, a differential gear (DG: Differential Gear). ) 140, front wheels 150L and 150R, rear wheels 160L and 160R, front seats 170L and 170R, a rear seat 180, and a dashboard 190 (refer to JP-A-2005-175439 for basic operations).

  The battery 110 is electrically connected to the voltage regulator 120 through a power supply cable, supplies a DC voltage to the voltage regulator 120, and is charged by the DC voltage from the voltage regulator 120. The voltage regulator 120 is electrically connected to the power output device 130 via a power supply cable, and the power output device 130 is connected to the DG 140.

  Voltage regulator 120 boosts the DC voltage from battery 110, converts the boosted DC voltage to an AC voltage, drives and controls two motor generators MG1 and MG2 included in power output device 130, and outputs power. The battery 110 is charged by converting the AC voltage generated by the motor generator included in the device 130 into a DC voltage.

  The voltage regulator 120 includes a voltage regulator using the overshoot suppression circuit according to the present invention. Therefore, the voltage regulator 120 is small and can reduce power consumption, and can improve overshoot and perform stable operation. .

1 is a circuit diagram of a voltage regulator showing a first embodiment of the present invention. It is a circuit diagram of the voltage regulator which shows the 2nd Example of this invention. It is a circuit diagram of the voltage regulator which shows the 3rd Example of this invention. It is a figure which shows the Example which applied the overheat protection function which concerns on this invention to the hybrid vehicle. It is an overshoot suppression circuit diagram for demonstrating a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10: Voltage regulator 11: Reference voltage generation circuit 20: Load P1-P4: PMOS transistor N1-N6: NMOS transistor P4: Output transistor R1-R3, R11-R14: Resistor C1, C11: Capacitor CMP: Comparator SW11: Switch means

Claims (9)

An error amplifying circuit for amplifying a difference between a reference voltage and an output voltage or a voltage proportional to the output voltage; an output transistor controlled by an output of the error amplifying circuit; connected between an input terminal and an output terminal; In an overshoot suppression circuit that includes bias current supply means for supplying a bias current to the circuit and suppresses overshoot of the output voltage,
An auxiliary bias current supply means connected in parallel to the bias current supply means for increasing the bias current; and an auxiliary load means for connecting a predetermined load to the output terminal;
An overshoot suppression circuit, wherein the auxiliary bias current supply means and the auxiliary load means are operated when the output voltage rises by a predetermined voltage from a steady state. The overshoot suppression circuit according to claim 1,
The auxiliary bias current supply means includes a first MOS transistor connected in parallel to the bias current supply means, and a gate voltage setting means for setting a gate voltage of the first MOS transistor,
An overshoot suppression circuit, wherein the output terminal and the gate of the first MOS transistor are connected via a capacitor. The overshoot suppression circuit according to claim 2,
The overshoot suppression circuit according to claim 1, wherein the gate voltage setting means comprises a fixed resistor connected between the gate and source of the first MOS transistor, and a voltage drop caused by a current flowing through the fixed resistor is used as a gate voltage. The overshoot suppression circuit according to claim 2,
The overshoot suppressing circuit, wherein the gate voltage setting means uses a divided voltage obtained by dividing the output voltage by a plurality of resistors as a gate voltage. The overshoot suppression circuit according to claim 1,
The auxiliary bias current supply means includes a first MOS transistor connected in parallel to the bias current supply means, and a gate voltage setting means for setting a gate voltage of the first MOS transistor,
The overshoot suppressing circuit, wherein the gate voltage setting means uses a divided voltage obtained by dividing the output voltage by a plurality of resistors as a gate voltage of the first MOS transistor. In the overshoot suppression circuit according to any one of claims 1 to 5,
The auxiliary load means comprises a second MOS transistor having the same conductivity type as the first MOS transistor, the gate and source of the second MOS transistor are connected in common with the first MOS transistor, and the drain is connected to the output terminal via a resistor. An overshoot suppression circuit characterized by being connected.   A voltage regulator using the overshoot suppression circuit according to claim 1.   An electronic device using the voltage regulator according to claim 7.   9. The electronic device according to claim 8, wherein the electronic device is any one of a portable electronic device, an in-vehicle electrical component, and a home appliance.

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