JP2013223109A - Differential amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement a satisfactorily flat group delay characteristic.SOLUTION: A differential amplifier includes: first and second transistors Q11 and Q12 forming a differential transistor pair; and a current source IS1 having an output terminal connected to a supply potential. The first transistor Q11 has a base terminal connected to a non-inverting input terminal IT, a collector terminal connected to a source potential via a first load resistance RL1, and an emitter terminal connected to an input terminal of the current source IS1 via a first inductive element LE1. The second transistor Q12 has a base terminal connected to an inverting input terminal IC, a collector terminal connected to the source potential via a second load resistance RL2, and an emitter terminal connected to the input terminal of the current source via a second inductive element LE2.

Description

  The present invention relates to an amplifier circuit technology, and more particularly to a differential amplifier with good group delay characteristic flatness.

In optical transmission systems such as optical transmission systems, optical interconnections, and passive optical network (PON) systems that enable high-speed data transmission, electrical signals obtained from optical signals are amplified by optical receivers. A differential amplifier is used as the amplifier.
In such an optical transmission circuit, in order to handle a wide-band electric signal, a differential amplifier having a good flatness in a characteristic in which a time delay in an amplification operation does not change depending on a signal frequency, that is, a group delay characteristic is required.

  FIG. 6 is a circuit diagram showing a configuration of a conventional differential amplifier. The differential amplifier 50 includes transistors Q11 and Q12 forming a differential transistor pair (see, for example, Non-Patent Document 1).

Q11 has a base terminal connected to the non-inverting input terminal IT, a collector terminal connected to the power supply potential VCC via the load resistor RL1, and an emitter terminal connected to the input terminal of the current source IS1 via the emitter resistor RE1. It is connected.
Q12 has a base terminal connected to the inverting input terminal IC, a collector terminal connected to VCC via the load resistor RL2, and an emitter terminal connected to the input terminal of the current source IS1 via the emitter resistor RE2. .
The output terminal of IS1 is connected to the ground potential (supply potential) VEE.

  Therefore, an amplifier circuit that amplifies the non-inverted input signal input from IT by Q11, RL1, RE1, and IS1 and outputs the obtained inverted output signal to the inverted output terminal OC connected to the collector terminal of Q11. Q12, RL2, RE2, and IS1 are used to amplify the inverted input signal input from the IC, and the obtained non-inverted output signal is output to the non-inverted output terminal OT connected to the collector terminal of Q12. An amplifier circuit is configured.

  FIG. 7 is a circuit diagram showing another configuration of a conventional differential amplifier. The differential amplifier 60 is a differential amplifier using a voltage follower, and includes transistors Q11 and Q12 forming a differential transistor pair, transistors Q13 and Q14 forming a differential transistor pair, and a transistor Q21 forming a differential transistor pair. , Q22 (voltage follower) (for example, see Non-Patent Document 2).

Among these, Q11 has a base terminal connected to the non-inverting input terminal IT and an emitter terminal connected to the input terminal of the current source IS1 via the emitter resistor RE1.
Q12 has a base terminal connected to the inverting input terminal IC and an emitter terminal connected to the input terminal of the current source IS1 via the emitter resistor RE2.

Q21 has a base terminal connected to the collector terminal of Q11, a collector terminal connected to the power supply potential VCC via the load resistor RL1, and an emitter terminal connected to the input terminal of the current source IS2.
Q22 has a base terminal connected to the collector terminal of Q12, a collector terminal connected to VCC via a load resistor RL2, and an emitter terminal connected to the input terminal of the current source IS2.

Q13 has a base terminal connected to the collector terminal of Q21, a collector terminal connected to VCC, and an emitter terminal connected to the collector terminal of Q11 via a feedback resistor RF1.
Q14 has a base terminal connected to the collector terminal of Q22, a collector terminal connected to VCC, and an emitter terminal connected to the collector terminal of Q12 via a feedback resistor RF2.
The output terminals of IS1 and IS2 are connected to the ground potential (supply potential) VEE, respectively.

  Therefore, Q11, Q13, Q21, RL1, RF1, RE1, IS1, and IS2 amplify the non-inverted input signal input from IT, and the obtained inverted output signal is an inverted output connected to the collector terminal of Q21. An amplifying circuit for outputting to the terminal OC is configured, and Q12, Q14, Q22, RL2, RF2, RE2, IS1, IS2 are used to amplify the inverting input signal input from the IC, and the obtained non-inverting output signal is obtained. , An amplifier circuit that outputs to a non-inverting output terminal OT connected to the collector terminal of Q22 is configured.

P.R.Gray / R.G.Meyer, translated by Jun Nagata, “Analog Integrated Circuit Design Technology for VLSI (Part 1)”, p.181, Baifukan, 1990 N. Ishihara, O. Nakajima, H. Ichino, and Y. Yamauchi, Electronics Letters, Vol. 25, No. 19, 1989, P. 1317

  However, in such a conventional technique, a peaking phenomenon in which a gain increases in a high frequency region is likely to occur due to circuit parasitic components such as wiring inductance and the characteristics of the amplifier itself. On the other hand, there has been a problem that the group delay characteristic is lost due to a large change in the phase characteristic.

  An object of the present invention is to solve such a problem, and an object of the present invention is to provide a differential amplifier having good flatness in group delay characteristics.

  In order to achieve such an object, a differential amplifier according to the present invention is a differential amplifier that amplifies a differential input signal input from a non-inverting input terminal and an inverting input terminal, and includes a differential transistor pair. And a current source having an output terminal connected to a supply potential. The first transistor has a base terminal connected to the non-inverting input terminal and a collector terminal connected to the first load resistor. And the emitter terminal is connected to the input terminal of the current source via the first inductive element. The second transistor has a base terminal connected to the inverting input terminal and a collector terminal connected to the power supply potential. A power supply potential is connected via a second load resistor, and an emitter terminal is connected to an input terminal of the current source via a second inductive element.

Another differential amplifier according to the present invention is a differential amplifier that amplifies a differential input signal input from a non-inverting input terminal and an inverting input terminal, and includes first and second differential transistor pairs. Transistors, third and fourth transistors forming a differential transistor pair, fifth and sixth transistors forming a differential transistor pair, and first and second transistors each having an output terminal connected to a supply potential. The first transistor has a base terminal connected to the non-inverting input terminal, an emitter terminal connected to the input terminal of the first current source via the first inductive element, and a second transistor The base terminal is connected to the inverting input terminal, the emitter terminal is connected to the input terminal of the first current source via the second inductive element, and the third transistor is the base terminal. The collector terminal of the first transistor is connected, the collector terminal is connected to the power supply potential via the first load resistor, the emitter terminal is connected to the input terminal of the second current source, and the fourth transistor is The base terminal is connected to the collector terminal of the second transistor, the collector terminal is connected to the power supply potential via the second load resistor, the emitter terminal is connected to the input terminal of the second current source, The transistor 5 has a base terminal connected to the collector terminal of the third transistor, a collector terminal connected to the power supply potential, and an emitter terminal connected to the collector terminal of the first transistor via the first feedback resistor. And
The sixth transistor has a base terminal connected to the collector terminal of the fourth transistor, a collector terminal connected to the power supply potential, and an emitter terminal connected to the collector terminal of the second transistor via the second feedback resistor. ing.

  According to the present invention, the gain of the differential amplifier can be reduced as the signal frequency increases. Therefore, the group delay characteristic deteriorated due to excessive peaking phenomenon occurring in the high frequency region is improved. As a result, the fluctuation range of the time delay can be suppressed over a wide frequency band, and good flatness is obtained in the group delay characteristic. Can do.

1 is a circuit diagram showing a configuration of a differential amplifier according to a first embodiment. FIG. It is explanatory drawing which shows the group delay characteristic of the differential amplifier concerning 1st Embodiment. It is an output waveform diagram of a conventional differential amplifier. It is an output waveform diagram of the differential amplifier according to the first embodiment. It is a circuit diagram which shows the structure of the differential amplifier concerning 2nd Embodiment. It is a circuit diagram which shows the structure of the conventional differential amplifier. It is a circuit diagram which shows the other structure of the conventional differential amplifier.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a differential amplifier according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram showing the configuration of the differential amplifier according to the first embodiment.

  The differential amplifier 10 converts an optical signal into an electrical signal in an optical transmission system such as an optical transmission system, an optical interconnection, or a passive optical network (hereinafter referred to as PON) system that enables high-speed data transmission. An amplifier used in a data communication apparatus such as an optical receiver, which amplifies a differential input signal input from a non-inverting input terminal IT and an inverting input terminal IC, and outputs a non-inverting output terminal OT and an inverting output terminal OC. It has a function to output from.

  In this embodiment, an inductive element (inductance) is used as the emitter resistance of a differential transistor pair that amplifies a differential input signal input from an input terminal.

Next, the configuration of the differential amplifier according to the present exemplary embodiment will be described in detail with reference to FIG.
The differential amplifier 10 includes a transistor (first transistor) Q11 forming a differential transistor pair, a transistor (second transistor) Q12, and a current source whose output terminal is connected to the ground potential (supply potential) VEE. IS1 is provided.

Among these, Q11 has a base terminal connected to the non-inverting input terminal IT, a collector terminal connected to the power supply potential VCC via a load resistance (first load resistance) RL1, and an emitter terminal connected via the induction element LE1. It is connected to the input terminal of IS1.
Q12 has a base terminal connected to the inverting input terminal IC, a collector terminal connected to VCC via a load resistance (second load resistance) RL2, and an emitter terminal connected to the current source IS1 via the induction element LE2. Connected to the input terminal.

  Therefore, an amplifier circuit that amplifies the non-inverted input signal input from IT by Q11, RL1, LE1, and IS1, and outputs the obtained inverted output signal to the inverted output terminal OC connected to the collector terminal of Q11. Q12, RL2, LE2, and IS1 amplify the inverting input signal input from the IC, and output the obtained non-inverting output signal to the non-inverting output terminal OT connected to the collector terminal of Q12. An amplifier circuit is configured.

Among these, LE1 and LE2 have a value of jωL as impedance. For this reason, the impedance is small in the low frequency region and large in the high frequency region.
Therefore, when LE1 and LE2 having such characteristics are inserted between the emitter terminals of Q11 and Q12 and IS1, the value of the emitter resistance increases in the high frequency region. As the frequency increases, the gain of the differential amplifier decreases.

  For this reason, by inserting appropriate inductance components as LE1 and LE2, the group delay characteristic deteriorated due to the excessive peaking phenomenon occurring in the high frequency region is flattened, and the fluctuation width of the time delay is reduced over a wide frequency band. Good flatness is obtained in the group delay characteristic.

  FIG. 2 is an explanatory diagram illustrating group delay characteristics of the differential amplifier according to the first embodiment. Here, the change of the time delay with respect to the frequency change of the differential input signal input to the differential amplifier 10 is obtained by simulation. The horizontal axis represents the frequency of the differential input signal, and the vertical axis represents the signal delay time between the input and output terminals.

  Compared with the group delay characteristic 31 of the conventional differential amplifier 50 shown in FIG. 6 and the group delay characteristic 32 of the differential amplifier according to the present embodiment, the group delay in a wide frequency band from about 5 MHz to about 5 GHz. The delay time of the group delay characteristic 32 is shortened from the characteristic 31, and the delay time does not change for 30 GHz where the peaking phenomenon occurs. For this reason, for example, in the frequency band of 100 MHz to 30 GHz, which is a practical frequency band, the fluctuation width of the delay time is about 15 psec in the group delay characteristic 31, but in the group delay characteristic 32, it is about 1/3 of 5 psec. Has been reduced to. Therefore, it can be seen that the peaking phenomenon is alleviated and the group delay characteristic is flattened in a wide frequency band.

FIG. 3 is an output waveform diagram of the conventional differential amplifier, and FIG. 4 is an output waveform diagram of the differential amplifier according to the first embodiment. Here, an output waveform obtained by simultaneously amplifying differential input signals having different frequencies is obtained by simulation. The horizontal axis represents time, and the vertical axis represents the amplitude voltage of the output signal.
Comparing FIG. 3 and FIG. 4, in FIG. 3, the phase of the differential input signal varies depending on the frequency, but in FIG. 4, a good output waveform having a substantially constant phase is obtained.

[Effect of the first embodiment]
Thus, since this embodiment uses an inductive element as the emitter resistance of the differential transistor pair that amplifies the differential input signal input from the input terminal, the differential frequency increases as the signal frequency increases. The gain of the amplifier can be reduced. Therefore, the group delay characteristic deteriorated due to excessive peaking phenomenon occurring in the high frequency region is improved. As a result, the fluctuation range of the time delay can be suppressed over a wide frequency band, and good flatness is obtained in the group delay characteristic. Can do.

[Second Embodiment]
Next, a differential amplifier according to the second exemplary embodiment of the present invention will be described with reference to FIG. FIG. 5 is a circuit diagram illustrating a configuration of a differential amplifier according to the second embodiment.
In the present embodiment, a differential amplifier 20 using a voltage follower will be described as another configuration of the differential amplifier.

  The differential amplifier 20 includes a transistor Q11 (first transistor) and a transistor (second transistor) Q12 forming a differential transistor pair, and a voltage follower transistor (third transistor) forming a differential transistor pair. Q21 and transistor (fourth transistor) Q22, a differential transistor pair (fifth transistor) Q13 and transistor (sixth transistor) Q14, and an output terminal are connected to the ground potential (supply potential) VEE. A current source (first current source) IS1 and a current source (second current source) IS2 are provided.

Among these, Q11 has a base terminal connected to the non-inverting input terminal IT and an emitter terminal connected to the input terminal of IS1 via an inductive element (first inductive element) LE1.
Q12 has a base terminal connected to the inverting input terminal IC and an emitter terminal connected to the input terminal of IS1 via an induction element (second induction element) LE2.
Q21 has a base terminal connected to the collector terminal of Q11, a collector terminal connected to the power supply potential VCC via a load resistor (first load resistor) RL1, and an emitter terminal connected to the input terminal of IS2. Yes.
Q22 has a base terminal connected to the collector terminal of Q12, a collector terminal connected to VCC via a load resistor (second load resistor) RL2, and an emitter terminal connected to the input terminal of IS2.

Q13 has a base terminal connected to the collector terminal of Q21, a collector terminal connected to VCC, and an emitter terminal connected to the collector terminal of Q11 via a feedback resistor (first feedback resistor) RF1.
Q14 has a base terminal connected to the collector terminal of Q22, a collector terminal connected to VCC, and an emitter terminal connected to the collector terminal of Q12 via a feedback resistor (second feedback resistor) RF2.

  Therefore, Q11, Q13, Q21, RL1, RF1, RL1, IS1, and IS2 amplify the non-inverted input signal input from IT, and the obtained inverted output signal is an inverted output connected to the collector terminal of Q13. An amplifying circuit for outputting to the terminal OC is configured, and Q12, Q14, Q22, RL2, RF2, RL2, IS1, and IS2 are used to amplify the inverting input signal input from the IC, and the obtained non-inverting output signal is obtained. , An amplifier circuit that outputs to a non-inverting output terminal OT connected to the collector terminal of Q12 is configured.

Among these, LE1 and LE2 have a value of jωL as impedance. For this reason, the impedance is small in the low frequency region and large in the high frequency region.
Therefore, when LE1 and LE2 having such characteristics are inserted between the emitter terminals of Q11 and Q12 and IS1, the value of the emitter resistance increases in the high frequency region. As the frequency increases, the gain of the differential amplifier decreases.

  For this reason, by inserting appropriate inductance components as LE1 and LE2, the group delay characteristic deteriorated due to the excessive peaking phenomenon occurring in the high frequency region is flattened, and the fluctuation width of the time delay is reduced over a wide frequency band. Good flatness is obtained in the group delay characteristic.

[Effect of the second embodiment]
Thus, since this embodiment uses an inductive element as the emitter resistance of the differential transistor pair that amplifies the differential input signal input from the input terminal, the differential frequency increases as the signal frequency increases. The gain of the amplifier can be reduced. Therefore, the group delay characteristic deteriorated due to excessive peaking phenomenon occurring in the high frequency region is improved. As a result, the fluctuation range of the time delay can be suppressed over a wide frequency band, and good flatness is obtained in the group delay characteristic. Can do.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  In each embodiment, the case where the differential amplifiers 10 and 20 are configured by NPN bipolar transistors has been described as an example. However, the present invention is not limited to this, and the voltage values of the power supply potential VCC and the ground potential VEE are not limited thereto. And may be configured with a PNP-type bipolar transistor. In place of the bipolar transistor, an N-type or P-type MOSFET may be used.

  10, 20 ... Differential amplifier, Q11 ... Transistor (first transistor), Q12 ... Transistor (second transistor), Q13 ... Transistor (fifth transistor), Q14 ... Transistor (sixth transistor), Q21 ... Transistor (third transistor), Q22 ... transistor (fourth transistor), LE1 ... inductive element (first inductive element), LE2 ... inductive element (second inductive element), RL1 ... load resistance (first Load resistance), RL2 ... load resistance (second load resistance), IS1 ... current source (first current source), IS2 ... current source (second current source), RF1 ... feedback resistance (first feedback resistance) ), RF2 ... feedback resistor (second feedback resistor), IT ... non-inverting input terminal, IC ... inverting input terminal, OT ... non-inverting output terminal, OC ... inverting output terminal, VCC ... power supply , VEE ... ground potential (supply potential).

Claims (2)

A differential amplifier that amplifies a differential input signal input from a non-inverting input terminal and an inverting input terminal,
A first transistor and a second transistor forming a differential transistor pair; and a current source having an output terminal connected to a supply potential,
The first transistor has a base terminal connected to the non-inverting input terminal, a collector terminal connected to a power supply potential via a first load resistor, and an emitter terminal connected to the current source via the first inductive element. Connected to the input terminal,
The second transistor has a base terminal connected to the inverting input terminal, a collector terminal connected to the power supply potential via a second load resistor, and an emitter terminal connected to the current source via a second induction element. A differential amplifier characterized by being connected to the input terminal. A differential amplifier that amplifies a differential input signal input from a non-inverting input terminal and an inverting input terminal,
First and second transistors forming a differential transistor pair, third and fourth transistors forming a differential transistor pair, fifth and sixth transistors forming a differential transistor pair, and an output terminal are respectively supplied. First and second current sources connected to a potential;
The first transistor has a base terminal connected to the non-inverting input terminal and an emitter terminal connected to the input terminal of the first current source via a first inductive element,
The second transistor has a base terminal connected to the inverting input terminal, and an emitter terminal connected to the input terminal of the first current source via a second inductive element,
The third transistor has a base terminal connected to the collector terminal of the first transistor, a collector terminal connected to a power supply potential via a first load resistor, and an emitter terminal input to the second current source. Connected to the terminal,
The fourth transistor has a base terminal connected to the collector terminal of the second transistor, a collector terminal connected to the power supply potential via a second load resistor, and an emitter terminal connected to the second current source. Connected to the input terminal,
The fifth transistor has a base terminal connected to the collector terminal of the third transistor, a collector terminal connected to the power supply potential, and an emitter terminal connected to the collector of the first transistor via a first feedback resistor. Connected to the terminal,
The sixth transistor has a base terminal connected to the collector terminal of the fourth transistor, a collector terminal connected to the power supply potential, and an emitter terminal connected to the collector of the second transistor via a second feedback resistor. A differential amplifier characterized by being connected to a terminal.

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