JP2013222942A - Method for manufacturing interposer and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an interposer adaptive to narrowing pitches and increasing pins of terminal connection for mounting a semiconductor chip to a semiconductor device, and a method for manufacturing the semiconductor device.SOLUTION: A method for manufacturing an interposer comprises: an arranging step of arranging a plurality of fiber members 11 at prescribed pitches P; a block body manufacturing step; a base material manufacturing step; a through hole forming step; a continuity step; a patterning step; and a multi-layers wiring layer forming step. In the arranging step, the pitch P is set so that a relation of 2D≤P<4D for a thickness D of the fiber member 11 is satisfied.

Description

  The present invention relates to an interposer, and more particularly to a method for manufacturing an interposer for a semiconductor device and a method for manufacturing a semiconductor device.

  2. Description of the Related Art In recent years, semiconductor devices having small and large-scale integrated circuits are used in semiconductor devices used for electronic devices, particularly computers and communication devices. For example, a SIP (System In Package) in which a plurality of semiconductor chips are mounted on a multilayer wiring board (also referred to as a package substrate) via solder bumps has been proposed. In such flip chip mounting, in order to increase the mechanical strength of the semiconductor device and increase the water resistance, the wiring substrate and the semiconductor chip are sealed with an insulating resin such as an epoxy resin, for example. . However, in a semiconductor device in which wiring is formed with high density by flip chip mounting, the wiring board, the semiconductor chip, and the sealing resin have different linear expansion coefficients. Chip breakage, dropout, or abnormal operation is a problem. In order to solve this problem, a semiconductor device is configured by interposing an interposer between a wiring board and a semiconductor chip. Further, since the terminal pitch of the semiconductor chip is narrow, this interposer can also exhibit a function as a means for converting the mounting pitch when the semiconductor device is mounted on the mother board.

  Such an interposer is known in which a through electrode penetrating in the thickness direction is formed on a substrate such as a resin substrate, a ceramic substrate, a glass substrate, or a silicon substrate so as to achieve front-back conduction. As a means for forming a via hole for front and back conduction, for example, laser processing (mainly a resin substrate or glass substrate), sandblasting (mainly for a glass substrate), punching (mainly for a ceramic substrate) For example, mechanical drilling means such as wet etching (mainly for a glass substrate or silicon substrate) or dry etching (mainly for a silicon substrate) or other means such as chemical etching has been used. However, the via hole formed by the conventional via hole forming means as described above does not have a constant via hole diameter in the thickness direction of the substrate. Therefore, the aspect ratio is low, and there is a limit to refinement of the via hole diameter and narrow pitch. was there. In addition, for example, in the deepening of a silicon substrate capable of forming a via hole having a substantially constant via hole diameter dimension and a high aspect ratio in the thickness direction of the substrate, miniaturization is possible, but it takes a long time to manufacture and the cost is reduced. There was also a problem with a significant increase.

  On the other hand, there has been proposed a radiation detector in which a radiation detector and a signal processing element are connected to an inner wall of a through hole formed in a glass substrate through a wiring board provided with a conductive member that conducts the front and back (Patent) Reference 1). The wiring board here functions as an interposer, setting the number and arrangement of through-holes according to the configuration of the radiation detector, among the plurality of through-holes, in the through-holes at positions where front and back conduction is necessary, It is described that a conductive member is formed by selecting with a mask or the like. Also, a hollow glass member having both ends opened is fused and integrated to form a multi-channel member, and the multi-channel member is fused and integrally formed in a two-dimensional arrangement. There has been proposed an electrode substrate having a capillary substrate and a conductive member that fills the through-hole and electrically conducts between both principal surfaces of the capillary substrate (Patent Document 2).

Japanese Patent No. 4365108 JP 2004-363186 A

  The radiation detector described in Patent Document 1 is provided with a conductive member on the inner wall of the through hole, and the inside of the through hole has a hollow structure. However, since the radiation detector is used in a special environment, there is little history of temperature change. On the other hand, generally used semiconductor devices require reliability in temperature change. And the front-and-back conduction of the hollow structure as described in Patent Document 1 is that when a semiconductor chip or the like is mounted, the air inside becomes a void and breaks the connection part with the semiconductor chip, thereby fixing the semiconductor chip. There was a problem of causing defects and poor connections. In addition, in order to use in a general semiconductor device, there is a problem that the number and arrangement of through holes must be set in accordance with the semiconductor chip to be mounted.

Further, in the electrode substrate described in Patent Document 2, there is no problem due to the air inside the through hole becoming a void. However, since a multi-channel member in which hollow glass members are fused and formed integrally is used, the number and arrangement of through-holes are mounted for use in general semiconductor devices. There is a problem that it is extremely difficult to set according to the semiconductor chip. That is, in the application of radiation detection, the semiconductor chip used is almost the same, and the electrode position of the semiconductor chip and the arrangement of the through holes can be made constant to some extent, so the wiring board does not need many types, In general semiconductor devices, since there are various semiconductor chip sizes, pin numbers, electrode positions, and the like, there is a problem that many types of interposers must be designed and manufactured. Furthermore, there has been a problem that the product management of the interposer becomes more complicated due to the increase in the number of products, and the product itself becomes expensive.
The present invention has been made in view of the above-described circumstances, and a method of manufacturing an interposer and a method of manufacturing a semiconductor device corresponding to a narrower terminal connection pitch and a larger number of pins in mounting a semiconductor chip on a semiconductor device. The purpose is to provide.

  In order to achieve such an object, the interposer manufacturing method of the present invention includes an arranging step of arranging a plurality of fiber members at a predetermined pitch P, and filling between the arranged fiber members with an insulating material, A block body production process for producing a block body in which the fiber member is held by an insulator, and a base substrate production for producing the base substrate by cutting the block body so that the fiber member is divided in the longitudinal direction. Through-hole formation in which the fiber member exposed on both main surfaces of the base substrate is removed by etching to form a plurality of through-holes whose openings are located in a partial region or the entire region of both main surfaces A conductive material is filled in the through hole of the base substrate to form a front and back conductive member, and both main surfaces of the base substrate are conductive so as to be connected to the front and back conductive member. A conduction step of forming a layer, a patterning step of patterning the conductor layers formed on both main surfaces of the base substrate to form a conductor layer pattern, and the above-mentioned steps formed on both main surfaces of the base substrate A multilayer wiring layer forming step of forming a multilayer wiring layer on at least one conductor layer pattern of the conductor layer pattern, and in the arranging step, 2D ≦ P <4D with respect to the thickness D of the fiber member The pitch P is set so as to satisfy the above relationship.

As another aspect of the present invention, in the through hole forming step, among the fiber members exposed on both main surfaces of the base substrate, a fiber member that does not require through hole formation is covered with an insulating protective layer. Thereafter, the exposed fiber member is removed by etching to form the through hole.
As another aspect of the present invention, in the multilayer wiring layer forming step, the conductive layer pattern formed on one main surface of the base substrate is connected to the conductive material inside the unnecessary through hole. The conductor layer pattern was covered with an insulating protective layer, and the multilayer wiring layer was formed on the conductor layer pattern formed on the other main surface of the base substrate.
As another aspect of the present invention, the fiber member and the insulating material are configured to have heat ductility.
As another aspect of the present invention, in the block body manufacturing step, a space between the arrayed fiber members is filled with an insulating material, and a subblock body in which the fiber members are held by an insulator is manufactured. The array pitch of the fiber members is narrowed by stretching the fiber member, and the array pitch P of the fiber members after stretching satisfies the relationship of 2D ≦ P <4D with respect to the thickness D of the fiber members after stretching. It was set as the structure which produces a block body.

As another aspect of the present invention, in the block body manufacturing step, a space between the arrayed fiber members is filled with an insulating material, and a subblock body in which the fiber members are held by an insulator is manufactured. The array pitch of the fiber members is narrowed by stretching the fiber member, and the array pitch P of the fiber members after stretching satisfies the relationship of 2D ≦ P <4D with respect to the thickness D of the fiber members after stretching. A small block body was produced, and a plurality of small block bodies were filled with an insulating material to produce a block body in which the small block body was held by an insulator.
As another aspect of the present invention, the fiber member and the insulating material have different colors.
As another aspect of the present invention, in the base substrate manufacturing step, at least one main surface of the base substrate obtained by cutting the block body is polished.

  The method of manufacturing a semiconductor device according to the present invention includes a mounting substrate manufacturing step of mounting a semiconductor chip on an interposer including a multilayer wiring layer, and a region in which one or more semiconductor chips are mounted and a circuit is formed. A cutting step of cutting the mounting substrate into individual pieces of the size of the semiconductor device, and the interposer is configured to be manufactured by the method for manufacturing an interposer described above.

  Further, in the method of manufacturing a semiconductor device of the present invention, an arrangement step of arranging a plurality of fiber members at a predetermined pitch P, and filling the space between the arranged fiber members with an insulating material, the fiber members are insulators. A block body manufacturing process for manufacturing a held block body, a base base material manufacturing process for cutting the block body to prepare a base base material so that the fiber member is divided in the longitudinal direction, and the base base material A step of forming a plurality of through holes in which the fiber members exposed on both main surfaces are removed by etching to form openings in a partial region or the entire region of both main surfaces; and the base substrate A conductive step of filling the through hole with a conductive material to form a front and back conductive member, and forming a conductor layer on both main surfaces of the base substrate so as to be connected to the front and back conductive member; A patterning step of patterning the conductor layer formed on one main surface of the source substrate to form a conductor layer pattern; a multilayer wiring layer forming step of forming a multilayer wiring layer on the conductor layer pattern; A mounting substrate manufacturing process for mounting a semiconductor chip on the multilayer wiring layer, and polishing from the side of the conductor layer formed on the other main surface of the base substrate to remove the conductor layer and the base A polishing step for adjusting the thickness of the base material, and a cutting step for cutting the mounting substrate in a region where one or more semiconductor chips are mounted and a circuit is formed, and singulates into the size of the semiconductor device. In the arrangement step, the pitch P is set so as to satisfy the relationship of 2D ≦ P <4D with respect to the thickness D of the fiber member.

As another aspect of the present invention, in the through hole forming step, among the fiber members exposed on both main surfaces of the base substrate, a fiber member that does not require through hole formation is covered with an insulating protective layer. Thereafter, the exposed fiber member is removed by etching to form the through hole.
As another aspect of the present invention, the fiber member and the insulating material are configured to have heat ductility.
As another aspect of the present invention, in the block body manufacturing step, a space between the arrayed fiber members is filled with an insulating material, and a subblock body in which the fiber members are held by an insulator is manufactured. The array pitch of the fiber members is narrowed by stretching the fiber member, and the array pitch P of the fiber members after stretching satisfies the relationship of 2D ≦ P <4D with respect to the thickness D of the fiber members after stretching. It was set as the structure which produces a block body.
As another aspect of the present invention, in the block body manufacturing step, a space between the arrayed fiber members is filled with an insulating material, and a subblock body in which the fiber members are held by an insulator is manufactured. The array pitch of the fiber members is narrowed by stretching the fiber member, and the array pitch P of the fiber members after stretching satisfies the relationship of 2D ≦ P <4D with respect to the thickness D of the fiber members after stretching. A small block body was produced, and a plurality of small block bodies were filled with an insulating material to produce a block body in which the small block body was held by an insulator.

As another aspect of the present invention, the fiber member and the insulating material have different colors.
As another aspect of the present invention, in the base substrate manufacturing step, at least one main surface of the base substrate obtained by cutting the block body is polished.
As another aspect of the present invention, the polishing step is configured such that the insulator is etched from the polished surface side to partially expose the front and back conductive members.

  In the interposer manufacturing method of the present invention, since the fiber members are arranged at a pitch having a predetermined relationship with the thickness thereof, the through hole formed in the through hole forming step has an inner diameter that is constant in the depth direction, and Higher aspect ratio enables through holes to be made finer and narrower, and through-hole conductive members are formed in the through holes to reduce the pitch of terminal connections in mounting semiconductor chips on semiconductor devices. In addition, it is possible to manufacture an interposer that prevents connection failure and fixing failure at low cost, and by appropriately designing a multilayer wiring layer to be formed in the conductor layer pattern, It is possible to manufacture semiconductor chips and interposers corresponding to various semiconductor device sizes.

  In the semiconductor device manufacturing method of the present invention, the interposer is manufactured so that the diameter and pitch of the front and back conductive members have a predetermined relationship, and the semiconductor chip is mounted on the multilayer wiring layer of the interposer and then separated into individual pieces. Therefore, it is possible to manufacture a semiconductor device at a low cost with high connection reliability in the mounting of a semiconductor chip, improved material use efficiency, and furthermore, appropriately design a multilayer wiring layer to be formed in a conductor layer pattern By doing so, it is possible to cope with various types of semiconductor chips and to manufacture a semiconductor device of a desired size.

FIG. 1 is a view showing a state in which fiber members are arranged at a predetermined pitch in the interposer manufacturing method of the present invention. FIG. 2 is a view for explaining the arrangement of the fiber members. FIG. 3 is a diagram illustrating an example of an arrangement jig for arranging fiber members at a predetermined pitch. FIG. 4 is a perspective view showing an example of a block body manufactured in the block body manufacturing process of the interposer manufacturing method of the present invention. FIG. 5 is a diagram for explaining another example of the block body manufacturing process. FIG. 6 is a diagram for explaining another example of the block body manufacturing process. FIG. 7 is a diagram for explaining a base substrate manufacturing step of the interposer manufacturing method of the present invention. FIG. 8 is a view for explaining a through hole forming step of the interposer manufacturing method of the present invention. FIG. 9 is a diagram for explaining another example of the through-hole forming step of the interposer manufacturing method of the present invention. FIG. 10 is a diagram for explaining a conduction process of the interposer manufacturing method of the present invention. FIG. 11 is a diagram for explaining a patterning step of the interposer manufacturing method of the present invention. FIG. 12 is a view for explaining land formation in the patterning step. FIG. 13 is a diagram for explaining a multilayer wiring layer forming step of the interposer manufacturing method of the present invention. FIG. 14 is a diagram for explaining another example of the interposer manufacturing method of the present invention. FIG. 15 is a diagram for explaining another example of the interposer manufacturing method of the present invention. FIG. 16 is a diagram for explaining another example of the interposer manufacturing method of the present invention. FIG. 17 is a diagram for explaining another example of the interposer manufacturing method of the present invention. FIG. 18 is a view for explaining a mounting substrate manufacturing process of the semiconductor device manufacturing method of the present invention. FIG. 19 is a diagram for explaining a cutting step of the semiconductor device manufacturing method of the present invention. FIG. 20 is a diagram for explaining another example of the semiconductor device manufacturing method of the present invention. FIG. 21 is a diagram for explaining another example of the semiconductor device manufacturing method of the present invention. FIG. 22 is a diagram for explaining the manufacture of an interposer in another example of the semiconductor device manufacturing method of the present invention. FIG. 23 is a diagram for explaining a polishing step in another example of the method for manufacturing a semiconductor device of the present invention. FIG. 24 is a diagram for explaining another example of the semiconductor device manufacturing method of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Method of manufacturing interposer]
<Sequence process>
In the present invention, first, in the arranging step, a plurality of fiber members 11 are arranged at a predetermined pitch P (FIG. 1). In FIG. 1, complicated description is avoided so as to facilitate the explanation of the present invention. For example, the number and length of the fiber members 11 are described for convenience, but the present invention is limited to the illustrated example. It is not something. The same applies to the following drawings.
In the illustrated example, the fiber member 11 has a circular cross-sectional shape, but is not limited thereto, and the cross-sectional shape may be a polygonal shape such as a quadrangle or a hexagon. However, in the case where there is a drawing process described later, the cross-sectional shape is preferably circular considering the stability of the shape of the fiber member 11 after drawing. The thickness D of the fiber member 11 (when the cross-sectional shape is circular, the diameter thereof, and when the cross-sectional shape is a polygon, the length is the longest line segment connecting the two vertices) is: When there is no stretching step to be described later, the inner diameter of the through-hole of the interposer to be manufactured is determined, and can be appropriately set within a range of 5 to 500 μm, for example.
Moreover, when there exists an extending | stretching process mentioned later, the thickness of the fiber member 11 after extending | stretching determines the internal diameter of the through-hole of the interposer to manufacture. For this reason, the thickness D of the fiber member 11 can be set in consideration of the reduced thickness after stretching.

The material of the fiber member 11 is an acid-soluble glass that can be etched by an etching solution that etches and removes the fiber member, for example, an acid-based etching solution such as hydrofluoric acid, nitric acid, and acetic acid. Examples thereof include glass materials such as boric acid-lanthanum oxide-barium carbonate glass.
For example, as shown in FIG. 2A, such fiber members 11 can be arranged at a pitch P such that the centers of the fiber members 11 form a close-packed arrangement having an equilateral triangle. Further, as shown in FIG. 2B, the fiber members 11 may be arranged at a pitch P so that the center of the fiber member 11 forms an XY arrangement forming a lattice point.

  The pitch P in the arrangement of the fiber members 11 is set so as to satisfy the relationship 2D ≦ P <4D with respect to the thickness D of the fiber members 11. For example, the fiber members 11 having a thickness D of 50 μm can be arranged in an XY arrangement so that the pitch P is 100 μm. When the pitch P of the arrangement of the fiber members 11 is less than 2D, the area ratio of the front and back conductive members formed by filling the through holes with a conductive material in the conductive process described later becomes too large on the main surface of the interposer, Stress due to the difference between the thermal expansion coefficient of the front and back conductive members and the thermal expansion coefficient of the fiber member 11 and the insulating material used in the block body manufacturing process described later increases, causing problems such as cracks, cracks or distortion in the interposer. It may occur and is not preferable. Further, if the pitch P of the arrangement of the fiber members 11 is less than 2D, it may be difficult to form connection lands and front and back conductive via lands in the conductive layer pattern formation described later, and when mounting on a motherboard as an interposer. This may cause a short circuit between adjacent electrodes, which is not preferable.

  Further, if the pitch P of the arrangement of the fiber members 11 is 4D or more, it is not preferable because it cannot cope with a product that requires an interposer in which the front and back conductive members have a narrow pitch. That is, for example, when the arrangement pitch P is 2D, it is possible to deal with products that require a large number of front and back conductive members whose arrangement pitch is twice the thickness of the fiber member 11 (the inner diameter of the through hole in the interposer). In addition, it is possible to deal with products that require the pitch of the arrangement of the front and back conductive members to be four times the thickness of the fiber member 11. However, when the arrangement pitch P is 4D, the arrangement pitch of the front and back conductive members cannot be applied to products that require the arrangement pitch of the front and back conductive members to be twice the thickness of the fiber member 11. However, since a new product which may be four times the thickness of the fiber member 11 is required, the manufacturing cost increases correspondingly, and the productivity also decreases. In addition, when the pitch P of the arrangement of the fiber members 11 is 4D or more, the area ratio of the front and back conductive members occupying the main surface of the interposer becomes too small, and the heat dissipation function by the front and back conductive members with good thermal conductivity is reduced, It is not preferable because a good heat dissipation path of an interposer in a semiconductor device cannot be formed. Further, when there is a drawing process described later, the shape of the fiber member 11 is deformed by the drawing, and the variation in the shape and dimensions of the through holes is not preferable.

  As described above, in order to arrange the plurality of fiber members 11 at the predetermined pitch P, for example, an arrangement jig can be used. FIG. 3 is a diagram for explaining an example of such an arrangement jig, and the fiber members 11 are arranged at a pitch P so that the center of the fiber member 11 forms an equilateral triangle (see FIG. 2A). It is the jig | tool for arrangement | sequence for. This arrangement jig 21 includes a jig 22 having a plurality of grooves 23 on one surface 22a with a pitch P, a plurality of grooves 25 having a pitch P on one surface 24a, and a pitch P on the other surface 24b. And a jig 24 having a plurality of grooves 26. The groove 25 and the groove 26 of the jig 24 are formed at the same pitch P in a state shifted by P / 2. Further, the groove 23 of the jig 22 and the grooves 25 and 26 of the jig 24 have a size that allows the fiber member 11 to be placed therein and have a substantially semicircular concave shape. When the fiber member 11 is placed in the groove 23 of the jig 22 and the jig 24 is disposed on the jig 22 so that the groove 23 and the groove 25 face each other, the opposed groove 23 and groove The shape and size of the groove 23 and the groove 25 are set so that the fiber member 11 can be accommodated in a cylindrical space formed by the groove 25. Further, the fiber member 11 is placed in the groove 26 of the jig 24 arranged on the jig 22 in this way, and another jig is placed on the jig 24 so that the groove 26 and the groove 25 face each other. The shape and dimensions of the groove 26 and the groove 25 are set so that the fiber member 11 can be accommodated in a cylindrical space formed by the opposed groove 26 and the groove 25 when the 24 is disposed. Then, as described above, the fiber member 11 accommodated in the cylindrical space formed by the opposed grooves 23 and 25 and the cylindrical space formed by the opposed grooves 26 and 25 are accommodated. The depths of the grooves 23, 25, and 26 and the thickness of the jig 24 are set so that the fiber members 11 are arranged closest to each other with a pitch P. Thus, the fiber members 11 can be arranged at the pitch P by placing the fiber members 11 in the grooves while sequentially stacking the plurality of jigs 24 on the jig 22.

  As a procedure for this arrangement, for example, as shown in FIG. 3, two jigs 22A and 22B are arranged so that the axial direction of groove 23 (the direction along arrow a in FIG. 3) is aligned. The fiber member 11 as the step is placed in each groove 23. At this time, by placing an adhesive in advance in the groove 23 of the jig 22A close to the end of the fiber member 11, the placed fiber member 11 can be temporarily fixed. Thereafter, jigs 24 are arranged on the two jigs 22 </ b> A and 22 </ b> B so that the grooves 23 and the grooves 25 face each other, and the second-stage fiber member 11 is placed in each groove 26 of the jig 24. Is placed. Also in this case, the adhesive 2 is placed in advance in the groove 26 of the jig 24 near the end of the fiber member 11 (the jig 24 arranged on the jig 22A). The stage fiber member 11 can be temporarily fixed. Thereafter, the fiber members 11 can be arranged in a desired number of stages using the jig 24 in the same manner. Then, by moving the jig 22B on which the adhesive is not placed and the jig 24 stacked on the jig 22B in the direction of arrow a in FIG. An array bundle of fiber members 11 arranged in a close packing is obtained (see FIG. 1). The overall outer shape of the array bundle of fiber members 11 is not particularly limited and can be set as appropriate. For example, a cylindrical shape or a prismatic shape is used so as to be the same as or similar to the outer shape of a block body to be manufactured in a later process. It can be a shape or the like. Note that either the jig 22 or the jig 24 may be disposed on the jig 24 on which the last-stage fiber member 11 arranged in multiple stages as described above is placed.

The number of grooves 23 included in the jig 22 constituting the arrangement jig 21 and the number of grooves 25 and 26 included in the jig 24 can be appropriately set according to the number of fiber members 11 arranged. . The material of the jigs 22 and 24 may be an inorganic material such as silicon, metal or the like, and the grooves 23, 25 and 26 can be formed by etching or machining. The cylindrical space formed by the grooves 23 and 25 and the cylindrical space formed by the opposed grooves 26 and 25 are slightly larger than the outer shape of the fiber member 11, for example, about several μm. It is preferable to set so as to cause play.
Note that the above-described arrangement jig 21 is merely an example, and for example, the shape of the recesses of the grooves 23, 25, and 26 is not limited to a semicircle, and may be a semi-polygon such as a semi-rectangle. Further, a plurality of gauge plates in which a plurality of holes are formed at a predetermined pitch P in the plate material is used as an arrangement jig, and the fiber member 11 is inserted and placed so as to bridge over the corresponding holes of the gauge plates arranged opposite to each other. Thereafter, the bundle of fiber members 11 arranged at a predetermined pitch P may be obtained by separating the gauge plates. Also in this case, it is preferable to temporarily fix the fiber member 11 inserted into the hole of one gauge plate to the gauge plate with an adhesive or the like.

<Block body production process>
Next, the space between the fiber members 11 arranged as described above is filled with an insulating material to produce a block body 31 in which the fiber members 11 are held by an insulator 32 as shown in FIG. In FIG. 4, the fiber member 11 is shown protruding from the insulator 32 for easy understanding.
In the manufactured block body 31, the arrangement pitch P of the fiber members 11 held by the insulator 32 satisfies the relationship 2D ≦ P <4D with respect to the thickness D of the fiber member 11. The shape and dimensions of the block body 31 thus manufactured are not particularly limited, and the length (longitudinal direction of the fiber member 11) and the diameter are appropriately set in consideration of the cutting device in the base substrate manufacturing process which is a subsequent process. For example, a cylindrical shape having a length of 500 mm and a diameter of 200 mm can be used, and about 3 million fiber members 11 can be held by the insulator 32. The block body 31 may have a prismatic shape such as a quadrangular prism shape or a hexagonal prism shape.

The insulating material used for manufacturing the block body 31 is preferably an insulating material such as non-alkali glass or borosilicate glass having acid resistance such as silicate glass. When the insulating material contains an alkali metal, it is necessary to consider the elution of the alkali metal in various chemical treatments in the subsequent steps.
In the present invention, the color may be different between the insulating material and the fiber member. Thereby, in the process mentioned later, the presence or absence of the fiber member 11 in the base base material 41 and the identification of an existing location become easy. Such a color difference can be achieved by, for example, a method of adding a desired pigment to the insulating material and / or the fiber member, a method of adding a small amount of a colored metal oxide, or the like.

  In such a block body 31, the number of fiber members 11 held by the insulator 32 is very large. Therefore, in the present invention, as shown in FIG. 5, the block body 31 is produced by stretching the sub-block body 31 ′. May be. That is, the thickness is set to be proportional to the arrangement pitch P of the fiber members 11 and the thickness D of the fiber members 11 (which satisfy the relationship of 2D ≦ P <4D) in the block body 31 that is a production target. A sub-block body 31 'in which D' fiber members 11 'are arranged at a pitch P' (these satisfy the relationship 2D'≤P '<4D', D <D ', P <P'). First, make it. FIG. 5B is a diagram showing the thickness D ′ and the pitch P ′ of such a fiber member 11 ′. Here, the fiber member 11 ′ and the insulator 32 ′ located around the fiber member 11 ′ are made of a material having heat ductility. Next, as shown in FIG. 5A, the block body 31 is produced by stretching the sub-block body 31 '. The sub-block body 31 ′ can be stretched, for example, by heating it to a temperature at which ductility is manifested using a heating ring 61 and stretching it as shown in the illustrated example. By this stretching, the thickness D ′ of the fiber member 11 ′ in the sub-block body 31 ′ and the pitch P ′ of the fiber member 11 ′ are proportionally reduced, and the fiber members 11 having the thickness D are arranged at the pitch P. A block body 31 is obtained (see FIG. 5C). For example, about 10,000 fiber members 11 ′ having a thickness D ′ of 5 mm are arranged in an XY arrangement so that the pitch P ′ is 10 mm to produce a sub-block body 31 ′. On the other hand, by performing predetermined stretching, a block body 31 in which the fiber members 11 having a thickness D of 50 μm are arranged in an XY arrangement at a pitch P of 100 μm is obtained. In order to facilitate understanding, in FIG. 5A, the extending tip portion is omitted, and the fiber member 11 is shown protruding from the insulator 32.

Further, in the present invention, as described above, the fiber members 11 having the thickness D are arranged at the pitch P by the stretching of the sub-block bodies 31 'in which the fiber members 11' having the thickness D 'are arranged at the pitch P'. A small block body 31 ″ is manufactured, and a plurality of small block bodies 31 ″ are filled with an insulating material, as shown in FIG. 6, and a block body 31 in which the small block bodies 31 ″ are held by an insulator 32 is manufactured. As a result, it is possible to manufacture an interposer having a large main surface area. When a plurality of small block bodies 31 ″ are combined as described above, the fiber members between the small block bodies 31 ″ can be combined. 11 is placed in such a state that it is arranged at a pitch P, and fiber members 11 of thickness D are additionally arranged at a pitch P in the gap between them, in FIG. It is shown by a chain line.
Furthermore, the block body 31 produced as shown in FIG. 6 can be further extended to manufacture an interposer that meets the demand for a narrower pitch.
The extending means of the sub-block body 31 'is not limited to the method of pulling out the block body using a heating ring. For example, the entire sub-block body 31' is heated and extruded into a funnel-shaped container. The extrusion method etc. which form can also be mentioned.

<Base substrate manufacturing process>
Next, the base body 41 is produced by cutting the block body 31 with a desired thickness so that the fiber member 11 is divided in the longitudinal direction (see FIGS. 7A and 7B). The manufactured base substrate 41 has both main surfaces 41a and 41b which are cut surfaces of the block body 31, and the fiber member 11 is exposed on both main surfaces 41a and 41b. For ease of understanding, FIG. 7A shows the fiber member 11 protruding from the insulator 32, and FIG. 7B shows the fiber member 11 exposed on the main surface 41a. The end face is shown with diagonal lines.
The cut part of the block body 31 is a part which attached | subjected the chain line to FIG. 7 (A), for example, can cut out the base base material 41 with thickness of 500 micrometers. The cutting method of the block body 31 is not particularly limited. For example, a grinder or the like can be used. However, in the mechanical cutting method, since the main surfaces 41a and 41b of the base substrate 41 have irregularities, flatness If this is insufficient, surface polishing is preferred. By such surface polishing, for example, the base substrate 41 cut out with a thickness of 500 μm may be thinned to a desired thickness (for example, 300 μm).
The peripheral shape of the base substrate 41 produced in this way reflects the outer shape of the block body 31. If the block body 31 is a columnar shape, the peripheral shape is a circle, and if the block body 31 is a prismatic shape. The peripheral shape is a square. When the peripheral shape of the base substrate 41 is circular, there is an advantage that various manufacturing apparatuses used in the existing semiconductor wafer manufacturing process can be used. When the semiconductor device is cut out, it is cut into a lattice and separated into individual pieces, so that there is an advantage that the utilization efficiency of the interposer is increased (the occurrence of circuit chipping in the circumferential portion is small).

<Through hole formation process>
Next, the fiber member 11 exposed on both the main surfaces 41a and 41b of the base substrate 41 is removed by etching to form a plurality of through holes 42 whose openings are located in desired regions of the both main surfaces 41a and 41b. (See FIGS. 8A and 8B). In order to facilitate understanding, in FIG. 8A, the end surface of the fiber member 11 exposed on the main surface 41a is indicated by hatching.
The fiber member 11 is removed by etching using, for example, an acid-based etching solution such as hydrofluoric acid, nitric acid, and acetic acid. As described above, the fiber member 11 is made of an acid-soluble insulating material that can be corrosive etched with an acid-based etchant, while the insulating material used to manufacture the block body 31 is an electrical insulating material that has acid resistance. Therefore, the fiber member 11 can be removed by etching with an acid-based etchant. This etching can be performed by, for example, a spray method, an immersion method, or the like. In addition, it is not impossible to etch and remove the fiber member 11 in the state of the block body 31, but it is preferable to etch and remove the fiber member 11 after cutting as a base substrate because it becomes a fine through hole. .

After the formation of the through hole 42, the base substrate 41 is cleaned with water or the like by spraying or ultrasonic waves to smooth the surfaces of the main surfaces 41a and 41b of the base substrate 41. The adhesiveness of the conductor layer to be formed can be improved. Further, by performing alkali cleaning, the opening edge of the through hole 42 is smoothed, and the conductor layer and front and back conductive members formed in the subsequent process are prevented from being disconnected, and the base portion 41 is cut at the periphery. The sharp part of the head becomes smooth and the safety during handling is improved.
In the example of the base substrate 41 described above, the opening of the through hole 42 is located in the entire area of both the main surfaces 41a and 41b. However, the present invention is not limited to this, and desired regions of the both main surfaces 41a and 41b. The opening of the through hole 42 may be located only on the surface. For example, in the production of the block body 31 described above, the fiber member 11 is disposed so as to be located in a desired region of both the main surfaces 41a and 41b of the base substrate 41, and the fiber member 11 is removed by etching. Thus, the through hole 42 can be formed.

  Further, among the fiber members 11 exposed on both main surfaces 41a and 41b of the base substrate 41, the fiber member 11 that does not require the formation of a through hole is covered with an insulating protective layer, and then the exposed fiber. The member 11 may be removed by etching to form a through hole. FIG. 9 is a diagram for explaining such a case. Here, insulating protective layers 43a and 43b that cover the fiber member 11 that does not require through-hole formation are provided on the main surfaces 41a and 41b, respectively (FIG. 9A), and the fiber member exposed in this state. 11 can be removed by etching to form a through hole 42 (FIG. 9B). The fiber member 11 that does not require the formation of the through hole can be set in accordance with various specifications according to the semiconductor device, and thereby, in the method for manufacturing the semiconductor device described later, at the place where the front and back conduction is unnecessary. Front and back insulation can be performed more easily. That is, when all the fiber members 11 of the base substrate 41 are removed by etching and the through holes 42 are formed, and the front and back conductive members 44 are formed in the subsequent conductive process, the front and back conductive members 44 are not required at the places where the front and back conductive are unnecessary. Insulator layers that cover the ends of the film are required. However, by leaving the fiber member 11 that does not require through-hole formation (front / back conduction) in advance without etching away, the front / back insulation becomes easier and the manufacture of a highly reliable interposer and semiconductor device is easier. It becomes.

  The insulating protective layers 43a and 43b are made of an electrically insulating resin having good adhesion to the base substrate 41, such as polyimide resin, epoxy resin, benzocyclobutene (BCB), etc., by spin coating, doctor blade method, etc. Thus, it can be applied on the base substrate 41 and patterned. For this patterning, for example, a resist mask is formed by a method of removing a desired portion using a laser or the like, or a photolithography method, and unnecessary portions are removed by etching through the resist mask, and then the resist mask is removed. And a method of patterning by exposing, developing and patterning directly using a photosensitive resin by a photolithography method. The thicknesses of the insulating protective layers 43a and 43b can be appropriately set within a range of 1 to 10 μm, for example. In addition, the size of the opening of the insulating protective layers 43a and 43b for exposing the fiber member 11 for forming the through hole is the same as or slightly larger than the size of the exposed surface of the fiber member 11 in the main surfaces 41a and 41b. Is preferred. If the size of the opening of the insulating protective layers 43a and 43b is smaller than the size of the exposed surface of the fiber member 11 on the main surfaces 41a and 41b, a wrinkle of the insulating layer is formed at the opening portion in a later step. There is a possibility that a void is generated behind the screen, which is not preferable. For example, when the dimension of the exposed surface of the fiber member 11 (the thickness of the fiber member) is 50 μm, the size of the openings of the insulating protective layers 43a and 43b can be a circle having a diameter of about 70 μm.

<Conduction process>
Next, the through hole 42 of the base base material 41 is filled with a conductive material to form a front and back conductive member 44, and the main surfaces 41 a and 41 b of the base base material 41 are conductive to be connected to the front and back conductive member 44. Body layers 45a and 45b are formed (see FIG. 10).
Such front and back conductive member 44 and conductor layers 45a and 45b are formed by, for example, forming a copper or nickel seed layer on the surface of the base substrate 41 by electroless plating, and using the seed layer as a power feeding means. The conductive material of copper or nickel can be deposited by electroplating in 42 and on both main surfaces 41a and 41b.
The seed layer may be thin, for example, about 500 nm is sufficient. The seed layer may be a metal thin film formed by dry film formation such as vacuum deposition or sputtering. In this case, a refractory metal having good adhesion to glass such as chromium, titanium, tungsten, etc. is used. It is preferable to do.

The thicknesses of the conductor layers 45a and 45b can be appropriately set in consideration of the refinement of the conductor layer pattern formed in a later process, pattern accuracy, and the like, and can be set to, for example, about 1 to 5 μm. . Moreover, since the conductive material (for example, copper, nickel, etc.) is filled into the fine through-hole 42 by electroplating, depending on the electroplating conditions, the opening of the through-hole 42 in the formed conductor layers 45a and 45b. The part corresponding to the part may be convexly thick. In such a case, it is desirable to flatten the conductor layers 45a and 45b by polishing or the like so as not to hinder the formation of a multilayer wiring layer in a subsequent process.
In the present invention, the formation of the front and back conductive member 44 by filling the through hole 42 with the conductive material and the formation of the conductor layers 45a and 45b may be performed separately.

<Patterning process>
Next, the conductor layers 45a and 45b formed on the two main surfaces 41a and 41b of the base substrate 41 are patterned to form desired conductor layer patterns 46a and 46b (see FIG. 11).
The patterning of the conductor layers 45a and 45b can be performed using a conventional technique. For example, a resist mask is formed on the conductor layers 45a and 45b by photolithography, unnecessary portions of the conductor layers 45a and 45b are removed by etching, and then the resist mask is removed to remove the conductor layer pattern. 46a and 46b can be formed. In etching and removing unnecessary portions of the conductor layers 45a and 45b, for example, after etching copper or nickel formed by electroplating as described above, the seed layer material is also etched through the same resist mask.

  The patterns 46a and 46b, for example, lands, connected to the front / back conducting member 44 by this patterning are preferably larger than the opening size of the through hole 42 (thickness of the front / back conducting member 44), as shown in FIG. . This is for preventing the formation of stepped portions and holes in the conductor layer patterns 46a and 46b due to etching into the through holes due to misalignment of the resist mask during pattern formation. More specifically, for example, when through holes having a circular opening size of 50 μm are arranged at a pitch of 100 μm and the front and back conductive members 44 are positioned in the through holes, the land diameter is set to 80 μm in consideration of misalignment accuracy and the like. It can be. In this case, the distance between adjacent lands is 20 μm, and the insulation is sufficiently maintained.

<Multilayer wiring layer formation process>
Next, the multilayer wiring layer 51 is formed on the conductor layer pattern 46a formed on the main surface 41a of the base substrate 41 (see FIG. 13). Thereby, the interposer 1A is obtained.
In the illustrated example, a multilayer wiring layer is formed on the conductor layer pattern 46a, but a multilayer wiring layer may be formed on the conductor layer pattern 46b. Further, a multilayer wiring layer may be formed on both of the conductor layer patterns 46a and 46b. In this case, the front and back multilayer wiring layers may have different designs.
The multilayer wiring layer 51 has a fine pattern, and is used for interconnecting semiconductor chips in the method for manufacturing a semiconductor device of the present invention described later. The multilayer wiring layer 51 can be formed by repeating the formation of the insulating layer and the conductor layer on the conductor layer pattern 46a a desired number of times. In the illustrated example, the formation of the insulating layer and the conductor layer is performed twice. Is going. The insulating layer is formed by applying an insulating material such as polyimide with a desired thickness (for example, 10 μm) by a coating method such as spin coating, and then thermally curing, and then removing the portion where the interlayer connection via is provided by etching. Can be formed. Further, for example, a negative photosensitive polyimide varnish may be used as an insulating material, and a portion where an interlayer connection via is provided by a photomask may be shielded from light, exposed, developed, and thermally cured to form an insulating layer. . The conductor layer is formed, for example, by forming a conductive multilayer film (Ti / Cu, Cr / Cu / Cr, etc.) or a single layer film (Al, etc.) by a vacuum film formation method such as sputtering (for example, a thickness of 1 μm). And pattern formation (for example, minimum wiring width 10 μm / space 10 μm) by photolithography. Further, the thickness of the conductor layer may be increased (for example, about 5 μm) by electroplating or the like.

  In the method of manufacturing an interposer according to the present invention as described above, the fiber members are arranged at a pitch having a predetermined relationship with the thickness thereof, so that the inner diameter is constant in the depth direction and a high aspect ratio through-hole is stabilized. Can be formed. As a result, the through holes can be made finer and the pitch can be reduced, and the through-hole conductive members can be formed in the through holes to cope with the narrowing of the terminal connection pitch and the increase in the number of pins when the semiconductor chip is mounted on the semiconductor device. In addition, it is possible to manufacture an interposer in which connection failure and fixing failure are prevented at low cost. Furthermore, by appropriately designing the multilayer wiring layer formed in the conductor layer pattern, it is possible to manufacture an interposer corresponding to various semiconductor chips and various semiconductor device sizes.

  The above-described embodiment of the manufacturing method of the interposer is an exemplification, and the present invention is not limited to this. For example, as shown in FIG. 11, after the conductor layer patterns 46a and 46b are formed on both main surfaces 41a and 41b of the base substrate 41, as shown in FIG. 14 and FIG. Of the conductor layer pattern 46b formed on the surface 41b, the conductor layer pattern 46b connected to the front / back conducting member 44 inside the through hole 42 which does not require front / back conduction is covered with the insulating protective layer 48, and the base substrate The interposer 1B may be manufactured by forming the multilayer wiring layer 51 on the conductor layer pattern 46a formed on the other main surface 41a of 41. In FIG. 15, the insulating protective layer 48 is indicated by hatching. In this way, by covering the unnecessary conductor layer pattern 46b with the insulating protective layer 48, it is possible to prevent occurrence of a short circuit when the interposer is separately mounted on the mother board. The insulating protective layer 48 can be formed using, for example, an insulating material such as polyimide. The thickness of the insulating protective layer 48 only needs to prevent unnecessary contact between the conductor layer pattern 46b and the external terminal. It can be about several μm.

  Further, in the present invention, in the patterning step, the conductor layer pattern 46b formed on the main surface 41b of the base substrate 41 is formed as a large pattern connected to the plurality of front and back conductive members 44, and insulating protection is provided at a desired site. The layer 48 may be formed to manufacture the interposer 1C (see FIG. 16). Thereby, the dimension of the connection site | part at the time of mounting an interposer separately on a motherboard can also be enlarged. In FIG. 16, the conductor layer 45a on the main surface 41a side of the base substrate 41 is completely removed, and the multilayer wiring layer 51 is formed without forming the conductor layer pattern 46a. As described above, the patterning step includes the complete removal of the conductor layer as necessary.

  Moreover, as shown in FIG. 9 described above, insulating protective layers 43a and 43b that cover the fiber member 11 that does not require the formation of through holes are provided on the main surfaces 41a and 41b, respectively, and the exposed fiber member 11 is exposed. Then, after forming the through hole 42 by etching, the insulating protective layers 43a and 43b may be used as they are, and the conduction process and the subsequent steps may be performed as shown in FIG. In this case, with the insulating protective layers 43a and 43b left, the conductive material is filled in the through-holes 42 of the base substrate 41 to form the front and back conductive members 44 in the same manner as in the conductive process described above. Conductor layers 45a and 45b are formed on both main surfaces 41a and 41b of the base substrate 41 so as to be connected to the front and back conducting member 44 (see FIG. 17A). Next, in the same manner as the above patterning step, the conductor layers 45a and 45b formed on both the main surfaces 41a and 41b of the base substrate 41 are patterned to form desired conductor layer patterns 46a and 46b (FIG. 17 (B)). Further, the multilayer wiring layer 51 is formed on the conductor layer pattern 46a formed on the main surface 41a of the base substrate 41 in the same manner as in the multilayer wiring layer forming step described above (see FIG. 17C). Thereby, the interposer 1D is obtained.

[Method for Manufacturing Semiconductor Device]
(First embodiment)
This embodiment of the semiconductor device manufacturing method uses an interposer manufactured by the above-described interposer manufacturing method of the present invention, and here, a case where the above-described interposer 1B is used will be described as an example.
<Mounting board manufacturing process>
In the method for manufacturing a semiconductor device of the present invention, the semiconductor chip 100 is mounted on the multilayer wiring layer 51 of the interposer 1B to form the mounting substrate 110 (see FIG. 18).

The multilayer wiring layer 51 is configured with a fine pattern, and is also used for interconnecting the semiconductor chips 100. The semiconductor chip 100 to be mounted is not particularly limited. For example, a semiconductor chip in which terminals are rearranged can be used, and a three-dimensionally stacked semiconductor chip whose development has been activated recently can also be used.
Various flip chip mounting techniques can be used for connection between the semiconductor chip 100 and the interposer 1B. For example, a solder ball can be used, and Au stud bumps or copper pillars can be used as protruding electrodes. The protruding electrode of the formed semiconductor chip and the pad of the interposer may be connected by solder.

<Cutting process>
After mounting the semiconductor chip 100 as described above, the mounting substrate 110 is cut at a desired region 111 where one or more semiconductor chips are mounted and a circuit is formed, and the semiconductor device is separated into a desired size. (See FIG. 19). In the illustrated example, in order to show the positional relationship between the front and back conducting member 44, the semiconductor chip 100, and the region 111, the conductor layer pattern, the insulating layer constituting the multilayer wiring layer, and the conductor layer are omitted, and the semiconductor chip 100 is It is indicated by a chain line, and the cutting line is indicated by a two-dot chain line. Thereby, a semiconductor device is obtained. When two or more semiconductor chips 100 are mounted in the region 111 to be separated, these semiconductor chips 100 may be of the same type or different types.
In the present invention, in order to protect the semiconductor chip mounted on the interposer, the gap between the semiconductor chip 100 and the interposer 1B may be sealed with the resin member 105 as shown in FIG. 20, or as shown in FIG. As described above, the mounted semiconductor chip 100 may be sealed with the resin member 105.
In the above example, the interposer 1B manufactured by the method for manufacturing an interposer of the present invention is used, but any interposer manufactured by the method for manufacturing an interposer of the present invention such as the above-described interposers 1A, 1C, 1D, etc. is used. be able to.

(Second Embodiment)
In the embodiment of the semiconductor device manufacturing method, first, the interposer is manufactured as follows. In the production of this interposer, the arrangement process, the block body production process, the base substrate production process, the through hole formation process, and the conduction process of the above-described interposer production method of the present invention are common. For this reason, description to an arrangement process, a block body production process, a base substrate production process, a through-hole formation process, and a conduction process is omitted.

  After the conduction process of the manufacturing method of the above-described interposer of the present invention is completed, of the conductor layers 45a and 45b formed on both the main surfaces 41a and 41b of the base substrate 41 in the patterning process, the main surface 41a The formed conductor layer 45a is patterned to form a desired conductor layer pattern 46a. On the other hand, the conductor layer 45b formed on the main surface 41b is left as it is without patterning. Next, in the multilayer wiring layer forming step, the multilayer wiring layer 51 is formed on the conductor layer pattern 46a formed on the main surface 41a of the base substrate 41 to form the interposer 1E (see FIG. 22). In FIG. 22, the same member number as the member number in the description of the method for manufacturing the interposer of the present invention is used. This patterning step is different from the above-described patterning step of the method for manufacturing an interposer of the present invention in that only one conductor layer 45a is patterned. The conductor layer to be patterned is the conductor layer 45a in the illustrated example, but may be the conductor layer 45b. In addition, the formation of the multilayer wiring layer 51 in the multilayer wiring layer forming step can be the same as the multilayer wiring layer forming step of the above-described method for manufacturing the interposer of the present invention.

Next, in the mounting substrate manufacturing process, as in the first embodiment, the semiconductor chip 100 is mounted on the multilayer wiring layer 51 of the manufactured interposer 1E to form the mounting substrate 110.
Next, in the polishing step, polishing is performed from the side of the conductor layer 45b located on the main surface 41b of the base substrate 41 constituting the mounting substrate 110 to remove the conductor layer 45b, and the base substrate 41 Is reduced to a desired thickness (see FIG. 23). Reduction of the thickness of the interposer is inevitable in the demand for thinning of the semiconductor device. However, when the thickness of the base substrate 41 is reduced from, for example, 500 μm to 200 μm by polishing at the stage of manufacturing the interposer, handling is performed. Becomes difficult. However, in the method for manufacturing a semiconductor device of the present invention, since the base substrate 41 is polished and thinned after the semiconductor chip 100 is mounted on the interposer 1E in the mounting substrate manufacturing process, a reduction in handling properties is avoided. Can do.
Thereafter, in the cutting step, as in the first embodiment, the mounting substrate 110 is cut at a desired region 111 where one or more semiconductor chips are mounted and a circuit is formed. Divided into sizes (see FIG. 19 above). Thereby, a semiconductor device is obtained.

  In the present invention, as described above, the polishing process is performed to remove the conductor layer 45b, and the polishing surface in which the thickness of the base substrate 41 is reduced to a desired thickness is further etched, so that the base substrate 41 Part of the insulating material may be removed to expose the front and back conductive members 44 at a length of about 10 to 100 μm (see FIG. 24). The exposed tip portions of the front and back conductive members 44 thus formed serve as projecting electrodes, and such projecting electrodes have a uniform height compared to the projecting electrodes separately formed by electroplating, and the interposer is separately mounted on the motherboard. Connection reliability is high. In addition, you may perform surface treatments, such as a soldering process, to such a protruding electrode as needed.

  Further, as shown in FIG. 17A, after the above-described conduction process of the interposer manufacturing method of the present invention is completed, the semiconductor device can be manufactured by the manufacturing method of the second embodiment. In this case, a desired conductor layer is formed by patterning the conductor layer 45a formed on the main surface 41a out of the conductor layers 45a and 45b formed on both the main surfaces 41a and 41b of the base substrate 41 in the patterning step. A pattern 46a is formed. On the other hand, the conductor layer 45b formed on the main surface 41b is patterned to form the conductor layer pattern 46b in FIG. 17B. However, in this embodiment, the conductor layer 45b is left as it is without being patterned. Next, in the multilayer wiring layer forming step, the multilayer wiring layer 51 is formed on the conductor layer pattern 46a formed on the main surface 41a of the base substrate 41 to form an interposer. This patterning step is different from the patterning step of the method of manufacturing the interposer of the present invention shown in FIG. 17 in that only one of the conductor layers 45a is patterned. The conductor layer to be patterned is the conductor layer 45a in the illustrated example, but may be the conductor layer 45b. In addition, the formation of the multilayer wiring layer 51 in the multilayer wiring layer forming step can be the same as the multilayer wiring layer forming step of the above-described method for manufacturing the interposer of the present invention.

Next, in the mounting substrate manufacturing process, as in the first embodiment, the semiconductor chip 100 is mounted on the multilayer wiring layer 51 of the manufactured interposer to form the mounting substrate 110.
Next, in the polishing process, polishing is performed from the side of the conductor layer 45b located on the main surface 41b of the base substrate 41 constituting the mounting substrate 100, and the conductor layer 45b and the insulating protective layer 43b are removed. At the same time, the base substrate 41 is thinned to a desired thickness (see FIG. 23). Reduction of the thickness of the interposer is inevitable in the demand for thinning of the semiconductor device. However, when the thickness of the base substrate 41 is reduced from, for example, 500 μm to 200 μm by polishing at the stage of manufacturing the interposer, handling is performed. Becomes difficult. However, in the method for manufacturing a semiconductor device of the present invention, since the base substrate 41 is polished and thinned after the semiconductor chip 100 is mounted on the interposer 1E in the mounting substrate manufacturing process, a reduction in handling properties is avoided. Can do.
Thereafter, in the cutting step, as in the first embodiment, the mounting substrate 110 is cut at a desired region 111 where one or more semiconductor chips are mounted and a circuit is formed. Divided into sizes (see FIG. 19 above). Thereby, a semiconductor device is obtained.

Also in this embodiment, as described above, the polishing process is performed to remove the conductor layer 45b and the insulating protective layer 43b, and the polishing surface in which the thickness of the base substrate 41 is reduced to a desired thickness is further etched. Then, a part of the insulating material of the base substrate 41 may be removed to expose the front and back conductive members 44 at a length of about 10 to 100 μm (see FIG. 24). The exposed tip portions of the front and back conductive members 44 thus formed serve as projecting electrodes, and such projecting electrodes have a uniform height compared to the projecting electrodes separately formed by electroplating, and the interposer is separately mounted on the motherboard. Connection reliability is high. In addition, you may perform surface treatments, such as a soldering process, to such a protruding electrode as needed.
In the semiconductor device manufacturing method of the present invention as described above, the interposer is manufactured so that the diameter and pitch of the front and back conductive members have a predetermined relationship, and the semiconductor chip is mounted on the multilayer wiring layer of the interposer. Therefore, the connection reliability in mounting the semiconductor chip is high, the material use efficiency is improved, and the semiconductor device can be manufactured at low cost. In addition, by appropriately designing the multilayer wiring layer formed in the conductor layer pattern, it is possible to deal with various types of semiconductor chips and to manufacture a semiconductor device having a desired size.
The embodiment of the semiconductor device manufacturing method of the present invention described above is an exemplification, and the present invention is not limited to this.

Next, the present invention will be described in more detail by showing specific examples.
[Example]
<Sequence process>
A fiber member having a thickness D of 50 μm and an acid-soluble B ₂ O ₃ —BaO—La ₂ O ₃ glass was prepared. 780,000 fiber members were arranged in an XY arrangement so that the pitch P was 100 μm (twice the thickness D) using an arrangement jig as shown in FIG.
<Block body production process>
Next, acid-resistant borosilicate glass was prepared as an insulating material. With this insulating material in a molten state, the gap between the above fiber members was filled and then cooled to produce a cylindrical block having a diameter of 100 mm and a length of 100 mm.

<Base substrate manufacturing process>
The block body was cut with a grinder so that the fiber member was divided in the longitudinal direction to obtain a base substrate having a thickness of 500 μm. The surface of this base substrate is polished by buffing to a thickness of 300 μm, and then a nitric acid-based etchant is used as an acid-based etching solution, and fibers exposed on both main surfaces of the base substrate by an immersion method. The member was removed by etching, and then alkali cleaning and water cleaning were performed. As a result, 780,000 through holes with an opening diameter of 50 μm were formed in the base substrate in an XY arrangement with a pitch of 100 μm.
<Conduction process>
A copper thin film (thickness of about 500 nm) is formed on the base substrate by electroless plating to form a seed layer, and then a front and back conductive member is formed in the through hole of the base substrate by copper electroplating. Conductor layers (thickness 5 μm) were formed on both main surfaces.
<Patterning process>
A photosensitive resist (OFPR800 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied onto the conductor layer by spin coating, and exposed and developed through a desired photomask to form a resist mask. This resist mask was a circular mask having a diameter of 80 μm located on a portion where the front and back conductive members (diameter 50 μm) located in each through hole of the base substrate were exposed. Next, the conductor layer was removed by etching with a ferric chloride etchant through this resist mask to form a land having a diameter of 80 μm as a conductor layer pattern.

<Temperature cycle test>
The sample with the land formed on the base substrate as described above was subjected to the following temperature cycle test, and then the surface state was observed. As a result, defects such as cracks in the base substrate (thermoset resin) were not observed.
(Temperature cycle test conditions)
The temperature cycle is held 1000 times at -25 ° C for 30 minutes and then at 125 ° C for 30 minutes.

[Comparative example]
Except that the pitch P of the fiber member was 90 μm (1.8 times the thickness D), the land formation was performed in the same manner as in the example, and a sample was manufactured. This sample was subjected to the same temperature cycle test as in the example, and then the surface state was observed. As a result, occurrence of cracks in the base substrate (thermoset resin) was confirmed.

  The present invention can be applied to manufacture of an interposer and various products using the interposer.

1A, 1B, 1C, 1D, 1E ... Interposer 11, 11 '... Fiber member 31 ... Block body 31' ... Sub-block body 31 "... Small block body 32, 32 '... Insulator 41 ... Base substrate 42 ... Through hole 43a, 43b ... Insulating protective layer 44 ... Front / back conducting member 45a, 45b ... Conductor layer 46a, 46b ... Conductor layer pattern 51 ... Multilayer wiring layer 100 ... Semiconductor chip 110 ... Mounting substrate

Claims (17)

An arrangement step of arranging a plurality of fiber members at a predetermined pitch P;
A block body manufacturing step of filling a space between the arrayed fiber members with an insulating material and manufacturing a block body in which the fiber members are held by an insulator;
A base substrate production step of producing a base substrate by cutting the block body so that the fiber member is divided in the longitudinal direction;
A through-hole forming step in which the fiber member exposed on both main surfaces of the base substrate is removed by etching, and a plurality of through-holes in which openings are located in a partial region or the entire region of both main surfaces;
A conductive step of filling the through hole of the base substrate with a conductive material to form a front and back conductive member, and forming a conductor layer on both main surfaces of the base substrate so as to be connected to the front and back conductive member; ,
A patterning step of patterning the conductor layers formed on both main surfaces of the base substrate to form a conductor layer pattern;
A multilayer wiring layer forming step of forming a multilayer wiring layer on at least one conductor layer pattern of the conductor layer pattern formed on both main surfaces of the base substrate,
In the arranging step, the pitch P is set so as to satisfy the relationship of 2D ≦ P <4D with respect to the thickness D of the fiber member.   In the through-hole forming step, among the fiber members exposed on both main surfaces of the base substrate, a fiber member that does not require through-hole formation is covered with an insulating protective layer, and then exposed. The method for manufacturing an interposer according to claim 1, wherein the through hole is formed by etching away a fiber member.   In the multilayer wiring layer forming step, among the conductor layer patterns formed on one main surface of the base substrate, the conductor layer pattern connected to the conductive material inside the unnecessary through hole is insulated. 2. The method for manufacturing an interposer according to claim 1, wherein the multilayer wiring layer is formed on the conductor layer pattern formed on the other main surface of the base substrate by covering with a protective layer.   The method for manufacturing an interposer according to any one of claims 1 to 3, wherein the fiber member and the insulating material have heat ductility.   In the block body manufacturing step, the fiber members are arranged by filling a space between the arrayed fiber members with an insulating material, manufacturing a subblock body in which the fiber members are held by an insulator, and extending the subblock body. The arrangement pitch is made narrower, and a block body in which the arrangement pitch P of the drawn fiber members satisfies the relationship of 2D ≦ P <4D with respect to the thickness D of the drawn fiber members is produced. The manufacturing method of the interposer of Claim 4.   In the block body manufacturing step, the fiber members are arranged by filling a space between the arrayed fiber members with an insulating material, manufacturing a subblock body in which the fiber members are held by an insulator, and extending the subblock body. The arrangement pitch P is narrowed to produce a small block body in which the arrangement pitch P of the fiber members after drawing satisfies the relationship 2D ≦ P <4D with respect to the thickness D of the fiber members after drawing. 5. The method of manufacturing an interposer according to claim 4, wherein a space between the small block bodies is filled with an insulating material to produce a block body in which the small block bodies are held by the insulator.   The method for manufacturing an interposer according to any one of claims 1 to 6, wherein the fiber member and the insulating material have different colors.   The interposer manufacturing method according to any one of claims 1 to 7, wherein, in the base substrate preparation step, at least one main surface of the base substrate obtained by cutting the block body is polished. Method. A mounting substrate manufacturing step of mounting a semiconductor chip on the multilayer wiring layer of the interposer including the multilayer wiring layer;
A cutting step of cutting the mounting substrate in a region where one or more semiconductor chips are mounted and a circuit is formed, and singulating into a size of a semiconductor device,
The method for manufacturing a semiconductor device, wherein the interposer is manufactured by the method for manufacturing an interposer according to any one of claims 1 to 8. An arrangement step of arranging a plurality of fiber members at a predetermined pitch P;
A block body manufacturing step of filling a space between the arrayed fiber members with an insulating material and manufacturing a block body in which the fiber members are held by an insulator;
A base substrate production step of producing a base substrate by cutting the block body so that the fiber member is divided in the longitudinal direction;
A through-hole forming step in which the fiber member exposed on both main surfaces of the base substrate is removed by etching, and a plurality of through-holes in which openings are located in a partial region or the entire region of both main surfaces;
A conductive step of filling the through hole of the base substrate with a conductive material to form a front and back conductive member, and forming a conductor layer on both main surfaces of the base substrate so as to be connected to the front and back conductive member; ,
A patterning step of patterning the conductor layer formed on one main surface of the base substrate to form a conductor layer pattern;
A multilayer wiring layer forming step of forming a multilayer wiring layer on the conductor layer pattern;
A mounting substrate manufacturing step of mounting a semiconductor chip on the multilayer wiring layer;
A polishing step of performing polishing from the conductor layer side formed on the other main surface of the base substrate to remove the conductor layer and adjusting the thickness of the base substrate;
A cutting step of cutting the mounting substrate in a region where one or more semiconductor chips are mounted and a circuit is formed, and singulating into a size of a semiconductor device,
In the arranging step, the pitch P is set so as to satisfy the relationship of 2D ≦ P <4D with respect to the thickness D of the fiber member.   In the through-hole forming step, among the fiber members exposed on both main surfaces of the base substrate, a fiber member that does not require through-hole formation is covered with an insulating protective layer, and then exposed. The method for manufacturing an interposer according to claim 10, wherein the through hole is formed by etching away a fiber member.   The method for manufacturing an interposer according to claim 10 or 11, wherein the fiber member and the insulating material have heat ductility.   In the block body manufacturing step, the fiber members are arranged by filling a space between the arrayed fiber members with an insulating material, manufacturing a subblock body in which the fiber members are held by an insulator, and extending the subblock body. The arrangement pitch is made narrower, and a block body in which the arrangement pitch P of the drawn fiber members satisfies the relationship of 2D ≦ P <4D with respect to the thickness D of the drawn fiber members is produced. The method for producing an interposer according to claim 12.   In the block body manufacturing step, the fiber members are arranged by filling a space between the arrayed fiber members with an insulating material, manufacturing a subblock body in which the fiber members are held by an insulator, and extending the subblock body. The arrangement pitch P is narrowed to produce a small block body in which the arrangement pitch P of the fiber members after drawing satisfies the relationship 2D ≦ P <4D with respect to the thickness D of the fiber members after drawing. 13. The method of manufacturing an interposer according to claim 12, wherein a space between the small block bodies is filled with an insulating material to produce a block body in which the small block bodies are held by the insulator.   The method for manufacturing an interposer according to any one of claims 10 to 14, wherein the fiber member and the insulating material have different colors.   The interposer production according to any one of claims 10 to 15, wherein, in the base substrate manufacturing step, at least one main surface of the base substrate obtained by cutting the block body is polished. Method.   17. The semiconductor device according to claim 10, wherein, in the polishing step, the insulator is etched from a polished surface side to partially expose the front and back conductive members. Production method.

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