JP2013219521A - Comparator and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a comparator and semiconductor device, capable of concurrently achieving high switching speed of a signal level of an output signal and power saving.SOLUTION: A voltage to be compared is applied within a period from the time that the magnitude of the voltage to be compared reaches a magnitude corresponding to a release voltage with a shunt channel 19 closed by closing a continuity path in a current adjustment circuit 18 to the time that the magnitude reaches a magnitude corresponding to a closing voltage to close the continuity path in the current adjustment circuit 18 and hence an electric current generated by a constant current circuit 12 is controlled to increase.

Description

  The present invention relates to a comparator and a semiconductor device.

  Patent Document 1 discloses a technique for improving the operation speed or power saving of a comparator included in a semiconductor device. A specific circuit configuration according to this technique is shown in FIG.

  The comparator 100 shown in FIG. 21 includes a current mirror circuit 102, a differential circuit 104, and a bias enhancement circuit 106. The current mirror circuit 102 includes a plurality of P-channel MOS field effect transistors (hereinafter referred to as “PMOS transistors”) 102A, 102B, and 102C, and each of the PMOS transistors 102A, 102B, and 102C has a current mirror ratio. A constant current flows.

  The differential circuit 104 includes two pairs of PMOS transistors 104A and 104B and N-channel MOS field effect transistors (hereinafter referred to as “NMOS transistors”) 104C and 104D which are paired with each other. An input signal IN is input to the differential circuit 104, and when the voltage of the input signal IN exceeds the magnitude of the reference voltage VR applied to the reference terminal A, the output signal OUT output from the output terminal The signal level becomes low level. On the other hand, when the voltage of the input signal IN falls below the reference voltage VR, the signal level of the output signal OUT becomes high.

  The bias enhancement circuit 106 contributes to improvement in the operation speed of the comparator 100 or power saving. FIG. 22 shows a specific circuit configuration of the bias enhancement circuit 106. A reference voltage VC, which is a voltage smaller than the reference voltage VR, is applied to the reference terminal B shown in FIG. When the input signal IN shown in the upper graph of FIG. 23 is input to the input terminal and the voltage of the input signal IN exceeds the reference voltage VC, as shown in the middle graph of FIG. 22 and FIG. A drain current ID flows. As a result, as shown in the lower graphs of FIGS. 21, 22, and 23, the bias enhancement current IB is supplied as a drive current to the differential circuit shown in FIG.

  In this way, by setting the reference voltage VC in advance, the driving current of the differential circuit 104 shown in FIG. 21 can be converted into the output signal OUT before the voltage of the input signal IN reaches the reference voltage VR. The optimal current value required for switching the signal level can be reached, and the time from when the input signal IN is input to when the signal level of the output signal OUT is switched can be shortened. In the comparator 100 shown in FIG. 21, after switching the signal level of the output signal OUT, the driving current of the differential circuit 104 shown in FIG. I try to plan.

  In Patent Document 1, a comparator 101 shown in FIG. 24 is proposed in order to further reduce power consumption. The comparator 101 shown in FIG. 24 is different from the comparator 100 shown in FIG. 22 in that a bias enhancement circuit 108 is applied instead of the bias enhancement circuit 106. A specific configuration of the bias enhancement circuit 108 shown in FIG. 24 is shown in FIG. The bias enhancement circuit 108 shown in FIG. 25 includes a first feedback circuit 110 and a second feedback circuit, and inputs the feedback signal output from the connection point A shown in FIG. 24 to the first feedback circuit 112. As shown in FIG. 24, the feedback signal output from the connection point B is input to the second feedback circuit 112, so that the bias enhancement current IB flows only in the vicinity of the inversion operation time of the differential circuit 104 shown in FIG. That is, when the switching operation of the signal level of the output signal OUT of the comparator 101 is detected, the driving current of the differential circuit 104 shown in FIG. 24 is increased to improve the operation speed of the comparator 101 and the input signal IN. Without waiting for the voltage to drop, the driving current of the differential circuit 104 shown in FIG. 24 is reduced to save power.

Japanese Patent Laid-Open No. 2002-217691

  However, since the bias enhancement circuit 106 shown in FIG. 22 is a technique based on the premise that the voltage due to the input signal IN decreases after the signal level of the output signal OUT of the comparator 100 is switched, the differential circuit shown in FIG. In order to lower the driving current 104 again, it is necessary to wait for a voltage drop due to the input signal IN, so that the current consumption during that time is wasted. 25 detects the switching operation of the signal level of the output signal OUT of the comparator 101 and increases the driving current of the differential circuit 104 shown in FIG. 24, so that at least the switching operation is performed. Therefore, the switching of the signal level of the output signal OUT of the comparator 101 is delayed by the amount of waiting for the detection of this. As described above, the technique described in Patent Document 1 has a problem that it is difficult to achieve both improvement in the switching speed of the signal level of the output signal OUT and power saving.

  The present invention has been made to solve the above-described problems, and provides a comparator and a semiconductor device capable of realizing both improvement in the switching speed of the signal level of the output signal and power saving. With the goal.

  In order to achieve the above object, the comparator according to claim 1 includes a current generating unit that generates a current having a predetermined magnitude, a shunt path that shunts a current generated by the current generating unit, and the current. An output switching means that is driven by supplying the current generated by the generating means and switches the output level when the magnitude of the applied comparison target voltage reaches the reference voltage magnitude, and is inserted into the branch flow path And having a conducting path capable of conducting the shunt path, and closing the conducting path by applying the comparison target voltage having a magnitude corresponding to a closing voltage of a magnitude that closes the conducting path. Control for controlling the current flowing through the diversion channel by releasing the closing of the conduction path by applying the comparison target voltage having a magnitude corresponding to the release voltage having a magnitude for releasing the closing of the conduction path A level corresponding to the closing voltage after the magnitude of the comparison target voltage reaches a magnitude corresponding to the release voltage in a state where the shunt flow path is closed by closing the conduction path. Control means for controlling to increase the current generated by the current generating means by releasing the closing of the conduction path by applying the voltage to be compared until it reaches .

  In order to achieve the above object, the semiconductor device according to claim 15 is obtained by integrating the comparator according to any one of claims 1 to 14 into one chip.

  According to the present invention, it is possible to achieve an effect that an improvement in switching speed of a signal level of an output signal and power saving can be realized.

It is a circuit diagram which shows an example of a structure of the comparator which concerns on embodiment. It is a characteristic view which shows the characteristic of the comparator which concerns on embodiment. It is a state transition diagram showing an example of a switching state transition of a pair of NMOS transistors included in the current adjustment circuit according to the embodiment. It is a schematic diagram which shows an example of the flow of the electric current in the comparator which concerns on embodiment. It is a state transition diagram which shows another example of the state transition of switching of a pair of NMOS transistor contained in the current adjustment circuit which concerns on embodiment. It is a characteristic view which shows the characteristic of a comparator when alternating current is supplied to the comparator which concerns on embodiment. It is a circuit diagram which shows the other example (the 1) of the comparator which concerns on embodiment. It is a characteristic view which shows the characteristic of the comparator shown in FIG. It is a circuit diagram which shows the other example of a form of the comparator which concerns on embodiment (the 2). It is a circuit diagram which shows the other example (the 3) of the comparator which concerns on embodiment. It is a characteristic view which shows the characteristic of the comparator shown in FIG. It is a circuit diagram which shows the other example of a comparator which concerns on embodiment (the 4). It is a circuit diagram which shows the other example (No. 5) of the comparator which concerns on embodiment. It is a circuit diagram which shows the other form example (the 6) of the comparator which concerns on embodiment. It is a circuit diagram which shows the other example (the 7) of the comparator which concerns on embodiment. FIG. 16 is a circuit diagram illustrating an example of a circuit inserted in the comparator illustrated in FIG. 15. It is a circuit diagram which shows the other example of a comparator which concerns on embodiment (the 8). It is a circuit diagram which shows the other form example (the 9) of the comparator which concerns on embodiment. It is a circuit diagram which shows the other form example (the 10) of the comparator which concerns on embodiment. It is a circuit diagram which shows the other example (11) of the comparator which concerns on embodiment. It is a circuit diagram which shows an example of a structure of the conventional comparator. FIG. 22 is a circuit diagram showing an example of a configuration of a bias enhancement circuit included in the comparator shown in FIG. 21. FIG. 22 is a characteristic diagram illustrating characteristics of the comparator illustrated in FIG. 21. It is a circuit diagram which shows an example of a structure of the conventional comparator. FIG. 25 is a circuit diagram showing an example of a configuration of a bias enhancement circuit included in the comparator shown in FIG. 24.

  Embodiments for carrying out the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing an example of the configuration of the comparator 10 according to the present embodiment. As shown in FIG. 1, the comparator 10 includes a high voltage line VDD, a low voltage line VSS, a constant current circuit 12, a current mirror circuit 14, an output switching circuit 16, a current adjustment circuit 18, a shunt path 19, and an adjustment timing setting circuit 20. And the output circuit 22, which are a single-chip semiconductor device.

  The high voltage line VDD applies a high voltage (3V as an example here) to circuit elements constituting the comparator 10 (hereinafter simply referred to as “circuit elements”), and the low voltage line VSS is a circuit element. In contrast, a low voltage (here, 0 V as an example) is applied to the circuit element.

  The constant current circuit 12 is a circuit for generating a current having a predetermined magnitude and supplying the generated current to a circuit element, and includes a constant current source 12a and NMOS transistors 12b and 12c. . The constant current source 12a has a positive terminal and a negative terminal. The positive terminal of the constant current source 12a is connected to the high voltage line VDD, and the negative terminal of the constant current source 12a is connected to the drain of the NMOS transistor 12b. In the NMOS transistor 12b, the drain is connected to the gate, and the source is connected to the low voltage line VSS. In the NMOS transistor 12b, the back gate is connected to the source. In the NMOS transistor 12c, the source is connected to the low voltage line VSS, and the back gate is connected to the source. The constant current circuit 12 is connected to the current mirror circuit 14. Therefore, the constant current circuit 12 can generate a current having a predetermined magnitude and supply the generated current to the current mirror circuit 14.

  The current mirror circuit 14 includes PMOS transistors 14a, 14b, and 14c. The sources of the PMOS transistors 14a, 14b, and 14c are connected to the high voltage line VDD. The gates of the PMOS transistors 14a, 14b, and 14c are connected to each other. In each of the PMOS transistors 14a, 14b, and 14c, the back gate is connected to the source. In the PMOS transistor 14a, the gate is connected to the drain. In addition, the drain of the PMOS transistor 14a is connected to the drain of the NMOS transistor 12C included in the constant current circuit 12, whereby the constant current circuit 12 and the current mirror circuit 14 are connected. The current mirror circuit 14 is also connected to the output switching circuit 16, the current adjustment circuit 18, and the adjustment time setting circuit 20. Accordingly, the current mirror circuit 14 determines the current supplied from the constant current circuit 12 according to the sizes of the PMOS transistors 14a, 14b, and 14c with respect to the output switching circuit 16, the current adjustment circuit 18, and the adjustment timing setting circuit 20. A current having a magnitude corresponding to the current mirror ratio (hereinafter also referred to as “driving current”) can be applied. Here, “size” means the size of the active region included in the PMOS transistor or NMOS transistor, and means the size defined by the gate length and the gate width, for example.

The output switching circuit 16 has an external voltage applied to the comparator 10 (hereinafter referred to as “input voltage”) IN ₁ and IN ₂ , one of which is a reference voltage and the other is a target voltage (hereinafter referred to as a reference voltage) to be compared with the reference voltage. The output level of the comparator 10 is switched by outputting a comparison result signal indicating the comparison result between the magnitude of the reference voltage and the magnitude of the comparison target voltage. Here, “switching the output level” means switching the signal level of the output signal OUT that is finally output from the comparator 10.

The output switching circuit 16 is a so-called differential circuit, and includes PMOS transistors 16a and 16b and NMOS transistors 16c and 16d. In each of the PMOS transistors 16a and 16b, the back gate is connected to the back gate of the PMOS transistor 14c included in the current mirror circuit 14, and the source is connected to the drain of the PMOS transistor 14c. The gate of the PMOS transistor 16a is an input voltage IN ₁ is connected to the inverting input terminal 24 is applied. The gate of the PMOS transistor 16b, the input voltage IN ₂ is connected to a non-inverting input terminal 26 is applied.

  In the NMOS transistors 16c and 16d, the gates are connected to each other, and the sources are connected to the low voltage line VSS. In the NMOS transistor 16c, the back gate is connected to the source. In the NMOS transistor 16c, the drain is connected to the gate, and is connected to the drain of the PMOS transistor 16a. In the NMOS transistor 16d, the back gate is connected to the source, and the drain is connected to the drain of the PMOS transistor 16b.

  The drains of the PMOS transistors 16 a and 16 b included in the output switching circuit 16 are connected to the output circuit 22. Therefore, the output switching circuit 16 can output the comparison result signal to the output circuit 22.

  The shunt channel 19 is a current path that shunts the current generated by the constant voltage circuit 12. One end of the shunt channel 19 is connected to the drain of the PMOS transistor 14a included in the current mirror circuit 14, and the other end of the shunt channel 19 is connected to the low voltage line VSS. Therefore, the shunt channel 19 can shunt the current flowing through the PMOS transistor 14a of the current mirror circuit 14 (current generated by the constant voltage circuit 12).

  The current adjustment circuit 18 is a circuit for adjusting the current flowing through the current mirror circuit 14. The current adjusting circuit 18 is inserted into the branch channel 19 and includes NMOS transistors 18a and 18b. The NMOS transistors 18a and 18b are connected in series so as to form a conduction path that allows the branch path 19 to be conducted.

  The back gates of the NMOS transistors 18a and 18b are connected to the source of the NMOS transistor 18b. The source of the NMOS transistor 18a is connected to the drain of the NMOS transistor 18b. The drain of the NMOS transistor 18 a is connected to the drain of the PMOS transistor 14 a included in the current mirror circuit 14. The source of the NMOS transistor 18b is connected to the low voltage line VSS. The gates of the NMOS transistors 18 a and 18 b are connected to the adjustment timing setting circuit 20. Therefore, the current adjustment circuit 18 can adjust the current flowing through the current mirror circuit 14 by switching on and off each of the NMOS transistors 18 a and 18 b by the adjustment timing setting circuit 20.

  The adjustment time setting circuit 20 is a circuit for setting a time when the current adjustment circuit 18 adjusts the current flowing through the current mirror circuit 14. The adjustment timing setting circuit 20 is a so-called differential circuit, and generates a pair of control voltages that increase and decrease so that the magnitudes are inconsistent with each other in accordance with the difference between the magnitude of the reference voltage and the magnitude of the applied comparison target voltage. To do. The pair of control voltages are used as a closing voltage with a magnitude for closing the conduction path of the current adjusting circuit 18 and a release voltage with a magnitude for releasing the closure of the conduction path.

  The adjustment timing setting circuit 20 includes PMOS transistors 20a and 20b and NMOS transistors 20c and 20d, and is a circuit configured by connecting two series circuits in parallel. That is, a series circuit in which the PMOS transistor 20a and the NMOS transistor 20c are connected in series and a series circuit in which the PMOS transistor 20b and the NMOS transistor 20d are connected in series are connected in parallel.

  In each of the PMOS transistors 20a and 20b, the back gate is connected to the back gate of the PMOS transistor 14b included in the current mirror circuit 14, and the source is connected to the drain of the PMOS transistor 14b.

  In each of the NMOS transistors 20c and 20d, the back gate is connected to the source, and the gate is connected to the drain. In the NMOS transistor 20c, the drain is connected to the drain of the PMOS transistor 20a, and the source is connected to the low voltage line VSS. In the NMOS transistor 20d, the drain is connected to the drain of the PMOS transistor 20b, and the source is connected to the low voltage line VSS.

  The gate of the PMOS transistor 20 a is connected to the non-inverting input terminal 26, and the gate of the PMOS transistor 20 b is connected to the inverting input terminal 24. The drain of the PMOS transistor 20a is connected to the gate of the NMOS transistor 18b included in the current adjustment circuit 18, and the drain of the PMOS transistor 20b is connected to the gate of the NMOS transistor 18a included in the current adjustment circuit 18.

  The adjustment timing setting circuit 20 configured as described above applies one of a pair of control voltages having a magnitude corresponding to the closing voltage to one of the NMOS transistors 18a and 18b included in the current adjustment circuit 18, and the NMOS transistor 18a. , 18b is applied to the other one of a pair of control voltages having a magnitude corresponding to the closing voltage, so that the NMOS transistors 18a, 18b are in an opposite switching state (for example, the NMOS transistor 18a is turned on and the NMOS transistor 18b is turned off). To do. The adjustment timing setting circuit 20 applies one of a pair of control voltages having a magnitude corresponding to the release voltage to one of the NMOS transistors 18a and 18b included in the current adjustment circuit 18 and the other of the NMOS transistors 18a and 18b. The other of the pair of control voltages having a magnitude corresponding to the release voltage is applied to the NMOS transistors 18a and 18b. After the NMOS transistors 18a and 18b are turned on in this way, the adjustment timing setting circuit 20 applies a pair of control voltages having a magnitude corresponding to the closing voltage to one of the NMOS transistors 18a and 18b included in the current adjustment circuit 18. And the other of the pair of control voltages having a magnitude corresponding to the closing voltage is applied to the other of the NMOS transistors 18a and 18b, thereby causing the NMOS transistors 18a and 18b to switch to another opposite switching state (for example, an NMOS transistor). 18a is turned off and NMOS transistor 18b is turned on).

Therefore, the adjustment timing setting circuit 20 can set the ON / OFF switching timing of each of the NMOS transistors 18a and 18b included in the current adjustment circuit 18 based on the input voltages IN ₁ and IN ₂ . The timing for adjusting the current flowing through the current mirror circuit 14 by the current adjustment circuit 18 can be set.

  The output circuit 22 is a circuit that outputs an output signal OUT having a signal level corresponding to the signal level of the comparison result signal output from the output switching circuit 16, and includes a current mirror circuit 28, CMOS inverters 30 and 32, and NMOS transistors 22a, 22b is comprised. The current mirror circuit 28 includes PMOS transistors 28a and 28b. The sources of the PMOS transistors 28a and 28b are connected to the high voltage line VDD. The gates of the PMOS transistors 28a and 28b are connected to each other. In each of the PMOS transistors 28a and 28b, the back gate is connected to the source. In the PMOS transistor 28a, the gate is connected to the drain. Therefore, a current having a magnitude obtained by multiplying the magnitude of the current flowing between the source and drain of the PMOS transistor 28a by a predetermined coefficient flows between the source and drain of the PMOS transistor 28b. . Here, the “predetermined coefficient” means a value corresponding to a current mirror ratio that is uniquely determined by the size ratio between the PMOS transistor 28a and the PMOS transistor 28b.

  The CMOS inverter 30 includes a PMOS transistor 30a and an NMOS transistor 30b. In the PMOS transistor 30a, the source is connected to the high voltage line VDD, and the back gate is connected to the source. In the NMOS transistor 30b, the source is connected to the low voltage line VSS, and the back gate is connected to the source. The gates of the PMOS transistor 30a and the NMOS transistor 30b are connected to each other, and are connected to the drain of the PMOS transistor 28b included in the current mirror circuit 28. Further, the drains of the PMOS transistor 30a and the NMOS transistor 30b are connected to each other.

  The CMOS inverter 32 includes a PMOS transistor 32a and an NMOS transistor 32b. In the PMOS transistor 32a, the source is connected to the high voltage line VDD, and the back gate is connected to the source. In the NMOS transistor 32b, the source is connected to the low voltage line VSS, and the back gate is connected to the source. The gates of the PMOS transistor 32 a and the NMOS transistor 32 b are connected to each other, and are connected to the drain of the PMOS transistor 30 a included in the CMOS inverter 30. The PMOS transistor 32 a and the NMOS transistor 32 b are connected to each other at their drains and are connected to the output terminal 34 of the comparator 10.

  In the NMOS transistor 22 a, the source is connected to the low voltage line VSS, and the drain is connected to the drain of the PMOS transistor 28 a included in the current mirror circuit 28. In the NMOS transistor 22 a, the back gate is connected to the source, and the gate is connected to the drain of the PMOS transistor 16 a included in the output switching circuit 16.

  In the NMOS transistor 22 b, the source is connected to the low voltage line VSS, and the drain is connected to the drain of the PMOS transistor 28 b included in the current mirror circuit 28. In the NMOS transistor 22 b, the back gate is connected to the source, and the gate is connected to the drain of the PMOS transistor 16 b included in the output switching circuit 16.

  The output circuit 22 configured in this manner outputs an output signal OUT whose signal level is low level (L level) or high level (H level). That is, in the normal state, the output signal OUT having the signal level of L level is output, and the signal level of the output signal OUT is shifted to H level based on the comparison result signal input from the output switching circuit 16. In this embodiment, the normal signal level of the output signal OUT is set to the L level. However, the present invention is not limited to this, and the normal signal level may be set to the H level.

  By the way, in the comparator 10 according to the present embodiment, the sizes of the PMOS transistors 16a, 16b, 20a, and 20b are determined in advance so that the threshold voltages of the PMOS transistors 16a, 16b, 20a, and 20b are uniform, and the NMOS transistor 16c. , 16d, 20c, and 20d, the sizes of the NMOS transistors 16c, 16d, 20c, and 20d are determined in advance so that the threshold voltages are uniform. Further, the NMOS transistors 18a and 18b have predetermined sizes so that the threshold voltages are not different from each other, and the transition speed from on to off and the transition speed from off to on are not different under a predetermined voltage application condition. ing. Further, the sizes of the NMOS transistors 18a and 18b are the currents that flow through the current adjustment circuit 18 during the transition of the signal level of the output signal OUT (for example, the center of the transition process) when the comparison target voltage reaches the reference voltage. (The magnitude of the current flowing between the NMOS transistor 18a and the NMOS transistor 18b) is determined in advance. Specifically, as shown in FIG. 3 as an example, one of the NMOS transistors 18a and 18b has an on-to-off transition period and the other off-to-on transition period that overlap each other in the overlapping period. The sizes of the NMOS transistors 18a and 18b are set in advance so that the time when the sizes of the paths are equal coincides with the transition time of the signal level of the output signal OUT (preferably the center of the transition time).

Next, the operation of the comparator 10 according to the present embodiment will be described. In the following, in order to avoid complications, a case where the input voltage IN ₁ is set as a reference voltage and the input voltage IN ₂ is set as a comparison target voltage will be described with reference to FIGS. FIG. 2 is a graph showing temporal changes in voltage and current in the comparator 10 when direct current is supplied to the non-inverting input terminal 26. In FIG. 2, “VIN” is a voltage to be compared (in this example, the input voltage IN ₂ ), and “VREF” is a reference voltage (in this example, the input voltage IN ₁ ). “VOUT” is a voltage generated by the output signal OUT, and “IDD” is a current flowing through the current mirror circuit 14.

When the input voltage IN ₂ is 0V, the constant current circuit 12 generates a current having a predetermined magnitude. This current is adjusted to a magnitude corresponding to the current mirror ratio determined by the current mirror circuit 14 and supplied to the output switching circuit 16, the current adjustment circuit 18 and the adjustment timing setting circuit 20. At this time, the input voltage IN ₁ is maintained at a predetermined magnitude shown in FIG. 2 as an example. Therefore, the current path between the source and drain of the PMOS transistor 20b is opened to a predetermined size (for example, an intermediate state between “ON” and “OFF”). As a result, current flows between the source and drain of the PMOS transistor 20b and NMOS transistor 20d, and the PMOS transistor 20a and NMOS transistor 20c are turned on, and between the source and drain of each of the PMOS transistor 20a and NMOS transistor 20c are PMOS transistors. A current larger than the current flowing between the source and drain of each of 20b and NMOS transistor 20d flows.

  At this time, a voltage exceeding the threshold voltage is applied to the gate of the NMOS transistor 18b of the current adjustment circuit 18, and the NMOS transistor 18b is turned on. At this time, although current flows between the sources and drains of the PMOS transistor 20b and the NMOS transistor 20d, a voltage exceeding the threshold voltage is not applied to the gate of the NMOS transistor 18a of the current adjustment circuit 18. Since no voltage is applied, the NMOS transistor 18a is turned off. At this time, the PMOS transistors 16a and 16b and the NMOS transistors 16c and 16d included in the output switching circuit 16 are also in the same switching state as the PMOS transistors 20a and 20b and the NMOS transistors 20c and 20d included in the adjustment timing setting circuit 20. Become. That is, the PMOS transistor 16a is in the same switching state as the PMOS transistor 20b, the PMOS transistor 16b is in the same switching state as the PMOS transistor 20a, the NMOS transistor 16c is in the same switching state as the NMOS transistor 20d, and the NMOS transistor 16d is the NMOS transistor. The switching state is the same as in 20c.

  As a result, in the output circuit 22, a voltage exceeding the threshold voltage is not applied to the gate of the NMOS transistor 22a, and the NMOS transistor 22a is turned off. At this time, since a voltage exceeding the threshold voltage is applied to the gate of the NMOS transistor 22b and the NMOS transistor 22b is turned on, a current flows between the source and drain of each of the PMOS transistor 28b and the NMOS transistor 22b. Although the PMOS transistor 28a included in the current mirror circuit 28 is turned on, since the NMOS transistor 22a is turned off as described above, no current flows between the sources and drains of the PMOS transistor 28a and the NMOS transistor 22a. . Therefore, in the CMOS inverter 30, the PMOS transistor 30a is turned on and the NMOS transistor 30b is turned off. In response, in the CMOS inverter 32, the PMOS transistor 32a is turned off and the NMOS transistor 32b is turned on. As a result, an L level output signal OUT is output from the output terminal 34.

When the input voltage IN ₂ rises as shown in FIG. 2 as an example, the adjustment timing setting circuit 20, the PMOS transistor 20a begins switched from on to off while the switching state of the PMOS transistor 20b is held. That is, the current path between the source and drain of the PMOS transistor 20a starts to narrow. Therefore, the current flowing between the source and drain of each of the PMOS transistor 20a and the NMOS transistor 20c starts to decrease. On the other hand, since the switching state of the PMOS transistor 20b is still maintained, the PMOS transistor 20b and the NMOS transistor 20d correspond to the amount of decrease in the current flowing between the source and drain of each of the PMOS transistor 20a and the NMOS transistor 20c. The current flowing between each source and drain begins to increase.

  As the current flowing between the source and drain of each of the PMOS transistor 20a and the NMOS transistor 20c decreases, the NMOS transistor 18b included in the current adjustment circuit 18 is turned from on to off as shown by a broken line in FIG. 3 as an example. And start switching. That is, the current path between the source and drain of the NMOS transistor 18b starts to narrow. On the other hand, as the current flowing between the source and drain of each of the PMOS transistor 20b and the NMOS transistor 20d increases, the NMOS transistor 18a included in the current adjustment circuit 18 is, for example, as shown by the solid line in FIG. Start switching from off to on. That is, the current path between the source and drain of the NMOS transistor 18a begins to expand.

  Thus, as an example, as shown in FIG. 2, the comparison target voltage rises, and eventually the comparison target voltage reaches a magnitude corresponding to the release voltage, whereby a pair of magnitudes corresponding to the release voltage is obtained. A control voltage is generated by the adjustment timing setting circuit 20, one of the pair of control voltages is applied to one gate of the NMOS transistors 18a and 18b included in the current adjustment circuit 18, and the other of the pair of control voltages is the NMOS. Applied to the other gate of the transistors 18a and 18b. When the comparison target voltage rises, the magnitudes of the pair of control voltages increase or decrease correspondingly, so that the NMOS transistor 18b is switched from on to off and the NMOS transistor 18a is switched from off to on. Progresses. As the switching of the NMOS transistor 18b from on to off and the switching of the NMOS transistor 18a from off to on proceed, the current flowing into the current adjustment circuit 18 increases, and accordingly, the current generated by the constant current circuit 12 also increases. To do. Then, when the switching period from on to off of the NMOS transistor 18b and the switching period from off to on of the NMOS transistor 18a are crossed as shown in FIG. 3 as an example (hereinafter referred to as NMOS transistors 18a and 18b). The point at which one on-to-off switching period and the other off-to-on switching period intersect is referred to as an “intersection point”), and passes between the source and drain of the PMOS transistor 14a of the current mirror circuit 14. Thus, the current flowing into the current adjusting circuit 18 reaches the maximum. Along with this, the current generated by the constant current circuit 12 reaches the maximum.

That is, in the process in which the NMOS transistor 18b is switched from on to off and in the process in which the NMOS transistor 18a is switched from off to on, the size of the opening of the current path between the source and the drain of the NMOS transistor 18b and the source of the NMOS transistor 18a And the time has come when the openings of the current path between the drain and the drain are aligned. For example, as shown in FIG. 3, at the time of switching of the signal level of the output signal OUT of the comparator 10, at the time of crossing of the switching period from one on to off of the NMOS transistors 18a and 18b and the switching time from the other off to on. As shown in FIG. 2 as an example, the magnitude of the current supplied to the output switching circuit 16 is maximized. In other words, when the input voltage IN ₂ reaches a magnitude corresponding to the input voltage IN ₁ (when the current amount is most required to switch the signal level of the output signal OUT), the current switching circuit 16 outputs the output switching circuit 16. The driving current supplied to is maximized.

On the other hand, when the input voltage IN ₂ reaches the size corresponding to the input voltage IN ₁ eventually rises, will be PMOS transistors 16b, the magnitude voltage exceeding a threshold voltage to the gate of 20a is applied, whereby The PMOS transistors 16b and 20a are turned off. When the PMOS transistor 16b is turned off, the NMOS transistor 22b included in the output circuit 22 is turned off. When the PMOS transistor 16b is turned off, the current that has flown between the source and the drain of the PMOS transistor 16b so far flows between the source and the drain of the PMOS transistor 16a. A voltage exceeding the threshold voltage is applied to the gate of the transistor 22a, and the NMOS transistor 22a is turned on. As a result, in the CMOS inverter 30, the NMOS transistor 30b is turned on and the PMOS transistor 30a is turned off. In response, in the CMOS inverter 32, the PMOS transistor 32a is turned on and the NMOS transistor 32b is turned off. As a result, the signal level of the output signal OUT output from the output terminal 34 transitions to the H level (switches from the L level to the H level).

As described above, the driving current supplied to the output switching circuit 16 becomes the maximum, and when the intersection is passed, the current flowing into the current adjustment circuit 18 via the source and drain of the PMOS transistor 14a of the current mirror circuit 14 decreases. As a result, the current generated by the constant current circuit 12 also decreases. Increase in the input voltage IN ₂ proceeds, eventually, when the PMOS transistor 20a is turned off, the current flowing between the source and the drain of the PMOS transistor 20a will flow between the source and the drain of the PMOS transistor 20b before. As a result, a voltage exceeding the threshold voltage (one of a pair of control voltages having a magnitude corresponding to the closing voltage) is applied by the adjustment timing setting circuit 20 to the gate of the NMOS transistor 18a included in the current adjustment circuit 18. The NMOS transistor 18a is turned on, and the gate of the NMOS transistor 18b included in the current adjustment circuit 18 is supplied to the gate of the predetermined time by the adjustment timing setting circuit 20 (the other of the pair of control voltages having a magnitude corresponding to the closing voltage). ) Is applied to turn off the NMOS transistor 18b. Thus, when the switching from the on-off of the NMOS transistor 18b and the switching from the off-on of the NMOS transistor 18a is completed, no current flows into the current adjusting circuit 18, and accordingly, the constant current circuit 12 generates the current. Current also returns to a predetermined magnitude (size before rising).

The signal level of the output signal OUT as described above from the transition to the H level, then the input voltage IN ₂ begins to drop, the adjustment timing setting circuit 20, PMOS while switching state of the PMOS transistor 20b is held Transistor 20a begins to switch from off to on. That is, the current path between the source and drain of the PMOS transistor 20a begins to expand. Therefore, the current flowing between the source and drain of each of the PMOS transistor 20a and the NMOS transistor 20c starts to increase. On the other hand, since the switching state of the PMOS transistor 20b is still maintained, the PMOS transistor 20b and the NMOS transistor 20d correspond to the increasing amount of current flowing between the source and drain of each of the PMOS transistor 20a and the NMOS transistor 20c. The current flowing between each source and drain begins to decrease.

  As the current flowing between the source and drain of each of the PMOS transistor 20a and the NMOS transistor 20c increases, the NMOS transistor 18b included in the current adjustment circuit 18 starts to be switched from off to on. That is, the current path between the source and drain of the NMOS transistor 18b begins to expand. On the other hand, as the current flowing between the source and drain of each of the PMOS transistor 20b and the NMOS transistor 20d decreases, the NMOS transistor 18a included in the current adjustment circuit 18 starts to be switched from on to off. That is, the current path between the source and drain of the NMOS transistor 18a begins to narrow.

  As described above, when the switching of the NMOS transistor 18b from OFF to ON and the switching of the NMOS transistor 18a from ON to OFF proceed, the current flowing into the current adjustment circuit 18 increases, and the constant current circuit 12 generates the current accordingly. The current also increases. At the intersection, the current flowing into the current adjustment circuit 18 via the source and drain of the PMOS transistor 14a of the current mirror circuit 14 reaches a maximum. Along with this, the current generated by the constant current circuit 12 reaches the maximum.

That is, in the process in which the NMOS transistor 18b is switched from off to on and in the process in which the NMOS transistor 18a is switched from on to off, the size of the opening of the current path between the source and drain of the NMOS transistor 18b and the source of the NMOS transistor 18a are eventually reached. And the time has come when the openings of the current path between the drain and the drain are aligned. For example, when the switching of the signal level of the output signal OUT of the comparator 10 coincides with the crossing time of one of the NMOS transistors 18a and 18b from on to off and the other switching time from off to on. The magnitude of the drive current supplied to the switching circuit 16 is maximized. In other words, when the input voltage IN ₂ reaches a magnitude corresponding to the input voltage IN ₁ (when the current amount is most required to switch the signal level of the output signal OUT), the current switching circuit 16 outputs the output switching circuit 16. The driving current supplied to is maximized.

On the other hand, eventually PMOS transistor 16b when the input voltage IN ₂ drops is turned on. When the PMOS transistor 16b is turned on, the NMOS transistor 22b included in the output circuit 22 is turned on. When the PMOS transistor 16b is turned on, a part of the current that has flown between the source and drain of the PMOS transistor 16a so far flows between the source and drain of the PMOS transistor 16b. The voltage applied to the included NMOS transistor 22a is lowered and the NMOS transistor 22a is turned off. Thereby, in the CMOS inverter 30, the NMOS transistor 30b is turned off and the PMOS transistor 30a is turned on. In response, in the CMOS inverter 32, the PMOS transistor 32a is turned off and the NMOS transistor 32b is turned on. As a result, the signal level of the output signal OUT output from the output terminal 34 transitions to the L level (switches from the H level to the L level).

Drop of the input voltage IN ₂ proceeds, eventually, the PMOS transistor 20a is once turned on, the current flowing between the source and the drain of the PMOS transistor 20b will flow between the source and the drain of the PMOS transistor 20a far. As a result, a voltage exceeding the threshold voltage (one of a pair of control voltages having a magnitude corresponding to the closing voltage) is applied by the adjustment timing setting circuit 20 to the gate of the NMOS transistor 18b included in the current adjustment circuit 18. The NMOS transistor 18b is turned on, and the gate of the NMOS transistor 18a included in the current adjustment circuit 18 is supplied to the gate of the NMOS transistor 18a by the adjustment timing setting circuit 20 (the other of the pair of control voltages having a magnitude corresponding to the closing voltage). ) Is applied to turn off the NMOS transistor 18a. Thus, when the switching from the on-off of the NMOS transistor 18a and the switching from the off-on of the NMOS transistor 18b are completed, no current flows into the current adjusting circuit 18, and accordingly, the constant current circuit 12 generates the current. Current also returns to a predetermined magnitude (size before rising).

  FIG. 4 is a schematic diagram showing an example of a current flow according to the present embodiment. As shown in FIG. 4, the current Idd generated by the constant current circuit 12 is driven by the current flowing in the section between the constant current circuit 12 and the shunt path 19 (section surrounded by a broken line) via the current mirror circuit 14. The current is supplied to the output switching circuit 16 and the adjustment time setting circuit 20 as a current.

  As shown in FIG. 4, the route through which the current generated by the constant current circuit 12 flows is roughly divided into a main channel 17 and a branch channel 19. Since the conduction path of the current adjusting circuit 18 inserted into the branch channel 19 is normally closed, the current Idd flows only into the main channel 17 and eventually the magnitude of the comparison target voltage applied to the adjustment timing setting circuit 20. When the release voltage reaches the magnitude of the release voltage, the current adjustment circuit 18 releases the closing of the conduction path under the control of the adjustment timing setting circuit 20, and the current also flows into the branch path 19. As a result, current flows in both the main flow path 17 and the diversion flow path 19. In the main flow path 17, the magnitude of the current on the downstream side of the connection point with the diversion flow path 19 is not different from the normal time. When the current Idd is diverted to the diversion channel 19, the magnitude of the current upstream from the connection point with the diversion channel 19 becomes larger than normal (before diversion).

  Further, when the magnitude of the comparison target voltage applied to the adjustment time setting circuit 20 in the state where the closing of the conduction path is released reaches the magnitude of the closing voltage, the current adjustment circuit 18 under the control of the adjustment time setting circuit 20. As a result, the conduction path is closed and no current flows into the branch path 19. As a result, a current flows only in the main flow path 17, and the magnitude of the current upstream of the connection point with the branch flow path 19 in the main flow path 17 returns to the normal level (before the diversion flow).

  Thus, in the comparator 10 according to the present embodiment, the adjustment time setting circuit 20 sets the opening time of the conduction path of the current adjustment circuit 18 so as to match the output level switching time of the comparator 10, thereby making the constant. The current generated by the current circuit 12 is controlled.

  As described in detail above, according to the comparator 10 according to the present embodiment, the magnitude of the comparison target voltage becomes the release voltage in the state where the branch path 19 is closed by closing the conduction path in the current adjustment circuit 18. The current is generated by the constant current circuit 12 by closing the conduction path in the current adjustment circuit 18 by applying the voltage to be compared until reaching the magnitude corresponding to the closing voltage after reaching the corresponding magnitude. Since the current adjustment circuit 18 and the adjustment time setting circuit 20 which are examples of control means for controlling the current to increase are provided, the signal level of the output signal is compared with the case where the current adjustment circuit 18 and the adjustment time setting circuit 20 are not provided. Improvement of the switching speed and power saving can be realized together.

  Further, the comparator 10 according to the present embodiment includes the NMOS transistors 18a and 18b inserted in series in the shunt channel 19, and the switching state (for example, the NMOS transistor 18a is turned on) opposite to the NMOS transistors 18a and 18b. , The NMOS transistor 18b is turned off), and after the shunt channel 19 is closed, the comparison target voltage reaches the magnitude corresponding to the release voltage until it reaches the magnitude corresponding to the closing voltage. The NMOS transistor 18a, 18b is configured to increase the current generated by the constant current circuit 12 by switching each of the NMOS transistors 18a, 18b to another conflicting (counterpolar) switching state so that the periods of the switching operations overlap each other. Compared to the case without this configuration, it is easier and more accurate It is possible to increase the flow.

  Note that it is not necessary for the NMOS transistors 18a and 18b to overlap each other in their switching operation periods. For example, as shown in FIG. 5, other NMOS transistors 18a and 18b may be turned on. The same effect can be obtained even when the current generated by the constant current circuit 12 is increased by switching to the opposite switching state. In this case, for example, a period during which both the NMOS transistors 18a and 18b are turned on may be generated by delaying the start time of one of the NMOS transistors 18a and 18b from the start time of the other switching operation. Thereby, switching of a switching state can be performed easily and correctly. Further, the timing at which the voltage is applied to the gates of the NMOS transistors 18a and 18b may be shifted. The delay at the start of the other switching operation relative to the start of the other switching operation is, for example, changing the size of the NMOS transistors 18a and 18b, or the PMOS transistors 20a and 20b and the NMOS transistors included in the adjustment timing setting circuit 20 This can be realized by adjusting the sizes of 20c and 20d in advance. It can also be realized by inserting a load into the adjustment time setting circuit 20 as will be described later.

  Further, according to the comparator 10 according to the present embodiment, the current flowing through the branch channel 19 is the maximum when the magnitude of the comparison target voltage applied to the adjustment timing setting circuit 20 reaches the magnitude corresponding to the reference voltage. Thus, the NMOS transistors 18a and 18b are controlled so that the switching speed of the output signal level and the power saving can be efficiently realized as compared with the case where the NMOS transistors 18a and 18b are not provided.

  In addition, according to the comparator 10 according to the present embodiment, the adjustment timing setting circuit 20 increases or decreases so that the magnitude is contradictory in accordance with the difference between the magnitude of the reference voltage and the magnitude of the applied comparison target voltage. A pair of control voltages is generated (one increases and the other decreases), and one of the pair of control voltages having a magnitude corresponding to the closing voltage is applied to one of the NMOS transistors 18a and 18b and the NMOS transistor 18a. , 18b is applied with the other of a pair of control voltages having a magnitude corresponding to the closing voltage, thereby causing the NMOS transistors 18a, 18b to switch to an opposite switching state, and one of the NMOS transistors 18a, 18b corresponds to the release voltage. One of a pair of control voltages of a magnitude that applies is applied to the other of the NMOS transistors 18a and 18b. When the other of the pair of control voltages having a magnitude corresponding to the voltage is applied, the NMOS transistors 18a and 18b are turned on, the NMOS transistors 18a and 18b are turned on, and then closed to one of the NMOS transistors 18a and 18b. One of the pair of control voltages having a magnitude corresponding to the voltage is applied, and the other of the pair of control voltages having a magnitude corresponding to the closing voltage is applied to the other of the NMOS transistors 18a and 18b. Since it has the structure which makes 18a and 18b the other opposite switching state, compared with the case where it does not have this structure, the improvement of the switching speed of the signal level of an output signal and power saving can be implement | achieved efficiently.

  Further, according to the comparator 10 according to the present embodiment, one of a pair of control voltages is generated by a series circuit in which the PMOS transistor 20b and the NMOS transistor 20d are connected in series, and the PMOS transistor 20a and the NMOS transistor 20c are connected in series. Since the other of the pair of control voltages is generated by the series circuit connected to the first and second control voltages, the pair of control voltages can be supplied to the NMOS transistors 18a and 18b more easily and accurately than in the case without this configuration. can do.

  Further, according to the comparator 10 according to the present embodiment, the current generated by the constant current circuit 12 is supplied to the adjustment time setting circuit 20 via the current mirror circuit 14, and thus the adjustment time setting circuit 20 is driven. Therefore, it is not necessary to provide a separate power source.

  Further, according to the comparator 10 according to the present embodiment, the current mirror circuit 14 that supplies the current generated by the constant current circuit 12 to the output switching circuit 16 and the adjustment timing setting circuit 20 based on a predetermined current mirror ratio. Therefore, compared with the case where the current mirror circuit 14 is not provided, the current can be supplied to the output switching circuit 16 and the adjustment timing setting circuit 20 efficiently and accurately.

  Further, according to the comparator 10 according to the present embodiment, after the output level is switched (for example, after the signal level of the output signal OUT is switched from the L level to the H level, or the signal level of the output signal OUT is H level). Since the output circuit 22 is an example of a sustain circuit that maintains the current output level while the magnitude of the comparison target voltage does not reach the reference voltage level after the level is switched from the level to the L level, the output circuit The output level can be maintained while suppressing an increase in power consumption, as compared with the case where 22 is not provided.

  In the above-described embodiment, the case where the direct current is supplied to the inverting input terminal 24 has been described as an example. However, as an example, the polarity is switched when the alternating current is supplied to the inverting input terminal 24 as shown in FIG. Every time, the operation is the same as in the case of the direct current. The PMOS transistors 16a and 16b and the NMOS transistors 16c and 16d included in the output switching circuit 16 and the PMOS included in the adjustment timing setting circuit 20 so that the current ratio becomes “adjustment timing setting circuit 20> output switching circuit 16”. By adjusting the sizes of the transistors 20a and 20b and the NMOS transistors 20c and 20d in advance, it is possible to improve the response even in the case of alternating current.

In the above embodiment, the case where the input voltage IN ₁ is the reference voltage and the input voltage IN ₂ is the comparison target voltage has been described. However, the present invention is not limited to this, and the input voltage IN ₂ is the reference voltage. Needless to say, the same operation as described above is performed when ₁ is used as the comparison target voltage.

  In the above-described embodiment, the comparator 10 that sets the current adjustment time by the adjustment time setting circuit 20 is exemplified. However, for example, a hysteresis comparator 10A shown in FIG. 7 may be applied. The hysteresis comparator 10A shown in FIG. 7 differs from the comparator 10 shown in FIG. 1 in that an adjustment time setting circuit 20A is applied instead of the adjustment time setting circuit 20. The adjustment time setting circuit 20A is different from the adjustment time setting circuit 20 shown in FIG. 1 in that NMOS transistors 20e and 20f and resistance elements 20g and 20h as examples of loads are provided. In the resistance element 20g, one end is connected to the source of the NMOS transistor 20c, and the other end is connected to the low voltage line VSS. In the resistance element 20h, one end is connected to the source of the NMOS transistor 20d, and the other end is connected to the low voltage line VSS. In the NMOS transistor 20e, the drain is connected to the source of the NMOS transistor 20c, and the source is connected to the low voltage line VSS. The gate of the NMOS transistor 20 e is connected to the drain of the PMOS transistor 30 a included in the CMOS inverter 30. On the other hand, in the NMOS transistor 20f, the drain is connected to the source of the NMOS transistor 20d, and the source is connected to the low voltage line. The gate of the NMOS transistor 20 f is connected to the drain of the PMOS transistor 32 a included in the CMOS inverter 32. The back gate of the NMOS transistor 20e is connected to the back gate of the NMOS transistor 20c, and the back gate of the NMOS transistor 20f is connected to the back gate of the NMOS transistor 20d.

  According to the hysteresis comparator 10A configured as described above, when the signal level of the output signal OUT is L level, the NMOS transistor 20e is turned on and the NMOS transistor 20f is turned off. At this time, the resistance element 20g is disabled (short-circuited), and the resistance element 20h is enabled. Therefore, the adjustment timing setting circuit 20A generates a negative offset voltage with respect to the reference voltage. Subsequently, when the signal level of the output signal OUT is switched from the L level to the H level, the NMOS transistor 20e is turned off and the NMOS transistor 20f is turned on. When the output signal OUT having a signal level of H level is output from the output terminal 34, the resistance element 20g is enabled and the resistance element 20h is disabled (short-circuited). Thus, a positive offset voltage is generated. Therefore, as shown in FIG. 8 as an example, the period during which the drive current is supplied to the output switching circuit 16 can be made longer than that shown in FIG. It is possible to shorten the length as well as lengthen, and this can be realized by changing the resistance values of the resistance elements 20g and 20h, for example.

  Further, the hysteresis comparator 10A shown in FIG. 7 may be replaced with a hysteresis comparator 10B shown in FIG. 9 as an example. The hysteresis comparator 10B shown in FIG. 9 differs from the hysteresis comparator 10A shown in FIG. 7 in that an adjustment time setting circuit 20B is applied instead of the adjustment time setting circuit 20A. The adjustment time setting circuit 20B is different from the adjustment time setting circuit 20A in that NMOS transistors 20i, 20j, 20k, and 20m are provided except for the NMOS transistors 20e and 20f and the resistance elements 20g and 20h. In the NMOS transistor 20k, the gate and drain are connected to the drain of the NMOS transistor 20c, and the source is connected to the drain of the NMOS transistor 20i. In the NMOS transistor 20 i, the source is connected to the low voltage line VSS, and the gate is connected to the drain of the PMOS transistor 30 a included in the CMOS inverter 30. On the other hand, in the NMOS transistor 20m, the gate and drain are connected to the drain of the NMOS transistor 20d, and the source is connected to the drain of the NMOS transistor 20j. In the NMOS transistor 20j, the source is connected to the low voltage line VSS, and the gate is connected to the drain of the PMOS transistor 32a included in the CMOS inverter 32. The back gates of the NMOS transistors 20i and 20k are connected to the back gate of the NMOS transistor 20c, and the back gates of the NMOS transistors 20j and 20m are connected to the back gate of the NMOS transistor 20d. Even the comparator 10B configured as described above exhibits the same operations and effects as the comparator 10A illustrated in FIG.

  Further, instead of the adjustment time setting circuit 20 shown in FIG. 1, an adjustment time setting circuit 20C shown in FIG. 10 may be applied as an example. The adjustment time setting circuit 20C included in the comparator 10C shown in FIG. 10 is different from the adjustment time setting circuit 20 shown in FIG. 1 in that a resistance element 20n is provided. One end of the resistance element 20n is connected to the source of the NMOS transistor 20d, and the other end of the resistance element 20n is connected to the back gate of the NMOS transistor 20d and the low voltage line VSS. According to the comparator 10C configured in this way, as shown in FIG. 11 as an example, the rate of increase in the current supplied from the current mirror circuit 14 to the output switching circuit 16 is increased compared to the case shown in FIG. Can do. In the example shown in FIG. 11, the comparison target voltage is applied to the non-inverting input terminal 26.

  Further, in order to increase the increase rate of the drive current supplied to the output switching circuit 16 when the comparison target voltage is applied to the non-inverting input terminal 26, the circuit configuration is not limited to that shown in FIG. The comparator 10D shown in FIG. In the comparator 10 shown in FIG. 1, the size of the NMOS transistor 20c and the size of the NMOS transistor 20d are the same, but in the comparator 10D shown in FIG. 12, the adjustment time setting circuit 20D is applied instead of the adjustment time setting circuit 20. In the adjustment time setting circuit 20D, the size of the NMOS transistor 20c is made larger than the size of the NMOS transistor 20d. Thereby, as shown in FIG. 11 as an example, the increase rate of the drive current supplied to the output switching circuit 16 can be increased compared to the case shown in FIG.

  In order to increase the rate of increase in the current supplied from the current mirror circuit 14 to the output switching circuit 16 when a voltage to be compared is applied to the inverting input terminal 24, for example, as shown in FIG. What is necessary is just to insert in the NMOS transistor 20c side. That is, in this case, one end of the resistance element 20n is connected to the source of the NMOS transistor 20c, and the other end of the resistance element 20n is connected to the back gate of the NMOS transistor 20c and the low voltage line VSS. For example, as shown in FIG. 14, the size of the NMOS transistor 20d may be larger than the size of the NMOS transistor 20c.

  Further, when trimming the output signal OUT and trimming the current supplied from the current mirror circuit 14 to the output switching circuit 16, for example, a comparator 10E including an output switching circuit 16A shown in FIG. 15 may be applied. Compared to the comparator 10 shown in FIG. 1, the comparator 10 </ b> E shown in FIG. 15 applies the output switching circuit 16 </ b> A instead of the output switching circuit 16, and applies the adjustment time setting circuit 20 </ b> E instead of the adjustment time setting circuit 20. The point is different. The output switching circuit 16A is different from the output switching circuit 16 shown in FIG. 1 in that circuits 16e and 16f, which are examples of loads, are provided. The circuit 16e is inserted between the source of the NMOS transistor 16c and the low voltage line VSS, and the circuit 16f is inserted between the source of the NMOS transistor 16f and the low voltage line VSS. On the other hand, the adjustment time setting circuit 20E is different from the adjustment time setting circuit 20 shown in FIG. 1 in that circuits 20q and 20r as examples of loads are provided. The circuit 20q is inserted between the source of the NMOS transistor 20c and the low voltage line VSS, and the circuit 20r is inserted between the source of the NMOS transistor 20r and the low voltage line VSS.

  Each of the circuits 16e, 16f, 20q, and 20r includes, for example, a resistor circuit X configured by connecting resistors R0 to R4 in series and fuses FR0 to FR4 connected in series as shown in FIG. Any circuit configured by connecting the circuit Y in parallel may be used.

  According to the comparator 10E configured as described above, when the voltage to be compared is applied to the non-inverting input terminal 26, the output signal OUT can be offset in the plus direction by trimming the circuit 16f. The output signal OUT can be offset in the minus direction by trimming, and the current supply from the current mirror circuit 14 to the output switching circuit 16 can be offset in the plus direction by trimming the circuit 20r. By trimming, the current supply from the current mirror circuit 14 to the output switching circuit 16 can be offset in the minus direction. In order to obtain the same effect when the comparison target voltage is applied to the inverting input terminal, the trimming target may be reversed.

  In the above embodiment, the configuration example in which the output circuit 22 includes the NMOS transistor 22a and the PMOS transistor 28a has been described. However, this is only an example. For example, as illustrated in FIG. 17, the NMOS transistor 22a and the PMOS transistor are illustrated. The comparator 10F except 28a may be used. In the comparator 10F, by connecting the gate of the PMOS transistor 28b to the gate of the PMOS transistor 14c, a current mirror circuit 14A is configured instead of the current mirror circuit 14 shown in FIG. In this case as well, the same operations and effects as the comparator 10 described in the above embodiment are obtained.

  As an example, as shown in FIG. 18, the comparator 10G to which the output switching circuit 16B is applied instead of the output switching circuit 16 shown in FIG. 1 is basically the same as the comparator 10 described in the above embodiment. Actions and effects can be obtained. The output switching circuit 16B included in the comparator 10G shown in FIG. 18 differs from the output switching circuit 16 shown in FIG. 1 in the connection destinations of the gates of the NMOS transistors 16c and 16d. That is, in the example shown in FIG. 1, the NMOS transistor 16c and the NMOS transistor 16d are current-mirror connected, but in the output switching circuit 16B shown in FIG. 18, the NMOS transistor 16c and the NMOS transistor 16d are diode-connected. In the example shown in FIG. 18, the gate of the NMOS transistor 16c is connected to the drain of the NMOS transistor 16c, and the gate of the NMOS transistor 16d is connected to the drain of the NMOS transistor 16d.

  As an example, as shown in FIG. 19, the comparator 10H to which the adjustment time setting circuit 20F is applied instead of the adjustment time setting circuit 20 shown in FIG. 1 is basically the same as the comparator 10 described in the above embodiment. Similar actions and effects can be obtained. The adjustment timing setting circuit 20F included in the comparator 10H illustrated in FIG. 19 is different from the adjustment timing setting circuit 20 illustrated in FIG. 1 in the connection destinations of the gates of the NMOS transistors 20c and 20d. That is, in the example shown in FIG. 1, the NMOS transistor 20c and the NMOS transistor 20d are each diode-connected, but in the adjustment timing setting circuit 20F shown in FIG. 19, the NMOS transistor 20c and the NMOS transistor 20d are current-mirror connected. In the example shown in FIG. 19, the gate of the NMOS transistor 20c is connected to the gate of the NMOS transistor 20d, and the gate of the NMOS transistor 20d is connected to the drain of the NMOS transistor 20d.

  Note that another active load may be applied without applying the output switching circuit 16B shown in FIG. 18 or the adjustment timing setting circuit 20F shown in FIG. Examples of other active loads mentioned here include active loads such as a cascode current mirror and a low voltage cascode current mirror.

  Further, in the above-described embodiment, the description has been given by taking the form example in the case where the constant current circuit 12 is used. The comparator 10J shown in FIG. 20 differs from the comparator 10 shown in FIG. 1 in that a constant current source 11 is applied instead of the constant current circuit 12. Specifically, the positive terminal of the constant current source 11 is connected to one end of the branch channel 19, and the negative terminal of the constant current source 11 is connected to the low voltage line VSS. The comparator 10J configured in this way also exhibits basically the same operations and effects as the comparator 10 described in the above embodiment.

  In the above embodiment, the configuration example in which the current adjustment circuit 18 includes the NMOS transistors 18a and 18b has been described. However, a pair of PMOS transistors may be applied instead of the NMOS transistors 18a and 18b. One may be an NMOS transistor and the other may be a PMOS transistor.

  In the above-described embodiment, an example in which a field effect transistor is used has been described, but it goes without saying that another type of transistor such as a bipolar transistor may be used.

  In the above embodiment, the P-channel type input differential circuit is exemplified. However, the N-channel type input differential circuit and the P-channel type and N-channel type input differential circuits (Rail-to-Rail differential) are exemplified. Other differential circuits (for example, a folded cascode or a telescopic differential circuit).

10, 10C, 10D, 10E, 10F, 10G, 10H, 10J Comparator 10A, 10B Hysteresis comparator 11 Constant current source 12 Constant current circuit 14, 14A Current mirror circuit 16, 16A, 16B Output switching circuit 16e, 16f, 20q, 20r Circuit 18 Current adjustment circuit 18a, 18b NMOS transistor 19 Branch channel 20, 20A, 20B, 20C, 20D, 20E, 20F Adjustment time setting circuit 22 Output circuit

Claims (15)

Current generating means for generating a current of a predetermined magnitude;
A shunt path for shunting the current generated by the current generating means;
Driving by being supplied with the current generated by the current generating means, and output switching means for switching the output level when the magnitude of the applied comparison target voltage reaches the magnitude of the reference voltage;
A conducting path that is inserted into the shunt path and is capable of conducting the shunt path, and the comparison target voltage having a magnitude corresponding to a closing voltage that closes the conducting path is applied. A current flowing through the branch flow path by closing the conduction path by applying the comparison target voltage having a magnitude corresponding to a release voltage of a magnitude for closing the passage and releasing the closure of the conduction path. Control means for controlling the voltage, the closed voltage is equivalent to the closing voltage after the magnitude of the comparison target voltage reaches a magnitude corresponding to the release voltage in a state where the shunt flow path is closed by closing the conduction path The control means for controlling the current generated by the current generating means to increase by releasing the closing of the conduction path by applying the voltage to be compared until the magnitude of the current is reached. And,
Including comparator.   The control means has a pair of switching elements that form the conduction path by being inserted in series in the branch path, and the branch path is closed by putting the pair of switching elements in opposite switching states. Each of the pair of switching elements is switched between each other during a period from when the comparison target voltage reaches a magnitude corresponding to the release voltage until it reaches a magnitude corresponding to the closing voltage. The comparator according to claim 1, wherein the current generated by the current generating means is controlled to increase by switching to another conflicting switching state so that the periods overlap.   The control means has a pair of switching elements that form the conduction path by being inserted in series in the branch path, and the branch path is closed by putting the pair of switching elements in opposite switching states. In this state, there is a period in which both the pair of switching elements are turned on from when the magnitude of the comparison target voltage reaches the magnitude corresponding to the release voltage until it reaches the magnitude corresponding to the closing voltage. The comparator according to claim 1, wherein the current generated by the current generating means is controlled to increase by switching to another conflicting switching state.   4. The comparator according to claim 3, wherein a period for conducting both the pair of switching elements is generated by delaying a start time of one switching operation of the pair of switching elements from a start time of the other switching operation.   The control means further switches the pair of switching elements so that the current flowing through the shunt flow path becomes maximum when the magnitude of the applied comparison target voltage reaches a magnitude corresponding to the reference voltage. The comparator according to any one of claims 2 to 4, which is controlled. The control means further generates a pair of control voltages each of which increases or decreases so as to conflict with the difference between the reference voltage and the applied comparison target voltage. Have a circuit,
One of the pair of control voltages having a magnitude corresponding to the closing voltage is applied to one of the pair of switching elements by the differential circuit and the closing of the pair of switching elements to the other by the differential circuit. The other of the pair of control voltages having a magnitude corresponding to a voltage is applied to bring the pair of switching elements into the opposite switching state,
One of the pair of control voltages having a magnitude corresponding to the release voltage is applied to one of the pair of switching elements by the differential circuit, and the release to the other of the pair of switching elements by the differential circuit. Each of the pair of switching elements is made conductive by applying the other of the pair of control voltages having a magnitude corresponding to a voltage,
One of the pair of control voltages having a magnitude corresponding to the closing voltage is applied to one of the pair of switching elements by the differential circuit, after each of the pair of switching elements is turned on. The other switching element is applied with the other of the pair of control voltages having a magnitude corresponding to the closing voltage by the differential circuit, so that the pair of switching elements is switched to the other opposite switching state. The comparator according to any one of claims 2 to 5.   The differential circuit is two sets of series circuits in which switching elements of different conductivity types are connected in series, one of which generates one of the pair of control voltages, and the other is the pair of control voltages. The comparator of claim 6 having two sets of series circuits that produce the other of the two.   The comparator according to claim 6, wherein the differential circuit is driven by being supplied with a current generated by the current generation unit.   The comparator according to any one of claims 6 to 8, wherein the differential circuit is a hysteresis comparator.   The comparator according to any one of claims 6 to 9, wherein an offset load is inserted into the differential circuit. The power generation means is a constant current source,
The comparator according to any one of claims 2 to 10, wherein the constant current source and the pair of switching elements are connected in parallel.   The comparator according to claim 1, wherein an offset load is inserted into the output switching unit.   13. The current mirror circuit according to claim 1, further comprising a current mirror circuit that supplies the current generated by the power generation unit to the output switching unit and the control unit based on a predetermined current mirror ratio. Comparator.   14. The maintenance circuit according to claim 1, further comprising a maintaining circuit that maintains the current output level while the magnitude of the comparison target voltage does not reach the reference voltage after the output level is switched. The comparator according to item 1.   The semiconductor device which made the comparator of any one of Claims 1-14 into 1 chip.