JP2013218565A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a storage device.SOLUTION: A storage device includes plural nonvolatile memories and a memory control unit for controlling the plural nonvolatile memories. The memory control unit is connected to the plural nonvolatile memories through a common address/data bus, and the memory control unit is connected individually to the plural nonvolatile memories through selection signal lines for selecting a predetermined nonvolatile memory from the plural nonvolatile memories. When first write data received from a host is written, the memory control unit uses the selection signal lines to select a nonvolatile memory from the plural nonvolatile memories as a write destination, generates second write data by adding to the first write data redundant data including identification information for identifying the selected nonvolatile memory to which the data is to be written, and writes the second write data to the write destination nonvolatile memory through the common address/data bus.

Description

  The present invention relates to a storage device technology.

  There are storage devices with flash memory. However, due to the structure of the flash memory, there is a possibility that the read data includes an error. Therefore, there is a technique for detecting and correcting an error in data content read from the flash memory device. For example, there is a technique in which an error correction code (ECC (Error Correcting Code)) is added to data to be written in a flash memory and the error is corrected using the error correction code when data is read from the flash memory. . In addition, for example, there is a technique of creating a mirroring configuration using two flash memories and comparing the two data when reading data from each flash memory device, and determining that the data is normal if they match. (Patent Document 1).

JP 2007-257547 A

  In the case of a storage device including a plurality of non-volatile memories such as a flash memory, in addition to the possibility that an error is included in the read data content as described above, the following failure may occur. That is, in a storage device including a plurality of nonvolatile memories, when data is written to a selected nonvolatile memory, the data may be erroneously written to another nonvolatile memory due to a failure. If such a failure occurs, when data is read from another nonvolatile memory of the storage device, the erroneously written data may be read as correct data.

  An object of the present invention is to provide a storage device that improves the reliability of data read from a nonvolatile memory. Another object of the present invention is to provide a storage device that detects whether or not data read from a nonvolatile memory is erroneously written data.

  The storage device includes a plurality of nonvolatile memories and a memory control unit that controls the plurality of nonvolatile memories. The memory control unit and the plurality of nonvolatile memories are connected by a common address / data bus. The memory control unit and each of the plurality of nonvolatile memories are individually connected by a selection signal line for selecting any one of the plurality of nonvolatile memories. When writing the first write data received from the host, the memory control unit selects a write destination nonvolatile memory from the plurality of nonvolatile memories using the selection signal line, and selects the selected write destination nonvolatile memory. Redundant data including identification information for identifying the first write data is added to the first write data to generate second write data, and the second write data is written to the write destination nonvolatile memory via the common address / data bus .

3 is a block diagram illustrating an example of a hardware configuration of a storage device 11. FIG. 6 is a schematic diagram for explaining a problem that may occur when data is read from the FM chip 25. FIG. 3 is an example of a configuration diagram of data stored in an FM chip 25. FIG. 4 is a flowchart showing a process of writing data to the FM chip 25. 4 is a flowchart showing a process of reading data from the FM chip 25.

  In the present embodiment, when data is read from one nonvolatile semiconductor memory among a plurality of nonvolatile semiconductor memories, it can be determined whether or not the data is read from the correct nonvolatile semiconductor memory. It is characterized by doing. Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating an example of a hardware configuration of the storage device 11. The storage device 11 includes an MPU (Micro Processing Unit) 20 that executes a computer program (hereinafter referred to as “program”) and a host I / F (Interface) control unit 22 that controls communication with the host 10. The storage device 11 includes a program storage memory 23 that stores a program and a main memory 24 that holds data when the program is executed. The storage device 11 includes a plurality of FM (Flash Memory) chips 25 that store data as storage media, and a memory I / F control unit 21 that controls communication with the plurality of FM chips 25.

  The host I / F control unit 22, the MPU 20, the program storage memory 23, the memory I / F control unit 21, and the main memory 24 are connected by a control bus 32 capable of bidirectional data transmission. . The control bus 32 may be either a serial bus or a parallel bus.

  The memory I / F control unit 21 and the plurality of FM chips 25a, 25b, and 25c are connected by an FM chip bus 30 that is a common address / data bus capable of bidirectional data transmission. The FM chip bus 30 may be either a serial bus or a parallel bus. In the case of a parallel bus, the address and data may be transmitted on different buses, or the address and data may be transmitted on a common bus. The FM chips 25a, 25b, and 25c may be collectively referred to as an FM chip 25.

  The memory I / F control unit 21 and each of the FM chips 25a, 25b, and 25c are connected by independent CE signal lines (signal lines for selecting the FM chip 25) 29a, 29b, and 29c. The CE signal lines 29a, 29b, and 29c may be collectively referred to as a CE signal line 29. When the CE signal line 29 is in a valid (active) state, it is called “assert”, and when it is in an invalid (inactive) state, it is called a “negate”. The CE signal line 29 may be set to assert a high voltage level state and negate a low voltage level state. Conversely, a low voltage level state is asserted and a high voltage level state is set to negate. May be.

  The host I / F control unit 22 is connected to the host 10 outside the storage device 11 through a host bus 12 capable of bidirectional data transmission. The host bus 12 may be either a serial bus or a parallel bus.

  A program to be executed by the MPU 20 is stored in the program storage memory 23. The program storage memory 23 is configured by a nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable And Programmable Read-only Memory) or an FM chip, for example.

  The main memory 24 is used as a work memory when a program is executed in the MPU 20. The main memory 24 is configured by a volatile semiconductor memory such as a DRAM (Dynamic Random Access Memory), for example.

  The MPU 20 controls the entire storage device 11. The MPU 20 reads the program from the program storage memory 23 and executes it.

  The host I / F control unit 22 controls data transmitted between the host 10 and the storage device 11 via the host bus 12. For example, the host I / F control unit 22 performs the following processing. When receiving data from the host 10 via the host bus 12, the host I / F control unit 22 notifies the MPU 20 to that effect. The MPU 20 confirms a predetermined register of the host I / F control unit 22, interprets the request from the host 10, and issues an instruction to the host I / F control unit 22 based on the interpretation.

  For example, when receiving a data read instruction from the MPU 20, the host I / F control unit 22 issues a data read instruction to the memory I / F control unit 21. The memory I / F control unit 21 receives the read instruction and reads data from the FM chip 25. The host I / F control unit 22 transmits the data read by the memory I / F control unit 21 to the host 10 via the host bus 12.

  For example, when receiving a data write instruction from the MPU 20, the host I / F control unit 22 issues a data write instruction to the memory I / F control unit 21. In response to the write instruction, the memory I / F control unit 21 writes data to the FM chip 25. The memory I / F control unit 21 returns write success / failure to the host I / F control unit 22. The host I / F control unit 22 transmits the success / failure response to the host 10 via the host bus 12.

  The FM chip 25 is composed of a nonvolatile semiconductor memory, and can retain data even when power is not supplied. The FM chip 25 writes, reads, and erases data only when the FM chip 25 is selected by the memory I / F control unit 21. Hereinafter, writing, reading and erasing may be collectively referred to as “writing or the like”. That is, the FM chip 25 writes data and the like only when the CE signal line 29 connected to the FM chip 25 is asserted. Processing such as writing to the FM chip 25 will be described later. This embodiment assumes a NAND type FM chip 25. However, the FM chip 25 may have another configuration (for example, a NOR type).

  The memory I / F control unit 21 controls transmission / reception of data between the host I / F control unit 22, the program storage memory 23 and the main memory 24, and the plurality of FM chips 25 in accordance with an instruction from the MPU 20. The memory I / F control unit 21 and the plurality of FM chips 25 are connected by a common FM chip bus 30. That is, the data transmitted from the memory I / F control unit 21 reaches all the FM chips 25 connected to the common FM chip bus 30. Therefore, the memory I / F control unit 21 selects an FM chip 25 that is a target for data writing or the like. That is, the memory I / F control unit 21 asserts the CE signal line 29 connected to the target FM chip 25 for data writing or the like. Thereby, only the asserted FM chip 25 performs writing or the like. Next, processing such as writing will be further described.

  A case where the memory I / F control unit 21 reads the storage data 70 stored in a certain FM chip 25 will be described. The stored data 70 includes a logical block 71 and redundant data 72, as will be described later with reference to FIG. The memory I / F control unit 21 asserts the CE signal line 29 connected to the FM chip 25 that holds the stored data 70.

  Then, the memory I / F control unit 21 transmits data requesting reading (hereinafter referred to as “reading request”) via the FM chip bus 30. The transmitted read request reaches all the FM chips 25 connected to the FM chip bus 30. The asserted FM chip 25 executes this read request. The FM chip 25 that is not asserted does not execute this read request. That is, the asserted FM chip 25 reads the storage data 70 indicated by the read request from its own FM chip 25 and transmits it to the memory I / F control unit 21 via the FM chip bus 30.

  Thereby, the memory I / F control unit 21 can read desired storage data 70 from the FM chip 25. The memory I / F control unit 21 performs ECC processing, CRC processing, and the like on the redundant data 72 included in the stored data 70, and extracts the logical block 71. The memory I / F control unit 21 restores the read logical block 71 and stores it in the main memory 24. When receiving an instruction from the MPU 20 to transfer the restored data to the host I / F control unit 22, the memory I / F control unit 21 transfers the restored data stored in the main memory 24 to the host I / F control unit 22. To do.

  When the memory I / F control unit 21 erases the stored data 70 of a certain FM chip 25, instead of sending the above-described read request, the FM chip asserted by sending the data requesting the erase. Data in 25 predetermined areas is erased.

  A case where the memory I / F control unit 21 writes data to a certain FM chip 25 will be described. Here, a process after data for writing is stored in the main memory 24 will be described. The memory I / F control unit 21 reads write data from the main memory 24. The memory I / F control unit 21 executes CRC processing, ECC processing, and the like, and generates storage data 70 in which redundant data 72 is added to the logical block 71. The memory I / F control unit 21 asserts the CE signal line 29 of the FM chip 25 to which the stored data 70 is to be written.

  Then, the memory I / F control unit 21 transmits data to be written (hereinafter referred to as “write request”) and storage data 70 via the FM chip bus 30. This write request and stored data 70 reach all the FM chips 25 connected to the FM chip bus 30. The asserted FM chip 25 executes this write request. The FM chip 25 that is not asserted does not execute this write request. That is, only the asserted FM chip 25 writes the storage data 70 transmitted together with the write request to its own FM chip 25.

  The memory I / F control unit 21 includes a CRC (Cyclic Redundancy Check) circuit 213. The CRC circuit 213 performs CRC75 generation processing and error detection processing using the CRC75. The CRC 75 may be referred to as error detection information. When writing data to the FM chip 25, the memory I / F control unit 21 generates a CRC using the CRC circuit 213 and includes the CRC in the redundant data 72. When reading data from the FM chip 25, the memory I / F control unit 21 extracts a CRC from the redundant data 72 and detects a data error using the CRC circuit 213.

  The memory I / F control unit 21 includes an ECC circuit 212. The ECC circuit 212 performs ECC 76 generation processing and error correction processing using the ECC 76. The ECC 76 may be referred to as error correction information. When writing data to the FM chip 25, the memory I / F control unit 21 generates an ECC 76 using the ECC circuit 212 and includes it in the redundant data 72. When reading data from the FM chip 25, the memory I / F control unit 21 extracts ECC from the redundant data 72 and corrects a data error using the ECC circuit 212.

  In the configuration as shown in FIG. 1, a certain problem may occur. The problem will be described below.

  FIG. 2 is a schematic diagram for explaining a problem that may occur when data is read from the FM chip 25. FIG. 2 shows a state where the CE signal line 29c is short-circuited due to a failure. That is, the FM chip 25c shown in FIG. 2 is always in a selected state (asserted state).

  FIG. 2A shows an operation when erasing data in a predetermined area of the FM chip 25a when the CE signal line 29c is short-circuited. After asserting the CE signal line 29 a, the memory I / F control unit 21 transmits an erase request for a predetermined area to the FM chip bus 30. However, since the CE signal line 29c is asserted due to a failure, the erase request for the predetermined area is executed not only by the FM chip 25a but also by the FM chip 25c. That is, in the FM chip 25c, data in a predetermined area that should not be erased is erased.

  FIG. 2B shows the operation when new data is written in the predetermined erased area of the FM chip 25a after FIG. 2A. After asserting the CE signal line 29a, the memory I / F control unit 21 transmits a write request to a predetermined area to the FM chip bus 30. However, since the CE signal line 29c is asserted due to a failure, a write request to the predetermined area is executed not only in the FM chip 25a but also in the FM chip 25c. In other words, erroneous data that should not be written is written to the FM chip 25c in a predetermined area.

  FIG. 2C shows an operation when data is read from a predetermined area where erroneous data is written in the FM chip 25c in FIG. 2B. After asserting the CE signal line 29c, the memory I / F control unit 21 transmits a read request from a predetermined area to the bus for the FM chip 25c. In this case, the memory I / F control unit 21 reads erroneous data from a predetermined area of the FM chip 25c. This is because the correct data that should originally exist in the predetermined area of the FM chip 25c has been erased by mistake in FIG. 2A, and the incorrect data in FIG. 2B has been written in the predetermined area. It is because it is closed.

  The erroneous data read in FIG. 2C cannot be detected by either the ECC circuit 212 or the CRC circuit 213. This is because there is no error in the read data value. Therefore, the storage device 11 in which the failure of the CE signal line 29 as described above has occurred may return erroneous data completely different from the original correct data to the host 10. Therefore, an embodiment according to the present invention that solves this problem will be described below.

  FIG. 3 is a data configuration diagram illustrating an example of a data configuration stored in the FM chip 25. The storage data 70 as “second write data” written to the FM chip 25 is composed of logical block data (hereinafter referred to as “logical block”) 71 and redundant data 72.

  The write data as “first write data” requested to be written by the host 10 includes one or more logical blocks 71 having a predetermined size (for example, 512 bytes). In FIG. 3, only one logical block is shown. The data unit constituting the write data and the unit for writing to the FM chip 25 are different. For example, the FM chip 25 has a plurality of blocks (different from the logical blocks), each block has a plurality of pages, and data can be read and written in units of these pages. Data is erased in units of a block consisting of a plurality of pages.

  The redundant data 72 is data of a predetermined size given to each logical block 71. The redundant data 72 includes a CE short check code 73 for checking a short circuit of the CE signal line 29, a relative LBA (Logical Block Address) 74 for managing the logical block 71, a CRC 75, and an ECC 76. .

  The CE short circuit check code 73 is a code for checking the short circuit of the CE signal line 29 as described in FIG. The CE short check code 73 holds identification information for identifying each FM chip 25. That is, when writing data, the memory I / F control unit 21 causes the CE short check code 73 to hold identification information corresponding to the FM chip 25 that is the write destination. When the memory I / F control unit 21 reads data, the memory I / F control unit 21 stores the identification information corresponding to the FM chip 25 selected (asserted) as the read destination and the identification held in the CE short check code 73 of the read data. By comparing with the information, it is determined whether or not the read data is written in the correct FM chip 25. If the identification information matches, the memory I / F control unit 21 determines that the read data is data read from the correct FM chip 25. If the identification information does not match, the read data is incorrect ( That is, it is determined that the data is read from the FM chip 25 (asserted due to a failure).

  The CE short-circuit check code 73 is composed of a bit flag string 77 corresponding to each FM chip 25, for example. That is, the FM chips 25a, 25b, and 25c are associated with the bit flags 78a, 78b, and 78c of the bit flag string 77, respectively. For example, when writing data to the FM chip 25a, the memory I / F control unit 21 sets “1” only to the bit flag 78a corresponding to the FM chip 25a selected (asserted) as the write destination, and sets other bits. Data is written by setting "0" in the flags 78b and 78c. When reading data from the FM chip 25a, the memory I / F control unit 21 determines whether or not “1” is set only in the bit flag 78a corresponding to the FM chip 25a selected as the read destination. If this determination is affirmative, the memory I / F control unit 21 determines that the read data is data read from the correct FM chip 25. If this determination is negative, the read data is incorrect. It is determined that the data is read from the FM chip 25. The CE short check code 73 may have any data configuration as long as each FM chip 25 can be distinguished. For example, a number assigned to the FM chip 25 may be stored in the CE short check code 73.

  The relative LBA 74 is information for managing the logical block 71. That is, the relative LBA 74 is used when restoring data to be provided from the logical block 71 to the host 10.

  CRC75 is a code used to detect data errors. The CRC circuit 213 generates a CRC 75 for the logic block 71, the CE short check code 73, and the relative LBA 74. That is, the CRC circuit 213 can detect data errors in the logic block 71, the CE short check code 73, and the relative LBA 74.

  The ECC 76 is a code used to correct data errors. The ECC circuit 212 generates an ECC 76 for the logic block 71, the CE short check code 73, the relative LBA 74, and the CRC 75. That is, the ECC circuit 212 can correct a predetermined bit error of data in the logic block 71, the CE short check code 73, the relative LBA 74, and the CRC 75.

  FIG. 4 is a flowchart showing a process for writing data to the FM chip 25.

  The memory I / F control unit 21 creates a relative LBA 74 (S101). The memory I / F control unit 21 creates a CE short check code 73. That is, “1” is set to the bit flag 78 corresponding to the FM chip 25 selected as the write destination (S102).

  The memory I / F control unit 21 creates the CRC 75 using the CRC circuit 213 (S103). The memory I / F control unit 21 creates an ECC 76 using the ECC circuit 212 (S104).

  The memory I / F control unit 21 generates storage data 70 in which the redundant data 72 is added to the logical block 71 (S105).

  The memory I / F control unit 21 asserts the CE signal line 29 of the FM chip 25 that is the write destination (S106). The memory I / F control unit 21 outputs the write request and the stored data 70 to the FM chip bus 30 (S107).

  Through the above processing, the storage data 70 is written to the FM chip 25 selected by asserting the CE signal line 29.

  FIG. 5 is a flowchart showing a data check process when reading data from the FM chip 25.

  The memory I / F control unit 21 asserts the CE signal line 29 of the FM chip 25 to be read (S201). The memory I / F control unit 21 outputs a read request to the FM chip bus 30 (S202). Then, the memory I / F control unit 21 receives the storage data 70 via the FM chip bus 30 (S203).

  The memory I / F control unit 21 uses the ECC circuit 212 to execute the processing of the ECC 76 (S204), and determines whether or not there is an error in the data content (S205). If it is determined in step S205 that there is an error in the data contents (S205: YES), the memory I / F control unit 21 uses the ECC circuit 212 to execute error correction processing (S206), and then step The process proceeds to S207. If it is determined in step S205 that there is no error in the data contents (S205: NO), the memory I / F control unit 21 proceeds to the process of step S207 as it is.

  In step S207, the memory I / F control unit 21 uses the CRC circuit 213 to execute CRC75 processing (S207), and determines whether there is an error in the data content (S208). If it is determined in step S208 that there is an error in the data content (S208: YES), the memory I / F control unit 21 determines that the CRC 75 is abnormal (the data content has an error) (S209). ), The process ends.

  If it is determined in step S208 that there is no error in the data contents (S208: NO), the memory I / F control unit 21 next determines whether or not the CE short check code 73 is correct (S210). That is, the memory I / F control unit 21 determines whether or not the identification information of the selected FM chip 25 matches the identification information included in the CE short check code 73. In this step S210, when it is determined that the CE short check code 73 is correct (S210: YES), the memory I / F control unit 21 determines that the read data is normal (S211), and ends the processing. . If it is determined in step S210 that the CE short-circuit check code 73 is not correct (S210: NO), the memory I / F control unit 21 determines that the CE signal line 29 is short-circuited (S212), and ends the process. .

  In response to the read request from the host 10, the storage device 11 returns only the data determined to be normal in step S211. That is, the storage device 11 returns to the host 10 only data that has been determined that there is no error in the data contents and that there is no error in the data read destination.

According to the present embodiment, for example, the following effects can be obtained.
(1) It is possible to prevent a problem that erroneous data is read from the erroneous FM chip 25 and returned to the host 10 that may occur when a certain CE signal line 29 is short-circuited due to a failure. That is, the reliability of the storage device 11 can be improved.

  The above-described embodiments of the present invention are examples for explaining the present invention, and are not intended to limit the scope of the present invention only to those embodiments. Those skilled in the art can implement the present invention in various other modes without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 11 ... Memory | storage device 21 ... Memory I / F control part 25 ... Bus for flash memory CE signal line 29 73 ... CE short-circuit check code

Claims (5)

A storage device comprising: a plurality of nonvolatile memories; and a memory control unit that controls the plurality of nonvolatile memories,
The memory control unit and the plurality of nonvolatile memories are connected by a common address / data bus,
The memory control unit and each of the plurality of nonvolatile memories are individually connected by a selection signal line for selecting any one of the plurality of nonvolatile memories, respectively.
When writing the first write data received from the host to the non-volatile memory, the memory control unit selects and selects the non-volatile memory to be written from among the plurality of non-volatile memories using the selection signal line. Redundant data including identification information for identifying the write destination nonvolatile memory is added to the first write data to generate second write data, and the second write data is used as the common address / data bus. A storage device that writes to the non-volatile memory at the write destination via the storage device.
When reading the second write data from the non-volatile memory, the memory control unit selects a read-out non-volatile memory using the selection signal line, and A) reads the read destination through the common address / data bus. It is determined whether or not the identification information included in the redundant data of the second write data acquired from the non-volatile memory selected as the same as the identification information of the non-volatile memory selected as the read destination. 2. The storage device according to claim 1, wherein the second write data is determined to be normal if they match, and the second write data is determined to be abnormal if the determination does not match.
The redundant data further includes error detection information for detecting an error in the data including the first write data and the identification information,
The memory control unit determines whether or not there is an error in the data including the first write data and the identification information using the error detection information, and if it is determined that there is no error in the determination The storage device according to claim 2, wherein A) is executed.
The redundant data further includes error correction information for correcting an error of data including the first write data, the identification information, and the error detection information,
The storage device according to claim 3, wherein the memory control unit executes the step B) after correcting an error in data including the first write data, the identification information, and the error detection information using the error correction information. apparatus.
The identification information is a string of bit flags corresponding to each of the plurality of nonvolatile memories,
The memory control unit generates identification information in which only the bit flag corresponding to the nonvolatile memory selected as the write destination is enabled when writing the first write data to the nonvolatile memory,
When the memory control unit reads the second write data from the non-volatile memory, in the above A), the valid bit flag of the identification information acquired through the common address / data bus selects the non-volatile The storage device according to claim 2, wherein it is determined whether or not the bit flag corresponds to a memory.

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