JP2013207821A - Power conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power conversion circuit capable of preventing variation of a threshold voltage of a transistor while preventing reduction of the current flowing to a reflux diode.SOLUTION: A power conversion circuit 1 includes: transistors 11U and 12U and a control section 20 that controls the transistors. When setting the transistors to be conductive, the control section 20 applies a positive first voltage across the gate and source of the transistors. When setting the transistors to be non-conductive, if the potential of the drain with respect to the source as the reference is negative in the previous conductive state of the transistor, the control section 20 applies a second voltage which is a positive voltage smaller than the first voltage or zero across the gate and the source. If the potential of the drain with respect to the source as the reference is positive in the previous conductive state of the transistor, the control section 20 applies a third negative voltage across the gate and the source.

Description

  The present invention relates to a power conversion circuit such as an inverter or a converter.

Generally, power conversion circuits such as inverters and converters are configured using switching elements and are used in many fields. The power conversion circuit is provided between the power source and the load, and functions to convert the power supplied from the power source to the load into a specific format.
As a power conversion circuit, a circuit used particularly in the power electronics field that handles a high voltage requires a high breakdown voltage for the switching element. In order to make the switching element have a high withstand voltage, for example, the switching element may be configured using a semiconductor material having a large band gap. As this semiconductor material, SiC (silicon carbide), which is a semiconductor material having a larger band gap than Si (silicon), has attracted attention. In recent years, as a switching element using SiC, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a kind of MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor: Metal-Insulator-Semiconductor Field Effect Transistor). Metal-oxide-semiconductor field effect transistors) are used (see Patent Document 1). Patent Document 1 discloses that a diode built in a transistor is used as a free-wheeling diode.

  When a voltage equal to or higher than a threshold voltage (hereinafter referred to as Vt) is applied to the gate electrode of the transistor, the source electrode and the drain electrode become conductive, and when a voltage lower than Vt is applied, the transistor becomes nonconductive.

US Pat. No. 7,598,567

Materials Science Forum Vols. 600-603 (2009) PP 807-810

However, the threshold voltage Vt of the transistor may fluctuate in the positive direction when a positive voltage is applied to the gate electrode (see Non-Patent Document 1).
In a power conversion circuit provided with a transistor, when Vt varies, the timing of the conduction state and non-conduction state of the transistor varies, so that a desired operation as a power conversion circuit cannot be expected. For this reason, there is a demand for suppressing fluctuations in Vt.

  Therefore, an object of the power conversion circuit disclosed in this specification is to suppress a change in threshold voltage of a transistor while suppressing a decrease in current flowing through a freewheeling diode.

  In order to solve the above problem, a power conversion circuit disclosed in the present specification is a power conversion circuit including first and second transistors connected in series and a control unit, and Each of the first and second transistors includes a gate electrode, a first ohmic electrode, and a second ohmic electrode, and each of the first and second transistors changes from the first ohmic electrode to the second ohmic electrode. The control unit includes a diode capable of flowing current, and the control unit allows the first and second transistors to conduct current from one of the first ohmic electrode and the second ohmic electrode to the other. The first and second non-conducting states in which no current can flow from the second ohmic electrode to the first ohmic electrode. And the second transistor is controlled so that one of the first and second transistors is in the conductive state, the positive ohmic electrode is used as a reference between the gate electrode and the first ohmic electrode of the one transistor. When one voltage is applied and one of the first and second transistors is brought into the non-conductive state, the second ohmic electrode of the transistor is used as a reference in the conductive state immediately before the one transistor. If the potential of the ohmic electrode is negative, a positive voltage lower than the first voltage or a second voltage that is zero voltage is applied between the gate electrode and the first ohmic electrode of the transistor, In the previous conductive state, the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is If the gate electrode of the transistor - applying a third voltage which is a negative voltage between the first ohmic electrode.

  The control method disclosed in the present specification is connected in series to each other, and each includes a gate electrode, a first ohmic electrode, and a second ohmic electrode, and the first ohmic electrode to the second ohmic electrode. A control method for controlling the first and second transistors including a diode capable of passing a current through the first and second transistors, wherein one of the first ohmic electrode and the second ohmic electrode is the other. The first and second transistor gate electrodes-first so as to repeat a conductive state in which a current can flow through and a non-conductive state in which a current cannot flow from the second ohmic electrode to the first ohmic electrode. When a voltage is applied between the ohmic electrodes and one of the first and second transistors is in the conductive state, When a positive first voltage is applied between the gate electrode and the first ohmic electrode of one transistor and one of the first and second transistors is in the non-conductive state, the conductive state immediately before the one transistor is If the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is negative, a positive voltage lower than the first voltage or zero between the gate electrode and the first ohmic electrode of the transistor If the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is positive in the conductive state immediately before the one transistor, the second voltage of the transistor is applied. A third voltage, which is a negative voltage, is applied between the gate electrode and the first ohmic electrode.

  According to the above configuration, fluctuations in the threshold voltage of the transistor can be suppressed while suppressing a decrease in the current flowing through the freewheeling diode.

1 is a circuit block diagram illustrating a configuration of a power conversion circuit according to a first embodiment. It is a figure which shows the waveform of the output current and gate drive voltage of the power converter circuit which concerns on Embodiment 1. FIG. FIG. 3 is a circuit diagram for explaining an operation of the power conversion circuit according to the first exemplary embodiment; FIG. 3 is a circuit diagram for explaining an operation of the power conversion circuit according to the first exemplary embodiment; 3 is a flowchart for determining the operation of the control circuit according to the first embodiment. It is a figure which shows the waveform of the output current and gate drive voltage of the power converter circuit which concerns on Embodiment 2. FIG. 6 is a flowchart for determining the operation of the control circuit according to the second embodiment. It is a figure which shows the waveform of the output current of the power converter circuit of Embodiment 2, and the gate drive voltage of an upper arm transistor. It is a figure which shows the waveform of the output current and gate drive voltage of the power converter circuit which concerns on Embodiment 3. FIG. It is a figure which shows the waveform of the output current and gate drive voltage of the power converter circuit which concerns on Embodiment 4. FIG. It is a circuit diagram which illustrates the circuit configuration of an upper arm drive circuit. It is a circuit diagram which illustrates the circuit configuration of an upper arm drive circuit. It is a figure which shows the waveform of the output current and gate drive voltage of the power converter circuit which concerns on the modification of Embodiment 1. FIG. 6 is a flowchart for determining an operation of a control circuit according to a modification of the first embodiment. FIG. 3 is a circuit block diagram of a device including the power conversion circuit according to the first embodiment. FIG. 3 is a circuit block diagram of a device including the power conversion circuit according to the first embodiment. FIG. 3 is a circuit block diagram of a device including the power conversion circuit according to the first embodiment. FIG. 3 is a circuit block diagram of a device including the power conversion circuit according to the first embodiment. It is a figure which shows the waveform of the electric current and gate drive voltage of the device shown in FIG. FIG. 3 is a circuit block diagram of a device including the power conversion circuit according to the first embodiment. It is sectional drawing which shows the structure of SiC-MISFET which is an example of a transistor. It is sectional drawing which shows the structure of SiC-MISFET which is an example of a transistor. It is sectional drawing which shows the structure of SiC-IGBT which is an example of a transistor. It is sectional drawing which shows the structure of SiC-IGBT which is an example of a transistor. It is a figure which shows the IV characteristic of the SiC-MOSFET disclosed by patent document 1. FIG.

[Background of obtaining one embodiment of the present invention]
Hereinafter, prior to specific description of the embodiments of the present invention, the background for obtaining the embodiments of the present invention will be described.
When a transistor is used as a switching element, when the power conversion circuit is driven and the Vt of the transistor fluctuates, the switching timing of the transistor between the conductive state and the non-conductive state fluctuates. Non-Patent Document 1 reports that when a positive voltage is applied to the gate electrode of the SiC-MOSFET, Vt varies in the positive direction, and when a negative voltage is applied to the gate electrode, Vt varies in the negative direction. . In view of this, the inventor examined applying a negative voltage to the gate electrode during the non-conduction period of the transistor in order to suppress a change in the positive direction of Vt of the transistor.

However, the inventor has noticed that when a free-wheeling diode built in a transistor is used, the conduction performance of the free-wheeling diode is reduced when a negative voltage is applied to the gate electrode of the transistor. This will be described in detail below.
FIG. 25 is a diagram illustrating IV characteristics of the SiC-MOSFET disclosed in Patent Document 1. In FIG. The horizontal axis in FIG. 25 represents the drain-source voltage (hereinafter abbreviated as Vds). When the source electrode side is a high potential side and the drain electrode side is a low potential side, Vds is a negative value. The vertical axis in FIG. 25 represents the drain current. Here, since current flows from the source electrode toward the drain electrode, the drain current is shown as a negative value.

  FIG. 25 shows that even when Vds is the same, when Vgs is negative, that is, when a negative voltage is applied to the gate electrode with reference to the source electrode, the drain current becomes small. For example, when Vds is −5 V, the drain current is about −0.5 A when the voltage applied to the gate electrode is −20 V, and the drain current is about −1.8 A when the voltage applied to the gate electrode is 0 V. . Here, the drain current that flows when the voltage applied to the gate electrode is −20 V and 0 V and Vds is negative is the current that flows through the diode built in the transistor. Thus, the drain current decreases when a negative voltage is applied to the gate electrode, because the forward voltage drop of the diode built in the transistor increases. Therefore, when the diode incorporated in the transistor is used as the freewheeling diode, it can be seen that the conduction performance of the freewheeling diode deteriorates when a negative voltage is applied to the gate electrode of the transistor.

The inventor paid attention to these events and decided to apply the negative voltage to the gate electrode of the transistor to suppress the fluctuation of Vt during a period when the current does not flow through the freewheeling diode. Thereby, the fluctuation | variation of the threshold voltage of a transistor can be suppressed, suppressing the fall of the conduction | electrical_connection performance of a free-wheeling diode. Specifically, for example, when a load is connected to the switching element, a constant voltage is supplied from the power supply, and no current is supplied to the load through the freewheeling diode, a negative voltage is applied to the gate electrode of the transistor. Apply.
<Embodiment 1>
Hereinafter, a power conversion circuit according to an embodiment of the present invention will be described with reference to the drawings.
1. Overall Configuration FIG. 1 is a circuit block diagram showing a configuration of a power conversion circuit according to the first embodiment.

  As shown in FIG. 1, the power conversion circuit 1 includes an upper arm transistor 11U and a lower arm transistor 11D. The upper arm transistor 11U includes a gate electrode, a source electrode that is a first ohmic electrode, a drain electrode that is a second ohmic electrode, and an upper arm free-wheeling diode 12U that can flow current from the source electrode to the drain electrode. Similarly to the upper arm transistor 11U, the lower arm transistor 11D can pass a current from the source electrode to the drain electrode, the source electrode as the first ohmic electrode, the drain electrode as the second ohmic electrode, and the drain electrode. A lower arm reflux diode 12D is provided. The upper arm freewheeling diode 12U and the lower arm freewheeling diode 12D (hereinafter simply referred to as “freewheeling diode 12” when there is no need to distinguish) are not separately connected to the upper arm transistor 11U and the lower arm transistor 11D, respectively. These are built in the upper arm transistor 11U and the lower arm transistor 11D, respectively. The power conversion circuit 1 controls the upper arm transistor 11U and the lower arm transistor 11D (hereinafter simply referred to as “transistor 11” when there is no need for distinction) to repeat the conduction state and the non-conduction state. 21, current detection means 22 that samples the current I flowing from the power conversion circuit 1 toward the load 2 and transmits a signal to the control circuit 21, and an upper arm gate drive circuit that applies a voltage between the gate and source of the transistor 11 30U and lower arm gate drive circuit 30D (hereinafter simply referred to as “gate drive circuit 30” when there is no need to distinguish between them. In addition, applying a voltage between the gate and source is simply referred to as “applying a voltage to the gate electrode”. Called). The control circuit 21 and the gate drive circuit 30 constitute a control unit 20 that applies a voltage to the gate electrode of the transistor 11. The power conversion circuit 1 converts the DC power supplied from the power source 3 into DC power or AC power and supplies it to the load 2.

  Voltage sources 31U1, 31U2, 31U3 (hereinafter simply referred to as “voltage source 31U” when there is no need to distinguish) connected to the upper arm gate drive circuit 30U are voltage sources that output voltages EU1, EU2, EU3, respectively. It is. On the other hand, voltage sources 31D1, 31D2, and 31D3 (hereinafter simply referred to as “voltage source 31D” when there is no need to distinguish) connected to the lower arm gate drive circuit 30D output voltages ED1, ED2, and ED3, respectively. The voltage source In the present embodiment, the threshold voltages Vt (hereinafter simply referred to as Vt) of the transistors 11U and 11D are both positive voltages. The voltages EU1 and ED1 are positive voltages equal to or higher than Vt. The voltages EU2 and ED2 are positive voltages that are less than Vt and smaller than EU1 and ED1. Voltages EU3 and ED3 are negative voltages. Note that the voltages EU2 and ED2 may be zero, and in that case, the voltage source 31U2 and the voltage source 31D2 may not be used.

  The transistor 11 is, for example, a MISFET. When a voltage equal to or higher than Vt is applied to the gate electrode of the transistor 11, the transistor 11 enters a state where current can flow from the drain electrode to the source electrode, that is, a conductive state. On the other hand, when a voltage lower than Vt is applied to the gate electrode of the transistor 11, the transistor 11 is in a state where no current can flow from the drain electrode to the source electrode, that is, a non-conductive state. Note that current can flow from the source electrode to the drain electrode through the free-wheeling diode 12 incorporated in the transistor 11 in either the conductive state or the non-conductive state.

The control circuit 21 is a circuit using, for example, a microcomputer, and the gate drive circuit 30 outputs any one of the voltages EU1, EU2, EU3 and voltages ED1, ED2, ED3 based on the signal obtained from the current detection means 22, for example. A signal for switching whether to do is output to the gate drive circuit 30. The upper arm gate drive circuit 30U controls the conduction state and the non-conduction state of the upper arm transistor 11U by switching the voltage applied to the gate electrode of the upper arm transistor 11U among EU1, EU2, and EU3. The lower arm gate drive circuit 30D controls the conductive state and the nonconductive state of the lower arm transistor 11D by switching the voltage applied to the gate electrode of the lower arm transistor 11D among ED1, ED2, and ED3.
2. Control Control of the power conversion circuit 1 will be described with reference to FIGS. FIG. 2 is a diagram illustrating waveforms of the output current and the gate drive voltage of the power conversion circuit according to the first embodiment. 3 and 4 are circuit diagrams for explaining the operation of the power conversion circuit according to the first embodiment. FIG. 5 is a flowchart for determining the operation of the control circuit according to the first embodiment.

  The gate drive circuit 30 uses a voltage command from the control circuit 21 to be applied in a non-conduction state and a signal obtained from a signal generation circuit (not shown) for commanding the conduction state or non-conduction state by using the PWM ( Pulse Width Modulation (pulse width modulation) control is performed. As a result, the gate drive voltage (voltage applied to the gate electrode) shown in FIGS. 2B and 2C is applied to the gate electrode of the transistor 11, and the current I shown in FIG. 2 flows through the power conversion circuit. . Here, a known circuit can be used as a generation circuit for the conduction state and non-conduction state signals. As a conduction | electrical_connection state and non-conduction state signal generation circuit, the circuit comprised by a carrier signal generator and a reference signal generator is mentioned, for example.

2A shows the waveform of the current I, FIG. 2B shows the gate drive voltage of the upper arm transistor 11U, and FIG. 2C shows the gate drive voltage of the lower arm transistor 11D. Here, the direction of the current I is assumed to be positive when the current I goes from the transistor 11 to the load 2 and negative when the current I goes from the load 2 to the transistor 11. From time TA to TB, the current I flows in the positive direction, and from time TB to TC, the current I flows in the negative direction. The dotted line in FIGS. 3 and 4 shows the flow of current I. 3A to 3D show the flow of the current I from T1 to T4 in FIG. 2, respectively. FIGS. 4A to 4D show the flow of the current I from T5 to T8 in FIG. 2, respectively. Show.
2-1. The control time T1 when the current I is positive or zero is a time when the upper arm transistor 11U is in a conductive state and the lower arm transistor 11D is in a nonconductive state. At time T1, EU1 is applied to the gate electrode of the upper arm transistor 11U, and ED2 is applied to the gate electrode of the lower arm transistor 11D. At this time, as shown in FIG. 3A, the current I flows through the upper arm transistor 11U toward the load 2. At this time, a reverse bias is applied to the upper arm freewheeling diode 12U built in the upper arm transistor 11U in the conductive state. Note that the reverse bias applied to the freewheeling diode 12 means a state in which the potential of the drain electrode with reference to the potential of the source electrode of the transistor is positive. The forward bias applied to the free wheeling diode 12 means a state in which the potential of the drain electrode with reference to the potential of the source electrode of the transistor is negative.

  Time T2 is a time (dead time) when the upper arm transistor 11U and the lower arm transistor 11D become non-conductive. As shown in FIG. 2, at time T2, EU3 is applied to the gate electrode of the upper arm transistor 11U, and ED2 is applied to the gate electrode of the lower arm transistor 11D. At this time, the load 2 tries to pass the current I in the same direction as at the time T1. Therefore, as shown in FIG. 3B, a forward bias is applied to the lower arm freewheeling diode 12D, and the current I flows through the lower arm freewheeling diode 12D to the load 2. Here, looking at the upper arm transistor 11U, at time T2, a reverse bias is applied to the upper arm freewheeling diode 12U in the non-conducting period of the upper arm transistor 11U and in the conductive state of the upper arm transistor 11U immediately before. It is a period. Hereinafter, this period is referred to as a “reverse bias non-conduction period”. During the reverse bias non-conduction period, no current flows through the upper arm return diode 12U, and even if the conduction performance of the upper arm return diode 12U is reduced, the output current of the power conversion circuit is not affected. Therefore, the negative voltage EU3 may be applied to the gate electrode of the upper arm transistor 11U. On the other hand, looking at the lower arm transistor 11D, at time T2, it is a forward bias non-conduction period that is not a reverse bias non-conduction period. In the forward bias non-conduction period, a current flows through the lower arm freewheeling diode 12D. Therefore, when the negative voltage ED3 is applied to the gate electrode of the lower arm transistor 11D, the conduction performance of the freewheeling diode 12D is lowered, which affects the output current of the power conversion circuit. Therefore, at time T2, not the negative voltage ED3 but ED2 is applied to the gate electrode of the lower arm transistor 11D.

  Time T3 is a time at which the upper arm transistor 11U is in a non-conductive state and the lower arm transistor 11D is in a conductive state. At time T3, EU3 is applied to the gate electrode of the upper arm transistor 11U, and ED1 is applied to the gate electrode of the lower arm transistor 11D. At this time, as shown in FIG. 3C, the current I mainly flows through the lower arm transistor 11D and goes to the load 2. Further, a forward bias is applied to the lower arm freewheeling diode 12D built in the lower arm transistor 11D in the conductive state.

Time T4 is a time (dead time) when the upper arm transistor 11U and the lower arm transistor 11D become non-conductive. As shown in FIG. 2, at time T4, EU3 is applied to the gate electrode of the upper arm transistor 11U, and ED2 is applied to the gate electrode of the lower arm transistor 11D. At this time, the load 2 tries to flow a current in the same direction as at time T3. Therefore, a forward bias is applied to the lower arm freewheeling diode 12D, and the current I flows to the load 2 through the lower arm freewheeling diode 12D. Here, looking at the upper arm transistor 11U, it is not a forward bias non-conduction period at time T4. Therefore, EU3 may remain applied to the gate electrode of the upper arm transistor 11U. On the other hand, when viewing the lower arm transistor 11D, time T4 is a non-conduction period of the lower arm transistor 11D, and a period in which a forward bias is applied to the lower arm freewheeling diode 12D in the conductive state of the immediately lower arm transistor 11D. This is a forward bias non-conduction period. Therefore, for the same reason as at time T2, not the negative voltage ED3 but ED2 is applied to the gate electrode of the lower arm transistor 11D.
2-2. The control time T5 when the current I is negative is the time when the upper arm transistor 11U is in a non-conductive state and the lower arm transistor 11D is in a conductive state. At time T5, EU2 is applied to the gate electrode of the upper arm transistor 11U, and ED1 is applied to the gate electrode of the lower arm transistor 11D. At this time, as shown in FIG. 4A, the current I flows from the load 2 to the lower arm transistor 11D. Further, a reverse bias is applied to the lower arm freewheeling diode 12D built in the lower arm transistor 11D in the conductive state.

  Time T6 is a time (dead time) at which the upper arm transistor 11U and the lower arm transistor 11D are turned off. As shown in FIG. 2, at time T6, EU2 is applied to the gate electrode of the upper arm transistor 11U, and ED3 is applied to the gate electrode of the lower arm transistor 11D. At this time, the load 2 tries to pass the current I in the same direction as at time T5. Therefore, as shown in FIG. 4B, a forward bias is applied to the upper arm freewheeling diode 12U, and the current I flows through the load 2 toward the upper arm freewheeling diode 12U. Here, at time T6, since a current flows through the freewheeling diode 12U, EU2 instead of the negative voltage EU3 is applied to the gate electrode of the upper arm transistor 11U. On the other hand, when viewing the lower arm transistor 11D, at time T6, the lower arm transistor 11D is in a non-conducting period, and a period in which a reverse bias is applied to the lower arm freewheeling diode 12D in the immediately preceding lower arm transistor 11D in a conducting state. Is a reverse bias non-conduction period. Therefore, the negative voltage ED3 is applied to the gate electrode of the lower arm transistor 11D.

  Time T7 is a time when the upper arm transistor 11U is in a conductive state and the lower arm transistor 11D is in a non-conductive state. At time T7, EU1 is applied to the gate electrode of the upper arm transistor 11U, and ED3 is applied to the gate electrode of the lower arm transistor 11D. At this time, as shown in FIG. 4C, the current I flows through the load 2 and mainly flows through the upper arm transistor 11U. Further, a forward bias is applied to the upper arm freewheeling diode 12U built in the upper arm transistor 11U in the conductive state.

Time T8 is a time (dead time) at which the upper arm transistor 11U and the lower arm transistor 11D are turned off. As shown in FIG. 2, at time T8, EU2 is applied to the gate electrode of the upper arm transistor 11U, and ED3 is applied to the gate electrode of the lower arm transistor 11D. At this time, the load 2 tries to pass the current I in the same direction as at time T7. Therefore, as shown in FIG. 4D, a forward bias is applied to the upper arm freewheeling diode 12U, and the current I flows through the load 2 toward the upper arm freewheeling diode 12U. Here, at time T8, since current flows through the freewheeling diode 12U, EU2 instead of the negative voltage EU3 is applied to the gate electrode of the upper arm transistor 11U. On the other hand, looking at the lower arm transistor 11D, it is not a forward bias non-conduction period at time T8. Therefore, ED3 may remain applied to the gate electrode of the lower arm transistor 11D.
2-3. Flowchart for Controlling Transistor from Conductive State to Non-Conductive State Hereinafter, a flowchart for performing the above control will be described.

FIG. 5 is a flowchart for determining an operation to be performed by the control circuit 21 when the transistor is repeatedly controlled from the conductive state to the non-conductive state. Here, a period in which the transistor is in a non-conduction state is referred to as a non-conduction period.
First, the control circuit 21 samples the signal output from the current detection means 22 (step S001), and determines whether or not the current I is 0 or more based on the sampled signal (step S002).

  When the current I is 0 or more (step S002: Yes), the voltage applied to the gate electrode of the upper arm transistor 11U in the non-conducting period is EU3, and the voltage applied to the gate electrode of the lower arm transistor 11D in the non-conducting period is ED2. (Step S003a). As a result, the negative voltage EU3 is applied to the gate electrode of the upper arm transistor 11U corresponding to the upper arm freewheeling diode 12U that is reversely biased. On the other hand, a positive voltage ED2 less than Vt is applied to the gate electrode of the lower arm transistor 11D corresponding to the lower arm freewheeling diode 12D that is forward biased.

  When the current I is less than 0 (step S002: No), the voltage applied to the gate electrode of the upper arm transistor 11U during the non-conduction period is EU2, and the voltage applied to the gate electrode of the lower arm transistor 11D during the non-conduction period is ED3. (Step S003b). As a result, a positive voltage EU2 less than Vt is applied to the gate electrode of the upper arm transistor 11U corresponding to the upper arm freewheeling diode 12U to which the forward bias is applied. On the other hand, the negative voltage ED3 is applied to the gate electrode of the lower arm transistor 11D corresponding to the lower arm freewheeling diode 12D to which the reverse bias is applied.

The control circuit 21 repeats the above processing at regular intervals (step S004).
In this way, the control circuit 21 instructs the gate drive circuit 30 to select the positive voltage EU2, ED2 or the negative voltage EU3, ED3, which is less than Vt, as the voltage applied to the gate electrode of the transistor 11 during the non-conduction period. To do. In this flowchart, the negative voltages EU3 and ED3 are applied to the gate electrode of the transistor 11 during the entire reverse bias non-conduction period. Further, positive voltages EU2 and ED2 less than Vt are applied to the gate electrode of the transistor 11 throughout the forward bias non-conduction period.
2-4. Summary The control of the upper arm transistor 11U will be summarized. The same applies to the lower arm transistor 11D.

A period (time T1, T7) in which the upper arm transistor 11U is conducted is defined as a conduction period. In the conduction period, EU1 which is a positive voltage equal to or higher than Vt is applied to the gate electrode of the upper arm transistor 11U.
In the forward bias non-conduction period, EU2 which is less than Vt and lower than EU1 is applied to the gate electrode of the upper arm transistor 11U. In the reverse bias non-conduction period, EU3 that is a negative voltage is applied to the gate electrode of the upper arm transistor 11U.

The negative voltage value EU3 (ED3) applied to the gate electrode preferably satisfies V ₀ <EU3 (ED3) <0. Here, V ₀ is a voltage at which the threshold voltage Vt starts to fluctuate in the negative direction when applied to the gate electrode. By setting the voltage value EU3 (ED3) of the negative voltage applied to the gate electrode in this way, it is possible to suppress the threshold voltage Vt from changing in the negative direction when the negative voltage is applied to the gate electrode.

V ₀ coincides with the gate voltage indicating the inflection point in the gate voltage-gate capacitance characteristic. Therefore, V ₀ can be obtained from the inflection point when the relationship between the gate voltage and the gate capacitance is measured. The gate voltage indicating the inflection point in the gate voltage-gate capacitance characteristic substantially matches the flat band voltage of the transistor. The flat band voltage is a gate voltage at which the energy band on the surface of the semiconductor layer in contact with the gate insulating film becomes flat.
3. Effect According to this configuration, by applying a negative voltage to the gate electrode of the transistor 11, fluctuations in Vt in the positive direction of the transistor 11 can be suppressed. Thereby, it is possible to suppress a change in timing of switching between the conductive state and the non-conductive state of the transistor 11 caused by the change in Vt of the transistor 11.

 In FIGS. 2B and 2C, the switching time between the conductive state and the non-conductive state of the transistor 11 is zero, but actually it takes time to rise and fall. Therefore, when Vt varies in the positive direction, for example, when the transistor 11 is started up, the time until the gate voltage of the transistor 11 changes from 0 to Vt increases. That is, when Vt varies in the positive direction, the rising timing of the transistor 11 is delayed. Further, if the timing of the conduction state and the non-conduction state of the transistor 11 fluctuates, it is necessary to lengthen the dead time so as not to be affected by it. If the dead time is lengthened, the power conversion efficiency of the power conversion circuit may decrease, which is not preferable.

By the way, when a negative voltage is applied to the gate electrode of the transistor 11, the forward voltage drop of the freewheeling diode 12 increases. However, in this configuration, even if the forward voltage drop of the freewheeling diode 12 increases due to application of a negative voltage and the conduction performance deteriorates, no current flows through the freewheeling diode 12 immediately after this. Therefore, even if a negative voltage is applied to the gate electrode of the transistor 11 and the conduction performance of the freewheeling diode 12 is reduced, the amount of current supplied to the load 2 connected to the transistor 11 does not change. Therefore, it is possible to provide a power conversion circuit using the transistor 11 that suppresses a decrease in the current flowing through the freewheeling diode 12 and suppresses a variation in the threshold voltage Vt of the transistor 11.
<Embodiment 2>
FIG. 6 is a diagram illustrating waveforms of an output current and a gate drive voltage of the power conversion circuit according to the second embodiment. Since the configuration other than the following is the same as that of the first embodiment, the description thereof is omitted. In the second embodiment, the application period of the negative voltages EU3 and ED3 necessary for suppressing the fluctuation of Vt is determined in advance (hereinafter, this period is referred to as Tm). Tm is set to an application period sufficient to suppress the fluctuation of Vt by the application operation of the negative voltages EU3 and ED3 once per repeating unit of the conduction state and the non-conduction state of the transistor 11. Note that the application time Tm of the negative voltage applied to the gate electrode may be set so that fluctuation in the positive direction of the threshold voltage Vt is suppressed according to the voltage value of the negative voltage to be applied. The application time Tm of the negative voltage applied to the gate electrode is preferably 1/10 or more of the time during which the positive voltage is applied to the gate electrode.

In the second embodiment, the negative voltages EU3 and ED3 are applied by Tm in the reverse bias non-conduction period, and the application period of EU3 and ED3 is the second half of the reverse bias non-conduction period. Note that the latter half here refers to a period including the switching time from the reverse bias non-conduction period to the conduction period.
1. Control In this configuration, the control in the reverse bias non-conduction period in the transistor 11 is different from that in the first embodiment.

  Time T2a is a time (dead time) at which the upper arm transistor 11U and the lower arm transistor 11D are turned off. As shown in FIG. 6, at time T2a, EU2 is applied to the gate electrode of the upper arm transistor 11U, and ED2 is applied to the gate electrode of the lower arm transistor 11D. At this time, as shown in FIG. 3B, forward bias is applied to the lower arm freewheeling diode 12D, and the current I flows through the lower arm freewheeling diode 12D toward the load 2.

  Time T3a is a time when the upper arm transistor 11U is in a non-conductive state and the lower arm transistor 11D is in a conductive state. At time T3a, EU2 is applied to the gate electrode of the upper arm transistor 11U, and ED1 is applied to the gate electrode of the lower arm transistor 11D. At this time, as shown in FIG. 3C, the current I mainly flows through the lower arm transistor 11D and goes to the load 2. Further, a forward bias is applied to the lower arm freewheeling diode 12D built in the lower arm transistor 11D in the conductive state.

  Time T4a is a time (dead time) when the upper arm transistor 11U and the lower arm transistor 11D become non-conductive. As shown in FIG. 6, at time T4a, EU3 is applied to the gate electrode of the upper arm transistor 11U, and ED2 is applied to the gate electrode of the lower arm transistor 11D. At this time, as shown in FIG. 3D, a forward bias is applied to the lower arm freewheeling diode 12D, and the current I flows through the lower arm freewheeling diode 12D toward the load 2.

  Time T6a is a time (dead time) at which the upper arm transistor 11U and the lower arm transistor 11D are turned off. As shown in FIG. 6, at time T6a, EU2 is applied to the gate electrode of the upper arm transistor 11U, and ED2 is applied to the gate electrode of the lower arm transistor 11D. At this time, as shown in FIG. 4B, a forward bias is applied to the upper arm freewheeling diode 12U, and the current I flows through the load 2 toward the upper arm freewheeling diode 12U.

  Time T7a is a time when the upper arm transistor 11U is in a conductive state and the lower arm transistor 11D is in a non-conductive state. At time T7a, EU1 is applied to the gate electrode of the upper arm transistor 11U, and ED2 is applied to the gate electrode of the lower arm transistor 11D. At this time, as shown in FIG. 4C, the current I flows mainly from the load 2 through the upper arm transistor 11U. Further, a forward bias is applied to the upper arm freewheeling diode 12U built in the upper arm transistor 11U in the conductive state.

  Time T8a is a time (dead time) at which the upper arm transistor 11U and the lower arm transistor 11D are turned off. As shown in FIG. 6, at time T8a, EU2 is applied to the gate electrode of the upper arm transistor 11U, and ED3 is applied to the gate electrode of the lower arm transistor 11D. At this time, as shown in FIG. 4D, a forward bias is applied to the upper arm freewheeling diode 12U, and the current I flows through the load 2 toward the upper arm freewheeling diode 12U.

Note that the length of the period during which the negative voltages EU3 and ED3 are applied to the gate electrode of the transistor 11 is Tm for both the upper and lower arms.
1-2. Summary Regarding the control of the upper arm transistor 11U, the parts different from the first embodiment will be described together. The same applies to the lower arm transistor 11D.

At time T2a in the reverse bias non-conduction period, EU2 that is a positive voltage less than Vt is applied to the gate electrode of the upper arm transistor 11U. Further, at time T4a in the reverse bias non-conduction period, EU3 that is a negative voltage is applied to the gate electrode of the upper arm transistor 11U. That is, EU3 that is a negative voltage is applied to the gate electrode of the upper arm transistor 11U only in the period Tm in the reverse bias non-conduction period.
1-3. FIG. 7 is a flowchart for determining the operation of the control circuit during the non-conduction period according to the second embodiment.

First, the control circuit 21 samples the signal output from the current detection means 22 (step S101), and determines whether or not the current I is 0 or more based on the sampled signal (step S102).
When the current I is 0 or more (step S102: Yes), the voltage applied to the gate electrode of the upper arm transistor 11U is set to EU3 at Tm in the non-conduction period, and EU2 is set to the remaining period in the non-conduction period. In the non-conduction period, the voltage applied to the gate electrode of the lower arm transistor 11D is ED2 (step S103a). Thereby, the negative voltage EU3 is applied at Tm to the gate electrode of the upper arm transistor 11U corresponding to the upper arm freewheeling diode 12U to which the reverse bias is applied, and the positive voltage EU2 is applied during the remaining period. On the other hand, the positive voltage ED2 is applied to the gate electrode of the lower arm transistor 11D corresponding to the lower arm freewheeling diode 12D to which the forward bias is applied.

  When the current I is less than 0 (step S102: No), the voltage applied to the gate electrode of the upper arm transistor 11U in the non-conduction period is EU2. Further, at Tm in the non-conduction period, the voltage applied to the gate electrode of the lower arm transistor 11D is ED3, and is ED2 in the remaining period in the non-conduction period (step S103b). As a result, the positive voltage EU2 is applied to the gate electrode of the upper arm transistor 11U corresponding to the upper arm freewheeling diode 12U to which the forward bias is applied. On the other hand, the negative voltage ED3 is applied at Tm to the gate electrode of the lower arm transistor 11D corresponding to the lower arm freewheeling diode 12D to which the reverse bias is applied, and the positive voltage ED2 is applied during the remaining period.

The control circuit 21 repeats the above processing at regular intervals (step S104).
The control circuit 21 instructs the gate drive circuit 30 to select the positive voltage EU2, ED2 or the negative voltage EU3, ED3 less than Vt as the voltage to be applied to the gate electrode of the transistor 11 during the non-conduction period. The drive waveforms shown in (b) and (c) are applied to the gate electrode of the transistor 11. That is, the negative voltages EU3 and ED3 are applied to the gate electrode of the transistor 11 in the predetermined period Tm of the reverse bias non-conduction period, and the positive voltage less than Vt is applied to the gate electrode of the transistor 11 in the remaining period of the reverse bias non-conduction period. EU2 and ED2 are applied.

  By the way, the transistor repeats a conductive state and a non-conductive state. Here, since the non-conduction period is long when the instantaneous value of the current I is small, the non-conduction period is longer than Tm. Therefore, as described above, a negative voltage can be applied to the gate electrode of the transistor 11 in the predetermined period Tm of the reverse bias non-conduction period. However, since the non-conduction period is short when the instantaneous value of the current I is large, the non-conduction period becomes smaller than Tm. At this time, it is conceivable that EU2, ED2 or EU3, ED3 is applied to the gate electrode of the transistor 11 throughout the reverse bias non-conduction period. This will be described in detail below.

As shown in FIG. 8B, the negative voltage EU3 is applied to the gate electrode of the upper arm transistor 11U during the entire reverse bias non-conduction period. As a result, the period during which the negative voltage EU3 is applied is smaller than Tm, but the Vt of the upper arm transistor 11U can be reduced to some extent, and the fluctuation of the Vt of each transistor 11 in the positive direction can be suppressed.
2. Effect Even with this configuration, it is possible to provide the power conversion circuit 1 that suppresses the fluctuation of the threshold voltage Vt of the transistor 11 while suppressing a decrease in the current flowing through the freewheeling diode 12.

By the way, if the time for applying the negative voltage to the gate electrode of the transistor 11 becomes long, the transistor 11 may be deteriorated. By limiting the period during which EU3 and ED3 that are negative voltages are applied to Tm as in this configuration, deterioration of the transistor 11 can be suppressed, and the power conversion circuit 1 having a longer life can be provided.
<Embodiment 3>
In the third embodiment, the negative voltages EU3 and ED3 are applied only during the period Tm in the reverse bias non-conduction period. The period Tm is the center of the reverse bias non-conduction period. The center here refers to a period around the center from the start to the end of the reverse bias non-conduction period.

FIG. 9 is a diagram illustrating waveforms of an output current and a gate drive voltage of the power conversion circuit according to the third embodiment. Since the configuration other than the following is the same as that of the second embodiment, the description thereof is omitted.
As shown in FIG. 9B, for the upper arm transistor 11U, in the reverse bias non-conduction period, a negative voltage EU3 is applied at time T3b corresponding to Tm, and a positive voltage EU2 is applied at times T2b and T4b not corresponding to Tm. Applied. As shown in FIG. 9C, for the lower arm transistor 11D, in the reverse bias non-conduction period, a negative voltage ED3 is applied at time T7b corresponding to Tm, and a positive voltage ED2 is applied at times T6b and T8b not corresponding to Tm. Applied.

Even with this configuration, it is possible to provide the power conversion circuit 1 that suppresses the variation in the threshold voltage Vt of the transistor 11 while suppressing a decrease in the current flowing through the freewheeling diode 12. Further, by limiting the period during which EU3 and ED3, which are negative voltages, are applied to Tm, it is possible to suppress the deterioration of the transistor 11 and provide the power conversion circuit 1 having a longer life.
<Embodiment 4>
In the fourth embodiment, the negative voltages EU3 and ED3 are applied only during the period Tm in the reverse bias non-conduction period. The period Tm is the first half of the reverse bias non-conduction period. Note that the first half here refers to a period including the time of switching from the conduction period to the reverse bias non-conduction period.

FIG. 10 is a diagram illustrating waveforms of the output current and the gate drive voltage of the power conversion circuit according to the fourth embodiment. Since the configuration other than the following is the same as that of the second embodiment, the description thereof is omitted.
As shown in FIG. 10B, for the upper arm transistor 11U, in the reverse bias non-conduction period, a negative voltage EU3 is applied at time T2c corresponding to Tm, and a positive voltage EU2 is applied at times T3c and T4c not corresponding to Tm. Applied. As shown in FIG. 10C, for the lower arm transistor 11D, in the reverse bias non-conduction period, a negative voltage ED3 is applied at time T6c corresponding to Tm, and a positive voltage ED2 is applied at times T7c and T8c not corresponding to Tm. Applied.

Even with this configuration, it is possible to provide the power conversion circuit 1 that suppresses the variation in the threshold voltage Vt of the transistor 11 while suppressing a decrease in the current flowing through the freewheeling diode 12. Further, by limiting the period during which EU3 and ED3, which are negative voltages, are applied to Tm, it is possible to suppress the deterioration of the transistor 11 and provide the power conversion circuit 1 having a longer life.
<Others>
1. Configuration Example of Gate Drive Circuit Here, a specific circuit configuration of the gate drive circuit 30 in the power conversion circuit 1 described in the above embodiment will be described with reference to FIGS. 11 and 12 show the upper arm gate drive circuit 30U, the same applies to the lower arm gate drive circuit 30D. Note that the circuit configuration here is merely an example, and is not limited to the configuration of the upper arm gate drive circuit 30U shown in FIGS. 11 and 12, and the voltages EU1, EU2, EU3 and ED1, ED2, ED3 are applied to the gate of the transistor 11. Other configurations that can be applied to the electrodes may be used.

FIG. 11 is a circuit diagram illustrating the circuit configuration of the upper arm drive circuit.
As shown in FIG. 11, the upper arm gate drive circuit 30U is connected to the transistors 41U1, 41U2, and 41U3 connected to the voltage sources 31U1, 31U2, and 31U3, respectively, and the transistors 41U1, 41U2, and 41U3 corresponding to the terminals on one side. And the remaining terminals are provided with resistance elements 42U1, 42U2, 42U3 connected to the gate electrode of the upper arm transistor 11U, and a diode 43. The transistors 41U1, 41U2, and 41U3 are bipolar transistors. The diode 43 is interposed between the transistor 41U2 and the resistance element 42U2.

  In this configuration, when the positive voltage EU1 is applied from the voltage source 31U1 to the gate electrode of the upper arm transistor 11U, the transistor 41U1 is turned on, the transistor 41U2 is turned off, and the transistor 41U3 is turned off. When applying positive voltage EU2 from voltage source 31U2, transistor 41U1 is turned off, transistor 41U2 is turned on, and transistor 41U3 is turned off. When the negative voltage EU3 from the voltage source 31U3 is applied, the transistor 41U1 is turned off, the transistor 41U2 is turned off, and the transistor 41U3 is turned on. Thus, by switching the conduction state and the non-conduction state of the transistors 41U1, 41U2, and 41U3, the voltage from the voltage sources 31U1, 31U2, and 31U3 can be applied to the gate electrode of the upper arm transistor 11U.

  The diode 43 switches the transistor 41U2 from the conductive state to the nonconductive state and the transistor 41U3 from the nonconductive state to the conductive state in order to switch the voltage applied to the gate electrode of the upper arm transistor 11U from the positive voltage EU2 to the negative voltage EU3. Are provided to prevent the current from flowing from the voltage source 31U2 to the voltage source 31U3 via the transistor 41U2, the resistor element 42U2, the resistor element 42U3, and the transistor 41U3. In this configuration, since the diode 43 is provided, the voltage applied to the gate electrode of the upper arm transistor 11U can be switched from the positive voltage EU2 to the negative voltage EU3. Therefore, the upper arm gate drive circuit 30U having this configuration can be used in the first and second embodiments.

FIG. 12 is a circuit diagram illustrating the circuit configuration of the upper arm drive circuit.
As shown in FIG. 12, the upper arm drive circuit 30U is connected to the transistors 41U1, 44U2a, 44U2b, and 41U3 connected to the voltage sources 31U1, 31U2, and 31U3, respectively, and the transistors 41U1, 44U2b, and 41U3 corresponding to the terminals on one side. And the remaining terminals include resistance elements 42U1, 42U2, and 42U3 connected to the gate electrode of the upper arm transistor 11U. The transistors 41U1 and 41U3 are bipolar transistors, and the transistors 44U2a and 44U2b are MISFETs.

  In FIG. 12, when the voltage from the voltage source 31U1 is applied, the transistor 41U1 is turned on, the transistors 44U2a and 44U2b are turned off, and the transistor 41U3 is turned off. When the voltage from the voltage source 31U2 is applied, the transistor 41U1 is turned off, the transistors 44U2a and 44U2b are turned on, and the transistor 41U3 is turned off. When the voltage from the voltage source 31U3 is applied, the transistor 41U1 is turned off, the transistors 44U2a and 44U2b are turned off, and the transistor 41U3 is turned on. In this way, the voltage from the voltage sources 31U1, 31U2, and 31U3 can be applied to the gate electrode of the upper arm transistor 11U by switching the conduction state and the non-conduction state of the transistors 41U1, 44U2a, 44U2b, and 41U3.

In addition, since the transistors 44U2a and 44U2b are provided, current can be cut off in both directions in the current path between the voltage source 31U2 and the upper arm transistor 11U. Therefore, the voltage applied to the gate electrode of the upper arm transistor 11U can be switched from the positive voltage EU2 to the negative voltage EU3, and can be switched from the negative voltage EU3 to the positive voltage EU2. Therefore, the upper arm gate drive circuit 30U having this configuration can be used in all of the first to fourth embodiments.
2. Modified example in which Vt fluctuation in the positive direction is suppressed by applying a plurality of negative voltages In the above-described embodiment, Tm is one negative voltage EU3 per one repetition unit of the conduction state and the non-conduction state of the transistor 11. And ED3 is set to a period sufficient to suppress the fluctuation of Vt. However, the present invention is not limited to this, and Tm is a period in which the variation of Vt can be suppressed by applying the negative voltages EU3 and ED3 a plurality of times, and the period in which the transistor 11 is in the non-conducting state due to repetition of the conductive state and the non-conductive state. Is repeated a plurality of times, the negative voltage EU3, ED3 may be applied at some or all of the plurality of times in the non-conducting period.

  FIG. 13 is a diagram illustrating waveforms of the output current and the gate drive voltage of the power conversion circuit according to the modification of the first embodiment. 13A shows a period switching signal output from the control circuit 21 to the gate drive circuit 30, FIG. 13B shows the waveform of the current I, and FIG. 13C shows the gate drive voltage of the upper arm transistor 11U. FIG. 13D shows the gate drive voltage of the lower arm transistor 11D.

  As shown in FIG. 13 (a), the control circuit 21 outputs a first period signal during the period denoted by reference numeral 1 in FIG. 13 (a), and outputs the first period signal during the period denoted by reference numeral 2 in FIG. 13 (a). 2 period signal is output. The first period signal and the second period signal are signals for switching the voltage applied to the gate electrode of the transistor 11 in the reverse bias non-conduction period. In the first period in the reverse bias non-conduction period, negative voltages EU3 and ED3 are applied to the gate electrode of the transistor 11, and in the second period in the reverse bias period, positive voltages EU2 and ED2 are applied to the gate electrode of the transistor 11. .

  Time T9 is a time corresponding to FIG. 3B, and the upper arm transistor 11U is in the reverse bias non-conduction period and is in the first period. At this time, EU3 is applied to the gate electrode of the upper arm transistor 11U. Time T10 is a time corresponding to FIG. 3D, and the upper arm transistor 11U is in the reverse bias non-conduction period and is in the second period. At this time, EU2 is applied to the gate electrode of the upper arm transistor 11U.

  Time T11 is a time corresponding to FIG. 4B, in which the lower arm transistor 11D is in the reverse bias non-conduction period and is in the first period. At this time, ED3 is applied to the gate electrode of the lower arm transistor 11D. Time T12 is a time corresponding to FIG. 4D, and the lower arm transistor 11D is in the reverse bias non-conduction period and is in the second period. At this time, ED2 is applied to the gate electrode of the lower arm transistor 11D.

FIG. 14 is a flowchart for determining the operation of the control circuit during the non-conduction period according to the modification of the first embodiment.
First, the control circuit 21 samples the signal output from the current detection means 22 (step S201), and determines whether or not the current I is 0 or more based on the sampled signal (step S202).

  When the current I is 0 or more (step S202: Yes), it is determined whether or not the current period is the first period (step S203a). In the first period (step S203a: Yes), the voltage applied to the gate electrode of the upper arm transistor 11U in the non-conduction period is EU3, and the voltage applied to the gate electrode of the lower arm transistor 11D in the non-conduction period is ED2. (Step S204a). When not in the first period (step S203a: No), the voltage applied to the gate electrode of the upper arm transistor 11U in the non-conduction period is EU2, and the voltage applied to the gate electrode of the lower arm transistor 11D in the non-conduction period is ED2. (Step S204b).

  When the current I is less than 0 (step S202: No), it is determined whether or not it is the first period (step S203b). In the first period (step S203b: Yes), the voltage applied to the gate electrode of the upper arm transistor 11U in the non-conduction period is EU2, and the voltage applied to the gate electrode of the lower arm transistor 11D in the non-conduction period is ED3. (Step S204c). When not in the first period (step S203b: No), the voltage applied to the gate electrode of the upper arm transistor 11U in the non-conduction period is EU2, and the voltage applied to the gate electrode of the lower arm transistor 11D in the non-conduction period is ED2. (Step S204d).

The control circuit 21 repeats the above processing at regular intervals (step S205).
Even with this configuration, it is possible to provide the power conversion circuit 1 that suppresses the variation in the threshold voltage Vt of the transistor 11 while suppressing a decrease in the current flowing through the freewheeling diode 12. Further, by limiting the period during which EU3 and ED3, which are negative voltages, are applied to Tm, it is possible to suppress the deterioration of the transistor 11 and provide the power conversion circuit 1 having a longer life.
3. Application Example of Power Conversion Circuit Here, a specific application example of the power conversion circuit described in the above embodiment and the like will be described with reference to FIGS. In all of the application examples shown in FIGS. 15 to 18, switching between the positive voltages EU <b> 2 and ED <b> 2 and the negative voltages EU <b> 3 and ED <b> 3 as described above is performed. The voltage sources 31U and 31D and the gate drive circuit 30 are not shown in the drawings.
3-1. Device with One Power Conversion Circuit FIGS. 15 and 16 are circuit block diagrams of a device with one power conversion circuit according to the first embodiment.
(Step-down circuit)
As shown in FIG. 15, the circuit configuration of the power conversion circuit 1 is a circuit configuration in which an arm composed of an upper arm transistor 11U and a lower arm transistor 11D is provided in one phase, and is a step-down circuit. The step-down circuit 200 includes a power conversion circuit 1, a coil 2 connected to the power conversion circuit 1, a control circuit 21 that controls the power conversion circuit 1, a current detection unit 22 that outputs a signal to the control circuit 21, power A DC power supply 203 connected to the conversion circuit 1 and a capacitor 204 connected to the coil 2 are provided. A load 205 is connected to the capacitor 204 in parallel.

When the upper arm transistor 11U is turned on and the lower arm transistor 11D is turned off, a current I flows through the upper arm transistor 11U to the coil 2. At this time, the current flowing through the power conversion circuit 1 is as shown in FIG. The current I enters the capacitor 204 via the coil 2, and the capacitor 204 is charged.
Next, when the upper arm transistor 11U is in a non-conductive state and the lower arm transistor 11D is in a conductive state, the coil 2 tries to pass the current I in the same direction as immediately before. Therefore, the current I flows from the coil 2 through the lower arm transistor 11D via the capacitor 204 and the load 205, and returns to the coil 2. At this time, the current flowing through the power conversion circuit 1 is as shown in FIG.

Since the current I flows in this manner, in the power conversion circuit 1, it is possible to apply a reverse bias to only one of the freewheeling diodes 12.
(Boost circuit)
As shown in FIG. 16, the power conversion circuit 1 has a circuit configuration in which an arm is provided in one phase, similar to that shown in FIG. 15, and is a booster circuit. The booster circuit 300 includes a DC power supply 303 connected to the power conversion circuit 1 via the coil 2 and a capacitor 304. A load 305 is connected to the capacitor 304 in parallel.

When the lower arm transistor 11D is turned on and the upper arm transistor 11U is turned off, the current I flows from the DC power source 303 through the coil 2 and the lower arm transistor 11D and returns to the DC power source 303. Thereafter, when the lower arm transistor 11D is turned off and the upper arm transistor 11U is turned on, a current I flows from the coil 2 to the upper arm transistor 11U, the capacitor 304, and the load 305, and returns to the DC power source 303. Since the current I flows in this way, the reverse bias can be applied to only one of the free-wheeling diodes 12 in the power conversion circuit 1.
3-2. Device provided with two power conversion circuits FIG. 17 is a circuit block diagram of a device provided with two power conversion circuits of the first embodiment.

  As shown in FIG. 17, the power conversion circuits 1a and 1b have a circuit configuration in which two-phase arms each composed of an upper arm transistor and a lower arm transistor are provided, and are transformer circuits. The transformer circuit 400 includes power conversion circuits 1a and 1b, a control circuit 21 that controls the power conversion circuits 1a and 1b, current detection units 22a and 22b that output signals to the control circuit 21, and power conversion circuits 1a and 1b. The primary side winding 402a and the secondary side winding 402b of the transformer respectively connected, the DC power source 403 connected to the power conversion circuit 1a, the coil 404 connected to the power conversion circuit 1b, and the coil 404 are connected. The capacitor 405 is provided.

  First, in the power conversion circuit 1a, when the upper arm transistor 11U1a and the lower arm transistor 11D2a are in a conductive state and the upper arm transistor 11U2a and the lower arm transistor 11D1a are in a nonconductive state, a current I flows through the upper arm transistor 11U1a and Heading to the secondary winding 402a. When the current of the primary side winding 402a changes, a current is also generated in the secondary side winding 402b by magnetic coupling. At this time, in the power conversion circuit 1b, the upper arm transistor 11U2b and the lower arm transistor 11D1b may be turned on, and the upper arm transistor 11U1b and the lower arm transistor 11D2b may be turned off.

On the other hand, in the power conversion circuit 1a, when the upper arm transistor 11U2a and the lower arm transistor 11D1a are turned on and the upper arm transistor 11U1a and the lower arm transistor 11D2a are turned off, the current I flows through the upper arm transistor 11U2a and becomes the primary side Go to winding 402a. When the current of the primary side winding 402a changes, a current is also generated in the secondary side winding 402b by magnetic coupling. At this time, in the power conversion circuit 1b, the upper arm transistor 11U1b and the lower arm transistor 11D2b may be turned on, and the upper arm transistor 11U2b and the lower arm transistor 11D1b may be turned off.
3-3. Device with 3 power conversion circuits (configuration)
FIG. 18 is a circuit block diagram of a device including three power conversion circuits according to the first embodiment.

As shown in FIG. 18, the circuit configuration of the power conversion circuit 1c is a circuit configuration in which three-phase arms each composed of an upper arm transistor and a lower arm transistor are provided. That is, in the power conversion circuit 1c, the upper arm transistors 11U1, 11U2, and 11U3 and the lower arm transistors 11D1, 11D2, and 11D3 constitute a three-phase inverter circuit. The inverter circuit 500 includes a power conversion circuit 1c, a control circuit 21 that controls the power conversion circuit 1c, current detection units 22a and 22b that output signals to the control circuit 21, and a DC power source 503 connected to the power conversion circuit 1c. And a resistance element 504 and a transistor 505 connected in parallel to the DC power supply 503. A three-phase motor 502 is connected to the power conversion circuit 1c. A series circuit of the resistance element 504 and the transistor 505 is a brake circuit 506 that functions during a regenerative operation. Note that the brake circuit 506 is not necessarily provided. Further, in a regenerative operation to be described later, it is not always necessary to perform control to apply a negative voltage to the gate electrodes of the transistors of the remaining arms during a period in which the transistors of one arm are non-conductive.
(Power running motion)
First, the power running operation of the inverter circuit 500 will be described.

During power running, the transistors 11U1, 11U2, 11U3, 11D1, 11D2, and 11D3 (hereinafter referred to as the transistor 11 when there is no need for distinction) are repeatedly turned on and off to output a three-phase alternating current to the motor 502. Then, the motor 502 is driven. Note that in the reverse bias non-conduction period, as described in Embodiment Mode 1 and the like, a negative voltage is applied to the gate electrode of the transistor.
(Regenerative operation)
First, the brake circuit 506 provided in the inverter circuit 500 will be described. In general, when a regenerative operation of a motor is performed, the inverter circuit outputs an applied voltage smaller than a counter electromotive voltage generated by the rotation of the motor. However, for example, when a DC voltage is generated from an AC voltage using a rectifier circuit such as a diode bridge and a smoothing capacitor, the regenerative energy cannot flow back to the AC voltage. Therefore, if the regenerative energy from the motor is large, the DC voltage on the inverter input side rises and becomes overvoltage, and the inverter circuit and the capacitor (not shown) constituting the DC voltage may be deteriorated. Therefore, in the inverter circuit 500, a brake circuit 506 in which a resistance element and a transistor are connected in series is provided on the DC power supply side. When the DC voltage is higher than a predetermined voltage, the brake circuit transistor is turned on, and a resistance element is connected in parallel to the DC power supply. As a result, energy is consumed by the resistance element, so that the DC voltage decreases.
(Drive voltage control and effects in regenerative operation)
It is preferable to reduce the regenerative energy output to the brake circuit because the cost can be reduced by downsizing and simplification of the brake circuit. Hereinafter, control of the gate drive voltage in the regenerative operation for reducing the regenerative energy output to the brake circuit will be described. This control utilizes the fact that the loss of the power conversion circuit increases by applying a negative voltage to the gate electrode of the transistor 11.

FIG. 19 is a diagram illustrating waveforms of a current flowing through the inverter circuit and a gate drive voltage.
19A shows the waveform of the current flowing through the inverter circuit, FIG. 19B shows the gate drive voltage of the upper arm transistor 11U1, and FIG. 19C shows the gate drive voltage of the lower arm transistor 11D1.
The difference from the first embodiment shown in FIG. 2 is the gate drive voltage of the lower arm transistor 11D1 when the current I is positive and the gate drive voltage of the upper arm transistor 11U1 when the current I is negative.

  In the first embodiment, the current is positive and the upper arm transistor is in a non-conductive state, that is, in T3 in which EU3 is applied to the gate electrode of the upper arm transistor, ED1 is applied to the gate electrode of the arm transistor. However, the regenerative operation in this configuration is different in that the negative voltage ED3 is applied to the gate electrode of the lower arm transistor 11D1 at this timing.

  Similarly, in the first embodiment, the current is negative and the lower arm transistor is non-conductive, that is, the upper arm transistor is made conductive at T7 when ED3 is applied to the gate electrode of the lower arm transistor. Therefore, EU1 is applied to the gate electrode of the upper arm transistor. However, the regenerative operation in this configuration is different in that the negative voltage EU3 is applied to the gate electrode of the upper arm transistor 11U1 at this timing. The same control can be applied to the gate drive voltages of the other transistors 11.

  The above operations are summarized as follows. During the regenerative operation in this configuration, when one transistor 11 of the upper arm transistor and the lower arm transistor is non-conductive, negative voltages EU3 and ED3 are applied to the gate electrode of the other transistor 11. Thereby, the forward voltage drop of the freewheeling diode 12 built in the transistor 11 to which the negative voltage is applied becomes large, and regenerative energy can be consumed. Therefore, it is possible to reduce the size of the brake circuit 506 described above.

  The control of one of the upper arm transistor and the lower arm transistor 11 has been described based on the first embodiment, but may be combined with the second, third, or fourth embodiment. In the present embodiment, an example in which a negative voltage is applied to the other transistor 11 only during the non-conduction period of one transistor 11 of the upper arm transistor and the lower arm transistor has been described, but the present invention is not limited to this. For example, a negative voltage may be applied to the other transistor 11 through a conduction period and a non-conduction period of one of the upper arm transistor and the lower arm transistor.

One aspect of the power conversion circuit disclosed in the present specification is a power conversion circuit including first and second transistors connected in series and a control unit, and the first and second transistors include: Each includes a gate electrode, a first ohmic electrode, and a second ohmic electrode, and each of the first and second transistors can flow current from the first ohmic electrode to the second ohmic electrode. The control unit includes a conduction state in which the first and second transistors can pass a current from one of the first ohmic electrode and the second ohmic electrode to the other; and the second ohmic The first and second transistors so as to repeat a non-conductive state in which no current can flow from the electrode to the first ohmic electrode The first and second transistors are connected to a motor, and the control circuit sets the other transistor in the non-conducting state when one of the first and second transistors is in a non-conducting state during a regenerative operation. The third transistor is turned off by applying the third voltage between the gate electrode and the first ohmic electrode of the other transistor.
4). Power conversion circuit in which transistors are connected in parallel in each arm In the above-described embodiment and the like, a configuration is adopted in which transistors are connected in series for each arm. However, the present invention is not limited to this, and the power conversion circuit may adopt a configuration in which the transistors are connected in parallel in the upper arm and the transistors are connected in parallel in the lower arm.

FIG. 20 is a circuit block diagram of a device including a power conversion circuit according to a modification of the first embodiment.
In the power conversion circuit 1d, the transistors 11U1, 11U2, 11U3, and 11U4 are connected in parallel in the upper arm, and the transistors 11D1, 11D2, 11D3, and 11D4 are connected in parallel in the lower arm. (Hereinafter, when there is no need to distinguish between the switching elements, they are simply referred to as “transistor 11”.) In the configuration in which the same transistors are connected in parallel in each arm, the Vt of each transistor 11 connected in parallel varies. This is especially problematic. For example, when a positive voltage equal to or higher than Vt is simultaneously applied to the gate electrode of the upper arm transistor 11U, if only the upper arm transistor 11U1 has a small Vt, current may concentrate only on the upper arm transistor 11U1. As a result, the upper arm transistor 11U1 may be deteriorated. Therefore, in particular, in a configuration in which transistors are connected in parallel to each other in each arm, it is preferable to suppress variations in Vt.

With this configuration, even if the maximum value of the current flowing through each transistor 11 is small, the current flowing through the coil 2 can be increased. As a result, the power conversion circuit 1d can be used even under conditions of a large voltage and a large current as in the power element.
5. Specific Structure of Transistor In the above embodiment, a MISFET is used as a transistor. However, the present invention is not limited to this, and other transistors, for example, an IGBT (Insulated Gate Bipolar Transistor) can be used. . In the case where an IGBT is used as the transistor, in the above description, the drain electrode (second ohmic electrode) may be read as the collector electrode and the source electrode (first ohmic electrode) as the emitter electrode.

Below, the structure of MISFET and IGBT is demonstrated concretely.
5-1. Structure of SiC-MISFET FIGS. 21 and 22 are cross-sectional views showing the structure of a SiC-MISFET which is an example of a transistor.
As illustrated in FIG. 21A, the transistor 600 has a structure in which a drift layer 620 is provided over a substrate 610. The substrate 610 and the drift layer 620 are of the first conductivity type. A second conductivity type body region 630 is provided on drift layer 620 so as to be in contact with drift layer 620. A source region 640 that is an impurity region of the first conductivity type is provided on the body region 630 so as to be in contact with the body region 630. A source electrode 670 that is a first metal electrode is provided on the source region 640 so as to be in contact with the source region 640. A gate insulating film 650 is provided over the body region 630 and the source region 640. A gate electrode 660 is provided over the gate insulating film 650. A drain electrode 680 which is a second metal electrode is provided on the back surface of the substrate 610. Substrate 610, drift layer 620, body region 630, and source region 640 are made of SiC.

In the transistor 600, when the first conductivity type is n-type and the second conductivity type is p-type, the transistor 600 is an n-channel MISFET. On the other hand, when the first conductivity type is p-type and the second conductivity type is n-type, a p-channel type MISFET is obtained.
In the transistor 600, a body diode is formed by a pn junction between the second conductivity type body region 630 and the first conductivity type drift layer 620. This body diode can be used as the freewheeling diode 12 in FIG.
5-2. Modified Example of SiC-MISFET Structure As shown in FIG. 21B, the transistor 601 may include a second conductivity type contact region 635 on the body region 630 so as to be in contact with the body region 630. Good. At this time, the source electrode 670 is provided in contact with the contact region 635.

22A, the transistor 602 may include a first conductivity type channel layer 645 between the gate insulating film 650, the body region 630, and the source region 640.
Furthermore, as illustrated in FIG. 22B, the transistor 603 may include a first conductivity type channel layer 645 and a second conductivity type contact region 635.

  The transistors 602 and 603 illustrated in FIGS. 22A and 22B can function as diodes capable of flowing current from the source electrode 670 to the drain electrode 680. By adjusting the impurity concentration of the first conductivity type in the channel layer 645, the film thickness of the channel layer 645, and the like, the absolute value of the rising voltage of the diode can be made smaller than the absolute value of the rising voltage of the body diode. . This diode is a diode in which a current flows from the source electrode 670 to the drain electrode 680 through the channel layer 645 (hereinafter referred to as a channel diode). Instead of the body diode, a channel diode may be used as the freewheeling diode.

The rising voltage of the diode is a voltage at which a current starts to flow through the diode when the voltage applied between the drain electrode and the source electrode is increased in the negative direction with reference to the source electrode. In the case of a transistor having a semiconductor region made of SiC, the rising voltage of the body diode at room temperature is about −3V.
5-3. Structure of SiC-IGBT FIGS. 23 and 24 are cross-sectional views showing the structure of a SiC-IGBT which is an example of a transistor.

  As shown in FIG. 23A, the transistor 700 has a structure in which a first conductivity type collector electrode region 715 and a second conductivity type collector electrode region 710 are provided under a first conductivity type drift layer 620. ing. An emitter electrode region 740 that is an impurity region of the first conductivity type is provided on the body region 630 so as to be in contact with the body region 630. An emitter electrode 770 that is a first ohmic electrode is provided on the emitter electrode region 740 so as to be in contact with the emitter electrode region 740. A collector electrode 780 which is a second ohmic electrode is provided below the first conductivity type drift layer 620 so as to be in contact with the first conductivity type collector electrode region 715 and the second conductivity type collector electrode region 710. Other structures are the same as those of the transistor 600 illustrated in FIG.

In the transistor 700, when the first conductivity type is n-type and the second conductivity type is p-type, an n-channel IGBT is obtained. On the other hand, when the first conductivity type is p-type and the second conductivity type is n-type, a p-channel IGBT is obtained.
In addition, since the transistor 700 includes the first conductivity type collector electrode region 715, a body diode constituted by a pn junction between the second conductivity type body region 630 and the first conductivity type drift layer 620 is provided. It can be used as a reflux diode.
5-4. Modified Example of SiC-IGBT Structure As shown in FIG. 23B, the transistor 701 may include a second conductivity type contact region 635 on the body region 630 so as to be in contact with the body region 630. . At this time, the emitter electrode 770 is provided in contact with the contact region 635.

In addition, as illustrated in FIG. 24A, the transistor 702 may include a first conductivity type channel layer 645 between the gate insulating film 650, the body region 630, and the emitter electrode region 740.
Further, as illustrated in FIG. 24B, the transistor 703 may include a contact region 635 and a channel layer 645.

In the transistors 702 and 703 shown in FIGS. 24A and 24B, the transistors 702 and 703 are formed by adjusting the impurity concentration of the first conductivity type in the channel layer 645, the film thickness of the channel layer 645, and the like. It can function as a channel diode in which a current flows from the electrode 770 to the collector electrode 780 through the channel layer 645. Instead of the body diode, a channel diode may be used as the freewheeling diode.
<Modification>
The configuration of the power conversion circuit according to the present invention is not limited to the above embodiment and the like, and various modifications and applications are possible within the scope of the effects of the present invention.

  The power conversion circuit according to the present invention is widely used in, for example, compressor inverter control for air conditioners, inverter control for refrigerators, inverter control for heat pump water heaters, inverter control for industrial servo amplifiers, inverters for electric vehicles and hybrid vehicles, etc. Applicable. Moreover, it is widely applicable to DC-DC converters, such as a solar power conditioner and a switching power supply.

DESCRIPTION OF SYMBOLS 1 Power converter circuit 11, 11U, 11D Transistor 12, 12U, 12D Free-wheeling diode 21 Control circuit 22 Current detection means 30U, 30D Gate drive circuit 31U1, 31U2, 31U3, 31D1, 31D2, 31D3 Voltage source

Claims (11)

First and second transistors connected in series;
A control unit;
A power conversion circuit comprising:
Each of the first and second transistors includes a gate electrode, a first ohmic electrode, and a second ohmic electrode,
Each of the first and second transistors includes a diode capable of flowing a current from the first ohmic electrode to the second ohmic electrode;
The controller is
The first and second transistors are in a conductive state in which a current can flow from one of the first ohmic electrode and the second ohmic electrode to the other, and a current flows from the second ohmic electrode to the first ohmic electrode Controlling the first and second transistors to repeat a non-conductive state that cannot be
When one of the first and second transistors is in the conductive state,
Applying a positive first voltage between the gate electrode of the one transistor and the first ohmic electrode with reference to the first ohmic electrode;
When one of the first and second transistors is in the non-conductive state,
If the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is negative in the conductive state immediately before the one transistor, the first ohmic electrode is connected between the gate electrode and the first ohmic electrode of the transistor. Applying a second voltage which is a positive voltage lower than one voltage or a zero voltage;
If the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is positive in the conductive state immediately before the one transistor, a negative voltage is generated between the gate electrode and the first ohmic electrode of the transistor. Applying a third voltage, which is a voltage,
Power conversion circuit. The controller is
When one of the first and second transistors is in the non-conductive state,
If the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is positive in the conductive state immediately before the one transistor, the transistor is in the non-conductive state during the entire period in which the transistor is non-conductive. Applying the third voltage between the gate electrode and the first ohmic electrode;
The power conversion circuit according to claim 1. The controller is
When one of the first and second transistors is in the non-conductive state,
In the conductive state immediately before the one transistor, if the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is positive, in a part of the period in which the transistor is turned off, Applying the third voltage between the gate electrode and the first ohmic electrode of the transistor;
The power conversion circuit according to claim 1. With the repetition of the conduction state and the non-conduction state of the first and second transistors, a period of making the one transistor non-conduction is repeated a plurality of times,
The controller is
In the conductive state immediately before the one transistor, if the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is positive, out of a plurality of periods in which the transistor is turned off Applying the third voltage between the gate electrode and the first ohmic electrode of the transistor at all times,
The power conversion circuit according to any one of claims 1 to 3. With the repetition of the conduction state and the non-conduction state of the first and second transistors, a period of making the one transistor non-conduction is repeated a plurality of times,
The controller is
In the conductive state immediately before the one transistor, if the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is positive, out of a plurality of periods in which the transistor is turned off Applying the third voltage between the gate electrode and the first ohmic electrode of the transistor at some times;
The power conversion circuit according to any one of claims 1 to 3. The first and second transistors are connected to a motor;
The control circuit, during the regenerative operation,
When one of the first and second transistors is turned off,
The other transistor is made non-conductive by applying the third voltage between the gate electrode and the first ohmic electrode of the other transistor,
The power conversion circuit according to any one of claims 1 to 5. The first and second transistors are composed of a plurality of transistors connected in parallel to each other.
The power conversion circuit according to any one of claims 1 to 6.
The first and second transistors are metal-insulator-semiconductor field effect transistors, the first ohmic electrode is a source electrode, and the second ohmic electrode is a drain electrode.
The power conversion circuit according to any one of claims 1 to 7. The first and second transistors are insulated gate electrode bipolar transistors, the first ohmic electrode is an emitter electrode, and the second ohmic electrode is a collector electrode.
The power conversion circuit according to any one of claims 1 to 7. The first and second transistors have a semiconductor region made of silicon carbide,
The power conversion circuit according to any one of claims 1 to 9. A first diode including a diode connected in series to each other, each including a gate electrode, a first ohmic electrode, and a second ohmic electrode, and capable of flowing a current from the first ohmic electrode to the second ohmic electrode; And a control method for controlling the second transistor,
The first and second transistors are in a conductive state in which a current can flow from one of the first ohmic electrode and the second ohmic electrode to the other, and a current flows from the second ohmic electrode to the first ohmic electrode Applying a voltage between the gate electrode and the first ohmic electrode of the first and second transistors so as to repeat the non-conducting state that cannot be performed,
When one of the first and second transistors is in the conductive state,
When a positive first voltage is applied between the gate electrode and the first ohmic electrode of the one transistor and one of the first and second transistors is brought into the non-conductive state,
If the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is negative in the conductive state immediately before the one transistor, the first ohmic electrode is connected between the gate electrode and the first ohmic electrode of the transistor. Applying a second voltage which is a positive voltage lower than one voltage or a zero voltage;
If the potential of the second ohmic electrode with respect to the first ohmic electrode of the transistor is positive in the conductive state immediately before the one transistor, a negative voltage is generated between the gate electrode and the first ohmic electrode of the transistor. Applying a third voltage, which is a voltage,
Control method.

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