JP2013207203A - Capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitor capable of preventing interlayer peeling.SOLUTION: A capacitor 1 includes: a stack 2 in which a plurality of dielectric layers 6 are stacked; internal electrodes 3 provided between the dielectric layers 6 so as to face to one another via the dielectric layers 6; external electrodes 4 to which the internal electrodes 3 are electrically connected and provided so as to cover end portions of the stack 2; and a solder layer 5 provided outside the external electrodes 4. The solder layer 5 includes a first layer 51 located at the most external electrodes 4 side, a second layer 52 provided so as to partially cover an outer surface of the first layer 51, and a third layer 53 provided on an outer surface of the second layer 52 and an exposed surface that is not covered by the second layer 52 of the outer surface of the first layer 51. The first layer 51, the second layer 52, and the third layer 53 are composed of different metals from one another, and are each composed of single metal.

Description

  The present invention relates to a capacitor.

  In the capacitor of Patent Document 1, a solder layer is provided by plating on the outside of the external electrode. Thus, by providing the solder layer in advance on the external electrode, the capacitor can be mounted on the electrode pad of the external substrate without applying another solder again. This solder layer has a two-layer structure, and the inner first layer is a layer made of Sn and the outer second layer is a layer made of Sn-Pb.

  In recent years, Pb-free solder is mainly used. This Pb-free solder is made of, for example, three or more kinds of metals such as Sn, Ag, and Cu. In order to provide such a solder layer made of three kinds of metals on the outside of the external electrode by plating, for example, it is conceivable to provide a second layer made of Ag—Cu on the outer surface of the first layer made of Sn. .

Japanese Unexamined Patent Publication No. 3-179713

  However, when a plurality of types of metals such as Ag and Cu are formed by plating as one alloy layer, there is a problem that precise control of the ratio of Ag and Cu is difficult. In general, if the type of metal is different, the conditions at the time of plating are also different, so it is difficult to form one alloy layer with an accurate ratio.

  In addition, when an attempt is made to form a solder layer by plating Sn, Ag, and Cu one layer at a time, the contact points of the three types of plating layers do not exist, and the melting point of the solder layer does not exist.

  The capacitor of the present invention includes a laminate in which a plurality of dielectric layers are laminated, an internal electrode provided between the dielectric layers so as to face each other with the dielectric layer interposed therebetween, and the internal electrode is electrically An external electrode provided so as to cover an end of the laminate, and a solder layer provided outside the external electrode, the solder layer being located closest to the external electrode. Of the first layer, the second layer provided to partially cover the outer surface of the first layer, the outer surface of the second layer, and the outer surface of the first layer A third layer provided on an exposed surface not covered with the second layer, and the first layer, the second layer, and the third layer are made of different metals, and Each is made of a single metal.

According to the capacitor of the present invention, the laminated body in which a plurality of dielectric layers are laminated, the internal electrode provided between the dielectric layers so as to face each other through the dielectric layer, and the internal electrode are electrically connected. A first layer located on the outermost electrode side, the outer electrode provided so as to cover the end of the laminate, and a solder layer provided on the outer side of the outer electrode. A second layer provided so as to partially cover the outer surface of the first layer, an outer surface of the second layer, and an exposure that is not covered by the second layer among the outer surfaces of the first layer A third layer provided on the surface,
Since the first layer, the second layer, and the third layer are made of different metals and are each made of a single metal, one plating layer can be formed with only one kind of metal. Therefore, it becomes easy to precisely control the ratio of the plurality of kinds of metals in the solder layer. Further, since there are points where the first layer, the second layer, and the third layer are in contact with each other in the solder layer, the melting point of the solder layer can be formed.

It is a perspective view which shows an example of embodiment of the capacitor | condenser of this invention. It is sectional drawing in the AA of the capacitor | condenser shown in FIG. (A) is an expanded sectional view of the edge part in an example of the capacitor | condenser of this invention, (b) is an end elevation at the time of removing the 3rd layer of the solder layer shown to (a). It is an expanded sectional view which shows the edge part in the other example of the capacitor | condenser of this invention. It is an end elevation at the time of removing the 3rd layer in other examples of the solder layer of the capacitor of the present invention. It is an end elevation at the time of removing the 3rd layer in other examples of the solder layer of the capacitor of the present invention. It is an end elevation at the time of removing the 3rd layer in other examples of the solder layer of the capacitor of the present invention. It is an expanded sectional view which shows the edge part in the other example of the capacitor | condenser of this invention. It is an end view of the other example of the solder layer of the capacitor of the present invention. It is an expanded sectional view which shows the edge part in the other example of the capacitor | condenser of this invention. It is an end view of the other example of the solder layer of the capacitor of the present invention. It is an expanded sectional view which shows the edge part in the other example of the capacitor | condenser of this invention. It is an end view of the other example of the solder layer of the capacitor of the present invention.

  Hereinafter, an example of an embodiment of a capacitor of the present invention will be described in detail with reference to the drawings. A capacitor 1 shown in FIGS. 1 and 2 includes a laminated body 2, an internal electrode 3, an external electrode 4, and a solder layer 5 as a basic configuration.

  The laminate 2 is formed by laminating a plurality of dielectric layers 6. This laminated body 2 is a rectangular parallelepiped dielectric block formed by laminating, for example, 20 to 2000 layers of a plurality of rectangular dielectric layers 6 each having a thickness of, for example, 1 to 5 μm.

Moreover, the dimension of the laminated body 2 makes the length of the long side of the laminated body 2 into 0.4-3.2 mm, for example, and makes the length of the short side of the laminated body 2 into 0.2-1.6 mm, for example. Examples of the material for the dielectric layer 6 include BaTiO ₃ , CaTiO ₃ , SrTiO _{3, and} CaZrO ₃ . As another _example, BaTiO _3, CaTiO 3, and SrTiO ₃ or CaZrO ₃ as a main component, Mn compound, Fe compound, Cr compounds, Co compounds, or may be Ni compound or the like is added .

  As shown in FIGS. 1 and 2, the laminate 2 includes a first main surface 2a (upper surface) and a second main surface (lower surface) 2b that face each other, and a first side surface 2c and a second surface that face each other. Are formed in a substantially rectangular parallelepiped shape having a first end surface 2e and a second end surface 2f facing each other.

  As shown in FIG. 2, the first external electrode 4a and the second external electrode 4b are connected to the first internal electrode 3a and the second internal electrode 3b, respectively. The first external electrode 4 a and the second external electrode 4 b are provided on the surface of the multilayer body 2. In the following description, when the term “external electrode 4” is simply used, it means both the first external electrode 4a and the second external electrode 4b.

  In the example shown in FIG. 2, the first external electrode 4 a and the second external electrode 4 b are provided at the end of the multilayer body 2. The external electrode 4 has a thickness of 5 to 50 μm. The external electrode 4 is electrically connected to an electrode pad on the wiring board and plays a role of ensuring electrical continuity with the wiring board.

  As shown in FIG. 2, the first external electrode 4a is formed on the second end face 2f. As shown in FIG. 1, the end of the first external electrode 4a reaches the first and second main surfaces 2a and 2b and the first and second side surfaces 2c and 2d. As shown in FIG. 2, the first external electrode 4a is electrically connected to each of the plurality of first internal electrodes 3a drawn to the second end face 2f.

  As shown in FIG. 2, the second external electrode 4b is formed on the first end face 2e. As shown in FIG. 1, the end of the second external electrode 4b reaches the first and second main surfaces 2a and 2b and the first and second side surfaces 2c and 2d. As shown in FIG. 2, the second external electrode 4b is electrically connected to each of the plurality of second internal electrodes 3b drawn to the first end face 2e.

  The first internal electrode 3a and the second internal electrode 3b are provided between the dielectric layers 6 so as to face each other with the dielectric layer 6 therebetween. In the following description, the expression “internal electrode 3” simply means both the first internal electrode 3a and the second internal electrode 3b.

  In the example illustrated in FIG. 2, a plurality of first internal electrodes 3 a and a plurality of second internal electrodes 3 b are alternately arranged in the stacked body 2 at intervals in the stacking direction. Thereby, the plurality of first internal electrodes 3a and the plurality of second internal electrodes 3b are insulated from each other.

  As shown in FIG. 2, one end of the plurality of first internal electrodes 3a is drawn out to the second end face 2f and connected to the first external electrode 4a. The first internal electrode 3a does not reach the first and second side surfaces 2c and 2d.

  As shown in FIG. 2, one end of the plurality of second internal electrodes 3b is drawn out to the first end face 2e and connected to the second external electrode 4b. The second internal electrode 3b does not reach the first and second side surfaces 2c and 2d.

  The internal electrode 3 is formed between 20 and 2000 layers between the dielectric layers 6 of the laminate 2. Examples of the material of the internal electrode 3 include metals such as Ni, Cu, Ag, Pd, and Au, or alloys such as an Ag—Pd alloy containing one or more of these metals. All the internal electrodes 3 are preferably formed of the same metal or alloy.

The overall dimensions of the internal electrode 3 are, for example, 0.39 to 3.1 mm in the long side direction of the multilayer body 2 in FIG.
For example, 0.19 to 1.5 mm in the short side direction of the laminate 2. The thickness of the internal electrode 3 is not particularly limited. The thickness of the internal electrode 3 is about 0.3 to 2 μm.

  In the example shown in FIG. 2, the first solder layer 5a and the second solder layer 5b are provided on the external electrode 4 via the solder erosion prevention layers 7a and 7b. In the following description, the simple expression “solder layer 5” means both the first solder layer 5a and the second solder layer 5b.

As long as the solder layer 5 is provided outside the external electrode 4, the solder layer 5 may be provided directly on the external electrode 4 without using the solder erosion preventing layers 7 a and 7 b. However, as in the example shown in FIG. 2, a configuration in which the solder layer 5 is provided on the external electrode 4 via the solder erosion prevention layers 7a and 7b is preferable. With such a configuration, even when the solder layer 5 is melted, the external electrode 4 can be prevented from melting simultaneously. The solder erosion preventing layers 7a and 7b are metal plating films made of a material such as Ni. Its thickness is about 2 to 8 μm.

  In the example shown in FIG. 3, the solder layer 5 b includes a first layer 51, a second layer 52, and a third layer 53.

The first layer 51 is located closest to the external electrode. In the example shown in FIG. 3, the first layer 51 is provided on the outer surface of the solder erosion preventing layer 7b. The thickness of the first layer 51 is 5-60.
It is about μm.

The second layer 52 is provided so as to partially cover the outer surface of the first layer 51. In the example shown in FIG. 3, the second layer 52 is composed of a plurality of partial metal layers 521. In the example shown in FIG. 3, one partial metal layer 521 is provided on one surface of the first layer 51. FIG. 3 (b)
In this example, the partial metal layer 521 has a circular shape, a diameter of about 0.15 to 1 mm, and a thickness of about 0.1 to 50 μm. In addition to the example shown in FIG. 3, the partial metal layer 521 may have an elliptical shape, a rectangular shape, or the like. Further, a plurality of partial metal layers 521 are formed on one surface of the first layer 51.
May be provided.

As a specific method for observing the shape or size of the second layer 52, first, the solder layer 5 provided on the surface of the external electrode 4 of the capacitor 1 is known so that the second layer 52 is exposed. Polishing is performed using a polishing means. As this polishing means, polishing with diamond paste using a polishing machine KEMET-V-300 can be applied. The surface exposed by this polishing treatment is observed with a metal microscope adjusted to a magnification of 100 times to obtain a surface image. The surface image is visually observed or component analysis using SEM is performed, and the second layer 52 What is necessary is just to observe the shape of this, or a magnitude | size. Note that the shape, size, etc. of other examples of the second layer 52 to be described later may be observed by the same means.

The third layer 53 is provided on the outer surface of the second layer 52 and the exposed surface of the outer surface of the first layer 51 that is not covered by the second layer 52. In the example shown in FIG. 3, the third layer 53 is provided so as to completely cover the first layer 51 and the second layer 52. The thickness of the third layer 53 is about 0.1 to 50 μm.

The first layer 51, the second layer 52, and the third layer 53 are made of different metals and are each made of a single metal. The first layer 51 is made of, for example, Sn. The second layer 52 is made of, for example, Ag or Cu
Consists of. The third layer 53 is, for example, Cu when the second layer 52 is Ag, and Ag when the second layer 52 is Cu.

  By mounting the solder layer 5 having the first layer 51, the second layer 52, and the third layer 53 on the external electrode 4 in advance by plating, the external electrode 4 of the capacitor 1 is mounted on an external mounting substrate. When doing so, it is not necessary to apply a separate solder.

  In addition, the first layer 51, the second layer 52, and the third layer 53 are made of different metals and are each made of a single metal, so that one plating layer is formed with only one kind of metal. Can do. Therefore, it becomes easy to precisely control the ratio of the plurality of kinds of metals in the solder layer. Therefore, characteristics such as the melting point, durability reliability, strength and the like of the solder layer 5 are less likely to fluctuate, so that the solder layer 5 can easily function as a good bonding material.

Further, even when three plating layers composed of only one kind are formed as described above, the second layer 52 is configured to partially cover the outer surface of the first layer 51, and the third layer 53 Are provided on the outer surface of the second layer 52 and the exposed surface of the outer surface of the first layer 51 that is not covered by the second layer 52. Therefore, in the solder layer 5, the first layer 51, There will be a point where the second layer 52 and the third layer 53 contact each other, and a melting point of the solder layer can be formed.

  The capacitor 1 having the above configuration is manufactured by a ceramic green sheet lamination method as described below.

  Specifically, a plurality of green sheets to be the dielectric layer 6 are prepared. In this step, the ceramic green sheet is obtained by preparing a slurry-like ceramic slurry by adding and mixing a suitable organic solvent or the like to the ceramic raw material powder and the organic binder, and molding the slurry by a doctor blade method or the like. .

  Next, the internal electrode 3 is formed on the green sheet. In this step, a conductive material to be a pattern of the internal electrode 3 is formed on the obtained ceramic green sheet by screen printing or the like. In addition, the pattern of the several internal electrode 3 is printed on this one green sheet so that many capacitors can be obtained from one green sheet.

  Next, after laminating and pressing a plurality of ceramic green sheets, a raw laminated body in which many pieces are integrated is produced. This laminated body is cut to obtain a raw body of the capacitor 1 as a single laminated body.

  Next, the capacitor body 1 in a raw state is fired to obtain a laminate 2. In this step, for example, the laminate 2 is obtained by firing at 1100 to 1200 ° C. By this step, the green sheet becomes the dielectric layer 6 and the conductive material becomes the internal electrode 3.

  Next, the external electrode 4 is formed by applying a conductive paste to both ends of the laminate 2 and baking it. The external electrode 4 may be formed by a thin film forming method such as vapor deposition, plating, or sputtering.

  The material of the external electrode 4 thus obtained may be a metal material such as silver, nickel, palladium, or an alloy thereof other than copper.

Next, a nickel (Ni) plating layer to be the solder erosion preventing layers 7a and 7b is formed on the surface of the obtained external electrode 4 as necessary. When performing nickel (Ni) plating, for example, a watt bath is used as a plating solution, the temperature is kept at 60 ° C., the current is 0.2 A, and plating may be performed for 60 minutes.

  Next, the first layer 51, the second layer 52, and the third layer 53 are sequentially plated on the surface of the nickel (Ni) plating layer, and as a result, the capacitor 1 is obtained.

As described above, any one of Sn, Ag, and Cu is used for the first layer 51, the second layer 52, and the third layer 53. Here, when Sn is plated, for example, Sn-23 (manufactured by Dupsall) is used as a plating solution, the temperature is kept at 33 ° C., the current is 0.1-1 A, and 60-80
What is necessary is just to perform plating for a minute. Further, when Ag is plated, for example, an aqueous silver cyanide solution is used as a plating solution, the temperature is kept at 40 to 50 ° C., the current is set to 0.05 to 0.1 A, and plating may be performed for 6 to 30 minutes. Further, when Cu is plated, for example, a copper pyrophosphate aqueous solution is used as a plating solution, the temperature is kept at 25 ° C., the current is 0.15 A, and plating may be performed for 6 to 8 minutes.

In order to form the second layer 52 composed of a plurality of partial metal layers 521 as in the example shown in FIG. 3, a mask having an opening in the shape of the partial metal layer 521 is formed on the surface of the first layer 51. Print. Thereafter, a plurality of partial metal layers 521 can be formed by selectively plating the mask openings. Further, the mask is removed before the third layer 53 is plated.

For example, as in the example shown in FIGS. 4 and 5, the second layer 52 is preferably composed of a plurality of metal deposits 522. In this case, since many contact points of the first layer 51, the second layer 52, and the third layer 53 are formed, the solder layer 5 is easily melted. Furthermore, it is preferable that the plurality of metal deposits 522 are evenly dispersed on the first layer 51 as in the example shown in FIG. In this case, since the solder layer 5 starts to melt almost simultaneously as a whole, the melting is accelerated.

In the example shown in FIG. 5, the metal deposit 522 has a circular shape in plan view and has a diameter of about 0.1 to 1 μm. The metal deposit 522 may have an elliptical shape or a rectangular shape in addition to the circular shape. It is preferable that there are 250,000 or more metal deposits 522 in a 1 mm square region on the first layer 51. In this case, many contact points of the first layer 51, the second layer 52, and the third layer 53 are formed. In order to form a plurality of metal deposits 522 in this manner, plating may be stopped before the metal deposits 522 are connected to each other as shown in FIG.

Further, for example, as in the example shown in FIG. 6, the second layer 52 may be composed of a plurality of metal masses 523. Also in this case, since many contact points of the first layer 51, the second layer 52, and the third layer 53 are formed, the solder layer 5 is easily melted. The metal block 523 has a shape in which a plurality of metal deposits 522 shown in FIG. 5 are connected. In the 1 mm square region on the first layer 51, it is preferable that there are 60000 or more metal masses 523. In this case, many contact points of the first layer 51, the second layer 52, and the third layer 53 are formed. In order to form a plurality of metal lumps 523 in this way, plating may be stopped before the second layer 52 is formed as a substantially complete film as shown in FIG.

Further, for example, as in the example shown in FIG. 7, the second layer 52 may be a plating layer having holes 524. The hole 524 penetrates the second layer 52, and the first layer 51 and the third layer 53 are in contact with each other inside the hole 524. The diameter of the holes 524 is about 0.1 to 1 μm, and it is preferable that there are 10,000 or more in the 1 mm square region of the second layer 52. In this case, the first layer 51,
Many contact points of the second layer 52 and the third layer 53 are formed. In order to form the plating layer having the holes 524 in this way, as shown in FIG. 6 described above, after the metal deposits 522 are connected to each other, the plating is continued and stopped before the film is completely formed. That's fine.

  Further, for example, as long as the third layer 53 is provided on the outer surface of the second layer 52 and the exposed surface of the first layer 51, the first layer 51 and The second layer 52 may be partially provided.

  In the example shown in FIGS. 8 and 9, not only the second layer 52 but also the third layer 53 is composed of a plurality of metal deposits 531. In order to achieve such a configuration, the amount of plating may be less than that of the first layer 51 in both the second layer 52 and the third layer 53.

Further, as in the example shown in FIGS. 8 and 9, the area of the metal deposit 531 of the third layer 53 is set to the second layer 52
The area of the metal deposit 522 is preferably larger. In this case, the probability that the third layer 53 contacts the contact point of the first layer 51 and the second layer 52 is increased. In order to achieve such a configuration, for example, Sn may be 99.0 wt% for the first layer 51, Ag may be 0.3 wt% for the second layer 52, and Cu may be 0.7 wt% for the third layer 53. . If such a weight ratio is set, the amount of plating of the third layer 53 is larger than that of the second layer 52 regardless of the film thickness of the solder layer 5, and the area of the metal deposit 531 of the third layer 53 is increased. The area of the metal deposit 522 of the second layer 52 becomes larger.

In addition to the examples shown in FIGS. 8 and 9, the area of the metal deposit 531 of the third layer 53 may be smaller than the area of the metal deposit 522 of the second layer 52. In order to achieve such a configuration, for example,
The first layer 51 may be Sn at 99.0 wt%, the second layer 52 may be Cu at 0.7 wt%, and the third layer 53 may be Ag at 0.3 wt%.

In the example shown in FIGS. 10 and 11, the third layer 53 is composed of a plurality of metal masses 532 in which metal deposits 531 are connected to each other, and the second layer 52 is composed of a plurality of metal attachments. It is composed of a kimono 522. In this case, compared to the configuration shown in FIGS. 8 and 9, there is an area difference between the metal mass 532 that is a part of the third layer 53 and the metal deposit 522 that is a part of the second layer 52. Since it becomes large, the probability that the 3rd layer 53 will contact the contact point of the 1st layer 51 and the 2nd layer 52 becomes high. In order to achieve such a configuration, for example, Sn may be 98.3 wt% for the first layer 51, Cu may be 0.7 wt% for the second layer 52, and Ag may be 1.0 wt% for the third layer 53. . In this case, since the third layer 53 has a larger plating amount than the second layer 52, the metal mass 532 is inevitably easily formed.

The second layer 52 is composed of a plurality of metal masses 523 in which the metal deposits 522 are connected to each other, and the third layer 53 is composed of a plurality of metal deposits 531. Also good. In order to obtain such a configuration, for example, Sn may be 98.3 wt% for the first layer 51, Ag may be 1.0 wt% for the second layer 52, and Cu may be 0.7 wt% for the third layer 53. .

In the example shown in FIGS. 12 and 13, the third layer 53 is a plating layer having pores 533, and the second layer 52 is composed of a plurality of metal deposits 522. In this case, compared with the configuration shown in FIGS. 10 and 11, the area difference between the third layer 53 and the metal deposit 522 which is a part of the second layer 52 becomes larger. The probability of contact with the contact point between the first layer 51 and the second layer 52 increases. In order to obtain such a configuration, for example, Sn may be 96.5 wt% for the first layer 51, Cu may be 0.5 wt% for the second layer 52, and Ag may be 3.0 wt% for the third layer 53. . In this case, the third
Since the amount of plating of the layer 53 is larger than that of the second layer 52, the layer 53 inevitably becomes an almost complete plating layer having pores 533.

The second layer 52 may be a plating layer having pores 524, and the third layer 53 may be composed of a plurality of metal deposits 531. In order to obtain such a configuration, for example, Sn is 96.5 wt% for the first layer 51, Ag is 3.0 wt% for the second layer 52, and Cu is 0.5 wt% for the third layer 53.
And it is sufficient.

  In the above example, only the three-layer structure is disclosed as the solder layer 5, but a fourth layer made of Sn may be provided on the outermost surface. In this case, the Ag layer and the Cu layer can be prevented from being exposed to the outside, so that Ag migration and Cu corrosion can be prevented. When the fourth layer is provided, the number of Sn plating layers is two. Therefore, the solder layer 5 is adjusted to have a desired metal ratio in a state where the two Sn layers are combined. It is necessary.

1: Capacitor 2: Laminate 3: Internal electrode 4: External electrode 5: Solder layer 6: Dielectric layer 7: Solder erosion prevention layer

Claims (1)

A laminate in which a plurality of dielectric layers are laminated;
Internal electrodes provided between the dielectric layers so as to face each other through the dielectric layers;
The internal electrode is electrically connected, and an external electrode provided to cover an end of the laminate;
A solder layer provided on the outside of the external electrode,
The solder layer is
A first layer located closest to the external electrode;
A second layer provided to partially cover the outer surface of the first layer;
An outer surface of the second layer, and a third layer provided on an exposed surface of the outer surface of the first layer that is not covered by the second layer,
The capacitor, wherein the first layer, the second layer, and the third layer are made of different metals and are each made of a single metal.

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