JP2013196721A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of suppressing noise generation when performing error correction encoding for information data and writing it.SOLUTION: An error correction encoding processing is performed for each N bit of information data to be written. The information data to which parity data obtained by the processing is added is temporarily captured into a latch unit as follows, so as to perform synchronous writing to a memory array. That is, while capturing and outputting the parity data, the latch unit captures the information data of N-bits in a time-division manner for each bit group each consisting of the number of bits that is smaller than N-bits, and sequentially outputs it. Then, a write bias voltage corresponding to each bit of the parity data and information data, which are output from the latch unit, is generated and applied to the memory array.

Description

  The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device in which data to which an error correction code is added is written.

  At present, as a read-only storage device, so-called ROM (Read-Only Memory), an EP (Erasable Programmable) ROM that can electrically write data and can be erased by ultraviolet rays, a write shipment type production programmed ROM, An EEPROM (Electrically Erasable & Programmable) ROM that can be electrically erased and rewritten as needed is known. However, in such a ROM capable of rewriting data, erroneous data may be written when the data is written.

  Therefore, even if erroneous data is written, in order to be able to correct the erroneous data at the time of reading, an error correcting code (ECC) called a parity bit is added to the information data to be written. There has been proposed a semiconductor memory device in which a device with a symbol added is written (see, for example, FIG. 1 of Patent Document 1). This semiconductor memory device is provided with a parity bit generation circuit for generating the parity bit based on information data to be written, and an error correction circuit for correcting an error occurring in the read information data. Further, in this semiconductor memory device, in order to form information data to be written with a parity bit added as one code block for writing, a latch (in which these information data and the parity bit are fetched at a synchronized timing ( Buffer).

  Also, in recent years, as such a semiconductor memory device, in order to read a large amount of data at a high speed, a code block length as an access unit for writing or reading becomes long, for example, 128 bits (or 256 bits). It has been commercialized. However, if the code block length that is a unit of one write access becomes long, when the data level for the number of bits of the code block is reversed at the same time when fetching into the latch as described above, the power supply or ground There was a problem that a large current temporarily flowed into the line, and noise was generated due to a sharp voltage drop.

JP 2000-348497 A

  An object of the present invention is to provide a semiconductor memory device capable of suppressing noise generation when information data is error-correction encoded and written.

  A semiconductor memory device according to the present invention is a semiconductor memory device including a memory array in which information data to be written is written by error correction encoding in units of N (N is a positive integer) bits, and the N bits An error encoding latch unit that captures and outputs the information data and outputs the parity data by performing error correction code processing on the N-bit information data output from the error encoding latch unit A correction code circuit, a first write latch unit that captures and outputs the parity data, and outputs the N bits of information data for each bit group each having a number of bits smaller than the N bits. A second write latch unit that sequentially captures and outputs in a time-sharing manner, and the parity data and the second write latch output from the first write latch unit Having a write bias circuit for applying to the memory array and generates a write bias voltage corresponding to the logic level of the bit per each bit of output the information data from.

  The semiconductor memory device according to the present invention is a semiconductor memory device comprising a memory array in which information data to be written is written by error correction encoding in units of N (N is a positive integer) bits. N-bit information data, each of which is obtained by time division for each bit group having a number of bits smaller than the N bits, and is stored in an error encoding latch unit and sequentially output from the error encoding latch unit An error correction code circuit that generates parity data by performing error correction code processing on the output N-bit information data; a write latch unit that captures and stores the parity data; and the write For each bit of the parity data output from the latch unit and the information data output from the error encoding latch unit, a write corresponding to the logical level of the bit And it generates a bias voltage having a write bias circuit for applying to the memory array.

  In the present invention, the information data to be written is added with parity data obtained by performing error correction coding processing every N bits, and is synchronized by temporarily fetching into the latch section as follows. And writing to the memory array. That is, the latch unit captures and outputs the parity data, and N-bit information data is captured in time division for each bit group having a number of bits smaller than N bits and sequentially output. . Then, a write bias voltage corresponding to each bit of the parity data and information data output from the latch unit is generated and applied to the memory array.

  According to such a configuration, the number of bits of one-time data that is taken into the latch unit and simultaneously output is smaller than N bits, which is the bit length of information data that is a unit of one-time write access. As a result, even if the logic levels of the data output from the latch units are reversed all at once, the amount of current that temporarily flows into the power supply or ground line is reduced. Therefore, a steep voltage drop due to a steep increase in the amount of current flowing into the power supply or ground line is less likely to occur, and noise generated with this steep voltage drop is suppressed.

1 is a block diagram showing an internal configuration of a ROM 100 as a semiconductor memory device according to the present invention. 3 is a diagram illustrating an example of an internal configuration of an ECC latch 7. FIG. 2 is a diagram showing an example of an internal configuration of a write latch 8. FIG. 2 is a time chart showing an operation at the time of data writing in the ROM 100 shown in FIG. 2 is a diagram showing a system configuration when data is written to a ROM 100. FIG. It is a block diagram which shows the modification of ROM100. It is a time chart which shows the operation | movement at the time of the data writing in ROM100 shown by FIG.

  The semiconductor memory device according to the present invention includes an error encoding latch unit (7) that captures and outputs N bits of information data, and outputs N bits of information data (LD) output from the error encoding latch unit. ) To perform error correction code processing to generate parity data (DP), a first write latch unit (10) that captures and outputs this parity data, and A second write latch section (8) for sequentially outputting the N-bit information data while fetching and storing it in a time-sharing manner for each bit group having a number of bits smaller than N bits; Write via corresponding to the logical level of each bit of the parity data (WDP) output from the latch latch unit (10) and the information data (WD) output from the second write latch unit (8) Having a write bias circuit (11, 12) to be applied to the memory array (14) to generate a voltage.

  In addition, the semiconductor memory device according to the present invention is an error encoding method in which N bits of information data are time-divisionally captured and stored in units of bits each having a number of bits smaller than N bits. A latch unit (7), an error correction code circuit (9) for performing error correction code processing on the N-bit information data (LD) output from the error encoding latch unit to generate parity data, and For each bit of the parity data (WDP) output from the write latch unit (10) that outputs and stores the parity data, and the information data (LD) output from the error encoding latch unit (7) And a write bias circuit (11, 12) for generating a write bias voltage corresponding to the logic level of the bit and applying it to the memory array (14).

  FIG. 1 is a block diagram showing an internal configuration of a ROM 100 capable of writing data as a semiconductor memory device according to the present invention.

In FIG. 1, the address buffer 1 is supplied via an external terminal PA _{0-22 of the} ROM 100 while a write bias command signal CEB of logic level 1 is supplied from a write control unit 2 (described later). The acquired 23-bit address data AD [0:22] is captured and stored. Then, the address buffer 1 supplies the third bit in the fetched address data AD [0:22] to the write control unit 2 as the address data A [2], and sends the first to third bits to the address data. This is supplied to the latch selector 3 as A [0: 2]. Further, the address buffer 1 uses the 4th to 23rd bits in the address data AD [0:22] as address data A [3:22] as a Y decoder (column decoder) 4 and an X decoder (row decoder) 5. Respectively.

  The latch selector 3 becomes active while the write mode signal PGMB having the logic level 0 indicating the write mode is supplied from the write control unit 2. In this active state, the latch selector 3 selects an 8-bit latch selection signal for selecting one of first to eighth latch groups (described later) of the ECC latch 7 based on the AD [0: 2]. LE [0: 7] is generated and supplied to the ECC latch 7 and the write latch 8. Each bit of the latch selection signal LE [0: 7], that is, LE [0], LE [1], LE [2],..., LE [6], LE [7] has the following correspondence relationship. Each latch group has a logic level indicating whether to activate the latch group.

LE [0]: First latch group LE [1]: Second latch group LE [2]: Third latch group LE [3]: Fourth latch group LE [4]: Fifth latch group LE [5]: Sixth latch group LE [6]: Seventh latch group LE [7]: Eighth latch group

The input buffer 6 takes in 16-bit information data DA [0:15] supplied via the external terminals PD _0-15 while the logic level 1 write bias command signal CEB is supplied. Remember. Then, the input buffer 6 supplies the fetched information data DA [0:15] as information data D [0:15] to the ECC latch 7 and the write latch 8 and also stores the information data D [0:15]. The first to eighth bits D [0: 7] are supplied to the write control unit 2.

  The ECC latch 7 is an error correction code latch provided for error correction coding, and includes, for example, 128 first to 128th latches for storing 128-bit data.

  FIG. 2 is a diagram illustrating an example of the internal configuration of the ECC latch 7.

  The 128 first to 128th latches described above are divided into eight first to eighth latch groups E1 to E8 each of 16 bits as shown in FIG.

First latch group E1: (8n-7) th latch Second latch group E2: (8n-6) th latch Third latch group E3: (8n-5) th latch Fourth latch group E4: (8n -4) 5th latch E5: (8n-3) th latch 6th latch group E6: (8n-2) th latch 7th latch group E7: (8n-1) th latch 8th Latch group E8: (8n) th latch
n: an integer from 1 to 16

  At this time, the first latch group E1 is supplied with the logic mode 0 write mode signal PGMB from the write controller 2, and when the logic level 1 latch selection signal LE [0] is supplied. The 16-bit information data D [0:15] supplied from the input buffer 6 is taken in and stored. Further, the first latch group E1 supplies the fetched information data D [0:15] to the ECC circuit 9 as data LD [0:15]. The second latch group E2 is supplied with the logic level 0 write mode signal PGMB and when the logic level 1 latch selection signal LE [1] is supplied, the information data D [0:15] described above. ] Is stored and stored, and the fetched 16-bit information data D [0:15] is supplied to the ECC circuit 9 as data LD [16:31]. The third latch group E3 is supplied with the logic mode 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [2] is supplied, the information data D [0:15 described above. ] Is stored and stored, and the fetched 16-bit information data D [0:15] is supplied to the ECC circuit 9 as data LD [32:47]. The fourth latch group E4 is supplied with the logic mode 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [3] is supplied, the information data D [0:15 described above. ] Is stored, and the acquired 16-bit information data D [0:15] is supplied to the ECC circuit 9 as data LD [48:63]. The fifth latch group E5 is supplied with the logic level 0 write mode signal PGMB and when the logic level 1 latch selection signal LE [4] is supplied, the information data D [0:15 described above. ] Is stored, and the fetched 16-bit information data D [0:15] is supplied to the ECC circuit 9 as data LD [64:79]. The sixth latch group E6 is supplied with the logic level 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [5] is supplied, the information data D [0:15 described above. ] And stores this, the supplied 16-bit information data D [0:15] is supplied to the ECC circuit 9 as data LD [80:95]. The seventh latch group E7 is supplied with the logic mode 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [6] is supplied, the information data D [0:15 described above. ] Is stored, and the acquired 16-bit information data D [0:15] is supplied to the ECC circuit 9 as data LD [96: 111]. The eighth latch group E8 is supplied with the logic level 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [7] is supplied, the information data D [0:15] described above. ] And stores this, the supplied 16-bit information data D [0:15] is supplied to the ECC circuit 9 as data LD [112: 127].

  That is, the ECC latch 7 is supplied from the input buffer 6 to one latch group E selected by the above-described latch selection signal LE [0: 7] among the first to eighth latch groups E1 to E8. 16-bit information data D [0:15] is taken in and stored and output. Then, the ECC latch 7 supplies the data for a total of 128 bits stored in order in the first to eighth latch groups E1 to E8 to the ECC circuit 9 as data LD [0: 127].

  The ECC circuit 9 is in an active state while the logic level 1 write bias command signal CEB is supplied, and performs error correction coding on the 128-bit data LD [0: 127]. Circuit. The ECC circuit 9 generates 8-bit parity data DP [0: 7] corresponding to the data LD [0: 127] by the error correction encoding process, and supplies this to the write latch 10.

  The write latch 10 becomes active while the write mode signal PGMB of logic level 0 is supplied from the write control unit 2. In this active state, the write latch 10 captures and stores the parity data DP [0: 7] described above in accordance with the logic level 1 parity data latch signal PGMATD supplied from the write control unit 2. Is supplied to the write bias circuit 11 as write parity data WDP [0: 7].

  The write bias circuit 11 supplies 8-bit parity data DP [0: 7] while the write bias application signal PGMDB having a logic level 0 urging application of the write bias is supplied from the write control unit 2. A write bias voltage corresponding to the logical level of each bit is generated and supplied to the multiplexer 13.

  Like the ECC latch 7, the write latch 8 includes 128 first to 128th latches for storing 128-bit data.

  FIG. 3 is a diagram showing an example of the internal configuration of the write latch 8.

  The 128 first to 128th latches described above are divided into eight first to eighth latch groups W1 to W8 each having 16 bits as shown in FIG.

First latch group W1: (8n-7) th latch Second latch group W2: (8n-6) th latch Third latch group W3: (8n-5) th latch Fourth latch group W4: (8n -4) 5th latch group W5: (8n-3) th latch 6th latch group W6: (8n-2) th latch 7th latch group W7: (8n-1) th latch 8th Latch group W8: (8n) th latch
n: an integer from 1 to 16

  At this time, the first latch group W1 is supplied with the logic mode 0 write mode signal PGMB from the write controller 2 and when the logic level 1 latch selection signal LE [0] is supplied. The 16-bit information data D [0:15] supplied from the input buffer 6 is taken in and stored. Further, the first latch group W1 supplies the fetched information data D [0:15] to the write bias circuit 12 as write information data WD [0:15]. The second latch group W2 is supplied with the logic level 0 write mode signal PGMB and when the logic level 1 latch selection signal LE [1] is supplied, the information data D [0:15] described above. ] Is stored, and the acquired 16-bit information data D [0:15] is supplied to the write bias circuit 12 as write information data WD [16:31]. The third latch group W3 is supplied with the logic level 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [2] is supplied, the information data D [0:15 described above. ] Is stored, and the acquired 16-bit information data D [0:15] is supplied to the write bias circuit 12 as write information data WD [32:47]. The fourth latch group W4 is supplied with the logic level 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [3] is supplied, the information data D [0:15 described above. ] Is stored and stored, and the acquired 16-bit information data D [0:15] is supplied to the write bias circuit 12 as write information data WD [48:63]. The fifth latch group W5 is supplied with the logic level 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [4] is supplied, the information data D [0:15 described above. ] Is stored, and the acquired 16-bit information data D [0:15] is supplied to the write bias circuit 12 as write information data WD [64:79]. The sixth latch group W6 is supplied with the logic level 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [5] is supplied, the information data D [0:15 described above. ] Is stored and this 16-bit information data D [0:15] is supplied to the write bias circuit 12 as write information data WD [80:95]. The seventh latch group W7 is supplied with the logic mode 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [6] is supplied, the information data D [0:15 described above. ] Is stored, and the acquired 16-bit information data D [0:15] is supplied to the write bias circuit 12 as write information data WD [96: 111]. The eighth latch group W8 is supplied with the logic level 0 write mode signal PGMB, and when the logic level 1 latch selection signal LE [7] is supplied, the information data D [0:15 described above. ] Is stored, and the acquired 16-bit information data D [0:15] is supplied to the write bias circuit 12 as write information data WD [112: 127].

  That is, the write latch 8 is supplied from the input buffer 6 to one latch group W selected by the latch selection signal LE [0: 7] among the first to eighth latch groups W1 to W8. The obtained 16-bit information data D [0:15] is captured and output while being stored. The write latch 8 supplies the data for a total of 128 bits stored in the first to eighth latch groups W1 to W8 to the write bias circuit 12 as write information data WD [0: 127]. It is.

  The write bias circuit 12 is a 127-bit write information data WD [0: 0] while a write bias application signal PGMDB having a logic level 0 urging application of the write bias is supplied from the write control unit 2. 127], a write bias voltage corresponding to the logic level of each bit is generated and supplied to the multiplexer 13.

  The Y decoder 4 becomes active while the logic level 1 write bias command signal CEB is supplied, and corresponds to the address indicated by the address data A [3:22] supplied from the address latch 1. A bit line selection signal for accessing the bit line is supplied to the multiplexer 13.

  The X decoder 5 is activated while the logic level 1 write bias command signal CEB is supplied, and corresponds to the address indicated by the address data A [3:22] supplied from the address latch 1. Various voltages necessary for reading, writing, and erasing are applied to the word lines of the memory array 14. The X decoder 5 generates a voltage required for writing based on the externally supplied power supply voltage VPP for writing.

  The multiplexer 13 applies the write bias voltage supplied from the write bias circuits 11 and 12 to the bit line of the memory array 14 selected by the bit line selection signal. Further, the multiplexer 13 applies the read bias voltage supplied from the read processing unit 15 to the bit line of the memory array 14 selected by the bit line selection signal, and the current sent to the bit line is read processing unit. 15 is supplied.

  The memory array 14 is configured by arranging a plurality of bit lines and a plurality of word lines so as to cross each other, and arranging a nonvolatile memory cell transistor having a floating gate at each intersection.

  In response to the output enable signal OE supplied via the external terminal P1 of the ROM 100 and the chip enable signal CE supplied via the external terminal P2, the read processing unit 15 first supplies the read bias voltage to the multiplexer 13. While being supplied, the current sent to each bit line of the memory array 15 is individually taken in via the multiplexer 13. Next, on the basis of the value of the current sent to each bit line, the read processing unit 15 performs each bit in the read data comprising 8 words (128 bits) of information data and the accompanying 8-bit parity data. Determine the logic level. Next, the read processing unit 15 performs error detection processing on the read data (136 bits) and corrects the error for the bit in which an error has occurred, thereby generating 128-bit corrected read data. . Then, the read processing unit 15 externally outputs the corrected read data for 16 bits as information data DA [0:15].

  The write control unit 2 includes a write voltage detection circuit 21, a write command detection circuit 22, a control circuit 23, a write bias application control circuit 24, and a parity data latch control circuit 25.

  The write voltage detection circuit 21 detects when the write power supply voltage VPP is applied to the external terminal PV of the ROM 100, and the write voltage that makes a transition from the logic level 1 state to the logic level 0 state is detected. The detection signal VPPHB is supplied to the write command detection circuit 22.

  When the write start signal WS is supplied via the external terminal P1, the control circuit 23 starts to take in the write target data only for a predetermined period T1 as shown in FIG. A write data fetch start signal OEB of logic level 0 to be made is supplied to the write command detection circuit 22. Further, when the write end signal WE is supplied via the external terminal P2, the control circuit 23 responds to the logic that prompts the application of the write bias voltage only during the predetermined period T2 shown in FIG. A level 0 write bias command signal CEB is supplied to the address buffer 1, Y decoder 4, X decoder 5, input buffer 6, ECC circuit 9, and write bias application control circuit 24.

  The write command detection circuit 22 is supplied with a write voltage detection signal VPPHB of a logic level 0 indicating that the write power supply voltage VPP is applied to the external terminal PV, and takes in write data of a logic level 0 When the start signal OEB is supplied, first, it is determined whether or not the information data D [0: 7] supplied from the input buffer 6 indicates a predetermined write command. When it is determined that the information data D [0: 7] indicates a predetermined write command, the write command detection circuit 22 indicates the write mode for a predetermined period T3 as shown in FIG. A logic mode 0 write mode signal PGMB is generated and supplied to the latch selector 3, the ECC latch 7, the write latches 8 and 10, and the write bias application control circuit 24.

  The write bias application control circuit 24 is supplied with a write mode signal PGMB having a logic level 0 indicating a write mode and a write bias command signal CEB having a logic level 0 urging application of a write bias voltage. Then, a logic level 0 write bias application signal PGMDB to which a write bias is to be applied is generated and supplied to the write bias circuits 11 and 12.

  The parity data latch control circuit 25, as shown in FIG. 4, when A [2], which is the third bit of the address data A [0:22], transitions from the logic level 1 state to the logic level 0 state. A pulse-like parity data latch signal PGMATD is generated and supplied to the write latch 10.

  Next, a data write operation to the ROM 100 having the configuration shown in FIG. 1 will be described.

  FIG. 5 is a diagram showing a system configuration when data is written to the ROM 100. As shown in FIG.

As shown in FIG. 5, a write power supply voltage VPP is fixedly supplied to the external terminal PV of the ROM 100, and the external terminals P1, P2, PA _0-22 and PD _0-15 are connected to the ROM writer 200. Has been.

  In the ROM writer 200, information data to be written in the ROM 100 is stored in advance, and data is written into the ROM 100 in the following procedure in accordance with a writing start command from the user.

First, as shown in FIG. 4, the ROM writer 200 writes 3-bit address data AD [0: 2] indicating an initial value “0” (decimal number expression) and 128-bit information data to be written. Address data AD [3:22] indicating the address to be processed in 20 bits is supplied to the external terminal AD [0:22] of the ROM 100. Further, the ROM writer 200 supplies a write start signal WS to start data writing to the ROM 100 while supplying information data D [0: 7] indicating a predetermined write command to the external terminals PD _0-7 of the ROM 100. To the external terminal P1. As a result, the write command detection circuit 22 of the ROM 100 converts the write mode signal PGMB having a logic level 0 as shown in FIG. 4 into the latch selector 3, the ECC latch 7, the write latches 8 and 10, and the write bias application control. Supply to circuit 24.

Next, as shown in FIG. 4, the ROM writer 200 supplies the _0th to 15th bits of the 128-bit information data to be written as information data DA [0:15] to the external terminals PD _0-15 of the ROM 100. To do. At this time, the latch selector 3 selects the first latch group among the first to eighth latch groups according to the address data A [0: 2] indicating the initial value “0”. LE [0] is supplied to the ECC latch 7 and the write latch 8. As a result, the first latch group of the ECC latch 7 fetches and stores the 0th to 15th bits of the 128-bit data as data LD [0:15] as shown in FIG. To supply. At the same time, the first latch group of the write latch 8 fetches and stores the 0th to 15th bits of the 128-bit data as data WD [0:15] as shown in FIG. Is supplied to the bias bias circuit 12.

Next, as shown in FIG. 4, the ROM writer 200 supplies the _16th to 31st bits of the 128-bit data to be written to the external terminal PD _{0-15 of the} ROM 100 as information data DA [0:15]. , 3-bit address data A [0: 2] indicating “1” (decimal number expression) is supplied to the external terminal PA _0-2 of the ROM 100. At this time, the latch selector 3 selects the second latch group among the first to eighth latch groups in accordance with the address data A [0: 2] indicating “1” described above. 1] is supplied to the ECC latch 7 and the write latch 8. As a result, the second latch group of the ECC latch 7 fetches and stores the 16th to 31st bits of the 128-bit data as described above as data LD [16:31], as shown in FIG. This is supplied to the ECC circuit 9. At the same time, the first latch group of the write latch 8 fetches and stores the 16th to 31st bits of the 128-bit data as data WD [16:31] as shown in FIG. Is supplied to the bias bias circuit 12.

Next, as shown in FIG. 4, the ROM writer 200 supplies the _32nd to 47th bits of the 128-bit data to be written to the external terminals PD _{0-15 of the} ROM 100 as information data DA [0:15]. , 3-bit address data A [0: 2] indicating “2” (decimal number expression) is supplied to the external terminal PA _0-2 of the ROM 100. At this time, the latch selector 3 selects the third latch group among the first to eighth latch groups in accordance with the address data A [0: 2] indicating “2” described above. 2] is supplied to the ECC latch 7 and the write latch 8. As a result, the third latch group of the ECC latch 7 fetches and stores the 32nd to 47th bits of the 128-bit data as described above as data LD [32:47] as shown in FIG. This is supplied to the ECC circuit 9. At the same time, the third latch group of the write latch 8 fetches and stores the 32nd to 47th bits of the 128-bit data as data WD [32:47] as shown in FIG. Is supplied to the bias bias circuit 12.

Next, the ROM writer 200 supplies the 48th to 63rd bits of the 128-bit data to be written as the information data DA [0:15] to the external terminal PD _0-15 of the ROM 100 and “3” (10 3-bit address data A [0: 2] indicating a decimal representation is supplied to the external terminal PA _0-2 of the ROM 100. At this time, the latch selector 3 selects the fourth latch group among the first to eighth latch groups in accordance with the address data A [0: 2] indicating “3” described above. 3] is supplied to the ECC latch 7 and the write latch 8. As a result, the fourth latch group of the ECC latch 7 fetches and stores the 48th to 63rd bits of the 128-bit data as described above as data LD [48:63], and supplies this to the ECC circuit 9. . At the same time, the fourth latch group of the write latch 8 fetches and stores the 48th to 63rd bits of the 128-bit data as data WD [48:63], and supplies this to the write bias circuit 12. To do.

Next, the ROM writer 200 supplies the 64th to 79th bits of the 128-bit data to be written as the information data DA [0:15] to the external terminal PD _0-15 of the ROM 100 and “4” (10 3-bit address data A [0: 2] indicating a decimal representation is supplied to the external terminal PA _0-2 of the ROM 100. At this time, the latch selector 3 selects the fifth latch group of the first to eighth latch groups in accordance with the address data A [0: 2] indicating “4” described above. 4] is supplied to the ECC latch 7 and the write latch 8. As a result, the fifth latch group of the ECC latch 7 fetches and stores the 64th to 79th bits of the 128-bit data as described above as the data LD [64:79], and supplies this to the ECC circuit 9. . At the same time, the fifth latch group of the write latch 8 fetches and stores the 64th to 79th bits of the 128-bit data as data WD [64:79], and supplies this to the write bias circuit 12. To do.

Next, the ROM writer 200 supplies the 80th to 95th bits of the 128-bit data to be written as information data DA [0:15] to the external terminal PD _0-15 of the ROM 100, and “5” (10 3-bit address data A [0: 2] indicating a decimal representation is supplied to the external terminal PA _0-2 of the ROM 100. At this time, the latch selector 3 selects the sixth latch group among the first to eighth latch groups in accordance with the address data A [0: 2] indicating “5” described above. 5] is supplied to the ECC latch 7 and the write latch 8. As a result, the sixth latch group of the ECC latch 7 fetches and stores the 80th to 95th bits of the 128-bit data as described above as the data LD [80:95], and supplies this to the ECC circuit 9. . At the same time, the sixth latch group of the write latch 8 fetches and stores the 80th to 95th bits of the 128-bit data as data WD [80:95], and supplies this to the write bias circuit 12. To do.

Next, the ROM writer 200 supplies the 96th to 111th bits of the 128-bit data to be written as the information data DA [0:15] to the external terminal PD _0-15 of the ROM 100 and “6” (10 3-bit address data A [0: 2] indicating a decimal representation is supplied to the external terminal PA _0-2 of the ROM 100. At this time, the latch selector 3 selects the seventh latch group among the first to eighth latch groups in accordance with the address data A [0: 2] indicating “6” described above. 6] is supplied to the ECC latch 7 and the write latch 8. As a result, the seventh latch group of the ECC latch 7 fetches and stores the 96th to 111th bits of the 128-bit data as described above as the data LD [96: 111], and supplies this to the ECC circuit 9. . At the same time, the seventh latch group of the write latch 8 fetches and stores the 96th to 111th bits of the 128-bit data as data WD [96: 111], and supplies this to the write bias circuit 12. To do.

Next, the ROM writer 200 supplies the 112th to 127th bits of the 128-bit data to be written as the information data DA [0:15] to the external terminal PD _0-15 of the ROM 100 and “7” (10 3-bit address data A [0: 2] indicating a decimal representation is supplied to the external terminal PA _0-2 of the ROM 100. At this time, the latch selector 3 selects the eighth latch group among the first to eighth latch groups in accordance with the address data A [0: 2] indicating “7” described above. 7] is supplied to the ECC latch 7 and the write latch 8. As a result, the eighth latch group of the ECC latch 7 fetches and stores the 112th to 127th bits of the 128-bit data as described above as the data LD [112: 127], and supplies this to the ECC circuit 9. . At the same time, the eighth latch group of the write latch 8 fetches and stores the 112th to 127th bits of the 128-bit data as data WD [112: 127], and supplies this to the write bias circuit 12. To do.

  Through a series of operations as described above, 128-bit information data to be written is sequentially fetched into 8 times of 16 bits, and sequentially taken into the ECC latch 7 and the write latch 8 of the ROM 100, and the ECC circuit 9 and the write It is sent to the bias circuit 12. At this time, the ECC circuit 9 performs error correction coding processing on the 128-bit information data finally obtained by the eighth capture, and the 8-bit parity data DP [0: 7] is supplied to the write latch 10.

  Next, the ROM writer 200 switches the value indicated by the address data A [0: 2] from “7” to “0” as shown in FIG. At this time, since the address data A [2] transitions from the logic level 1 state to the 0 state, the parity data latch control circuit 25 outputs the pulse-like parity data latch signal PGMATD shown in FIG. To supply. In response to the parity data latch signal PGMATD, the write latch 10 takes in and stores the parity data DP [0: 7] supplied from the ECC circuit 9 and sends it to the write bias circuit 11.

  Therefore, by a series of processes as described above, 128-bit information data to be written is taken into the write latch 8 and supplied to the write bias circuit 12. Further, 8-bit parity data DP [0: 7] corresponding to the 128-bit information data to be written is taken into the write latch 11 and supplied to the write bias circuit 12.

  Next, the ROM writer 200 supplies a write end signal WE to end data writing to the external terminal P2 of the ROM 100 as shown in FIG. In response to the write end signal WE, the control circuit 23 of the ROM 100 sends a write bias command signal CEB that is in a logic level 0 state for a predetermined period T2 to the write bias application control circuit 24 as shown in FIG. Supply. In response to the logic level 0 write bias command signal CEB, the write bias application control circuit 24 writes a logic level 0 write bias application signal PGMDB to which a write bias is to be applied, as shown in FIG. Supply to bias circuits 11 and 12. In response to the write bias application signal PGMDB having a logic level 0, the write bias circuits 11 and 12 have the bit logic level for each bit of 128-bit information data and 8-bit parity data to be written. Is generated and supplied to the multiplexer 13. As a result, a write bias voltage corresponding to the logic level of each bit is applied to the memory array 14, and the above-described code block of a total of 136 bits consisting of 128-bit information data and 8-bit parity data is applied to the memory array 14. Written. Thereafter, when the write bias command signal CEB transitions from the logic level 0 to 1, all the latches in the ECC latch 7 and the write latches 8 and 10 are reset accordingly.

  As described above, in the ROM 100 shown in FIG. 1, first, 8-bit parity data obtained by error-correcting encoding data data to be written in 128-bit units is converted into the first write latch 8 and 128 bits. Is taken into the second write latch 10. Then, a write bias voltage having a voltage value corresponding to the logical level of each bit of the data (WD, WDP) taken into and output from these write latches by the write bias circuit (11, 12) is stored in the memory array. 14, a total of 136 bits of data (parity data and information data) are written to the memory array at a time.

  Here, when fetching the 128-bit information data (WD), the write latch 8 sequentially writes the 128-bit information data for 16 bits in a time-sharing manner as shown in FIG. The data is sent to the bias circuit 12. Further, when the 8-bit parity data (WDP) is captured, the write latch 10 captures and writes the 8-bit parity data after the 128-bit information data is completely captured by the write latch 8. The data is sent to the bias circuit 11. At this time, the write bias circuit (11, 12) is configured to store the memory at the timing (PGMDB) after the 128-bit information data and 8-bit parity data are all captured by the write latch (8, 10). Application of a write bias voltage to the array 14 is started.

  Therefore, according to the ROM 100 shown in FIG. 1, even if the number of bits of information data as a unit of one write access is as long as 128 bits, a total of 128 bits output from the write latch 8 In the data, the number of bits whose logic levels are simultaneously inverted is 16 at the maximum. In short, the number of bits of one-time data fetched and output by the write latch 8 is smaller than the number of bits of information data that is a unit of one-time write access. As a result, even when the logic levels of the data output from the write latch 8 are reversed all at once, the amount of current that temporarily flows into the power supply or ground line is reduced. Therefore, a steep voltage drop due to a steep increase in the amount of current flowing into the power supply or ground line is less likely to occur, and noise generated with this steep voltage drop is suppressed.

  In the ECC circuit 9, 8-bit parity data is obtained by performing error correction coding on information data to be written in 128-bit units, but the number of bits to be error-corrected coding is 128. It is not limited to bits, and the number of bits of parity data is not limited to 8 bits. In the above-described embodiment, the write latch 8 is configured to capture 128 bits of information data in 16-bit increments 8 times in a time-sharing manner, but the number of capture bits per time is 16 bits. It is not limited.

  In short, the ECC circuit 9 generates M-bit (M is a positive integer) parity data by performing error correction coding on information data in units of N bits (N is a positive integer), and the write latch 8 has N bits. This information data may be sequentially sent to the write bias circuit 12 while being fetched and stored in a time-sharing manner for each bit group having a number of bits smaller than N bits. At this time, the write latch 8 includes a plurality of latch groups each storing the above-described bit group, and the latch selector 3 is a target for fetching the bit group based on the address data. A signal that generates a latch selection signal for selecting one of the latch groups to be used is adopted.

  FIG. 6 is a diagram showing a modification of the ROM 100 shown in FIG. 1, and FIG. 7 is a time chart showing an operation when data is written to the ROM 100 shown in FIG.

  In the configuration shown in FIG. 6, the write latch 8 shown in FIG. 1 is omitted, and the data LD [0: 127] sent from the first to eighth latch groups of the ECC latch 7 is directly written to the write bias circuit. Except for the point supplied to 12, the other configuration is the same as that shown in FIG.

  Further, the system configuration for writing data to the ROM 100 shown in FIG. 6 is the same as the system configuration shown in FIG. 5 as in the case of writing data to the ROM 100 shown in FIG.

That is, when writing the information data, first, the ROM writer 200, as shown in FIG. 7, the 3-bit address data AD [0: 0 which is incremented in order from the initial value “0” (decimal number expression) by “1”. 2] and address data AD [3:22] indicating the address in which the 128-bit data to be written is written in 20 bits are supplied to the external terminal AD [0:22] of the ROM 100. Further, the ROM writer 200 supplies a write start signal WS to start data writing to the ROM 100 while supplying information data D [0: 7] indicating a predetermined write command to the external terminals PD _0-7 of the ROM 100. To the external terminal P1. As a result, the write command detection circuit 22 of the ROM 100 outputs a write mode signal PGMB having a logic level 0 as shown in FIG. 7 to the latch selector 3, the ECC latch 7, the write latch 10, and the write bias application control circuit 24. To supply.

Here, the ROM writer 200 sequentially supplies 128-bit data to be written as 16-bit information data DA [0:15] to the external terminals PD _0-15 of the ROM 100 as shown in FIG. At this time, as shown in FIG. 7, the latch selector 3 sequentially increases the address data AD [0] such as initial values “0”, “1”, “2”,..., “6”, “7”. : 2], the latch selection signal LE [0: 7] for sequentially selecting one of the first to eighth latch groups is supplied to the ECC latch 7. As a result, first, the first latch group of the ECC latch 7 takes in the 0th to 15th bits of the 128-bit data as the data LD [0:15] and writes the ECC circuit 9 and the write as shown in FIG. This is supplied to the bias circuit 12. Next, as shown in FIG. 7, the second latch group of the ECC latch 7 takes in the 16th to 31st bits of the 128-bit data as data LD [16:31], and the ECC circuit 9 and the write bias circuit. 12 is supplied. Next, as shown in FIG. 7, the third latch group of the ECC latch 7 takes in the 32nd to 47th bits of the 128-bit data as data LD [32:47], and the ECC circuit 9 and the write bias circuit. 12 is supplied.

  Similarly, the fourth to eighth latch groups of the ECC latch 7 are the 48th to 63rd bits, the 64th to 79th bits, the 80th to 95th bits, and the 96th to 48th bits of the 128-bit data. The 111th bit and the 112th to 127th bits are sequentially fetched and supplied to the ECC circuit 9 and the write bias circuit 12 as LD [48:63] to LD [112: 127], respectively.

  As described above, in the ROM 100 shown in FIG. 6, the ECC latch 7 serving as an error encoding latch unit captures and stores 128-bit information data in a time-sharing manner for each 16-bit bit group. In turn, it is supplied directly to the write bias circuit 12.

Therefore, even when the configuration shown in FIG. 6 is adopted, as in the case where the configuration shown in FIG. 1 is adopted, the number of bits of information data as a unit of one write access is as long as 128 bits. Even so, the number of bits whose logic levels are simultaneously inverted in the 128-bit data supplied to the write bias circuit 12 is 16 at the maximum. In short, the number of bits of one-time data fetched and output by the ECC latch 7 is smaller than the number of bits of information data as a unit of one-time write access. As a result, even when the logic levels of the data output from the ECC latch 7 are reversed all at once, the amount of current that temporarily flows into the power supply or ground line is reduced. Therefore, a steep voltage drop due to a steep increase in the amount of current flowing into the power supply or ground line is less likely to occur, and noise generated with this steep voltage drop is suppressed. Further, when the configuration shown in FIG. 6 is adopted, the write latch 8 used in the configuration shown in FIG. 1 is not necessary, and the apparatus scale can be reduced accordingly. In the ECC latch 7 as the error encoding latch unit described above, 128-bit information data is fetched by 16 bits in a time-sharing manner, but the number of fetched bits per time is not limited to 16 bits.

  In short, the ECC latch 7 captures and stores information data that is error-correction-coded in units of N bits (N is a positive integer) in a time division manner for each bit group having a number of bits smaller than N bits. On the other hand, it may be sent directly to the write bias circuit 12 sequentially. At this time, as the latch selector 3, one that generates a latch selection signal for selecting one of the latch groups to be fetched from the bit group based on the address data is employed.

7 ECC latch 8, 10 Write latch 9 ECC circuit 11, 12 Write bias circuit 14 Memory array

Claims (6)

A semiconductor memory device including a memory array in which information data to be written is error correction encoded and written in N (N is a positive integer) bits,
An error encoding latch unit that captures and stores the N bits of information data; and
An error correction code circuit that generates parity data by performing error correction code processing on the N-bit information data output from the error encoding latch unit;
A first write latch unit that captures and outputs the parity data;
A second write latch unit for sequentially outputting the N-bit information data while capturing and storing the information data for each bit group having a number of bits smaller than the N bits in a time-sharing manner;
For each bit of the parity data output from the first write latch unit and the information data output from the second write latch unit, a write bias voltage corresponding to the logic level of the bit is generated. And a write bias circuit applied to the memory array.   The second write latch unit sequentially selects a plurality of latch groups each for storing the bit group and one of the latch groups to be fetched from the bit group from each of the latch groups. The semiconductor memory device according to claim 1, further comprising: a latch selector that generates a latch selection signal.   3. The semiconductor memory device according to claim 2, wherein the latch selector generates the latch selection signal based on address data. A semiconductor memory device including a memory array in which information data to be written is error correction encoded and written in N (N is a positive integer) bits,
An error encoding latch unit that sequentially outputs the N-bit information data while capturing and storing the N-bit information data in a time-sharing manner for each bit group having a number of bits smaller than the N bits;
An error correction code circuit that generates parity data by performing error correction code processing on the N-bit information data output from the error encoding latch unit;
A write latch unit that captures and outputs the parity data; and
Generating a write bias voltage corresponding to a logical level of each bit of the parity data output from the write latch unit and the information data output from the error encoding latch unit; And a write bias circuit applied to the semiconductor memory device.   The error encoding latch unit sequentially selects a plurality of latch groups each for storing the bit group and one of the latch groups to be fetched from the bit group from each of the latch groups. The semiconductor memory device according to claim 4, further comprising: a latch selector that generates a selection signal.   6. The semiconductor memory device according to claim 5, wherein the latch selector generates the latch selection signal based on address data.

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