JP2013196186A - Design device for semiconductor integrated circuit, design method of semiconductor integrated circuit, design program for semiconductor integrated circuit, recording medium, and data structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design device for a semiconductor integrated circuit, which can efficiently achieve wiring on a top of a semiconductor integrated circuit including a plurality of hierarchies.SOLUTION: The design device for a semiconductor integrated circuit has a storage section 14 that comprises: upper hierarchy wiring detailed information including the position, width and length of wiring arranged on a top 3; an internal detailed information file 14c including the position, width and length of wiring arranged on a hierarchy block 4a; an arrangement wiring information file 14b including the position of the hierarchy block 4a on the top 3 and the position of a cell 31a arranged on the top 3; and a design program 14a including a metal coverage calculation section for calculating a metal coverage on the top 3 by using the files 14b and 14c.

Description

  The present embodiment relates to a semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method, a semiconductor integrated circuit design program, a recording medium, and a data structure.

  Conventionally, in the design of a semiconductor integrated circuit, a plurality of cells, which are already designed basic circuits such as logic circuits such as AND circuits and OR circuits, flip-flop circuits, memory circuits, etc., are arranged in a predetermined area in the chip. The desired function has been realized by placing and wiring each signal connection. In recent years, with the improvement of semiconductor manufacturing technology, more functions can be mounted on one chip, and the mounting gate scale has increased. Along with this, the importance of cell layout and wiring design is increasing.

  Therefore, as a design method for a large-scale semiconductor integrated circuit, a hierarchical design method in which a cell is arranged and wired for each of a plurality of functional blocks and a layout design is further performed as one semiconductor integrated circuit device has been used. ing. In the conventional wiring design, after the arrangement and wiring of cells of functional blocks (hereinafter referred to as hierarchical blocks) constituting the lower hierarchy are designed, the arrangement and wiring of cells in the upper hierarchy called the top are designed.

  At this time, in an area where wirings are densely arranged, adjacent wirings may stick together in the manufacturing process of the wiring layer, which may cause a short circuit. On the other hand, in an area where the density of wiring is extremely low, there is a risk that the wiring will be thin or local chipping may occur in the manufacturing process of the wiring layer, and disconnection may occur. Therefore, when designing the wiring, the metal coverage is checked so that the wiring density does not become overcrowded or sparse in a specific area. Specifically, an area having a specific size (hereinafter, referred to as a check area) determined by the design rule is set, and the metal coverage ratio arranged in the area is calculated. If the calculated coverage value does not fall within the range from the minimum value to the maximum value set in advance as the specified range, rewiring such as distributing wiring to other areas or installing dummy wiring Is done.

  Conventionally, when designing the top, the upper surface of the hierarchical block is treated as a wiring prohibited area, and detailed information such as wiring in the hierarchical block cannot be known. For this reason, in the check of the metal coverage performed after the top wiring, the check is performed on the assumption that the metal density of the entire region in the hierarchical block is 100% or 0%. Therefore, the metal coverage is calculated with a value different from the actual value at a location where the check area extends between the top and the hierarchical block. For this reason, when checking the coverage of the top metal, even if the coverage is within the specified range, it is calculated in the final check that is finally performed flatly from the top to the hierarchical block. The actual metal coverage will not be within the specified range. In such a case, there is a problem that the rewiring of the top or the dummy wiring has to be performed so that the metal coverage falls within a specified range, resulting in rework of the design.

  Even after the wiring design is completed, the device for identifying the circuit information in the hierarchical block from the top hierarchical drawing cannot obtain detailed information in the hierarchical block at the time of the top design. It is not possible to accurately calculate the metal coverage at the part straddling the line.

JP 2000-187678 A

  Therefore, the present embodiment has been made in view of the above points, and a semiconductor integrated circuit design apparatus capable of efficiently designing a top wiring in designing a semiconductor integrated circuit composed of a plurality of layers. Another object of the present invention is to provide a semiconductor integrated circuit design method, a semiconductor integrated circuit design program, a recording medium, and a data structure.

  The semiconductor integrated circuit design apparatus according to the present embodiment includes, in a semiconductor integrated circuit composed of an upper layer and a lower layer, detailed information on upper layer wiring including the position, width, and length of the wiring arranged in the upper layer. , Detailed information on the lower layer wiring including the position, width, and length of the wiring arranged in the lower layer, the position in the upper layer of the hierarchical block constituting the lower layer, and the cell arranged in the upper layer The wiring in the upper layer occupies the placement and wiring information storage unit storing the position information including the position, the upper layer wiring detailed information, the lower layer wiring detailed information, and the placement position information. And a metal coverage calculation unit for calculating an area ratio.

1 is a diagram illustrating an example of a configuration of a semiconductor integrated circuit design apparatus according to an embodiment. The figure which showed notionally the example of a structure of the semiconductor integrated circuit designed by the semiconductor integrated circuit design apparatus 1 concerning this embodiment. The flowchart explaining a part of wiring procedure of top 3. Schematic explaining an example of a scanning method of the check area 5 in the top 3. The figure explaining the setting position of the check area 5 in the top 3. 7 is a flowchart for explaining a calculation procedure of a metal coverage in the check area 5. The figure explaining the area | region where the check area 5c is arrange | positioned. The figure explaining the internal information acquirable range of the hierarchical block 4a at the time of the top 3 design. The flowchart explaining the calculation procedure of the metal coverage in the hierarchy block 4a area | region contained in the check area 5. FIG.

  Hereinafter, embodiments will be described with reference to the drawings.

  First, the configuration of a semiconductor integrated circuit design apparatus according to the present embodiment will be described with reference to FIG. FIG. 1 is a diagram for explaining an example of the configuration of a semiconductor integrated circuit design apparatus according to this embodiment.

  As shown in FIG. 1, a semiconductor integrated circuit design apparatus 1 according to this embodiment includes a central processing unit (hereinafter referred to as a CPU) 11a that executes various software programs, an apparatus main body 11 including a ROM, a RAM, and the like. A computer such as a personal computer (PC) having an input device 12 such as a keyboard 12a and a mouse 12b, a display device 13, and an external storage device 14 such as a hard disk device (hereinafter simply referred to as storage device 14). is there.

  The storage device 14 stores, as various software programs, a design program 14a for designing the layout and wiring of the cells of the semiconductor integrated circuit. Further, the storage device 14 has more detailed information such as information on cell positions and connections, an arrangement / wiring information file 14b in which information on positions and connections of wiring is stored, and positions of wiring laid in the cells. Various files of an internal detailed information file 14c storing information and a metal merge information file 14d storing general wiring information are stored. The CPU 11 a of the main body device 11 can execute or read a program stored in the storage unit 14.

It should be noted that the information regarding the position and connection of the cell stored in the placement and routing information file 14b corresponds to the placement position information, and the information regarding the position and connection of the wiring similarly stored in the placement and routing information file 14b of the wiring is higher hierarchy. This corresponds to the wiring information laid between the cells in the detailed wiring information. Further, more detailed information such as the position of the wiring laid in the cell stored in the internal detailed information file 14c corresponds to the lower layer wiring detailed information and the upper layer wiring detailed information laid in the cell. Further, the design program 14a includes a metal coverage calculation unit that calculates the metal coverage. (The calculation of the metal coverage will be described in detail later.)
FIG. 2 is a diagram conceptually illustrating an example of the configuration of the semiconductor integrated circuit designed by the semiconductor integrated circuit design apparatus 1 according to the present embodiment. As shown in FIG. 2, the semiconductor integrated circuit designed by the design apparatus 1 is configured by arranging a lower hierarchy 4 and an upper hierarchy (hereinafter referred to as “top”) 3 in a stack.

  The lower hierarchy 4 is composed of one or more hierarchy blocks 4a and 4b, and cells (not shown) are arranged in the hierarchy blocks 4a and 4b, respectively. In addition, necessary wiring is laid inside and between the cells. The top 3 is arranged on the upper surface of the lower hierarchy 4, and one or more cells 31a and 31b are arranged. Necessary wiring is laid between the cells 31a and 31b, inside each cell, and between the cells 31a and 31b and the hierarchical blocks 4a and 4b. Further, an I / O unit 21 serving as an interface with the outside is disposed on the peripheral portion of the top 3, and between the cells 31 a and 31 b and the I / O unit 21 or inside the I / O unit 21. Necessary wiring is laid.

  In the top 3 design (placement of cells 31a and 31b and laying of necessary wiring), the area where the hierarchical blocks 4a and 4b are placed is treated as a wiring prohibited area. Accordingly, the cells 31a and 31b and necessary wirings are arranged and laid in regions other than the upper surfaces of the hierarchical blocks 4a and 4b. In FIG. 2, the flat layer (hereinafter simply referred to as flat) 2 shown on the top surface of the top 3 includes hierarchical cells 4 a, 4 b and all the cells 4 a, 4 b, 31 a, 31 b arranged in the top 3, and All the wirings are projected on the top surface of the top 3.

  A procedure for wiring of a semiconductor integrated circuit designed using the hierarchical design method as illustrated in FIG. 2, particularly, the top 3 wiring will be described below with reference to FIG. FIG. 3 is a flowchart for explaining a part of the top 3 wiring procedure. The flowchart shown in FIG. 3 shows a procedure for checking the metal coverage in a state where the wiring is laid on the top 3 and feeding back the check result to the actual wiring. The metal coverage is an area ratio occupied by wiring in a predetermined region. In this embodiment, a minute evaluation area (hereinafter referred to as a check area 5) is arranged on the top 3 as a predetermined area, and the metal coverage in the check area 5 is calculated.

  In an area where wirings are densely arranged, adjacent wirings may stick together in the manufacturing process of the wiring layer, which may cause a short circuit. On the other hand, in an area where the density of wiring is extremely low, there is a risk that the wiring will be thin or local chipping may occur in the manufacturing process of the wiring layer, and disconnection may occur. Therefore, when designing the wiring, it is necessary to perform a metal coverage check on the entire area where the wiring is laid so that the wiring density does not become overcrowded or sparse in a specific area. When the calculated metal coverage value does not fall within the range from the minimum value to the maximum value determined as the specified range, rewiring such as distributing the wiring to other areas or installing dummy wiring (Check result feedback).

  The check area 5 is set as a minute region having a rectangular shape with a side of 50 μm, for example. By checking the setting area of the check area 5 little by little and repeatedly performing the scan, the metal coverage is checked for all the top 3 areas. An example of a method for scanning the check area 5 will be described with reference to FIG. FIG. 4 is a schematic diagram illustrating an example of a scanning method of the check area 5 in the top 3.

  As shown in FIG. 4, the check area 5 is set at, for example, the lower left corner of the top 3, and the metal coverage is checked. When the check is completed, the check area 5 is moved in the right lateral direction (x direction in FIG. 4). At this time, the moving distance of the check area 5 is set to a distance (for example, 1 μm) shorter than the length (= lc) of one side of the check area 5. By doing so, an overlap area is provided in the immediately preceding check area 5 and the newly set check area 5 ′, so that check omission can be prevented.

  The metal coverage rate check and the movement of the check area 5 are repeated, and when the check area 5 reaches the right end of the top 3, the check area 5 is moved in the vertical direction (y direction in FIG. 4). In this case, the movement distance of the check area 5 is also set to a distance (for example, 1 μm) shorter than the length of one side of the check area 5 as in the horizontal direction.

  When the check of the metal coverage in the check area 5 ″ set by moving in the vertical direction is completed, the check area 5 is moved in the left horizontal direction. The check area 5 is in the upper right corner (or upper left corner) of the top 3. By performing such zigzag scanning until it reaches, all the top 3 areas are checked for metal coverage.

  Note that the size of the check area 5 and the top 3 scanning method (including the moving distance of the check area) are not limited to the above-described values and methods, and are optimal each time depending on the semiconductor integrated circuit to be designed. You can do it in a way.

  Returning to FIG. 3, the top 3 wiring (especially metal coverage check) procedure will be described. It is assumed that the design of the lower hierarchy 4 (cell and wiring arrangement) has been completed prior to the top 3 wiring.

  First, in step S1, a check area 5 for checking the metal coverage is set at a predetermined position on the top 3. Next, it progresses to step S2 and the metal coverage in the check area 5 is calculated. The method for calculating the metal coverage varies depending on the set position of the check area 5. The relationship between the setting position of the check area 5 and the metal coverage calculation method will be described with reference to FIG. FIG. 5 is a diagram for explaining a setting position of the check area 5 in the top 3.

  The top 3 shown in FIG. 5 is the same as the top 3 of the semiconductor integrated circuit shown in FIG. As described with reference to FIG. 2, the hierarchical blocks 4a and 4b are arranged in the lower layer of the top 3, and the cells 31a and 31b are arranged so as not to overlap therewith. The calculation method of the metal coverage is roughly divided into the following three methods depending on the set position of the check area 5.

  The first is a case where the entire area of the check area is arranged so as to overlap the hierarchical blocks 4a and 4b (in the case of the check area 5a in FIG. 5). The second case is a case where the entire area of the check area is arranged so as not to overlap the hierarchical blocks 4a and 4b (in the case of the check area 5b in FIG. 5). The third case is a case where the check area is arranged across the top 3 and the hierarchical blocks 4a and 4b so that a part of the check area overlaps the hierarchical blocks 4a and 4b (in the case of the check area 5c in FIG. 5). .

  Hereinafter, the calculation method of the metal coverage will be described for each case. First, the first case, that is, the case where the entire area of the check area 5a is arranged so as to overlap the hierarchical blocks 4a and 4b will be described. The metal coverage of the hierarchical blocks 4a and 4b has already been checked at the time of wiring design of the lower hierarchy, and the wiring is adjusted so as to be within the range defined as the specified range. Therefore, it is not necessary to check the metal coverage again for the upper part of the hierarchical blocks 4a and 4b. That is, when the entire area of the check area 5a is arranged so as to overlap the hierarchical blocks 4a and 4b, step S2 in FIG. 3 is omitted (skipped).

  Next, a second case, that is, a case where the entire area of the check area 5b is arranged so as not to overlap the hierarchical blocks 4a and 4b will be described. The calculation procedure of the metal coverage in this case will be described using the flowchart of FIG. FIG. 6 is a flowchart for explaining the calculation procedure of the metal coverage in the check area 5.

  First, in step S21, information on the number and length of wirings laid in the area where the check area 5b is set is acquired from the placement and routing information file 14b. The wiring information that can be acquired from the placement and routing information file 14b relates to wiring that connects various cells such as the cells 31a and 31b and primitive cells (IV, NAND, NOR, etc.). Therefore, when the cells 31a and 31b are arranged in the check area 5b, information is separately acquired for the wiring inside the cells 31a and 31b in the following procedure.

In step S22, information about the width of the wiring is acquired from the internal detailed information file 14c. In the subsequent step S23, the total length of the wiring is calculated from the number and length of the wiring acquired in step S21, and the wiring area S _to is calculated by multiplying this by the width of the wiring acquired in step S22. If all of the areas in which the check area 5b is set are included in the top cells 31a and 31b, the process proceeds from step S21 to step S23 to step S24 without performing the above steps.

  If the top 3 cells 31a and 31b are arranged in the area in which the check area 5b is set (Yes in step S24), the process proceeds to step S25, and the top 3 cell 31a existing in the area in which the check area 5b is set. , 31b is acquired from the placement and routing information file 14b. Subsequently, in step S26, information on the number, length, and width of the wires laid in the area included in the check area 5b in the cells 31a and 31b is acquired from the internal detailed information file 14c.

Next, the process proceeds to step S27, where the total length of the wiring is calculated from the number and length of the wiring acquired in step S26, and the wiring width _Sti is also calculated by multiplying this by the width of the wiring acquired in step S27. To do. Then, the area _{S ti} wires calculated in step S27, summing the area _S-to wiring calculated in step S23, to calculate the total area _{S ta} of interconnections included in the check area 5b (step S28) .

If the top 3 cells 31a and 31b are not arranged in the area where the check area 5b is set (No in step S24), the process proceeds from step S25 to step S27 and proceeds to step S28. In this case, in step S28, the wiring area S _to calculated in step S23 becomes the total area S _{ta of the} wirings included in the check area 5b.

Finally, in step S29, the total area _Sta of the wirings included in the check area 5b is divided by the area of the check area 5b to calculate the metal coverage of the check area 5b.

  Finally, a third case, that is, a case where the check area 5c is arranged across the top 3 and the hierarchical blocks 4a and 4b so as to partially overlap the hierarchical blocks 4a and 4b will be described. FIG. 7 is a diagram for explaining an area where the check area 5c is arranged.

  As shown in FIG. 7, the check area 5c includes a part of the hierarchical block 4a and a part of the top 3. Conventionally, the area of the hierarchical block 4a, which is a wiring-prohibited area, is treated as a black box at the time of designing the top 3, and wiring inside the hierarchical block 4a and detailed information cannot be obtained. For this reason, when calculating the metal coverage of the check area 5c, a fixed value such as 0% or 100% is used as the metal coverage of the portion where the hierarchical block 4a is arranged.

  However, as shown in FIG. 7, the metal coverage calculated using the wiring 41 actually laid inside the hierarchical block 4a is different from the fixed value described above. Therefore, when the metal coverage of the check area 5c is calculated with the coverage of the portion fixed at 0%, a value smaller than the value calculated using the actual wiring 41 is calculated. Conversely, when the metal coverage of the check area 5c is calculated with the coverage of the portion fixed at 100%, a value larger than the value calculated using the actual wiring 41 is calculated.

  When the metal coverage is calculated as a value smaller than the actual value and falls below the lower limit of the specified range, the top 3 wiring is performed by adding a dummy wiring in the check area 5c. Even though the actual metal coverage is within the specified range, if a fixed value is used and falls below the specified lower limit, unnecessary dummy wiring is added. Because of this unnecessary dummy wiring, the metal coverage rate check of the flat 2 performed as a final confirmation after the design of the top 3 (the wiring laid on the lower hierarchy 4 and the top 3 is projected onto a plane called the flat 2 is performed. In the metal coverage check), the metal coverage of the area may exceed the specified range. If the specified range is exceeded, the top 3 wiring must be redesigned, resulting in rework of the design.

  Further, when the metal coverage is calculated as a value larger than the actual value and exceeds the upper limit of the specified range, the top 3 rewiring is performed such as moving the wiring from the check area 5c to another area. Even though the actual metal coverage is within the specified range, if a fixed value is used and the specified lower limit is exceeded, the wiring that should originally be in that area will be moved to another area. Become. Due to this unnecessary rewiring, there is a possibility that the metal coverage of the area falls below the specified range in the metal coverage check of the flat 2 performed as a final confirmation after the top 3 is designed. If it falls below the specified range, the top 3 wiring must be redesigned in the same manner as described above, resulting in rework of the design.

  In order to efficiently perform the design without such rework, the semiconductor integrated circuit design apparatus of the present embodiment can acquire the wiring information of the hierarchical block 4a included in the arrangement area of the check area 5c, The metal coverage of the area is calculated using the wiring 41 actually laid in the hierarchical block 4a.

  That is, as shown in FIG. 8, in the semiconductor integrated circuit design apparatus of this embodiment, when checking the metal coverage of the top 3, a part of the check area 5 of the hierarchical block 4a may be arranged. For the area 43, detailed information such as the position, number, and length of the wiring can be acquired from the internal detailed information file 14c. FIG. 8 is a diagram for explaining the internal information obtainable range of the hierarchical block 4a when the top 3 is designed.

  The area where the check area 5 is set at the time of designing the top 3 is an area extending inward by the length (= lc) of one side of the check area 5 from the outer peripheral portion of the hierarchical block 4a, that is, the outermost boundary. Only the ring-shaped region 43, which is a region between the peripheral portions. Therefore, the area 42 inside is not required to have information on the wiring, and is therefore an area in which information cannot be acquired (so-called black box area) as in the prior art. In this way, by limiting the area 43 where wiring-related information can be obtained at the time of designing the top 3 to a necessary area of a part of the hierarchical block 4a, only the minimum necessary information amount is retained and the information amount is minimized. It can be suppressed to the limit.

  FIG. 6 and FIG. 9 are flowcharts for calculating the metal coverage when the check area 5c is arranged across the top 3 and the hierarchical blocks 4a and 4b so that a part of the check area 5c overlaps the hierarchical blocks 4a and 4b. Will be described. FIG. 9 is a flowchart for explaining a metal coverage calculation procedure in the hierarchical block 4 area included in the check area 5.

  First, in step S31 of FIG. 9, the position information of the hierarchical block 4a existing in the area where the check area 5c is set is acquired from the placement and routing information file 14b. Subsequently, in step S32, information on the number, length, and width of wirings laid in the area included in the check area 5b in the hierarchical block 4a is acquired from the internal detailed information file 14c.

Next, the process proceeds to step S33, where the total length of the wiring is calculated from the number and length of the wiring acquired in step S32, and the wiring area S _bi is calculated by multiplying the same by the width of the wiring acquired in step S32. To do.

Subsequently, steps S21 to S29 in the flowchart of FIG. 6 are executed. The procedure from step S21 to step S29 is the same as in the second case described above (when the entire area of the check area 5b is arranged so as not to overlap the hierarchical blocks 4a and 4b). Omitted. In step S28, the wiring area S _bi calculated in step S33, the wiring area S _ti calculated in step S27, and the wiring area S _to calculated in step S23 are added together in the check area 5c. The total area _Sta of the included wiring is calculated.

  As described above, when the calculation of the metal coverage (step S2 in the flowchart of FIG. 3) according to the installation position of the check area 5 is completed, the process proceeds to step S3, where the specified range in which the upper limit and the lower limit are set in advance is determined. The calculated metal coverage is compared (metal coverage check). Usually, the prescribed range of the metal coverage is set in the design rule, and a value such as 20% or more and 80% or less is set.

  Subsequently, in step S4, the check result in step S3 is output. The result may be sequentially output and displayed on the display device 13, or may be written to a file or the like and displayed as necessary. In addition, the result may be output for each check area 5 or the results of all the check areas 5 set in the top 3 may be output collectively.

  When the metal coverage check has been completed for all the top 3 regions (step S5, Yes), the flowchart shown in FIG. 3 is terminated. In addition, when the area | region where the metal coverage is not checked remains in the top 3 (step S5, No), the check area 5 is moved and reset, and the procedure of step S1 to step S4 is performed.

  After finishing the flowchart shown in FIG. 3, based on the result of checking the metal coverage obtained in step S1 to step S5, add dummy wiring to the laid wiring or move the wiring, Rewiring is performed so that the metal coverage falls within the specified range in all regions of the top 3, and the wiring design of the top 3 is completed.

  As described above, according to the present embodiment, in the wiring design of the semiconductor integrated circuit, when the design is performed using the hierarchical design method, the layer which is the lower layer 4 is checked when the metal coverage is checked after the top 3 wiring. Detailed information on the wirings laid in the outer peripheral area of the blocks 4a and 4b (area where the check area 5 may be set) can be acquired.

  Therefore, even when the setting area of the check area 5 includes the hierarchical blocks 4a and 4b, the metal coverage can be calculated using the detailed information of the wiring actually laid in the area, and the correct value is obtained. Can be calculated. If the rewiring is performed based on the correct metal coverage based on the actual wiring and the metal coverage of all areas of the top 3 is within the specified range, the flat 2 performed as the final check after the top 3 design is completed. Since the metal coverage check (detailed information of all wirings obtained from the metal merge information file 14d and the metal coverage check calculated using this) is also within the specified range, it is necessary to redesign the top 3 wiring design. The design time can be shortened and the design can be improved.

  In the above-described embodiment, various types of information necessary for calculating the metal coverage are stored in the placement and routing information file 14b and the internal detailed information file 14c so that they can be referred to. For example, information on the width of the wiring may be stored in the placement and routing information file 14b instead of the internal detailed information file 14c. Further, the number of files for storing information is not limited to two, and the information may be stored in one file or divided into three or more files.

  Further, as a modification of the present embodiment, it can be applied to a physical library such as a hardware macro or IP (Intellectual Property). For example, in a hardened megacell used as partial circuit information for constituting a part of an LSI chip, the details of the peripheral area of the layer (area corresponding to the area 43 in FIG. 8) for each layer constituting the hardware chip. The physical information (detailed wiring information and adjacent capacity detailed information described above) is made available for reference as data and provided together with the hardware megacell. When laying out hardened megacells on an LSI chip, designing with reference to the physical information can prevent a metal coverage error or the like in the entire LSI chip, leading to an improvement in yield.

  Although several embodiments of the present invention have been described, these embodiments are illustrated by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit design device, 11 ... Device main body, 11a ... CPU, 12 ... Input device, 12a ... Keyboard, 12b ... Mouse, 13 ... Display device, 14 ... Storage device, 14a ... Design program, 14b ... Placement wiring Information file, 14c ... internal detailed information file, 14d ... metal merge information file,

Claims (7)

In a semiconductor integrated circuit composed of an upper layer and a lower layer, detailed information on the upper layer wiring including the position, width, and length of the wiring arranged in the upper layer, and the position of the wiring arranged in the lower layer, The lower layer wiring detailed information including the width and the length, and the position information including the position of the hierarchical block constituting the lower layer in the upper layer and the position of the cell arranged in the upper layer are stored. A placement and routing information storage unit;
A check area that is a minute area compared to the area of the upper hierarchy is set, and the wiring in the check area is based on the upper hierarchy wiring detailed information, the lower hierarchy wiring detailed information, and the arrangement position information. A metal coverage calculation unit for calculating the area ratio occupied by
And the placement and routing information storage unit includes the lower layer in the ring-shaped peripheral region, which is a region from the outermost periphery of the hierarchical block to the inner periphery at a position extending inward by a predetermined length. Wiring detailed information is stored, and the predetermined length is longer than at least the shortest side among the sides constituting the check area. In a semiconductor integrated circuit composed of an upper layer and a lower layer, detailed information on the upper layer wiring including the position, width, and length of the wiring arranged in the upper layer, and the position of the wiring arranged in the lower layer, The lower layer wiring detailed information including the width and the length, and the position information including the position of the hierarchical block constituting the lower layer in the upper layer and the position of the cell arranged in the upper layer are stored. A placement and routing information storage unit;
A metal coverage ratio calculating unit that calculates an area ratio occupied by the wiring in the upper layer based on the upper layer wiring detailed information, the lower layer wiring detailed information, and the placement position information;
An apparatus for designing a semiconductor integrated circuit, comprising:   The metal coverage calculation unit sets a check area that is a minute area compared to the area of the upper layer, and calculates an area ratio occupied by the wiring in the check area. The semiconductor integrated circuit design apparatus described in 1. In the wiring design of the upper hierarchy of the semiconductor integrated circuit composed of the upper hierarchy and the lower hierarchy, a check area that is a minute area compared to the area of the upper hierarchy is set in the upper hierarchy,
Included in the check area by using placement position information including the position of the cell placed in the upper layer and upper layer wiring detailed information including the position, width, and length of the wiring placed in the upper layer Calculate the area of the wiring arranged in the upper hierarchy,
Using the arrangement position information including the position of the hierarchical block constituting the lower hierarchy in the upper hierarchy, and the lower hierarchy wiring detailed information including the position, width, and length of the wiring arranged in the lower hierarchy, Calculate the area of the wiring arranged in the hierarchical block included in the check area,
A method for designing a semiconductor integrated circuit, comprising: adding an area of wiring arranged in the upper hierarchy and an area of wiring arranged in the hierarchical block to calculate a ratio of the area of the check region. In the wiring design of the upper hierarchy of the semiconductor integrated circuit composed of the upper hierarchy and the lower hierarchy, a check area that is a minute area compared to the area of the upper hierarchy is set in the upper hierarchy,
Included in the check area by using placement position information including the position of the cell placed in the upper layer and upper layer wiring detailed information including the position, width, and length of the wiring placed in the upper layer Calculate the area of the wiring arranged in the upper hierarchy,
Using the arrangement position information including the position of the hierarchical block constituting the lower hierarchy in the upper hierarchy, and the lower hierarchy wiring detailed information including the position, width, and length of the wiring arranged in the lower hierarchy, Calculate the area of the wiring arranged in the hierarchical block included in the check area,
A process for calculating the ratio of the area of the wiring arranged in the upper layer and the area of the wiring arranged in the hierarchical block to calculate the ratio of the area in the check region is executed by a computer. Circuit design program. In a semiconductor integrated circuit composed of an upper layer and a lower layer, upper layer wiring detailed information including the position, width, and length of the wiring arranged in the upper layer;
Detailed information on lower layer wiring including the position, width and length of the wiring arranged in the lower layer,
Arrangement position information including the position of the hierarchical block constituting the lower hierarchy in the upper hierarchy, and the position of the cell arranged in the upper hierarchy;
A check area, which is a small area compared to the area of the upper hierarchy, is set in the upper hierarchy, and is arranged in the upper hierarchy included in the check area using the placement position information and the upper hierarchy wiring detailed information. And calculating the area of the wiring arranged in the hierarchical block included in the check region using the placement position information and the lower hierarchical wiring detailed information, and arranging the wiring in the upper hierarchy. A program for causing a computer to execute a process of calculating the ratio of the area of the check region to the area of the check region,
Is a recording medium on which is stored. A data structure of a semiconductor integrated circuit composed of an upper layer and a lower layer,
Detailed data on the upper layer wiring including the position, width and length of the wiring arranged in the upper layer, the position in the upper layer of the hierarchical block constituting the lower layer, and the position of the cell arranged in the upper layer And the position of the wiring, the width of the wiring arranged in the ring-shaped peripheral region, which is the region between the outermost periphery of the hierarchical block and the inner periphery at a position extending inward by a predetermined length, Data structure of a semiconductor integrated circuit, characterized in that the predetermined length is longer than at least the shortest side among the sides constituting the check area. .

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