JP2013196011A - Clock switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock switching circuit by which an increase of a circuit scale with an increase of input clock signals can be suppressed.SOLUTION: A clock switching circuit 1 has: a synchronization circuit 10 which synchronizes a selection signal SEL based on an output clock signal CLKOUT; a detection circuit 20 which generates a mask start signal MS when a change of a signal level of a selection signal SELa after synchronization is detected; and a release circuit 60 which generates a mask release signal MR when transition of an input clock signal selected by the selection signal SELa to an H level is detected. Further, the clock switching circuit 1 has: a mask signal generation circuit 30 which generates a mask signal MASK based on the mask start signal MS and the mask release signal MR; and a clock selection circuit 40 which outputs input clock signals CLK1,CLK2 or a signal fixed to a predetermined level as the output clock signal CLKOUT based on the selection signal SELa and the mask signal MASK.

Description

  The present invention relates to a clock switching circuit.

  In recent years, the frequency of a clock signal is dynamically switched in order to reduce power consumption of an LSI (Large Scale Integration). As a result, when high-speed operation is not necessary, for example, during standby, power consumption can be reduced by operating with a low-frequency clock signal. For example, in an LSI incorporating a PLL (Phase Locked Loop), an output clock signal of the PLL and another clock signal having a frequency and a phase different from that of the output clock signal are dynamically switched.

  However, when one clock signal is selected from a plurality of asynchronous clock signals having different operating frequencies by a simple selector, a pulse having a narrow width called a hazard or a whisker may be generated in the clock signal output from the selector. If a hazard exists in the clock signal, a circuit that operates with the clock signal may malfunction.

  Therefore, a clock switching circuit that suppresses the occurrence of a hazard at the time of clock switching has been proposed (for example, see Patent Documents 1 and 2). FIG. 16 shows an example of a conventional clock switching circuit 100.

  In the clock switching circuit 100, two input clock signals CLKA and CLKB that are asynchronous with each other are switched according to the selection signal SELA, and the input clock signal selected according to the selection signal SELA is output as the output clock signal CLKOUT. . The selection signal SELA in this example is set to L level when the input clock signal CLKA is selected, and to H level when the input clock signal CLKB is selected.

  The clock switching circuit 100 inhibits the output of the input clock signal CLKA when the input clock signal CLKA is not selected, and the first circuit 110 prohibits the output of the input clock signal CLKB when the input clock signal CLKB is not selected. 2 circuit 120. The clock switching circuit 100 includes an AND circuit 130 that receives the clock signal CKA from the first circuit 110 and the clock signal CKB from the second circuit 120 and outputs an output clock signal CLKOUT.

  The first circuit 110 includes two-stage D-flip flop circuits (D-FF) 111 and 112, inverter circuits 113 and 114, and OR circuits 115 and 116. The D-FF 111 holds a signal obtained by inverting the selection signal SELA by the inverter circuit 101 in response to the rising edge of the input clock signal CLKA. The D-FF 112 holds the output signal of the D-FF 111 in response to the rising edge of the input clock signal CLKA. The OR circuit 115 is a mask signal having a result obtained by performing an OR operation on a signal obtained by logically inverting the output signal of the D-FF 111 by the inverter circuit 113 and a signal obtained by logically inverting the output signal of the D-FF 112 by the inverter circuit 114. Output MASKA. The OR circuit 116 outputs a clock signal CKA having a result obtained by performing an OR operation on the input clock signal CLKA and the mask signal MASKA. In such a first circuit 110, the input clock signal CLKA is fixed to the H level and masked in the OR circuit 116 by the H level mask signal MASKA output from the OR circuit 115.

  The second circuit 120 includes two stages of D-FFs 121 and 122, inverter circuits 123 and 124, and OR circuits 125 and 126. The D-FF 121 holds the selection signal SELA in response to the rising edge of the input clock signal CLKB. The D-FF 122 holds the output signal of the D-FF 121 in response to the rising edge of the input clock signal CLKB. The OR circuit 125 outputs a mask signal MASKB having a result obtained by performing an OR operation on a signal obtained by inverting the output signal of the D-FF 121 by the inverter circuit 123 and a signal obtained by inverting the output signal of the D-FF 122. The OR circuit 126 outputs a clock signal CKB having a result obtained by performing an OR operation on the input clock signal CLKB and the mask signal MASK. In such a second circuit 120, the input clock signal CLKB is fixed to the H level and masked in the OR circuit 126 by the H level mask signal MASKB output from the OR circuit 125.

  As described above, in each of the circuits 110 and 120, the rising timings of the mask signals MASKA and MASKB are determined based on the signal output timings of the first-stage D-FFs 111 and 121, and the signals of the second-stage D-FFs 112 and 122 are determined. The rising timing of the mask signals MASKA and MASKB is determined based on the output timing. For this reason, when the input clock signals CLKA and CLKB are switched, a period in which both the mask signals MASKA and MASKB are at the H level occurs. Therefore, when the input clock signals CLKA and CLKB are switched, it is suppressed that the two input clock signals CLKA and CLKB are output in competition with each other, so that occurrence of a hazard can be suppressed.

Japanese Patent Laid-Open No. 06-268492 JP 2005-191877 A

  However, in the clock switching circuit 100, when the number of clock signals to be selected increases, the number of circuits corresponding to the circuit 110 increases by the number of the increased clock signals. For this reason, the clock switching circuit 100 has a problem that the circuit scale significantly increases as the number of input clock signals to be selected increases.

According to an aspect of the present invention, there is provided a clock switching circuit that selects any one input clock signal from a plurality of input clock signals according to a selection signal and outputs the selected input clock signal as an output clock signal. Based on the output clock signal, a detection circuit that generates a mask start signal when a change in the signal level of the selection signal after synchronization is detected, and the mask start signal, A mask signal generation circuit for generating a mask signal for masking the plurality of input clock signals at a predetermined level, and the selection signal selected from the plurality of input clock signals based on the synchronized selection signal and the mask signal A clock selection circuit for outputting one input clock signal or a signal fixed at the predetermined level as the output clock signal; and the synchronization Anda release circuit for generating a mask release signal when it detects a transition to the predetermined level of the input clock signal selected by the selection signal,
The mask signal generation circuit stops generating the mask signal based on the mask release signal.

  According to one aspect of the present invention, it is possible to suppress an increase in circuit scale accompanying an increase in an input clock signal to be selected while suppressing occurrence of a hazard at the time of clock switching.

The block diagram which shows the clock switching circuit of 1st Embodiment. A circuit diagram showing a clock switching circuit of a 1st embodiment. 3 is a timing chart illustrating the operation of the clock switching circuit according to the first embodiment. The circuit diagram which shows the clock switching circuit of a modification. The circuit diagram which shows the clock switching circuit of a modification. The circuit diagram which shows the clock switching circuit of a modification. The circuit diagram which shows the clock switching circuit of a modification. The circuit diagram which shows the clock switching circuit of a modification. The timing chart which shows the operation | movement of the clock switching circuit of a modification. The circuit diagram which shows the clock switching circuit of a modification. The timing chart which shows the operation | movement of the clock switching circuit of a modification. The circuit diagram which shows the clock switching circuit of a modification. The circuit diagram which shows the clock switching circuit of a modification. The circuit diagram which shows the clock switching circuit of 2nd Embodiment. The timing chart which shows the operation | movement of the clock switching circuit of 2nd Embodiment. The circuit diagram which shows the conventional clock switching circuit.

(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS.
In the clock switching circuit 1 shown in FIG. 1, two input clock signals CLK1 and CLK2 that are asynchronous with each other and have different frequencies are switched according to the selection signal SEL, and the input clock signal selected according to the selection signal SEL is changed. Output as an output clock signal CLKOUT. The selection signal SEL of the present embodiment is an asynchronous signal with respect to the input clock signals CLK1 and CLK2, and becomes a logic L level when the input clock signal CLK1 is selected, and becomes a logic H level when the input clock signal CLK2 is selected.

The clock switching circuit 1 includes a synchronization circuit 10, a detection circuit 20, a mask signal generation circuit 30, a clock selection circuit 40, and a release circuit 60.
The selection signal SEL, the output clock signal CLKOUT, and the initialization signal IS are input to the synchronization circuit 10. The synchronization circuit 10 synchronizes the selection signal SEL based on the output clock signal CLKOUT, and outputs the synchronized selection signal SELa to the detection circuit 20 and the clock selection circuit 40. When the synchronization circuit 10 is initialized (reset) by the initialization signal IS, it outputs an L level selection signal SELa.

  The detection circuit 20 generates the mask start signal MS when detecting a change in the signal level of the selection signal SELa (that is, a change from the H level to the L level and a change from the L level to the H level). The mask start signal MS is a signal for instructing generation start of a mask signal MASK for masking the output clock signal CLKOUT, specifically, for masking the plurality of input clock signals CLK1 and CLK2 at a predetermined level (here, H level). It is.

  The mask signal generation circuit 30 receives the mask start signal MS, the mask release signal MR from the release circuit 60, and the initialization signal IS. The mask signal generation circuit 30 generates a mask signal MASK based on the mask start signal MS, and stops generating the mask signal MASK based on the mask release signal MR. Note that the mask signal generation circuit 30 outputs an L level mask signal MASK when initialized by the initialization signal IS. The mask signal MASK is supplied to the clock selection circuit 40.

  A plurality of input clock signals CLK1, CLK2, a selection signal SELa, and a mask signal MASK are input to the clock selection circuit 40. Based on the selection signal SELa and the mask signal MASK, the clock selection circuit 40 outputs the input clock signals CLK1, CLK2 or a signal fixed at a predetermined level as the output clock signal CLKOUT. Specifically, the clock selection circuit 40 selects one input clock signal from the input clock signals CLK1 and CLK2 according to the selection signal SELa, and generates the selected signal as the selected clock signal SCLK. Further, the clock selection circuit 40 masks the selected clock signal SCLK according to the mask signal MASK and outputs a signal fixed at a predetermined level (here, H level) as the output clock signal CLKOUT. In other words, the clock selection circuit 40 masks the output clock signal CLKOUT at the H level according to the mask signal MASK. The clock selection circuit 40 outputs the selected clock signal SCLK as the output clock signal CLKOUT in response to the stop of the generation of the mask signal MASK.

  The cancel circuit 60 receives the mask signal MASK from the mask signal generation circuit 30 and the selection clock signal SCLK from the clock selection circuit 40. The cancel circuit 60 generates the mask cancel signal MR when it detects that the signal level of the selected clock signal SCLK has changed to a predetermined level when the mask signal MASK is generated. The mask release signal MR is a signal for instructing the generation stop of the mask signal MASK. The release circuit 60 stops generating the mask release signal MR when the generation of the mask signal MASK is stopped.

Next, an internal configuration example of each of the circuits 10 to 60 of the clock switching circuit 1 will be described with reference to FIG.
The synchronization circuit 10 has a FF group 13 including D-flip-flop circuits (D-FF) 11 and 12 in a plurality of stages (here, two stages). The FF group 13 receives a 1-bit selection signal SEL necessary for selecting one input clock signal from the two input clock signals CLK1 and CLK2. Here, FF groups in the synchronization circuit 10 are provided log ₂ N (rounded up after the decimal point), here log ₂ 2 = 1, where N is the number of input clock signals to be selected. .

  The first-stage D-FF 11 captures the selection signal SEL in synchronization with the rising edge (transition from L level to H level) of the output clock signal CLKOUT, and outputs the captured signal to the next-stage D-FF 11. The D-FF 12 captures the output signal of the D-FF 11 in synchronization with the rising edge of the output clock signal CLKOUT, and outputs the captured signal as the selection signal SELa. An initialization signal IS is input to the clear terminals CLR of these D-FFs 11 and 12. These D-FFs 11 and 12 are cleared when the initialization signal IS becomes L level during initialization, and hold the L level.

  As described above, the synchronization circuit 10 having a plurality of stages of D-FFs 11 and 12 is a circuit for avoiding the occurrence of metastable and correctly taking in the selection signal SEL in synchronization with the output clock signal CLKOUT. Here, metastable refers to a phenomenon in which the output level of the receiving side register becomes unstable when the data and the clock signal are asynchronous signals. At this time, since the selection signal SEL is an asynchronous signal with respect to the input clock signals CLK1 and CLK2 and the output clock signal CLKOUT, the output signal of the D-FF 11 may become indefinite. Therefore, in the synchronization circuit 10, D-FFs 11 and 12 for synchronization having an appropriate number of stages (here, two stages) are connected in series, and are retimed to the output clock signal CLKOUT in the D-FFs 11 and 12. Thus, the input selection signal SEL is synchronized. As a result, even if the output signal of the D-FF 11 becomes an indefinite value, the output value can be determined by the D-FF 12, so that the indefinite value can be prevented from propagating to the subsequent stage. Note that the number of stages of the D-FFs 11 and 12 in the synchronization circuit 10 is not particularly limited as long as the number of stages can avoid the occurrence of metastable.

The detection circuit 20 includes a detection unit 23 including an odd-numbered stage (here, one stage) inverter circuit 21 and an XOR circuit 22. The selection signal SELa is input to the detection unit 23. Here, when the number of input clock signals to be selected is N, the number of detection units in the detection circuit 20 is log ₂ N (rounded up after the decimal point), here log ₂ 2 = 1.

  The inverter circuit 21 outputs an inverted signal obtained by logically inverting the selection signal SELa from the synchronization circuit 10 to the XOR circuit 22. The XOR circuit 22 generates a mask start signal MS having a result obtained by performing an exclusive OR operation on the selection signal SELa from the synchronization circuit 10 and the inverted signal from the inverter circuit 21. Specifically, for example, when the signal level of the selection signal SELa transitions from H level to L level, both input signals of the XOR circuit 22 become L level for the delay time of the inverter circuit 21, so masking starts for the delay time. The signal MS becomes L level. Similarly, when the signal level of the selection signal SELa changes from L level to H level, both input signals of the XOR circuit 22 become H level for the delay time of the inverter circuit 21, so that the mask start signal MS is equal to the delay time. Becomes L level.

  The mask signal generation circuit 30 has a D-FF 31. A high potential power supply voltage VDD generated by a power supply circuit (not shown) is supplied to the input terminal D of the D-FF 31. The mask release signal MR is input from the release circuit 60 to the clock terminal of the D-FF 31. The inversion level of the initialization signal IS is input to the preset terminal PR of the D-FF 31. The mask start signal MS is input to the clear terminal CLR of the D-FF 31. Then, the mask signal MASK is output from the inverting output terminal XQ of the D-FF 31.

  The D-FF 31 is preset when the initialization signal IS becomes L level at the time of initialization, holds the high potential power supply voltage VDD level (H level), and outputs the L level mask signal MASK. The D-FF 31 is cleared when the mask start signal MS becomes L level in response to a change in the signal level of the selection signal SELa, and outputs an H level mask signal MASK. In response to the rising edge of the mask release signal MR, the D-FF 31 holds a signal (high potential power supply voltage VDD) supplied to the input terminal D and outputs an L level mask signal MASK.

  The clock selection circuit 40 includes a selector 41 and an OR circuit 42. The selector 41 selects one of the input clock signals CLK1 and CLK2 according to the selection signal SELa, and outputs the selected input clock signal as the selected clock signal SCLK. For example, the selector 41 outputs the input clock signal CLK1 as the selection clock signal SCLK in response to the L level selection signal SELa, and outputs the input clock signal CLK2 as the selection clock signal SCLK in response to the H level selection signal SELa. .

  The OR circuit 42 outputs an output clock signal CLKOUT having a result obtained by performing an OR operation on the selection clock signal SCLK and the mask signal MASK. Specifically, the OR circuit 42 outputs the selected clock signal SCLK as the output clock signal CLKOUT when the mask signal MASK is at L level. Thus, the input clock signal selected according to the selection signal SELa (selection signal SEL) is output as the output clock signal CLKOUT. On the other hand, when the mask signal MASK is at the H level, the OR circuit 42 outputs the output clock signal CLKOUT that is fixed at the H level regardless of the signal level of the selected clock signal SCLK. That is, the selection clock signal SCLK is masked by the H level mask signal MASK, and the output clock signal CLKOUT is fixed at the H level. Thus, the H level mask signal MASK functions as a signal for invalidating the selected clock signal SCLK (that is, the input clock signal CLK1 and the input clock signal CLK2), and the OR circuit 42 is a circuit for invalidating the selected clock signal SCLK. Function as. Here, the H level mask signal MASK responds to the L level mask start signal MS when the signal level of the selection signal SELa (selection signal SEL) changes, that is, when the input clock signals CLK1 and CLK2 are switched. Generated. Therefore, it can be said that the mask signal MASK at the H level is a signal that invalidates both the input clock signals CLK1 and CLK2 when the clock is switched and fixes the output clock signal CLKOUT at the H level when the clock is switched.

  The release circuit 60 has a NAND circuit 61. The NAND circuit 61 generates a mask release signal MR having a result obtained by performing a NAND operation on the inverted level of the selected clock signal SCLK and the mask signal MASK, and outputs the mask release signal MR to the clock terminal of the D-FF 31. . Specifically, when the mask signal MASK is at the L level, the NAND circuit 61 outputs the mask release signal MR that is fixed at the L level regardless of the signal level of the selected clock signal SCLK. That is, when the selected clock signal SCLK is not masked by the mask signal MASK, the mask release signal MR fixed at the H level is output. On the other hand, when the mask signal MASK is at the H level, the NAND circuit 61 outputs a mask release signal MR having the same logic level as that of the selected clock signal SCLK. Therefore, after the masking of the selected clock signal SCLK is started, when the selected clock signal SCLK transitions from the L level to the H level, the mask release signal MR also rises from the L level to the H level. In response to the rising edge of the mask release signal MR, the mask signal MASK is changed to L level in the D-FF 31.

In the present embodiment, the XOR circuit 22 is an example of a first logic circuit, the selector 41 is an example of a second logic circuit, and the OR circuit 42 is an example of a second logic circuit.
Next, the operation of the clock switching circuit 1 will be described with reference to FIG. First, the initialization operation of the clock switching circuit 1 will be described.

  At time t1, when the initialization signal IS falls to the L level, the D-FFs 11 and 12 are cleared and the L level selection signal SELa is output, and the D-FF 31 is preset and the L level mask is set. Signal MASK is output. In response to the L level mask signal MASK, the NAND circuit 61 outputs an H level mask release signal MR. Note that the L-level selection signal SEL is input to the clock switching circuit 1 (synchronization circuit 10).

  After such initialization, the input clock signal CLK1 of the input clock signals CLK1 and CLK2 is selected by the selector 41 in accordance with the L level selection signal SELa, and the input clock signal CLK1 is output as the selected clock signal SCLK. Is done. At this time, since the mask signal MASK is at the L level as described above, the selected clock signal SCLK, that is, the input clock signal CLK1 is output as the output clock signal CLKOUT. Therefore, in the synchronization circuit 10, the selection signal SEL is synchronized by the input clock signal CLK1 (output clock signal CLKOUT).

Next, an operation for switching from the input clock signal CLK1 to the input clock signal CLK2 will be described.
At time t2, the selection signal SEL transitions from the L level to the H level in order to switch from the input clock signal CLK1 to the input clock signal CLK2. Then, the H-level selection signal SEL is held in the D-FF 11 in response to the rising edge of the first output clock signal CLKOUT (here, the input clock signal CLK1) generated after the transition (time t3). Subsequently, in response to the rising edge of the next output clock signal CLKOUT, the H-level output signal output from the D-FF 11 is held in the D-FF 12, and the H-level selection signal SELa is output from the D-FF 12. (Time t4). That is, at time t4, the selection signal SELa output from the D-FF 12 is transitioned from the L level to the H level. Thus, the H-level selection signal SEL after the transition is synchronized with the output clock signal CLKOUT (that is, the input clock signal CLK1 before clock switching). It should be noted that until the selection signal SEL transitions from the L level to the H level until the synchronization with the selection signal SEL at the H level is completed (until the selection signal SELa transitions to the H level), the L level. In response to the selection signal SELa, the input clock signal CLK1 is output as the selection clock signal SCLK.

  As described above, when the selection signal SELa transitions from the L level to the H level, the L level mask start signal MS is transmitted from the XOR circuit 22 in response to the transition (change) for a predetermined period (the delay time of the inverter circuit 21). ) Only. In response to the L level mask start signal MS, the D-FF 31 outputs an H level mask signal MASK.

  On the other hand, in the clock selection circuit 40, the input clock signal CLK2 is selected by the selector 41 in accordance with the selection signal SELa at the H level after the transition, and the input clock signal CLK2 is output as the selection clock signal SCLK. That is, in the selector 41, switching from the input clock signal CLK1 to the input clock signal CLK2 is performed according to the selection signal SELa of the H level. However, since the H level mask signal MASK is input to the OR circuit 42 at this time, the selection clock signal SCLK is masked by the mask signal MASK, and the output clock signal CLKOUT is fixed to the H level. In this way, when the input clock signal CLK1 is switched to the input clock signal CLK2, the H level mask signal MASK is generated. For this reason, for example, when the input clock signal CLK1 immediately before the clock switching in the selector 41 is at the H level and the input clock signal CLK2 immediately after the clock switching is at the L level, a narrow H pulse hazard (selected clock signal SCLK) is generated. Output as the output clock signal CLKOUT is suppressed.

  In the release circuit 60, the mask release signal MR having the same logic level as that of the selected clock signal SCLK (that is, the input clock signal CLK2 after the clock switching) is generated in accordance with the H level mask signal MASK after the transition. Is output from. Since the selected clock signal SCLK at the time t4 is at the L level, the mask release signal MR transits to the L level at the time t4. Thereafter, when the selected clock signal SCLK transitions to the H level (time t5), the mask release signal MR rises to the H level. In response to the rising edge of the mask release signal MR, the mask signal MASK changes from H level to L level. Then, the mask for the selected clock signal SCLK is released, and the selected clock signal SCLK (here, the input clock signal CLK2 after the clock switching) is output as the output clock signal CLKOUT. In this way, switching from the input clock signal CLK1 to the input clock signal CLK2 is completed. When the mask signal MASK transitions to the L level, the NAND circuit 61 outputs the mask release signal MR fixed at the H level.

Next, an operation for switching from the input clock signal CLK2 to the input clock signal CLK1 will be described.
At time t6, the selection signal SEL transitions from the H level to the L level in order to switch from the input clock signal CLK2 to the input clock signal CLK1. Then, the L level selection signal SEL is synchronized with the output clock signal CLKOUT (here, the input clock signal CLK2), and the L level selection signal SELa is output in synchronization with the rising edge of the output clock signal CLKOUT ( Time t7). It should be noted that after the selection signal SEL transitions from the H level to the L level in this way until the synchronization with the L level selection signal SEL is completed (until the selection signal SELa transitions to the L level), the H level. In response to the selection signal SELa, the input clock signal CLK2 is output as the selection clock signal SCLK.

  When the selection signal SELa transitions from the H level to the L level as described above, the LOR mask start signal MS is output from the XOR circuit 22 for a predetermined period in response to the transition (change). In response to the L level mask start signal MS, the D-FF 31 outputs an H level mask signal MASK.

  On the other hand, in the clock selection circuit 40, the input clock signal CLK1 is selected by the selector 41 in accordance with the L level selection signal SELa after the transition, and the input clock signal CLK1 is output as the selection clock signal SCLK. That is, in the selector 41, switching from the input clock signal CLK2 to the input clock signal CLK1 is performed in accordance with the L level selection signal SELa. However, since the H level mask signal MASK is input to the OR circuit 42 at this time, the selection clock signal SCLK is masked by the mask signal MASK, and the output clock signal CLKOUT is fixed to the H level.

  At the time t7, the mask release signal MR transits to the L level in response to the H level mask signal MASK and the L level selected clock signal SCLK. Thereafter, when the selected clock signal SCLK transitions to the H level (time t8), the mask release signal MR rises to the H level. In response to the rising edge of the mask release signal MR, the mask signal MASK changes from H level to L level. Then, since the mask for the selected clock signal SCLK is released, the selected clock signal SCLK (here, the input clock signal CLK1 after the clock switching) is output as the output clock signal CLKOUT. In this way, switching from the input clock signal CLK2 to the input clock signal CLK1 is completed.

  As described above, the clock switching circuit 1 generates the H level mask signal MASK when the signal level of the selection signal SELa changes, that is, when the input clock signals CLK1 and CLK2 are switched. Since the selection signal SELa at this time is synchronized with the rising edge of the output clock signal CLKOUT, the mask signal MASK is also generated in synchronization with the rising edge of the output clock signal CLKOUT. Therefore, when the output clock signal CLKOUT transitions to the H level, the H level mask signal MASK is generated, and the selected clock signal SCLK is masked by the mask signal MASK, and the output clock signal CLKOUT is fixed to the H level. Thereby, the signal level of the output clock signal CLKOUT can be fixed to the H level at the time of clock switching. In other words, the input clock signal (selected clock signal SCLK) switched by the selector 41 according to the selection signal SELa can be prevented from being output as the output clock signal CLKOUT immediately after the switching. For this reason, even if the selected clock signal SCLK immediately after switching is at the L level, the output clock signal CLKOUT is prevented from transitioning to the L level, and the occurrence of a hazard at the time of clock switching can be suitably suppressed.

  Further, in the clock switching circuit 1, after the mask for the selected clock signal SCLK is started, the mask for the selected clock signal SCLK is released when the selected clock signal SCLK transitions from the L level to the H level. For this reason, the output clock signal CLKOUT is fixed at the H level during the period from when masking to the selected clock signal SCLK is started until the mask is released, and after the mask is released, the selected clock signal SCLK of the H level pulse is Output as an output clock signal CLKOUT. Therefore, at the time of clock switching, it is possible to suitably suppress the output of the signal having a shorter pulse width than the shorter one of the input clock signals CLK1 and CLK2 as the output clock signal CLKOUT. Note that when such a short pulse width appears in the output clock signal CLKOUT, the probability that a malfunction will occur in a circuit that operates according to the output clock signal CLKOUT increases, but a signal with a long pulse width appears in the output clock signal CLKOUT. In some cases, malfunctions usually do not occur.

According to this embodiment described above, the following effects can be obtained.
(1) When the selection signal SEL is synchronized with the output clock signal CLKOUT and the signal level of the synchronized selection signal SELa changes, the plurality of input clock signals CLK1 and CLK2 are set to a predetermined level (here, H level). The mask signal MASK for masking is generated. Further, after the mask signal MASK is generated, the mask signal is detected when a transition of the input clock signal selected according to the selection signal SELa, that is, the selection clock signal SCLK to a predetermined level (here, H level) is detected. The generation of MASK was stopped. As a result, the output clock signal CLKOUT is fixed at the H level during the period from when the masking to the selected clock signal SCLK is started until the masking is released, and after the masking is released, the selected clock signal SCLK of the H level pulse is Output as an output clock signal CLKOUT. Therefore, it is possible to suitably suppress the occurrence of a hazard at the time of clock switching.

(2) The synchronization circuit 10 synchronizes the selection signal SEL with one output clock signal (input clock signal after selection). Therefore, the circuit scale can be reduced as compared with the case where the selection signal SEL is synchronized for each of the input clock signals CLK1 and CLK2. Specifically, the FF group 13 in the synchronization circuit 10 does not have to be provided for the number N (here, 2) of input clock signals CLK1 and CLK2 to be selected, and is log ₂ N (rounded up to the nearest decimal place). It is sufficient to provide only minutes. For this reason, even when the number N of input clock signals to be selected increases, an increase in circuit scale can be suppressed as compared with the case where the same number N of FF groups 13 are provided.

  Furthermore, since one synchronized selection signal SELa is used for the two input clock signals CLK1 and CLK2, the detection circuit 20 and the mask signal generation circuit 30 generate the mask signal MASK in accordance with the selection signal SELa. And the increase in the circuit scale of the release circuit 60 can also be suppressed.

  (3) Since the occurrence of a hazard at the time of clock switching can be suppressed as described above, the signal level of the selection signal SEL can be switched at an arbitrary timing, that is, the input clock signals CLK1 and CLK2 can be switched at an arbitrary timing. it can. In addition, after the generation of the mask signal MASK, the switching of the input clock signals CLK1 and CLK2 can be completed in response to the first rising edge of the selected clock signal SCLK. Therefore, the input clock signals CLK1 and CLK2 can be switched in a short period after the synchronization of the selection signal SEL is completed, and the input clock signals CLK1 and CLK2 can be switched dynamically. Further, since the generation of the mask signal MASK is stopped in response to the rising edge of the input clock signal after the clock switching, the occurrence of the hazard is suppressed regardless of the frequency ratio and phase of the input clock signals CLK1 and CLK2. Can do.

  (4) By the way, in a circuit in which a hazard is generated at the time of clock switching, it is necessary to take measures such as partially changing the actual circuit and the simulation circuit when performing a simulation. There has been a problem that the circuit operates differently from the desired operation. On the other hand, in the clock switching circuit 1 that can suppress the occurrence of a hazard at the time of clock switching, the actual circuit and the simulation circuit can be made the same circuit, so that the above problem can be prevented from occurring. .

  (5) The selection signal SELa is synchronized with the rising edge of the output clock signal CLKOUT. Thus, when the output clock signal CLKOUT transitions to the H level, the H level mask signal MASK is generated, and the selected clock signal SCLK is masked by the mask signal MASK and the output clock signal CLKOUT is fixed to the H level. Therefore, the signal level of output clock signal CLKOUT can be fixed at the H level during clock switching. For this reason, even if the selected clock signal SCLK immediately after the clock switching is at the L level, the output clock signal CLKOUT is prevented from transitioning to the L level, and the occurrence of a hazard at the time of clock switching can be suitably suppressed.

  (6) Since the selection signal SEL is synchronized with the output clock signal, the input clock signals CLK1 and CLK2 can be switched according to the selection signal SEL which is an asynchronous signal with respect to the input clock signals CLK1 and CLK2. it can.

  (7) In the synchronization circuit 10, the selection signal SEL is fetched in accordance with the output clock signal CLKOUT by the plurality of stages of D-FFs 11 and 12. Thereby, generation | occurrence | production of a metastable can be suppressed and the selection signal SEL can be taken in correctly. Furthermore, as described above, when the number N of input clock signals to be selected is increased, the increase in the FF group 13 is suppressed, so that an increase in circuit scale when a metastable measure is taken can also be suppressed. .

  (8) In the detection circuit 20, the XOR circuit 22 detects the change in the signal level of the selection signal SELa, that is, both the change from the H level to the L level and the change from the L level to the H level. Therefore, an increase in circuit scale can be suppressed.

(Modification of the first embodiment)
In addition, the said 1st Embodiment can also be implemented in the following aspects which changed this suitably.

  The internal configuration example of the synchronization circuit 10 in the first embodiment is not particularly limited. For example, a single stage D-FF may be provided instead of the plurality of stages of D-FFs 11 and 12. Even if it is such a structure, there can exist an effect similar to (1)-(6) of the said 1st Embodiment, and (8).

  In the first embodiment, the D-FFs 11 and 12 are flip-flops with the clear terminal CLR, and the initialization signal IS is supplied to the clear terminal CLR. Thereby, at the time of initialization, the L-level selection signal SELa is output from the D-FF 12, and the input clock signal CLK1 is output from the selector 41 as the selection clock signal SCLK. For example, the D-FFs 11 and 12 may be changed to flip-flops with a preset terminal PR, and the initialization signal IS may be supplied to the preset terminal PR. In this case, since the selection signal SELa of the H level is output from the D-FF 12 at the time of initialization, the input clock signal CLK2 is output from the selector 41 as the selection clock signal SCLK. In this case, it is preferable to set the initial value of the selection signal SEL to the H level.

  As the D-FFs 11 and 12, flip-flops that do not have the clear terminal CLR or the preset terminal PR can be used. However, in the logic simulation at the design stage, the indefinite values of these flip-flops at the initial stage of the simulation are propagated to the selector 41. For this reason, it is preferable to use a flip-flop having a clear terminal CLR or a preset terminal PR.

  The internal configuration example of the detection circuit 20 in the first embodiment is not particularly limited. In the detection circuit 20 of the first embodiment, the inverter circuit 21 and the XOR circuit 22 detect changes in both signal levels of the selection signal SELa (change from H level to L level and change from L level to H level). I tried to do it. For example, the detection circuit 20 may be provided with a logic circuit that individually detects a change in the selection signal SELa from the H level to the L level and a change in the selection signal SELa from the L level to the H level. Also good. Even if it is such a structure, there can exist an effect similar to (1)-(7) of the said 1st Embodiment.

  The internal configuration example of the mask signal generation circuit 30 in the first embodiment is not particularly limited. For example, as shown in FIG. 4, an RS-FF 34 formed by two NAND circuits 32 and 33 may be provided instead of the D-FF 31. Specifically, the initialization signal IS, the mask start signal MS, and the output signal of the NAND circuit 33 having two input terminals are input to the NAND circuit 32 having three input terminals. The output signal of the NAND circuit 32 is output as the mask signal MASK, and the output signal of the NAND circuit 32 is input to the NAND circuit 33. The NAND circuit 33 is supplied with a mask release signal MR. In such an RS-FF 34, in response to an L level mask start signal MS (set signal) input to the set terminal S, the RS-FF 34 transitions to a set state and outputs an H level mask signal MASK. Further, in response to an L level mask release signal MR (reset signal) input to the reset terminal R, a transition is made to the reset state, and an L level mask signal MASK is output. Even with such a configuration, the same effects as those of the first embodiment can be obtained.

  Alternatively, in the D-FF 31 of the first embodiment, the high potential power supply voltage VDD is supplied to the input terminal D, and the mask signal MASK is output from the inverting output terminal XQ. For example, the low potential power supply voltage may be supplied to the input terminal of the D-FF 31 and the mask signal MASK may be output from the output terminal Q.

  -The internal configuration example of the release circuit 60 in the first embodiment is not particularly limited. For example, as shown in FIG. 5, a buffer circuit (delay circuit) 62 and an OR circuit 63 may be added. Specifically, a mask signal MASK is directly supplied to the OR circuit 63 and a delay signal obtained by delaying the mask signal MASK by the buffer circuit 62 is supplied. For this reason, when the mask signal MASK is transitioned to the L level in response to the rising edge of the mask release signal MR, the delay time (specifically, the output of the D-FF 31 is changed by the buffer circuit 62 after the transition). The mask release signal MR is reliably maintained at the H level for an amount of time). As a result, the pulse width of the mask release signal MR (clock pulse width of the D-FF 31) can be secured, so that the mask signal MASK can be reliably shifted to the L level.

  Alternatively, as shown in FIG. 6, the internal configuration of the release circuit 60 may be changed. Specifically, the release circuit 60 shown in FIG. 6 includes NAND circuits 64 and 65 having three input terminals. The NAND circuit 64 receives the inverted level of the selected clock signal SCLK, the mask signal MASK, and the output signal of the NAND circuit 65. The NAND circuit 65 receives the inverted level of the selected clock signal SCLK, the inverted level of the mask signal MASK, and the output signal of the NAND circuit 64. Then, the output signal of the NAND circuit 64 is output as the mask release signal MR. In such a circuit, when the L level mask signal MASK is input by the initialization operation, the NAND circuit 64 outputs the H level mask release signal MR. Thereafter, when the mask signal MASK transitions to the H level, the mask release signal MR having the same logic level as the selected clock signal SCLK at that time is output. When the mask signal MASK is at the H level and the selected clock signal SCLK transitions from the L level to the H level, the mask release signal MR also transitions from the L level to the H level. Then, in response to the rising edge of the mask release signal MR, the mask signal MASK transitions to the L level. That is, even with such a configuration, after the H level mask signal MASK is generated, the mask signal MASK can be shifted to the L level in response to the rising edge of the selected clock signal SCLK.

  The internal configuration examples of the clock selection circuit 40 and the release circuit 60 in the first embodiment are not particularly limited. For example, as shown in FIG. 7, the internal configurations of the clock selection circuit 40 and the release circuit 60 may be changed. Specifically, the clock selection circuit 40 includes an inverter circuit 43, AND circuits 44 and 45, and an OR circuit 46 having three input terminals. The AND circuit 44 receives the input clock signal CLK1 and a signal obtained by logically inverting the selection signal SELa by the inverter circuit 43. The AND circuit 45 receives the input clock signal CLK2 and the selection signal SELa. The output signal of the AND circuits 44 and 45 and the mask signal MASK are input to the OR circuit 46. The OR circuit 46 outputs the output clock signal CLKOUT. In such a clock selection circuit 40, the input clock signal CLK1 is output from the AND circuit 44 and the output signal fixed at the L level is output from the AND circuit 45 in response to the selection signal SELa at the L level. When the mask signal MASK is at the L level, the input clock signal CLK1 output from the AND circuit 44 is output as the output clock signal CLKOUT. On the other hand, in the clock selection circuit 40, an output signal fixed at the L level is output from the AND circuit 44 and the input clock signal CLK2 is output from the AND circuit 45 in response to the selection signal SELa at the H level. When mask signal MASK is at the L level, input clock signal CLK2 output from AND circuit 45 is output as output clock signal CLKOUT. When mask signal MASK is at the H level, output clock signal CLKOUT having a fixed H level is output regardless of the signal level of output signals of AND circuits 44 and 45 (that is, input clock signals CLK1 and CLK2). .

  On the other hand, the release circuit 60 includes an inverter circuit 66 and an OR circuit 67 having three input terminals. The OR circuit 67 receives a signal obtained by logically inverting the mask signal MASK by the inverter circuit 66 and the output signals of the AND circuits 44 and 45. The OR circuit 67 outputs the mask release signal MR. In such a release circuit 60, when the input clock signal CLK1 is output from the AND circuit 44 in response to the selection signal SELa at the L level and the mask signal MASK at the H level is output, The mask release signal MR having the same logic level is output. When the input clock signal CLK2 is output from the AND circuit 45 in response to the selection signal SELa at the H level and the mask signal MASK at the H level is output, the mask release at the same logic level as the input clock signal CLK2 is performed. A signal MR is output. When the L level mask signal MASK is output, the H level fixed output clock signal CLKOUT is output regardless of the signal levels of the output signals of the AND circuits 44 and 45. Even with such a configuration, the same effects as those of the first embodiment can be obtained.

  In the first embodiment, the selection signal SEL is synchronized with the rising edge of the output clock signal CLKOUT, and the selection clock signal SCLK (input clock signals CLK1 and CLK2) is masked at the H level. For example, the selection signal SEL may be synchronized with the falling edge of the output clock signal CLKOUT, and the selection clock signal SCLK (input clock signals CLK1, CLK2) may be masked at the L level.

  In the first embodiment, the selection signal SEL is synchronized with the rising edge of the output clock signal CLKOUT. Further, when the selected clock signal SCLK is masked by the mask signal MASK, the mask by the mask signal MASK is released in response to the rising edge of the selected clock signal SCLK. For example, the selection signal SEL may be synchronized with the falling edge of the output clock signal CLKOUT. Further, when the selected clock signal SCLK is masked by the mask signal MASK, the masking by the mask signal MASK may be canceled in response to the falling edge of the selected clock signal SCLK.

  In the first embodiment, the D-FF 31 in the mask signal generation circuit 30 is initialized by the initialization signal IS. For example, the initialization of the D-FF 31 may be performed by the initialization signal IS and the mask start signal MS. Specifically, as shown in FIG. 8, an AND circuit 24 to which the initialization signal IS and the output signal of the XOR circuit 22 are supplied is added to the detection circuit 20, and the output signal of the AND circuit 24 is masked. The start signal MS may be supplied to the clear terminal CLR of the D-FF 31. In this case, the supply of the initialization signal IS to the preset terminal of the D-FF 31 is omitted.

  In such a circuit, when the initialization signal IS falls to the L level at time t9 shown in FIG. 9, the D-FFs 11 and 12 are cleared and the L level selection signal SELa is output, while the AND circuit 24 outputs an L level mask start signal MS. Then, an H level mask signal MASK is output in response to the L level mask start signal MS. That is, when the L-level initialization signal IS is input to the D-FF 31 as the mask start signal MS, the D-FF 31 generates an H-level mask signal MASK. The selected clock signal SCLK is masked by the H level mask signal MASK, and the H level fixed output clock signal CLKOUT is output. On the other hand, the cancel circuit 60 outputs a mask cancel signal MR having the same logic level as the selected clock signal SCLK (L level at time t9) in response to the L level mask signal MASK. Thereafter, when the selected clock signal SCLK transits to the H level (time t10), the mask release signal MR transits from the L level to the H level, and the mask signal MASK goes to the L level in response to the rising edge of the mask release signal MR. Transition. Thereby, initialization of the clock switching circuit 1 is completed, and the input clock signal CLK1 selected according to the selection signal SELa is output as the output clock signal CLKOUT. Thus, in the clock switching circuit 1 shown in FIG. 8, the initialization is completed in synchronization with the rising edge of the selected clock signal SCLK.

  Alternatively, as shown in FIG. 10, the internal configurations of the synchronization circuit 10 and the release circuit 60 may be changed. Specifically, the synchronization circuit 10 illustrated in FIG. 10 includes D-FFs 11 and 12 and AND circuits 14 and 15. The AND circuit 14 outputs a signal having a result obtained by ANDing the selection signal SEL and the initialization signal IS to the input terminal D of the D-FF 11. The D-FF 11 captures the output signal of the AND circuit 14 in synchronization with the rising edge of the output clock signal CLKOUT, and outputs the captured signal to the AND circuit 15. The AND circuit 15 outputs the output signal of the D-FF 11 and the initialization signal IS to the input terminal D of the signal D-FF 12 having a result of the logical product operation. The D-FF 12 captures the output signal of the AND circuit 15 in synchronization with the rising edge of the output clock signal CLKOUT, and outputs the captured signal as the selection signal SELa.

  10 includes an AND circuit 68 having two input terminals, an OR circuit 69 having three input terminals, an OR circuit 70 having two input terminals, and an AND circuit 71 having two input terminals. And have. A selection clock signal SCLK and a mask signal MASK are input to the AND circuit 68. The OR circuit 69 receives the inversion level of the mask signal MASK, the inversion level of the initialization signal IS, and the output signal of the AND circuit 68. The OR circuit 70 receives the initialization signal IS and the selected clock signal SCLK. The output signal from the OR circuit 69 and the output signal from the OR circuit 70 are input to the AND circuit 71. Then, a mask release signal MR is output from the AND circuit 71.

  Next, the operation of the clock switching circuit 1 shown in FIG. 10 will be described. Here, when the power is turned on, the signal output from the output terminal Q of the D-FFs 11 and 12 is L level, and the signal (mask signal MASK) output from the inverted output terminal XQ of the D-FF 31 is L level. The operation in this case will be described.

  Immediately before time t11 shown in FIG. 11, that is, when the power is turned on, the L-level selection signal SELa is output from the D-FF 12, and the L-level mask signal MASK is output from the D-FF 31, so that the input clock signal CLK1 is output as the selected clock signal SCLK, and the input clock signal CLK1 is output as the output clock signal CLKOUT. Subsequently, when the initialization signal IS falls to L level at time t11, an output signal fixed at H level is output from the OR circuit 69, and the selected clock signal SCLK (here, the input clock signal CLK1) is output from the OR circuit 70. Output as an output signal. Therefore, the AND circuit 71 outputs a mask release signal MR having the same logic level as the input clock signal CLK1 (L level at time t11). Thereafter, when the output clock signal CLKOUT (here, the input clock signal CLK1) transitions to the H level (time t12), the L level output signal (L level initialization signal IS) output from the AND circuits 14 and 15 is generated. The signals are taken into the D-FFs 11 and 12 and L-level output signals are output from the D-FFs 11 and 12. In this manner, the logic level of the selection signal SELa is determined to be L level by the L level initialization signal IS. That is, in the synchronization circuit 10, the selection signal SELa is set to L level (initialized) based on the L level initialization signal IS.

  Further, as described above, when the input clock signal CLK1 transits to the H level, the mask release signal MR transits from the L level to the H level, and in response to the rising edge of the mask release signal MR, the mask signal MASK becomes the L level. To be confirmed. That is, in the release circuit 60, the mask release signal MR is generated in response to the transition from the L level to the H level of the input clock signal CLK1 selected according to the initialized L level selection signal SELa. The mask signal generation circuit 30 stops generating the mask signal MASK based on the mask release signal MR. Thereby, initialization of the clock switching circuit 1 is completed, and the input clock signal CLK1 selected according to the selection signal SELa is output as the output clock signal CLKOUT.

  Thus, in the clock switching circuit 1 shown in FIG. 10, the initialization is completed in synchronization with the rising edge of the output clock signal CLKOUT. Therefore, after the initialization signal IS in this modification falls to the L level, it is necessary to maintain the L level until the output clock signal CLKOUT changes from the L level to the H level. Therefore, for example, in a steady operation state in which one of the input clock signals CLK1 and CLK2 is output as the output clock signal CLKOUT, the initialization signal IS transits to the L level for a short time due to noise or the like. However, it is possible to prevent the D-FFs 11, 12, and 31 from being cleared according to the L level initialization signal IS. Specifically, for example, at time t13, even when the initialization signal IS transitions to the L level due to noise or the like, the output clock signal CLKOUT is set to the H level during the period when the initialization signal IS is at the L level. As long as this transition does not occur, the logic level of the selection signal SELa does not transition unintentionally. For this reason, it can suppress that the mask start signal MS falls to L level, and can suppress that D-FF31 is cleared. That is, unintentional generation of an H level mask signal MASK can be suppressed. As described above, the clock switching circuit 1 shown in FIG. 10 can improve noise tolerance.

  Note that the mask release signal MR having the same logic level as that of the selected clock signal SCLK is output while the initialization signal IS is at the L level. Is output.

  In the clock selection circuit 40 according to the first embodiment, after selecting either one of the input clock signals CLK1 and CLK2 according to the selection signal SELa, the mask signal MASK with respect to the selected clock signal SCLK after the selection. It was made to mask with. For example, after masking each of the input clock signals CLK1 and CLK2 with the mask signal MASK, one clock signal may be selected according to the selection signal SELa. A circuit example of the clock switching circuit 1 in this case is shown in FIG. The clock selection circuit 40 includes OR circuits 47 and 48 and a selector 49. The OR circuit 47 receives the input clock signal CLK1 and the mask signal MASK, and the OR circuit 48 receives the input clock signal CLK2 and the mask signal MASK. These OR circuits 47 and 48 output the input clock signals CLK1 and CLK2 to the selector 49 as output signals, respectively, when the mask signal MASK is at L level. Further, the OR circuits 47 and 48 each output an output signal fixed at H level to the selector 49 when the mask signal MASK is at H level. The selector 49 outputs the output signal of the OR circuit 47 as the output clock signal CLKOUT according to the L level selection signal SELa, and outputs the output signal of the OR circuit 48 as the output clock signal CLKOUT according to the H level selection signal SELa. To do. As described above, the clock selection circuit 40 outputs the input clock signals CLK1 and CLK2 or a signal fixed to a predetermined level (H level) as the output clock signal CLKOUT in accordance with the mask signal MASK and the selection signal SELa.

  In this case, the release circuit 60 includes NAND circuits 72 and 73 and a selector 74. The NAND circuit 72 receives the mask signal MASK and the inverted level of the input clock signal CLK1, and the NAND circuit 73 receives the mask signal MASK and the inverted level of the input clock signal CLK2. These NAND circuits 72 and 73 output an H level fixed output signal to the selector 74 when the mask signal MASK is at the L level. The NAND circuits 72 and 73 output the input clock signals CLK1 and CLK2 as output signals to the selector 74 when the mask signal MASK is at the H level. The selector 74 outputs the output signal of the NAND circuit 72 as a mask release signal MR according to the L level selection signal SELa, and outputs the output signal of the NAND circuit 73 as a mask release signal MR according to the H level selection signal SELa. To do. In such a release circuit 60, when the mask signal MASK is at the H level and the selection signal SELa is at the L level, the input clock signal CLK1 selected according to the selection signal SELa changes from the L level to the H level. Then, the mask release signal MR output from the selector 74 changes from L level to H level. Then, in response to the rising edge of the mask release signal MR, the mask signal MASK transitions to the L level. As described above, the cancel circuit 60 generates the mask signal MASK in response to the transition from the L level to the H level of the input clock signal selected by the selection signal SELa when the mask signal MASK is at the H level. A mask release signal MR to be stopped is generated.

  In the clock selection circuit 40 according to the first embodiment, after selecting either one of the input clock signals CLK1 and CLK2 according to the selection signal SELa, the mask signal MASK with respect to the selected clock signal SCLK after the selection. It was made to mask with. For example, the selection by the selection signal SELa and the masking by the mask signal MASK may be performed by a common circuit. A circuit example of the clock switching circuit 1 in this case is shown in FIG. The clock selection circuit 40 includes an inverter circuit 50, OR circuits 51 and 52 having three input terminals, and an AND circuit 53. An input clock signal CLK1, a selection signal SELa, and a mask signal MASK are input to the OR circuit 51. An input clock signal CLK2, a signal obtained by logically inverting the selection signal SELa by the inverter circuit 50, and a mask signal MASK are input to the OR circuit 52. The AND circuit 53 outputs a signal having a result obtained by performing an AND operation on the output signal of the OR circuit 51 and the output signal of the OR circuit 52 as the output clock signal CLKOUT. In such a clock selection circuit 40, for example, when the mask signal MASK is at the L level and the selection signal SELa is at the L level, the input clock signal CLK1 is output from the OR circuit 51, and the OR circuit 52 is fixed at the H level. An output signal is output. Therefore, the AND circuit 53 in this case outputs the output signal of the OR circuit 51, that is, the input clock signal CLK1 as the output clock signal CLKOUT. On the other hand, for example, when the mask signal MASK is at the H level, both the OR circuits 51 and 52 output the H level fixed output signal, so that the AND circuit 53 outputs the H level fixed output clock signal CLKOUT. Is done. As described above, the clock selection circuit 40 outputs the input clock signal CLK1, CLK2 or a signal fixed to the H level as the output clock signal CLKOUT in accordance with the mask signal MASK and the selection signal SELa.

  The release circuit 60 in this case includes inverter circuits 75, 76, 77, OR circuits 78, 79 having three input terminals, and an AND circuit 80. The OR circuit 78 receives the input clock signal CLK1, the selection signal SELa, and a signal obtained by logically inverting the mask signal MASK by the inverter circuit 75. The OR circuit 79 receives an input clock signal CLK2, a signal obtained by logically inverting the selection signal SELa by the inverter circuit 76, and a signal obtained by logically inverting the mask signal MASK by the inverter circuit 77. The AND circuit 80 outputs the mask release signal MR having a result obtained by performing an AND operation on the output signal of the OR circuit 78 and the output signal of the OR circuit 79. In such a release circuit 60, for example, when the mask signal MASK is at the H level and the selection signal SELa is at the L level, the input clock signal CLK1 is output from the OR circuit 78, and the OR circuit 79 outputs a fixed H level. A signal is output. Therefore, the AND circuit 80 in this case outputs the output signal of the OR circuit 78, that is, the input clock signal CLK1 as the mask release signal MR. Therefore, when the input clock signal CLK1 transits from L level to H level, the mask release signal MR also transits from L level to H level. Then, the generation of the mask signal MASK is stopped in response to the rising edge of the mask release signal MR. On the other hand, for example, when the mask signal MASK is at the L level, an output signal fixed at the H level is output from both the OR circuits 78 and 79, so that the AND circuit 80 outputs a mask release signal MR at the H level fixed. Is done.

  -You may make it combine the said 1st Embodiment and each said modification suitably. For example, in the clock switching circuit 1 shown in FIG. 8, the clock selection circuit 40 and the release circuit 60 shown in FIG. 8 may be changed to the clock selection circuit 40 and the release circuit 60 shown in FIG.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. 14 and 15. The clock switching circuit 1A of this embodiment is different from the first embodiment in that the number of input clock signals to be selected is increased from two to eight. Hereinafter, the difference from the first embodiment will be mainly described.

  As illustrated in FIG. 14, the clock switching circuit 1A includes a synchronization circuit 10A, a detection circuit 20A, a mask signal generation circuit 30, a clock selection circuit 40A, and a release circuit 60.

The synchronization circuit 10 </ b> A includes FF groups 13 </ b> A to 13 </ b> C including D-FFs 11 and 12. The FF groups 13A to 13C are respectively supplied with 3-bit selection signals SEL1 to SEL3 necessary for selecting one input clock signal from the eight input clock signals CLK1 to CLK8. Here, when the number of input clock signals to be selected is N, the FF group in the synchronization circuit 10A is log ₂ N (rounded up after the decimal point), here log ₂ 8 = log ₂ 2 ³ = 3. One is provided.

  The FF group 13A synchronizes the selection signal SEL1 at the rising edge of the output clock signal CLKOUT, and outputs the synchronized selection signal SEL1a to the detection circuit 20A and the clock selection circuit 40A. The FF group 13B synchronizes the selection signal SEL2 with the rising edge of the output clock signal CLKOUT, and outputs the synchronized selection signal SEL2a to the detection circuit 20A and the clock selection circuit 40A. The FF group 13C synchronizes the selection signal SEL3 at the rising edge of the output clock signal CLKOUT, and outputs the synchronized selection signal SEL3a to the detection circuit 20A and the clock selection circuit 40A.

The detection circuit 20 </ b> A includes detection units 23 </ b> A to 23 </ b> C including an inverter circuit 21 and an XOR circuit 22, and an AND circuit 25. Selection signals SEL1a to SEL3a are supplied to the detectors 23A to 23C, respectively. Here, when the number of input clock signals to be selected is N, the number of detection units in the detection circuit 20A is log ₂ N (rounded up after the decimal point), here, log ₂ 8 = 3.

  The detection unit 23A outputs an L level output signal from the XOR circuit 22 when detecting a change in the signal level of the selection signal SEL1a. The detection unit 23B outputs an L level output signal from the XOR circuit 22 when detecting a change in the signal level of the selection signal SEL2a. The detection unit 23C outputs an L level output signal from the XOR circuit 22 when detecting a change in the signal level of the selection signal SEL3a. The AND circuit 25 generates a mask start signal MS having a result obtained by performing an AND operation on the output signals of the XOR circuits 22 in the detection units 23A to 23C, that is, the three XOR circuits 22. That is, the AND circuit 25 generates an L-level mask start signal MS when a change in the signal level of any one of the selection signals SEL1a to SEL3a is detected in the detection units 23A to 23C. The mask start signal MS is supplied to the clear terminal of the D-FF 31 in the mask signal generation circuit 30.

  The clock selection circuit 40A includes a selector 41A and an OR circuit 42. The selector 41A selects any one of the input clock signals CLK1 to CLK8 according to the selection signals SEL1a to SEL3a, and outputs the selected input clock signal as the selected clock signal SCLK. For example, when all the selection signals SEL1a to SEL3a are at the L level, the input clock signal CLK1 is output as the selection clock signal SCLK, and when all the selection signals SEL1a to SEL3a are at the H level, the input clock signal CLK8 is output as the selection clock signal SCLK. The This selected clock signal SCLK is supplied to the OR circuit 42 and also to the NAND circuit 61 in the release circuit 60.

Next, the operation of the clock switching circuit 1A will be described with reference to FIG. Here, an operation of switching from the input clock signal CLK2 to the input clock signal CLK8 will be described.
Immediately before time t14, the selection signal SEL1a is at the H level, the selection signal SEL2a is at the L level, and the selection signal SEL3a is at the L level, and the input clock signal CLK2 is output as the output clock signal CLKOUT in accordance with these selection signals SEL1a to SEL3a Has been. Thereafter, at time t14, the selection signals SEL2a and SEL3a are changed from the L level to the H level in order to switch from the input clock signal CLK2 to the input clock signal CLK8. Then, the selection signals SEL2a and SEL3a are synchronized with the output clock signal CLKOUT (here, the input clock signal CLK2), and the H-level selection signals SEL2a and SEL3a are output in synchronization with the rising edge of the output clock signal CLKOUT. (Time t15).

  When these selection signals SEL2a and SEL3a transition from the L level to the H level, in response to the transition (change), an L level output signal is output from the detection units 23B and 23C for a predetermined period, and the AND circuit 25 outputs the L level signal. The mask start signal MS is output for a predetermined period. In response to the L level mask start signal MS, the D-FF 31 outputs an H level mask signal MASK.

  On the other hand, in the clock selection circuit 40, the input clock signal CLK8 is selected by the selector 41 in accordance with the selection signals SEL1a to SEL3a after the transition, and the input clock signal CLK8 is output as the selection clock signal SCLK. In other words, the selector 41 switches from the input clock signal CLK2 to the input clock signal CLK8 in accordance with the H level selection signals SEL1a to SEL3a. However, since the H level mask signal MASK is input to the OR circuit 42 at this time, the selection clock signal SCLK is masked by the mask signal MASK, and the output clock signal CLKOUT is fixed to the H level.

  At time t15, the mask release signal MR transits to L level in response to the H level mask signal MASK and the L level selected clock signal SCLK. Thereafter, when the selected clock signal SCLK (here, the input clock signal CLK8) transitions to the H level (time t16), the mask release signal MR rises to the H level. In response to the rising edge of the mask release signal MR, the mask signal MASK changes from the H level to the L level. Then, since the mask for the selected clock signal SCLK is released, the selected clock signal SCLK (here, the input clock signal CLK8 after the clock switching) is output as the output clock signal CLKOUT. In this way, switching from the input clock signal CLK2 to the input clock signal CLK8 is completed.

According to this embodiment described above, the same effects as those of the first embodiment can be obtained.
(Modification of the second embodiment)
The circuits 10A, 20A, 30, 40A, and 60 in the clock switching circuit 1A of the second embodiment may be changed in the same manner as the modification of the first embodiment.

  -The internal configuration example of the release circuit 60 in the second embodiment is not particularly limited. For example, a delay circuit that delays the mask signal MASK by a predetermined time may be provided before the NAND circuit 61. As a result, the NAND circuit 61 outputs the selected clock signal SCLK as the output clock signal CLKOUT after a predetermined time has elapsed since the mask signal MASK was changed to the H level. Therefore, it is preferable that the selection clock signal SCLK (input clock signal before clock switching) is output from the NAND circuit 61 as the output clock signal CLKOUT before the clock switching by the selector 41A in the clock selection circuit 40A is completed. Can be suppressed.

  -The internal configuration example of the detection circuit 20 in the second embodiment is not particularly limited. For example, a delay circuit that outputs a signal obtained by delaying the mask start signal MS output from the AND circuit 25 by a predetermined time to the AND circuit 25 may be provided. Thereby, after the mask start signal MS is transited to the L level, the output of the L level mask start signal MS can be maintained for a predetermined time.

(Other embodiments)
In addition, each said embodiment can also be implemented in the following aspects which changed this suitably.
In each of the above embodiments, the clock switching circuit that switches the input clock signals CLK1 and CLK2 (or the input clock signals CLK1 to CLK8 of the second embodiment) that are asynchronous clocks is embodied. The clock switching circuit for switching the input clock signal may be embodied. For example, the present invention may be embodied in a clock switching circuit that switches between the input clock signal CLK1 and the input clock signal CLK2 generated by dividing the input clock signal CLK1.

  In the above embodiments, the input clock signals CLK1 and CLK2 are switched according to the selection signal SEL that is an asynchronous signal with respect to the input clock signals CLK1 and CLK2. Further, the input clock signals CLK1 to CLK8 are switched according to the selection signals SEL1 to SEL3 which are asynchronous signals with respect to the input clock signals CLK1 to CLK8. For example, the input clock signals CLK1 to CLK8 may be switched according to a selection signal synchronized with at least one of the input clock signals CLK1 to CLK8.

1, 1A clock switching circuit 10, 10A synchronization circuit 20, 20A detection circuit 21 inverter circuit 22 XOR circuit (first logic circuit)
30 mask signal generation circuit 40, 40A clock selection circuit 41, 41A selector (selection circuit)
42 OR circuit (second logic circuit)
60 Release circuit CLK1 to CLK8 Input clock signal CLKOUT Output clock signal SEL, SEL1, SEL2, SEL3 selection signal SELa, SEL1a, SEL2a, SEL3a selection signal (selection signal after synchronization)
MASK mask signal MS mask start signal MR mask release signal IS initialization signal SCLK selection clock signal

Claims (9)

A clock switching circuit that selects any one input clock signal from a plurality of input clock signals according to a selection signal and outputs the selected clock signal as an output clock signal;
A synchronization circuit for synchronizing the selection signal based on the output clock signal;
A detection circuit that generates a mask start signal when a change in signal level of the selection signal after synchronization is detected;
A mask signal generation circuit for generating a mask signal for masking the plurality of input clock signals at a predetermined level based on the mask start signal;
A clock that outputs one input clock signal selected from the plurality of input clock signals or a signal fixed at the predetermined level as the output clock signal based on the selection signal after synchronization and the mask signal A selection circuit;
A release circuit that generates a mask release signal when a transition to the predetermined level of the input clock signal selected by the selection signal after synchronization is detected, and
The clock switching circuit, wherein the mask signal generation circuit stops generating the mask signal based on the mask release signal. The synchronization circuit synchronizes the selection signal in response to a transition of the output clock signal from a first level to a second level;
The release circuit responds to a transition from the first level to the second level of an input clock signal selected by the selection signal after synchronization when the predetermined level is the second level. 2. The clock switching circuit according to claim 1, wherein a mask release signal is generated. The synchronization circuit is initialized by an initialization signal and generates a signal set to a predetermined level as the selection signal after the synchronization,
3. The clock switching circuit according to claim 1, wherein the mask signal generation circuit is initialized by the initialization signal and stops generating the mask signal.   The mask signal generation circuit generates the mask signal when the initialization signal is input as the mask start signal, stops generating the mask signal based on the mask release signal, and completes the initialization. The clock switching circuit according to claim 3. The cancellation circuit detects the transition of the input clock signal selected according to the synchronized selection signal generated by the initialization based on the initialization signal when the transition to the predetermined level is detected. Generate a release signal,
The clock signal generation circuit according to claim 3, wherein the mask signal generation circuit stops generation of the mask signal based on the mask release signal generated based on the initialization signal and completes the initialization. Switching circuit.   6. The clock switching circuit according to claim 1, wherein the synchronization circuit includes a plurality of stages of flip-flop circuits that take in the selection signal in accordance with the output clock signal.   The detection circuit is configured to generate an odd-stage inverter circuit that generates a signal obtained by logically inverting the synchronized selection signal, and in response to a match between the synchronized selection signal and the output signal of the inverter circuit. The clock switching circuit according to claim 1, further comprising a first logic circuit that generates a mask start signal.   The clock selection circuit selects one input clock signal from a plurality of input clock signals according to the synchronized selection signal, and outputs the selected clock signal as a selection clock signal. The clock switching circuit according to claim 1, further comprising: a second logic circuit that masks the selected clock signal at the predetermined level. The release circuit generates the mask release signal according to the signal level of the selected clock signal in response to the mask signal,
9. The clock switching circuit according to claim 8, wherein the mask signal generation circuit includes a flip-flop circuit that inputs the mask release signal to a clock terminal and outputs the mask signal.