JP2010252012A - Semiconductor integrated circuit and operating method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the occurrence probability of a meta-stable failure in the last selection output of a clock selection circuit. <P>SOLUTION: The clock selection circuit incorporated in a semiconductor integrated circuit includes a decoder DEC, a control unit Cnt, and a multiplexer Mpx. A selection signal SEL is supplied to the DEC, first and second clock signals CKIN0 and 1 and first and second selection output signals of the decoder DEC are supplied to the Cnt, and first and second selection control signals Q'0 and 1 of the Cnt are supplied to the Mpx. The first and second selection output signals of the DEC are supplied to one input of first and second gates AND0 and 1 of the Cnt. First and second D type flip-flops D-FF0 and 2 connected in series are included between an output of the first gate AND0 and the other input of the second gate AND1, and third and fourth D type flip-flops D-FF1 and 3 connected in series are included between an output of the second gate AND1 and the other input of the first gate AND0. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a method for operating the same, and more particularly to a technique useful for reducing the occurrence probability of a metastable failure in a clock selection circuit.

  Patent Document 1 below describes a multiplexer that is supplied with a plurality of selection signals and a plurality of input signals and prevents glitches at the time of selection switching. In order to prevent the occurrence of glitches, when one selection signal of the plurality of selection signals is set to the selection level, one selection signal at the selection level is supplied to the multiplexer until the other selection signal becomes the non-selection level. It is prevented from being supplied.

  Non-Patent Document 1 below describes a synchronizer that generates a synchronization signal from an output by supplying an asynchronous signal and a clock. If the synchronizer is a single stage consisting of a single D-type flip-flop (FF), if the asynchronous input signal changes state too close to the clock transition, the setup and hold times of the flip-flop A violation occurs and a metastable occurs. Then, the propagation delay increases, and the time for the output to recover to the high level or the low level also increases due to the increase of the propagation delay. The time until the metastable is generated in the output of the synchronizer is called a mean time between failure (MTBF).

  Furthermore, the following Non-Patent Document 1 describes that by using a two-stage synchronizer, the metastable defect interval average time is increased by several orders of magnitude as compared with a single-stage synchronizer. In the two-stage synchronizer, two FFs are cascade-connected, an asynchronous input signal is supplied to the data input terminal D of the first-stage FF, and the data output signal Q of the first-stage FF is the second-stage FF. The clock signal is supplied in common to the trigger input of the first stage FF and the trigger input of the second stage FF, supplied to the data input terminal D, and the synchronous output signal is generated from the data output signal Q of the second stage FF. Generated. A metastable output may be generated in the data output signal Q of the first stage FF in response to the rising edge of the first clock pulse of the clock signal. In response to the rising edge, a high-level or low-level stable synchronous output signal can be generated for the data output signal Q of the second-stage FF.

JP-A-2005-174344

Tom Jackson, “FIFO Memories: Solution to Reduce FIFO Metastability”, First-In, First-Out Technology, SCAA011A March 1996, pp. 1-6, TEXAS INSTRUMENTS http: // focus. ti. com / lit / an / sca011a / sca011a. pdf [Search March 3, 2009]

  Prior to the present invention, the present inventors engaged in research and development of microcontrollers and system LSIs using a plurality of asynchronous clock sources.

  In the field of microcontrollers, system LSIs, and the like, there are many cases where a plurality of asynchronous clock sources are used. As one of a plurality of asynchronous clock sources, for example, there is a multiplied clock generated by a phase-locked loop (PLL) voltage-controlled oscillator from a reference frequency signal generated by a crystal resonator outside the chip. Other clock sources include an oscillation clock of a free-run on-chip oscillator prepared for a user who does not use an external crystal oscillator for system cost reduction, and a clock signal input supplied from the outside of the chip. From the viewpoint of ensuring system reliability, a watchdog timer for detecting system runaway and deadlock is required to operate with a clock source independent of the system clock.

  Since these asynchronous clock sources are not related to frequency division or multiplication, the phase relationship is unknown. One of the plurality of clock sources is selected and distributed as a system clock to an internal core such as a clock to the CPU and peripheral IP in the chip. No glitch is generated at the time of switching, it is necessary to reduce the failure probability of flip-flops and latch metastables, which can be a problem with asynchronous signal synchronization, to ensure practical reliability, and to switch at high speed. Become.

  In particular, when a certain event is detected to switch to a high-speed operation of 100 MHz from a low-speed and low-power operation state of 32 kHz, the large switching latency becomes a fatal performance deterioration in an application that requires real-time characteristics. Therefore, it is necessary to simultaneously achieve prevention of glitches, reduction of metastable failure probability, and reduction of switching latency.

  FIG. 1 is a diagram showing a configuration of a multiplexer as a clock selection circuit studied by the present inventors prior to the present invention.

  The multiplexer as a clock selection circuit shown in FIG. 1 includes first and second CMOS analog switches 101 and 102, an inverter 103, and a buffer amplifier 104. The first clock input signal CKIN0 is supplied to the signal input terminal of the first CMOS analog switch 101, the selection signal SEL and the output signal of the inverter 103 are supplied to the control input terminal of the first CMOS analog switch 101, The output signal of the first CMOS analog switch 101 is supplied to the input terminal of the buffer amplifier 104. The second clock input signal CKIN1 is supplied to the signal input terminal of the second CMOS analog switch 102, the output signal of the inverter 103 and the selection signal SEL are supplied to the control input terminal of the second CMOS analog switch 102, The output signal of the second CMOS analog switch 102 is supplied to the input terminal of the buffer amplifier 104.

  The first CMOS analog switch 101 includes a P-channel MOS transistor Qp1 and an N-channel MOS transistor Qn1 whose source / drain current paths are connected in parallel, a selection signal SEL is supplied to the gate electrode of the transistor Qp1, and the gate electrode of the transistor Qn1 Is supplied with the output signal of the inverter 103. The second CMOS analog switch 102 also includes a P-channel MOS transistor Qp2 and an N-channel MOS transistor Qn2 whose source / drain current paths are connected in parallel. The output signal of the inverter 103 is supplied to the gate electrode of the transistor Qp2, and the transistor Qn2 A selection signal SEL is supplied to the gate electrode.

  Since the first CMOS analog switch 101 is controlled to be in the on state and the second CMOS analog switch 102 is controlled to be in the off state while the selection signal SEL is at the low level “0”, the first clock input signal CKIN0 is The selected signal is output as the output clock signal CKOUT of the buffer amplifier 104. On the contrary, while the selection signal SEL is at the high level “1”, the first CMOS analog switch 101 is controlled to be in the off state and the second CMOS analog switch 102 is controlled to be in the on state. The signal CKIN1 is selected and output as the output clock signal CKOUT of the buffer amplifier 104.

  FIG. 2 is a diagram showing waveforms at various parts of the multiplexer as the clock selection circuit shown in FIG.

  As shown in FIG. 2, the first clock input signal CKIN0 has a relatively low clock frequency, while the second clock input signal CKIN1 has a relatively high clock frequency. As described above, the first clock input signal CKIN0 having a relatively low clock frequency is selected and output as the output clock signal CKOUT while the selection signal SEL is at the low level “0”. During 1 ″, the second clock input signal CKIN1 having a relatively high clock frequency is selected and output as the output clock signal CKOUT.

  However, as shown in FIG. 2, at the clock selection switching timings 201, 202, 203, and 204, it is understood that a pulse with a small pulse width is generated as the output clock signal CKOUT and a glitch occurs. Although the levels of the first and second clock input signals CKIN0 and CKIN1 at the two timings 201 and 202 in the first half are different from each other, a glitch having a small pulse width is generated. Although the levels of the first and second clock input signals CKIN0 and CKIN1 at the two timings 203 and 204 in the latter half are the same, a glitch having a small pulse width is also generated. As a result, it cannot be guaranteed that the pulse width of the output clock generated in the output clock signal CKOUT is equal to the pulse width of one of the first and second clock input signals CKIN0 and CKIN1. That is, the pulse width and edge interval of the glitch generated in the output clock signal CKOUT are shorter than the cycle of the highest frequency clock of the first and second clock input signals CKIN0 and CKIN1.

  Therefore, since the pulse width and edge interval of the output clock signal CKOUT cannot be guaranteed, various problems occur when the output clock signal CKOUT is distributed as a system clock to various internal cores of a microcontroller or system LSI. . For example, a malfunction of the metastable or the like is caused by a violation of the setup of the flip-flop of the internal core. Further, if the pulse width of the output clock signal CKOUT becomes extremely narrow and the pulse disappears, the operation cycle of the internal core may be delayed.

  In order to prevent glitches in a multiplexer that is supplied with a plurality of selection signals and a plurality of input signals and performs selection switching, the method described in Patent Document 1 can be employed. According to the method described in Patent Document 1, when one selection signal of a plurality of selection signals is set to a selection level in order to prevent the occurrence of glitches, until another selection signal becomes a non-selection level. One selection signal of the selection level is prevented from being supplied to the multiplexer.

  FIG. 3 is a diagram showing a configuration of a clock selection circuit studied by the present inventors prior to the present invention based on the description in Patent Document 1.

  The clock selection circuit shown in FIG. 3 includes an inverter INV0 as a decoder DEC, first and second AND circuits AND0 and AND1 of the control unit Cnt, and first and second D-type flip-flops D-FF0 and D-FF1, It is configured by a multiplexer Mpx. The first and second D-type flip-flops D-FF0 and D-FF1 are delay type flip-flops. In these D-type flip-flops, the triangle symbol to which the clock signals CKIN0 and CKIN1 are supplied means the edge trigger terminal, and the triangle symbol circles the input data as the output data in response to the falling edge of the clock signal. Means to be communicated to.

  The selection signal SEL is supplied to the input terminal of the inverter INV0 and one input terminal of the second AND circuit AND1, and the output signal of the inverter INV0 is supplied to one input terminal of the first AND circuit AND0. The output signal D0 of the first AND circuit AND0 is supplied to the data input terminal of the first D-type flip-flop D-FF0, while the output signal D1 of the second AND circuit AND1 is supplied to the second D-type flip-flop D. -Supplied to the data input terminal of FF1. The output data Q0 of the first D-type flip-flop D-FF0 is supplied to the inverting input terminal as the other input terminal of the second AND circuit AND1, while the output data of the second D-type flip-flop D-FF1 Q1 is supplied to the inverting input terminal as the other input terminal of the first AND circuit AND0.

  The multiplexer Mpx includes third and fourth AND circuits AND2 and AND3, and an OR circuit OR0. The output data Q0 of the first D-type flip-flop D-FF0 is supplied to one input terminal of the third AND circuit AND2, while the second D-type flip-flop is supplied to one input terminal of the fourth AND circuit AND3. The output data Q1 of the D-FF1 is supplied. The first clock signal CKIN0 is supplied to the falling edge trigger terminal of the first D-type flip-flop D-FF0 and the other input terminal of the third AND circuit AND2, while the second D-type flip-flop D is supplied. The second clock signal CKIN1 is supplied to the falling edge trigger terminal of -FF1 and the other input terminal of the fourth AND circuit AND3. Further, the first clock output signal CKG0 of the third AND circuit AND2 and the second clock output signal CKG1 of the fourth AND circuit AND3 are respectively supplied to one input terminal and the other input terminal of the OR circuit OR0. A clock output signal CKOUT is generated from the output terminal of the OR circuit OR0.

  As shown in the lower part of FIG. 3, the first and second D-type flip-flops D-FF0 and D-FF1 are configured by master / slave latches. A master latch (Master-Latch) and a slave latch (Slave-Latch) of the master-slave latch are configured by first and second inverters Inv1 and Inv2 that are cross-coupled to the switch SW, respectively. . The second inverter Inv2 includes a clocked inverter driven by non-inverted clock signals CKIN0 and CKIN1 and an inverted clock signal. For example, in the second D-type flip-flop D-FF1, the output signal D1 of the second AND circuit AND1 is in the master latch (Master-Latch) during the high level “1” of the second clock signal CKIN1. The signal is transmitted to the input terminal of the first inverter Inv1 via the switch SW in the on state. During this time, in the slave latch (Slave-Latch), the switch SW is turned off, and the output data Q1 held by the cross-coupled first and second inverters Inv1, Inv2 is output. In the second D-type flip-flop D-FF1, the switch SW is turned off in the master latch (Master-Latch) while the second clock signal CKIN1 is at the low level “0”. The output signal D1 of the second AND circuit AND1 is held by the connected first and second inverters Inv1 and Inv2. During this time, the output signal of the first inverter Inv1 of the master latch (Master-Latch) is transmitted to the slave latch (Slave-Latch) and input to the first inverter Inv1 via the switch SW in the ON state. Is transmitted to the terminal. Furthermore, the first D-type flip-flop D-FF0 operates in the same manner as the second D-type flip-flop D-FF1 in response to the first clock signal CKIN0. As a result, the first and second D-type flip-flops D-FF0 and D-FF1 respond to the falling edges of the first and second clock signals CKIN0 and CKIN1, respectively. , D1 level is output as first and second output data Q0, Q1.

  FIG. 4 is a diagram illustrating a state in which the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit illustrated in FIG.

  In FIG. 4, first, at timing T0, the selection signal SEL changes from low level “0” (selection of the first clock signal CKIN0) to high level “1” (selection of the second clock signal CKIN1). At timing T1 slightly delayed from timing T0, the output signal D0 of the first AND circuit AND0 changes from high level “1” to low level “0”. At the next timing T2, the first clock signal CKIN0 rises from the low level “0” to the high level “1”. However, the first D-type flip-flop D-FF0 composed of the master / slave latches receives the first input signal D0 at the low level “0” in response to the rising edge of the first clock signal CKIN0. The first output data Q0 at the high level “1” is held without being output as the output data Q0. Further, at the next timing T3, the first clock signal CKIN0 falls from the high level “1” to the low level “0”. Therefore, the first D-type flip-flop D-FF0 configured by the master / slave latch has the first input of the low level “0” at the timing T4 slightly delayed from the falling edge of the first clock signal CKIN0. The signal D0 is output as the first output data Q0. As a result, in the period from the timing T0 to the timing T4, the first output data Q0 of the first D-type flip-flop D-FF0 is held at the high level “1”. Accordingly, during this period, the first clock signal CKIN0 is selected as the first clock output signal CKG0 by the third AND circuit AND2 of the multiplexer Mpx, and the clock output signal CKOUT of the OR circuit OR0 is generated.

  At the timing T5 when the first output data Q0 of the first D-type flip-flop D-FF0 at the timing T4 is slightly delayed from the falling from the high level “1” to the low level “0”, the second AND circuit The output signal D1 of the AND1 changes from the low level “0” to the high level “1”. At the next timing T6, the second clock signal CKIN1 falls from the high level “1” to the low level “0”. Accordingly, the second D-type flip-flop D-FF1 formed of the master / slave latch has the second input signal of the high level “1” at the timing T7 slightly delayed from the falling edge of the second clock signal CKIN1. D1 is output as the second output data Q1. As a result, in the period from the timing T7, the second output data Q1 of the second D-type flip-flop D-FF1 is held at the high level “1”. Accordingly, during this period, the fourth clock AND signal AND3 of the second clock signal CKIN01 multiplexer Mpx is selected as the second clock output signal CKG1, and the clock output signal CKOUT of the OR circuit OR0 is generated.

  When the selection state of the first clock signal CKIN0 in the clock selection circuit of FIG. 3 shown in FIG. 4 is switched to the selection state of the second clock signal CKIN1, the first input signal D0 and the first clock signal CKIN0 are switched. Neither the timing relationship nor the timing relationship between the second input signal D1 and the second clock signal CKIN1 causes a setup or hold violation. Accordingly, the second output data Q1 at the high level “1” for selecting the second clock signal CKIN1 after switching after the selection signal SEL changes from the low level “0” to the high level “1” at the timing T0 is output. The switching latency up to timing T7 can be made relatively short.

  In the clock selection circuit shown in FIG. 3, the first output data Q0 selected by the first clock signal CKIN0 is changed when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1. The second output data Q1 selected by the second clock signal CKIN1 is selected from the low level “0” to the high level “1” unless the mode is changed from the high level “1” to the low level “0”. It is impossible to make a transition to Therefore, according to the clock selection circuit shown in FIG. 3, another clock signal selected after the transition of the non-selected clock signal from the high level “1” to the low level “0” is made. Therefore, the occurrence of glitches can be prevented.

  FIG. 5 shows that when the clock selection circuit shown in FIG. 3 is switched from the selection state of the first clock signal CKIN0 to the selection state of the second clock signal CKIN1, a violation occurs between the setup time and the hold time of the flip-flop. It is a figure which shows a mode that a metastable generate | occur | produces.

  A setup time violation occurs when the state change of the asynchronous input signal preceding the clock transition is too close to the clock transition. The hold time violation occurs when the state change of the asynchronous input signal following the clock transition is too close to the clock transition.

  At timing 2101 in FIG. 5, since the falling state change of the output signal D0 of the first AND circuit AND0 which is an asynchronous input signal is too close to the transition of the falling edge of the first clock signal CKIN0, A violation of the setup time and hold time of the first D-type flip-flop D-FF0 occurs. Therefore, at the next timing 2102 in FIG. 5, a failure of the metastable of the first D-type flip-flop D-FF0 occurs. That is, the first output data Q0 of the first D-type flip-flop D-FF0 maintains an intermediate level between the high level “1” and the low level “0” for a relatively long time. It takes a relatively long time to recover to the level “1” or the low level “0”. The relatively long time of this metastable is assumed to be one cycle of the second clock signal CKIN1. Since the first output data Q0 of the intermediate level first D-type flip-flop D-FF0 is supplied to the inverting input terminal of the second AND circuit AND1, the output signal D1 of the second AND circuit AND1 is also relatively high. Become intermediate level in a long time. On the other hand, the second D-type flip-flop D-FF1 outputs the level of the second input signal D1 as the second output data Q1 in response to the falling edge of the second clock signal CKIN1. As a result, the intermediate level second input signal D1 is output as a second output data Q1 of the second D-type flip-flop D-FF1 in a relatively long time.

  Therefore, an intermediate level is also generated in the second clock output signal CKG1 of the fourth AND circuit AND3 of the multiplexer Mpx, and at the timing 2103 in FIG. 5, an intermediate level is generated in the clock output signal CKOUT of the OR circuit OR0. A glitch having a short pulse width is generated.

  As described above, when the clock selection circuit shown in FIG. 3 is used to switch the selection between the first clock signal CKIN0 and the second clock signal CKIN1, a metastable failure occurs with a certain probability. It is. The occurrence probability of the metastable failure depends on the probability that the setup time and the hold time are violated. The probability that this violation occurs depends on the time width in which the violation between the setup time and the hold time occurs and the frequency of the asynchronous input signal and the clock signal.

  In general, in the case of a single-stage synchronizer that samples an asynchronous signal with a normal single flip-flop, for example, a product failure rate of 0.1% with a product lifetime of 10 years, that is, 1,000 products operating simultaneously. There is no guarantee of realistic reliability that one will fail once every 10 years. A semiconductor integrated circuit such as a microcontroller, system LSI, or the like that has a clock selection circuit that prevents glitches, reduces the probability of metastable failure, and enables high-speed clock switching with extremely high operational reliability. It is required to be mounted on.

  The present invention has been made as a result of the study of the present inventors prior to the present invention as described above.

  Accordingly, an object of the present invention is to reduce the probability of occurrence of a metastable failure at the final selection output terminal of the clock selection circuit.

  Another object of the present invention is to prevent glitches at the final selection output terminal of the clock selection circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a typical embodiment of the present invention is a semiconductor integrated circuit including a clock selection circuit having a decoder (DEC), a control unit (Cnt), and a multiplexer (Mpx).

  The selection signal (SEL) is supplied to the decoder (DEC), the first and second clock signals (CKIN0, CKIN1) and the first and second selection output signals from the decoder (DEC) are supplied to the control unit (Cnt). The first and second clock signals and the first and second selection control signals (Q′0, Q ″ 0, Q′1, Q ′) from the control unit (Cnt) are supplied to the multiplexer (Mpx). '1) is supplied.

  The control unit (Cnt) includes first and second gate circuits (AND0, AND1), and the first and second gate circuits from the decoder are connected to one input terminal of the first and second gate circuits. A selection output signal is provided.

  The control unit (Cnt) includes first and second Ds connected in series between an output terminal of the first gate circuit (AND0) and the other input terminal of the second gate circuit (AND1). Type flip-flops (D-FF0, D-FF2) and a second terminal connected in series between the output terminal of the second gate circuit (AND1) and the other input terminal of the first gate circuit (AND0). 3 and a fourth D-type flip-flop (D-FF1, D-FF3) (see FIG. 6).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to reduce the probability of occurrence of a metastable failure at the final selection output terminal of the clock selection circuit.

FIG. 1 is a diagram showing a configuration of a multiplexer as a clock selection circuit studied by the present inventors prior to the present invention. FIG. 2 is a diagram showing waveforms at various parts of the multiplexer as the clock selection circuit shown in FIG. FIG. 3 is a diagram showing a configuration of a clock selection circuit studied by the present inventors prior to the present invention based on the description in Patent Document 1. In FIG. FIG. 4 is a diagram illustrating a state in which the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit illustrated in FIG. FIG. 5 shows that when the clock selection circuit shown in FIG. 3 is switched from the selection state of the first clock signal CKIN0 to the selection state of the second clock signal CKIN1, a violation occurs between the setup time and the hold time of the flip-flop. It is a figure which shows a mode that a metastable generate | occur | produces. FIG. 6 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 7 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the first embodiment of the present invention shown in FIG. FIG. FIG. 8 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 9 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the second embodiment of the present invention shown in FIG. FIG. FIG. 10 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 11 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the third embodiment of the present invention shown in FIG. FIG. FIG. 12 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the fourth embodiment of the present invention. FIG. 13 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the fourth embodiment of the present invention shown in FIG. FIG. FIG. 14 is a diagram showing a configuration of the fourth AND circuit AND3 of the multiplexer Mpx of the clock selection circuit of FIG. FIG. 15 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the fifth embodiment of the present invention. FIG. 16 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the sixth embodiment of the present invention. FIG. 17 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the sixth embodiment of the present invention shown in FIG. FIG. FIG. 18 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the seventh embodiment of the present invention. FIG. 19 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the seventh embodiment of the present invention shown in FIG. FIG. FIG. 20 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the eighth embodiment of the present invention. FIG. 21 is a diagram showing the configuration of the semiconductor integrated circuit according to the ninth embodiment of the present invention.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A typical embodiment of the present invention includes a decoder (DEC) to which a selection signal (SEL) is supplied, a first clock signal (CKIN0) and a second clock signal (CKIN1), and a first clock signal from the decoder. A control unit (Cnt) to which at least one selection output signal and a second selection output signal are supplied, and the first clock signal, the second clock signal, and a first selection control signal (Q′0, Q from the control unit) ″ ″ 0) and a second selection control signal (Q′1, Q ″ 1) are semiconductor integrated circuits including a clock selection circuit having at least a multiplexer (Mpx) to which the signals are supplied.

  The control unit (Cnt) includes a first gate circuit (AND0) to which the first selection output signal from the decoder is supplied to one input terminal, and the second selection output signal from the decoder as one And a second gate circuit (AND1) supplied to the input terminal.

  The control unit (Cnt) includes first and second Ds connected in series between an output terminal of the first gate circuit (AND0) and the other input terminal of the second gate circuit (AND1). Type flip-flops (D-FF0, D-FF2) and a second terminal connected in series between the output terminal of the second gate circuit (AND1) and the other input terminal of the first gate circuit (AND0). 3 and a fourth D-type flip-flop (D-FF1, D-FF3) (FIG. 6, FIG. 8, FIG. 10, FIG. 12, FIG. 15, FIG. 18, FIG. 18). , See FIG.

  According to the embodiment, the first and second D-type flip-flops (D-FF0 and D-FF2) and the third and fourth D of the control unit (Cnt) included in the clock selection circuit. The type flip-flops (D-FF1, D-FF3) constitute the two-stage synchronizers described in Non-Patent Document 1, respectively. Therefore, it is possible to reduce the probability of occurrence of a metastable failure in the clock output signal (CKOUT) from the final output terminal of the multiplexer (Mpx) of the clock selection circuit (FIGS. 7, 9, 11, and 11). 13, FIG. 17, FIG. 19).

  In a preferred embodiment, the other input terminal of the second gate circuit (AND1) through the first and second D-type flip-flops (D-FF0, D-FF2) connected in series. Is supplied with a signal of the non-selection level of the output terminal of the first gate circuit (AND0), the second clock signal (CKIN1) becomes the second gate circuit (Cnt) of the control unit (Cnt). The clock output signal (CKOUT) can be output via AND1) and the multiplexer (Mpx).

  The second gate circuit is connected to the other input terminal of the first gate circuit (AND0) via the third and fourth D-type flip-flops (D-FF1, D-FF3) connected in series. The first clock signal (CKIN0) is supplied to the first gate circuit (AND0) and the multiplexer (Mpx) of the control unit (Cnt) by supplying a non-selection level signal of the output terminal of (AND1). ) To be output as the clock output signal (CKOUT).

  According to the preferred embodiment, it is possible to exclusively select the first clock signal (CKIN0) and the second clock signal (CKIN1), and to prevent the occurrence of glitches.

  In another preferred embodiment, output data of the second D-type flip-flop (D-FF2) on the rear stage side of the first and second D-type flip-flops connected in series is the first data A selection control signal (Q′0, Q ″ 0) is transmitted to the multiplexer (Mpx) and to the other input terminal of the second gate circuit (AND1).

  The output data of the fourth D-type flip-flop (D-FF3) on the subsequent stage side of the third and fourth D-type flip-flops connected in series is the second selection control signal (Q′1, Q ″ ″ 1) is transmitted to the multiplexer (Mpx) and also transmitted to the other input terminal of the first gate circuit (AND0) (see FIGS. 6, 8, and 10).

  In a more preferred embodiment, the control unit (Cnt) further includes first and second latches (FF0, FF1).

  The data input terminal of the first latch (FF0) and the data input terminal of the second D-type flip-flop (D-FF2) are connected to the first and second D-type flip-flops connected in series. Output data of the first D-type flip-flop (D-FF0) on the preceding stage side is supplied in parallel, and output data of the first latch (FF0) is used as the first selection control signal (Q'0). It is transmitted to the multiplexer (Mpx).

  The data input terminal of the second latch (FF1) and the data input terminal of the fourth D-type flip-flop (D-FF3) are connected to the third and fourth D-type flip-flops connected in series. Output data of the third D-type flip-flop (D-FF1) on the front stage side is supplied in parallel, and output data of the second latch (FF1) is used as the second selection control signal (Q′1). It is transmitted to the multiplexer (Mpx) (see FIGS. 12, 15, 16, 18, and 20).

  In another more preferred embodiment, the gate control terminal (G) of the first latch (FF0) and the both edge trigger terminals of the first and second D-type flip-flops connected in series are: Responding to the first clock signal (CKIN0).

  The gate control terminal (G) of the second latch (FF1) and the edge trigger terminals of the third and fourth D-type flip-flops connected in series respond to the second clock signal (CKIN1). (See FIGS. 12, 15, 16, 18, and 20).

  In a further preferred embodiment, the control unit (Cnt) further includes first and second delay circuits (DELAY0, DELAY1).

  The input terminal of the first delay circuit (DELAY0) is connected to the edge trigger terminal of the first D-type flip-flop (D-FF0) on the preceding stage side, and the output terminal of the first delay circuit is the It is connected to the edge trigger terminal of the second D-type flip-flop (D-FF2) on the rear stage side.

  The input terminal of the second delay circuit (DELAY1) is connected to the edge trigger terminal of the third D-type flip-flop (D-FF1) on the preceding stage side, and the output terminal of the second delay circuit is It is connected to the edge trigger terminal of the fourth D-type flip-flop (D-FF3) on the rear stage side (see FIGS. 16, 18, and 20).

  In another more preferred embodiment, the gate control terminal (G) of the first latch (FF0) is one of the input terminal and the output terminal of the first delay circuit (DELAY0). Connected to the terminal.

  The gate control terminal (G) of the second latch (FF1) is connected to one of the input terminal and the output terminal of the second delay circuit (DELAY1) (FIG. 16, (See FIGS. 18 and 20).

  In a specific embodiment, the multiplexer (Mpx) includes third, fourth, and fifth gate circuits (AND2, AND3, OR0).

  One input terminal and the other input terminal of the third gate circuit (AND2) are connected to the first selection control signal (Q′0, Q ″ 0) from the control unit and the first clock signal ( CKIN0).

  One input terminal and the other input terminal of the fourth gate circuit (AND3) are connected to the second selection control signal (Q′1, Q ″ 1) from the control unit and the second clock signal ( CKIN1).

  A first clock output signal (CKG0) generated from the third gate circuit (AND2) and a second clock generated from the fourth gate circuit (AND3) to the fifth gate circuit (OR0). When the output signal (CKG1) is supplied, the fifth gate circuit (OR0) generates a clock output signal (CKOUT) as a final output of the multiplexer (Mpx) (FIG. 6, FIG. 8, FIG. 10, FIG. 12, FIG. 15, FIG. 16, FIG. 18, FIG.

    The semiconductor integrated circuit according to the most specific embodiment further includes a first clock signal source (1) for generating the first clock signal and a second clock signal source (2) for generating the second clock signal. It has.

  Either the first clock signal generated from the first clock signal source (1) or the second clock signal generated from the second clock signal source (2) is used as the selection signal (SEL). In response, the clock selection circuit generates the final output of the multiplexer (Mpx).

  [2] A typical embodiment according to another aspect of the present invention includes a decoder (DEC) to which a selection signal (SEL) is supplied, a first clock signal (CKIN0) and a second clock signal (CKIN1), A control unit (Cnt) to which at least a first selection output signal and a second selection output signal from a decoder are supplied, a first selection control signal (Q from the first clock signal, the second clock signal, and the control unit) The operation method of a semiconductor integrated circuit including a clock selection circuit having a multiplexer (Mpx) to which at least “0, Q ″ 0) and a second selection control signal (Q′1, Q ″ 1) are supplied. is there.

  The control unit (Cnt) includes a first gate circuit (AND0) to which the first selection output signal from the decoder is supplied to one input terminal, and the second selection output signal from the decoder as one And a second gate circuit (AND1) supplied to the input terminal.

  The control unit (Cnt) includes first and second Ds connected in series between an output terminal of the first gate circuit (AND0) and the other input terminal of the second gate circuit (AND1). Type flip-flops (D-FF0, D-FF2) and a second terminal connected in series between the output terminal of the second gate circuit (AND1) and the other input terminal of the first gate circuit (AND0). 3 and a fourth D-type flip-flop (D-FF1, D-FF3).

  By setting the selection signal (SEL) to the first state (low level “0”), the first clock signal (CKIN0) can be output from the output of the multiplexer (Mpx) as a clock output signal (CKOUT). It is said.

  By setting the selection signal (SEL) to a second state (high level “1”) different from the first state (low level “0”), the second clock signal (CKIN0) is converted to the multiplexer ( Mpx) can be output as the clock output signal (CKOUT) (see FIGS. 6, 8, 10, 12, 15, 16, 18, and 20). .

  According to the embodiment, the first and second D-type flip-flops (D-FF0 and D-FF2) and the third and fourth D of the control unit (Cnt) included in the clock selection circuit. The type flip-flops (D-FF1, D-FF3) constitute the two-stage synchronizers described in Non-Patent Document 1, respectively. Therefore, it is possible to reduce the probability of occurrence of a metastable failure in the clock output signal (CKOUT) from the final output terminal of the multiplexer (Mpx) of the clock selection circuit (FIGS. 7, 9, 11, and 11). 13, FIG. 17, FIG. 19).

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<< Configuration of clock selector circuit >>
FIG. 6 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the first embodiment of the present invention.

  The clock selection circuit shown in FIG. 6 includes an inverter INV0 as a decoder DEC, first and second AND circuits AND0, AND1, and first and second D-type flip-flops D-FF0 and D-FF1 of a control unit Cnt. The third and fourth D-type flip-flops D-FF2, D-FF3, and a multiplexer Mpx are included.

  Compared with the clock selection circuit shown in FIG. 3, the clock selection circuit shown in FIG. 6 includes third and fourth D-type flip-flops D-FF2 and D-FF3. Therefore, in the clock selection circuit shown in FIG. 6, the first D-type flip-flop D-FF0 and the third D-type flip-flop D-FF2 constitute a two-stage synchronizer, while the second D-type flip-flop The D-FF1 and the fourth D-type flip-flop D-FF3 constitute a two-stage synchronizer.

  The selection signal SEL is supplied to the input terminal of the inverter INV0 and one input terminal of the second AND circuit AND1, and the output signal of the inverter INV0 is supplied to one input terminal of the first AND circuit AND0. The output signal D0 of the first AND circuit AND0 is supplied to the data input terminal of the first D-type flip-flop D-FF0, while the output signal D1 of the second AND circuit AND1 is supplied to the second D-type flip-flop D. -Supplied to the data input terminal of FF1. The output data Q0 of the first D-type flip-flop D-FF0 is supplied to the data input terminal of the third D-type flip-flop D-FF2, and the output data Q1 of the second D-type flip-flop D-FF1 is the fourth data To the data input terminal of the D-type flip-flop D-FF3. The output data Q′0 of the third D-type flip-flop D-FF2 is supplied to the inverting input terminal as the other input terminal of the second AND circuit AND1, while the output of the fourth D-type flip-flop D-FF3. The output data Q′1 is supplied to the inverting input terminal as the other input terminal of the first AND circuit AND0.

  The multiplexer Mpx includes third and fourth AND circuits AND2 and AND3, and an OR circuit OR0. The output data Q′0 of the third D-type flip-flop D-FF2 is supplied to one input terminal of the third AND circuit AND2, while the fourth D circuit is supplied to one input terminal of the fourth AND circuit AND3. The output data Q′1 of the type flip-flop D-FF3 is supplied. The first clock signal CKIN0 is applied to the rising edge trigger terminal of the first D-type flip-flop D-FF0, the rising edge trigger terminal of the third D-type flip-flop D-FF2, and the other input terminal of the third AND circuit AND2. Are supplied to the rising edge trigger terminal of the second D-type flip-flop D-FF1, the rising edge trigger terminal of the fourth D-type flip-flop D-FF3, and the other input terminal of the fourth AND circuit AND3. A second clock signal CKIN1 is supplied. Further, the first clock output signal CKG0 of the third AND circuit AND2 and the second clock output signal CKG1 of the fourth AND circuit AND3 are respectively supplied to one input terminal and the other input terminal of the OR circuit OR0. A clock output signal CKOUT is generated from the output terminal of the OR circuit OR0.

  As shown in the lower part of FIG. 6, the first and second D-type flip-flops D-FF0 and D-FF1, the third and fourth D-type flip-flops D-FF2 and D-FF3, Consists of latches. A master latch (Master-Latch) and a slave latch (Slave-Latch) of the master-slave latch are configured by first and second inverters Inv1 and Inv2 that are cross-coupled to the switch SW, respectively. . The second inverter Inv2 includes a clocked inverter driven by non-inverted clock signals CKIN0 and CKIN1 and an inverted clock signal. For example, in the second D flip-flop D-FF1, the output signal D1 of the second AND circuit AND1 is in the master latch (Master-Latch) while the second clock signal CKIN1 is at the low level “0”. The signal is transmitted to the input terminal of the first inverter Inv1 via the switch SW in the on state. During this time, in the slave latch (Slave-Latch), the switch SW is turned off, and the output data Q1 held by the cross-coupled first and second inverters Inv1, Inv2 is output. In the second D-type flip-flop D-FF1, the switch SW is turned off in the master latch (Master-Latch) while the second clock signal CKIN1 is at the high level “1”. The output signal D1 of the second AND circuit AND1 is held by the connected first and second inverters Inv1 and Inv2. During this time, the output signal of the first inverter Inv1 of the master latch (Master-Latch) is transmitted to the slave latch (Slave-Latch) and input to the first inverter Inv1 via the switch SW in the ON state. Is transmitted to the terminal. Furthermore, the first D-type flip-flop D-FF0 operates in the same manner as the second D-type flip-flop D-FF1 in response to the first clock signal CKIN0. As a result, the first and second D-type flip-flops D-FF0 and D-FF1, the third and fourth D-type flip-flops D-FF2 and D-FF3 are connected to the first and second clock signals CKIN0, In response to the rising edge of CKIN1, the level of the input signal is output as output data.

  In the clock selection circuit shown in FIG. 6, while the selection signal SEL is at the low level “0”, the first clock signal CKIN0 is selected and output from the clock output signal CKOUT of the multiplexer Mpx, and the selection signal SEL is at the high level “ During 1 ″, the second clock signal CKIN1 is selected and output from the clock output signal CKOUT of the multiplexer Mpx.

《Resolve metastable》
In the clock selection circuit shown in FIG. 6, the output signals D0 and D1 of the first and second AND circuits AND0 and AND1 as asynchronous signals are the first and second D-type flip-flops D-FF0 and D1 in the first stage. The first and second D-type flip-flops D-FF0 and D-FF1 are latched by -FF1, and output data Q0 and Q1 are output. The output data Q0 and Q1 of the first and second D-type flip-flops D-FF0 and D-FF1 at the first stage are further supplied to the third and fourth D-type flip-flops D-FF2 and D- at the second stage. The first and second clock signals CKIN0 and CKIN1 are latched in the FF3 after one cycle. Accordingly, it is assumed that a violation of the setup time and the hold time has occurred in the first and second D-type flip-flops D-FF0 and D-FF1 in the first stage, resulting in a metastable state. Even so, the third and fourth D-type flip-flops D-FF2 and D-FF3 in the second stage are stable if the metastable is resolved within one cycle of the clock and the level is fixed to the high level or the low level. Data can be latched. In this way, in the clock selection circuit shown in FIG. 6, by using the two-stage synchronizer for each of the plurality of signal selection paths, the metastable that can be solved within one cycle of the clock can be rendered harmless. The occurrence probability of metastable failure can be reduced by selective output, and practically sufficient operation reliability can be ensured.

<< Waveforms of each part of clock selection circuit >>
FIG. 7 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the first embodiment of the present invention shown in FIG. FIG.

  In the clock selection circuit shown in FIG. 6, as described above, the first and second D-type flip-flops D-FF0 and D-FF1, the third and fourth D-type flip-flops D-FF2, and D-FF3. Outputs the level of the input signal as output data in response to the rising edges of the first and second clock signals CKIN0 and CKIN1.

  Even at the timing 401 in FIG. 7, the transition of the rising edge of the first clock signal CKIN0 is too close to the falling state change of the output signal D0 of the first AND circuit AND0 that is an asynchronous input signal. The violation of the setup time and hold time of the D-type flip-flop D-FF0 of 1 occurs. Therefore, at the next timing 403, a failure of the metastable of the first D-type flip-flop D-FF0 occurs. That is, the first output data Q0 of the first D-type flip-flop D-FF0 maintains an intermediate level between the high level “1” and the low level “0” for a relatively long time. It takes a relatively long time to recover to the level “1” or the low level “0”. The relatively long time of the metastable corresponds to approximately one cycle of the second clock signal CKIN1. However, after completion of the metastable failure at timing 403, the first output data Q0 of the first D-type flip-flop D-FF0 recovers to the low level “0” or the high level “1”. The first output data Q0 after level recovery is latched in the third D-type flip-flop D-FF2 at the timing of the rising edge of the first clock signal CKIN0, and the output of the third D-type flip-flop D-FF2 The data Q′0 is also fixed at the low level “0” or the high level “1” at this timing.

  Since the output data Q′0 of the third D-type flip-flop D-FF2 is supplied to the inverting input terminal of the second AND circuit AND1, the output signal D1 of the second AND circuit AND1 is also the first clock signal. At the timing of the rising edge of CKIN0, the low level “0” or the high level “1” is determined. The second D-type flip-flop D-FF1 outputs the level of the output signal D1 of the second AND circuit AND1 as the second output data Q1 at the falling edge of the second clock signal CKIN1. Even at the timing 402 at this time, the change in the state of the output signal D1 of the second AND circuit AND1 as an asynchronous input signal is too close to the transition of the rising edge of the second clock signal CKIN1. A violation of the setup time and hold time of the D-type flip-flop D-FF1 occurs. Therefore, at the next timing 404, a failure of the metastable of the second D-type flip-flop D-FF1 occurs. That is, the second output data Q1 of the second D-type flip-flop D-FF1 maintains an intermediate level between the high level “1” and the low level “0” for a relatively long time. It takes a relatively long time to recover to the level “1” or the low level “0”. The relatively long time of the metastable corresponds to approximately one cycle of the second clock signal CKIN1. However, after the failure of the metastable at the timing 404, the second output data Q1 of the second D-type flip-flop D-FF1 is restored to the high level “1” or the low level “0”. The second output data Q1 after the level recovery is latched in the fourth D-type flip-flop D-FF3 at the timing of the rising edge of the second clock signal CKIN1, and the output of the fourth D-type flip-flop D-FF3 The data Q′1 is also fixed at the high level “1” or the low level “0” at this timing.

  In this way, a violation of the setup time and the hold time occurs at timings 401 and 402, and a metastable failure occurs at timings 403 and 404, but one cycle of the first and second clock signals CKIN0 and CKIN1. The metastable is resolved during As described above, by using the clock selection circuit shown in FIG. 6, it is possible to reduce the occurrence probability of the metastable failure in the output clock signal CKOUT as the final selection output terminal of the clock selection circuit. Furthermore, the operational reliability of the clock selection circuit mounted on the semiconductor integrated circuit such as a microcontroller or system LSI can be improved.

  However, the clock selection circuit shown in FIG. 6 is a two-stage synchronizer having first and second D-type flip-flops D-FF0 and D-FF1, and third and fourth D-type flip-flops D-FF2 and D-FF3. The third and fourth AND circuits AND2 and AND3 and the multiplexer Mpx including the OR circuit OR0 are relatively simple. In the clock selection circuit shown in FIG. 6 having a relatively simple configuration as described above, various problems occur due to the signal delay of the two-stage synchronizer. The first problem is that the first clock output signal CKG0 and the OR circuit OR0 of the third AND circuit AND2 of the multiplexer Mpx are caused by the falling delay of the output data Q′0 of the third D-type flip-flop D-FF2. That is, a glitch 405 having a small pulse width is generated in each of the clock output signals CKOUT. The second problem is that the second clock output signal CKG1 of the fourth AND circuit AND3 of the multiplexer Mpx and the OR circuit are caused by the falling delay TCQ of the output data Q′1 of the fourth D-type flip-flop D-FF2. The waveform of the rising portion 406 of the first pulse with the clock output signal CKOUT of OR0 disappears.

[Embodiment 2]
<< Configuration of other clock selector circuits >>
FIG. 8 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the second embodiment of the present invention.

  The clock selection circuit shown in FIG. 8 solves various problems caused by the signal delay of the two-stage synchronizer of the clock selection circuit shown in FIG.

  The clock selection circuit according to the second embodiment of the present invention shown in FIG. 8 is different from the clock selection circuit shown in FIG. 6 in that the control unit Cnt of the clock selection circuit in FIG. 6 has first and second latches FF0 and FF1. Is added. The data input terminal and the inverting gate control terminal G of the first latch FF0 are supplied with the output data Q′0 of the third D-type flip-flop D-FF2 and the first clock signal CKIN0, respectively, and the first latch FF0. Output data Q ″ 0 is supplied to one input terminal of the third AND circuit AND2 of the multiplexer Mpx. The output data Q′1 of the fourth D-type flip-flop D-FF3 and the second clock signal CKIN1 are supplied to the data input terminal and the inverting gate control terminal G of the second latch FF1, respectively. The output data Q ″ 1 is supplied to one input terminal of the fourth AND circuit AND3 of the multiplexer Mpx.

  Note that the first and second latches FF0 and FF1 added to the clock selection circuit shown in FIG. 8 are cross-coupled with, for example, the master-latch switch SW shown in the lower part of FIG. The first and second inverters Inv1, Inv2 and the output inverter are included. Therefore, the first and second latches FF0 and FF1 added to the clock selection circuit shown in FIG. 8 are supplied with the low-level first and second clock signals CKIN0 and CKIN1 to the inverting gate control terminal G. In the meantime, the input level of the data input terminal is transmitted to the data output. On the other hand, the first and second latches FF0 and FF1 receive the input level of the data input terminal while the high-level first and second clock signals CKIN0 and CKIN1 are supplied to the inverting gate control terminal G. Is prohibited from being transmitted to the data output, and the level of the data output at that time is held. The other configuration of the clock selection circuit of FIG. 8 is the same as that of the clock selection circuit of FIG.

<< Waveforms of other parts of other clock selection circuits >>
FIG. 9 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the second embodiment of the present invention shown in FIG. FIG.

  Even at the timing 401 in FIG. 9, the transition of the rising edge of the first clock signal CKIN0 is too close to the falling state change of the output signal D0 of the first AND circuit AND0 that is an asynchronous input signal. A violation of the setup time and hold time of the D-type flip-flop D-FF0 of 1 occurs. Therefore, even at the next timing 403, a failure of the metastable of the first D-type flip-flop D-FF0 occurs. However, after the metastable failure ends at timing 403, the first output data Q0 of the first D-type flip-flop D-FF0 recovers to the low level “0” or the high level “1”, and the third The output data Q′0 of the D-type flip-flop D-FF2 is also determined at the low level “0” or the high level “1” at this timing. Then, the first latch FF0 sets the level of the output data Q′0 of the third D-type flip-flop D-FF2 to the data output Q ′ while the low-level first clock signal CKIN0 is supplied. Transmit to '0. Therefore, in the operation by the clock selection circuit of FIG. 8 shown in FIG. 9, it is possible to prevent the occurrence of the glitch 405 having a small pulse width generated by the operation of the clock selection circuit of FIG.

  Even at the timing 402 in FIG. 9, since the change in the state of the output signal D1 of the second AND circuit AND1 as an asynchronous input signal is too close to the transition of the rising edge of the second clock signal CKIN1, the second A violation of the setup time and hold time of the D-type flip-flop D-FF1 occurs. Therefore, at the next timing 404, a failure of the metastable of the second D-type flip-flop D-FF1 occurs. However, after the metastable failure at timing 404 ends, the second output data Q1 of the second D-type flip-flop D-FF1 recovers to the high level “1” or the low level “0”, and the fourth output data Q1 is recovered. The output data Q′1 of the D-type flip-flop D-FF3 is also determined at the high level “1” or the low level “0” at this timing. Then, the second latch FF1 sets the level of the output data Q′1 of the fourth D-type flip-flop D-FF3 to the data output Q ″ 1 while the second clock signal CKIN1 at the low level is supplied. To communicate. Therefore, in the operation by the clock selection circuit of FIG. 8 shown in FIG. 9, the first of the second clock output signal CKG1 and the clock output signal CKOUT generated by the operation of the clock selection circuit of FIG. Loss of the waveform of the rising portion 406 of the pulse can be prevented.

  Further, when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 by the operation of the clock selection circuit of FIG. 8 shown in FIG. 9, after the level transition of the selection signal SEL, The clock selection switching can be completed by two rising transitions of the first clock signal CKIN0 and three rising transitions of the second clock signal CKIN1. Therefore, according to the clock selection circuit shown in FIG. 8, the switching latency of the selection of the clock signal can be reduced.

[Embodiment 3]
<< Configuration of Other Clock Selector Circuit >>
FIG. 10 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the third embodiment of the present invention.

  The clock selection circuit according to the third embodiment of the present invention shown in FIG. 10 is different from the clock selection circuit shown in FIG. 6 in the following points.

  In the control unit Cnt of the clock selection circuit shown in FIG. 6, the first and second D-type flip-flops D-FF0 and D-FF1, and the third and fourth D-type flip-flops D-FF2 and D-FF3 are respectively Had a rising edge trigger terminal. Therefore, these D-type flip-flops output the level of the input signal as output data in response to the rising edges of the first and second clock signals CKIN0 and CKIN1.

  On the other hand, in the control unit Cnt of the clock selection circuit shown in FIG. 10, the first and second D-type flip-flops D-FF0, D-FF1, the third and fourth D-type flip-flops D-FF2, D- Similarly to the first and second D-type flip-flops D-FF0 and D-FF1 in FIG. 3, the FF3 has a falling edge trigger terminal. Therefore, these D-type flip-flops output the level of the input signal as output data in response to the falling edges of the first and second clock signals CKIN0 and CKIN1.

<< Waveforms of other parts of other clock selection circuits >>
FIG. 11 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the third embodiment of the present invention shown in FIG. FIG.

  Even at the timing 401 in FIG. 11, the falling state change of the output signal D0 of the first AND circuit AND0 which is an asynchronous input signal is too close to the transition of the falling edge of the first clock signal CKIN0. A violation of the setup time and hold time of the first D-type flip-flop D-FF0 occurs. Therefore, even at the next timing 403, a failure of the metastable of the first D-type flip-flop D-FF0 occurs. However, after the failure of the metastable at the timing 403, the first output data Q0 of the first D-type flip-flop D-FF0 is restored to the low level “0” or the high level “1”, and the third output data Q0 is recovered. The output data Q′0 of the D-type flip-flop D-FF2 is also determined at the low level “0” or the high level “1” at this timing. Therefore, even with the operation of the clock selection circuit of FIG. 10 shown in FIG. 11, it is possible to prevent the occurrence of the glitch 405 having a small pulse width generated by the operation of the clock selection circuit of FIG.

  Also at the timing 402 in FIG. 11, since the change in the state of the output signal D1 of the second AND circuit AND1 as an asynchronous input signal is too close to the transition of the falling edge of the second clock signal CKIN1, the second The violation of the setup time and hold time of the D-type flip-flop D-FF1 occurs. Therefore, at the next timing 404, a failure of the metastable of the second D-type flip-flop D-FF1 occurs. However, after the metastable failure at timing 404 ends, the second output data Q1 of the second D-type flip-flop D-FF1 recovers to the high level “1” or the low level “0”, and the fourth output data Q1 is recovered. The output data Q′1 of the D-type flip-flop D-FF3 is also determined at the high level “1” or the low level “0” at this timing. Therefore, in the operation by the clock selection circuit of FIG. 10 shown in FIG. 11, the first of the second clock output signal CKG1 and the clock output signal CKOUT generated by the operation of the clock selection circuit of FIG. Loss of the waveform of the rising portion 406 of the pulse can be prevented.

  Further, when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 by the operation of the clock selection circuit of FIG. 10 shown in FIG. 11, after the level transition of the selection signal SEL. The switching of clock selection is completed by two falling transitions of the first clock signal CKIN0, two falling transitions of the second clock signal CKIN1, and the next rising transition of the second clock signal CKIN1. it can. Therefore, according to the clock selection circuit shown in FIG. 10, the switching latency of clock signal selection can be reduced.

[Embodiment 4]
<< Configuration of another clock selector circuit >>
FIG. 12 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the fourth embodiment of the present invention.

  The clock selection circuit according to the fourth embodiment of the present invention shown in FIG. 12 is different from the clock selection circuit shown in FIG. 8 in the following points.

  The inputs of the first and second latches FF0 and FF1 added to the control unit Cnt of the clock selection circuit shown in FIG. 8 are output to the outputs of the third and fourth D-type flip-flops D-FF2 and D-FF3. Cascade connection. On the other hand, the inputs of the first and second latches FF0 and FF1 added to the control unit Cnt of the clock selection circuit shown in FIG. 12 are input to the third and fourth D-type flip-flops D-FF2 and D-FF3. Connected in parallel to the input. As a result, the number of connection stages from the input terminal of the inverter INV0 to which the selection signal SEL is supplied to one input terminal of the third and fourth AND circuits AND2 and AND3 of the multiplexer MPx is compared with the clock selection circuit shown in FIG. Then, the number of the third and fourth D-type flip-flops D-FF2 and D-FF3 is reduced in the clock selection circuit shown in FIG.

  For the exclusive selection of the clock signal, the feedback loop from the outputs D0 and D1 of the first and second AND circuits AND0 and AND1 to the inverting input terminal as the other input terminal includes the first and second D-types. Cascade connection of the flip-flops D-FF0 and D-FF1 and the third and fourth D-type flip-flops D-FF2 and D-FF3 is arranged.

<< Waveforms of each part of another clock selection circuit >>
FIG. 13 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the fourth embodiment of the present invention shown in FIG. FIG.
Also at the timing 401 in FIG. 13, the transition of the rising edge of the first clock signal CKIN0 is too close to the falling state change of the output signal D0 of the first AND circuit AND0 that is an asynchronous input signal. Violation of the setup time and hold time of D-type flip-flop D-FF0 of 1 occurs. Therefore, at the next timing 403, a failure of the metastable of the first D-type flip-flop D-FF0 occurs. However, after completion of the metastable failure at timing 403, the first output data Q0 of the first D-type flip-flop D-FF0 recovers to the low level “0” or the high level “1”. At this timing, since the low level first clock signal CKIN0 is supplied to the inverting gate control terminal G of the first latch FF0, the first latch FF0 has the input low level “0” or high level “ Since the data Q0 recovered to “1” is transmitted to the output, the output Q′0 is also fixed to the low level “0” or the high level “1”. The third D-type flip-flop D-FF2 latches the first output data Q0 of the first D-type flip-flop D-FF0 at the timing of the rising edge of the first clock signal CKIN0. The output data Q ″ 0 of the D-type flip-flop D-FF2 is also determined at the low level “0” or the high level “1” at this timing.
Accordingly, in response to the determination of the low level “0” or the high level “1” of the output data Q ″ 0 of the third D-type flip-flop D-FF2, the output signal D1 of the second AND circuit AND1 is Set to high level “1” or low level “0”. However, at the timing 402, the transition of the rising edge of the second clock signal CKIN1 is too close to the falling state change of the output signal D1 of the second AND circuit AND1, which is an asynchronous input signal. Violation of the setup time and hold time of the D-type flip-flop D-FF1 occurs. Therefore, at the next timing 404, a metastable failure of the second D-type flip-flop D-FF1 occurs, and the second output data Q1 is between the high level “1” and the low level “0”. It is an intermediate level. At this timing, since the low level second clock signal CKIN1 is supplied to the inverting gate control terminal G of the second latch FF1, the second latch FF1 transmits the input intermediate level data Q1 to the output. Therefore, the output Q′1 is also in an intermediate level metastable state 1001. However, since the low-level second clock signal CKIN1 is supplied to the other input terminal of the fourth AND circuit AND3 of the multiplexer Mpx during this timing 1002, the second level of the fourth AND circuit AND3 The clock output signal CKG1 is fixed at a low level.

  Further, when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 by the operation of the clock selection circuit of FIG. 12 shown in FIG. 13, after the level transition of the selection signal SEL. The switching of the clock selection can be completed by one rising transition of the first clock signal CKIN0 and two rising transitions of the second clock signal CKIN1. Therefore, according to the clock selection circuit shown in FIG. 12, the switching latency of clock signal selection can be significantly reduced.

<< Configuration of AND circuit >>
FIG. 14 is a diagram showing a configuration of the fourth AND circuit AND3 of the multiplexer Mpx of the clock selection circuit of FIG.

  The fourth AND circuit AND3 shown in FIG. 14 includes two P-channel MOS transistors Qp1 and Qp2 having source / drain current paths connected in parallel and two N-channel MOS transistors having source / drain current paths connected in series. The NAND circuit includes Qn1 and Qn2, and an inverter including one P-channel MOS transistor Qp3 and one N-channel MOS transistor Qn3.

  In the fourth AND circuit AND3 shown in FIG. 14, the output data Q1 of the second latch FF1, which is an intermediate level between the high level “1” and the low level “0”, is output from the P channel MOS transistor Qp2. It is supplied to the gate and the gate of the N-channel MOS transistor Qn1. Therefore, there is a possibility that the P channel MOS transistor Qp2 and the N channel MOS transistor Qn1 have an intermediate continuity, and the output potential of the NAND circuit is also in an intermediate level metastable state. As a result, there is a possibility that the input potential and the output potential of the inverter including one P-channel MOS transistor Qp3 and one N-channel MOS transistor Qn3 are in a metastable state at an intermediate level.

  However, at this timing, the low-level second clock signal CKIN1 is supplied to the gate of the P-channel MOS transistor Qp1 and the gate of the N-channel MOS transistor Qn2 as the other input terminals of the fourth AND circuit AND3 of the multiplexer Mpx. It is what is done. Accordingly, the P-channel MOS transistor Qp1 is turned on and the N-channel MOS transistor Qn2 is turned off, so that the output potential of the NAND circuit is determined at the high level power supply voltage Vdd. As a result, the level of the second clock signal CKIN1 at the output terminal of the inverter is fixed to the low level ground potential Vss. In this manner, the output potential of the NAND circuit, the input potential of the inverter, and the metastable state of the output potential can be masked by the second clock signal CKIN1 set to the low level.

[Embodiment 5]
<< Configuration of yet another clock selector circuit >>
FIG. 15 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the fifth embodiment of the present invention.

  In the fifth embodiment of the present invention shown in FIG. 15, the first, second, and second clock selection circuits according to the fourth embodiment of the present invention shown in FIG. 12 to which the first and second clock signals CKIN0 and CKIN1 are supplied are shown. The third, fourth, fifth, and sixth clock signals CKIN0, CKIN1, CKIN2, CKIN3, CKIN4, and CKIN5 are extended. In order to select one clock signal from the six clock signals CKIN0 to CKIN5, the 3-bit clock selection signals SEL0, SEL1, and SEL2 are the six AND gates G0, G1, G2, G3, and G4 in the decoder DEC. , G5, six clock selection output signals d0, d1, d2, d3, d4, d5 are generated from the decoder DEC. Six clock selection output signals d0, d1, d2, d3, d4, and d5 generated by the decoder DEC are supplied to six AND circuits AND0, AND1, AND2, AND3, AND4, and AND5 of the control unit Cnt. .

  Also in the control unit Cnt of the clock selection circuit shown in FIG. 15, the inputs of the six latches FF0, FF1, FF2, FF3, FF4, and FF5 are the six D-type flip-flops D-FF6, D-FF7, and D-FF8. , D-FF9, D-FF10, and D-FF11 are connected in parallel. As a result, the number of connection stages from the input terminal of the decoder DEC to which the selection signals SEL0, SEL1, and SEL2 are supplied to one input terminal of the six AND circuits AND6, AND7, AND8, AND9, AND10, and AND11 of the multiplexer MPx is Similar to the clock selection circuit shown in FIG.

  For exclusive selection of clock signals, a feedback loop from the outputs D0, D1, D2, D3, D4, and D15 of the six AND circuits AND0, AND1, AND2, AND3, AND4, and AND5 to the other input terminal is used. Are arranged in cascade connection of six D-type flip-flops D-FF0 to D-FF5 in the preceding stage and six D-FF6 to D-FF11 in the subsequent stage.

  The multiplexer Mpx includes six AND6, AND7, AND8, AND9, AND10, AND11, and an OR circuit OR0. Also, the output data Q′0, Q′1, Q of the six latches FF0, FF1, FF2, FF3, FF4, FF5 are connected to one input terminal of the six AND6, AND7, AND8, AND9, AND10, AND11. '2, Q'3, Q'4, and Q'5 are supplied, while the other input terminal has first, second, third, fourth, fifth, and sixth clock signals CKIN0, CKIN1, CKIN2, CKIN3, CKIN4, and CKIN5 are supplied. The clock output signals CKG0, CKG1, CKG2, CKG3, CKG4, and CKG05 of the six AND6, AND7, AND8, AND9, AND10, and AND11 are respectively supplied to a number of input terminals of the OR circuit OR0, and are output from the output terminal of the OR circuit OR0. Generates a clock output signal CKOUT.

  In the clock selection circuit shown in FIG. 15, although the number of input clock signals CKIN0 to CKIN5 is greatly increased to 6, like the clock selection circuit shown in FIG. can do.

[Embodiment 6]
<< Configuration of different clock selector circuits >>
FIG. 16 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the sixth embodiment of the present invention.

  The sixth embodiment of the present invention shown in FIG. 16 further reduces the switching latency of clock signal selection as compared with the various embodiments described above.

  The clock selection circuit according to the sixth embodiment of the present invention shown in FIG. 16 differs from the clock selection circuit shown in FIG. 12 in that the first and second delay circuits are different from the control unit Cnt of the clock selection circuit in FIG. DELAY0 and DELAY1 are added.

  In the clock selection circuit shown in FIG. 16, the first clock signal CKIN0 is supplied to the input terminal of the first delay circuit DELAY0, and the first delay clock signal CKIDN0 from the output of the first delay circuit DELAY0 The signal is supplied to the inverting gate control terminal G of the latch FF0, the rising edge trigger terminal of the third D-type flip-flop D-FF2, and the other input terminal of the third AND circuit AND2 of the multiplexer Mpx. Furthermore, the second clock signal CKIN1 is supplied to the input terminal of the second delay circuit DELAY1, and the second delayed clock signal CKIDN1 from the output of the second delay circuit DELAY1 is controlled by the inverting gate of the second latch FF1. The signal is supplied to the terminal G, the rising edge trigger terminal of the fourth D-type flip-flop D-FF3, and the other input terminal of the fourth AND circuit AND3 of the multiplexer Mpx.

<< Waveforms of each part of different clock selection circuits >>
FIG. 17 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the sixth embodiment of the present invention shown in FIG. FIG.

  As shown in FIG. 17, the first and second delay circuits DELAY0 and DELAY1 delay the first and second clock signals CKIN0 and CKIN1 by a predetermined delay time Delay, respectively. Delayed clock signals CKIDN0 and CKIDN1 are generated. The predetermined delay time Delay is set to be equal to or less than half the pulse width of the first clock signal CKIN0 having the lower frequency, so that the first and second D-type flip-flops D− after the metastable are set. This corresponds to the level recovery timing of the first and second output data Q0 and Q1 of FF0 and D-FF1.

  Also in the waveform diagram shown in FIG. 17, a violation between the setup time and the hold time occurs at timings 401 and 402, and a metastable failure occurs at timings 403 and 404. However, the first and second output data Q0 of the first and second D-type flip-flops D-FF0 and D-FF1 that recover to the low level “0” or the high level “1” after the end of these faults. , Q1 can be latched early by the third and fourth D-type flip-flops D-FF2 and D-FF3 at the timing of rising edges of the first and second delayed clock signals CKIDN0 and CKIDN1. As a result, after the selection signal SEL transitions from the low level “0” to the high level “1”, the output data Q ″ 0, Q ′ of the third and fourth D-type flip-flops D-FF2 and D-FF3. “1” is restored to the low level “0” or the high level “1” relatively early. In this way, by using the clock selection circuit shown in FIG. 16, it is possible to greatly reduce the clock signal selection switching latency.

[Embodiment 7]
<< Configuration of a different clock selector circuit >>
FIG. 18 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the seventh embodiment of the present invention.

  According to the clock selection circuit of the sixth embodiment of the present invention shown in FIG. 16, the clock signal selection switching latency can be greatly reduced as described above.

  However, as can be understood from the waveform diagram shown in FIG. 17, the final phase of the clock output signal CKOUT by the clock selection is first and higher than the phases of the first and second clock signals CKIN0 and CKIN1 on the input side. The delay is delayed by a predetermined delay time Delay in the second delay circuits DELAY0 and DELAY1. On the other hand, the product specifications of semiconductor integrated circuits such as microcontrollers and system LSIs may not allow the phase of the clock output signal due to clock selection to be delayed more than the phase of the clock signal on the input side.

  The clock selection circuit mounted on the semiconductor integrated circuit according to the seventh embodiment of the present invention shown in FIG. 18 solves this problem. That is, in the control unit Cnt of the clock selection circuit shown in FIG. 18, the first and second delay circuits DELAY0 and DELAY1 are the rising edge triggers of the first and second D-type flip-flops D-FF0 and D-FF1. And a rising edge trigger terminal of the third and fourth D-type flip-flops D-FF2 and D-FF3. Therefore, in the clock selection circuit shown in FIG. 18, the first and second delay circuits DELAY0 and DELAY1 are not arranged in the signal transmission path of one input terminal of the third and fourth AND circuits AND2 and AND3 of the multiplexer Mpx. It will be a thing.

<< Waveforms of each part of different clock selection circuits >>
FIG. 19 illustrates the waveforms of the respective parts when the selection state of the first clock signal CKIN0 is switched to the selection state of the second clock signal CKIN1 in the clock selection circuit according to the seventh embodiment of the present invention shown in FIG. FIG.

  From the waveform diagram of FIG. 19, in the clock selection circuit of FIG. 18, the switching latency of the selection of the clock signal is slightly increased compared to the clock selection circuit of FIG. 16, but the final phase of the clock output signal CKOUT by the clock selection is input. It is understood that the phase of the first and second clock signals CKIN0 and CKIN1 on the side is substantially equal.

[Embodiment 8]
<< Specific clock selector circuit configuration >>
FIG. 20 is a diagram showing a configuration of a clock selection circuit mounted on the semiconductor integrated circuit according to the eighth embodiment of the present invention.

  The clock selection circuit according to the eighth embodiment of the present invention shown in FIG. 20 has a combination of the fifth embodiment of the present invention shown in FIG. 15 and the seventh embodiment of the present invention shown in FIG.

  In the clock selection circuit according to the eighth embodiment of the present invention shown in FIG. 20, the first clock signal CKIN0, the second clock signal CKIN1, the third clock signal CKIN2, the fourth clock signal CKIN3, and the fifth clock signal. The clock frequency increases in the order of CKIN4 and the sixth clock signal CKIN5.

  In the clock selection circuit of FIG. 20, the first delay circuit DELAY0 includes the rising edge trigger terminal of the D-type flip-flop D-FF0 and the rising edge of the D-type flip-flop D-FF6 in response to the first clock signal CKIN0 having the lowest speed. The second delay circuit DELAY1 is connected between the trigger terminal and the rising edge trigger terminal of the D-type flip-flop D-FF1 and the D-type flip-flop D-FF7 in response to the second slowest second clock signal CKIN1. Connected to the rising edge trigger terminal.

  Accordingly, in the clock selection circuit of FIG. 20, the delay times of the first and second delay circuits DELAY0 and DELAY1 for the lowest-speed first clock signal CKIN0 and the second-lowest second clock signal CKIN1 are This corresponds to the level recovery timing of the first and second output data Q0 and Q1 of the D-type flip-flops D-FF0 and D-FF1 after the metastable. Further, in the clock selection circuit of FIG. 20, for the third to sixth clock signals CKIN2 to CKIN5, the switching latency is remarkably reduced similarly to the clock selection circuit according to the fourth embodiment of the present invention shown in FIG. The clock signal can be selected.

[Embodiment 9]
<Configuration of semiconductor integrated circuit>
FIG. 21 is a diagram showing the configuration of the semiconductor integrated circuit according to the ninth embodiment of the present invention.

  The semiconductor integrated circuit according to the ninth embodiment of the present invention shown in FIG. 21 includes a semiconductor chip 10 of a microcontroller or a system LSI. The semiconductor chip 10 includes a phase-locked loop (PLL) 1, a high-frequency oscillator (HOCO) 2, a low-frequency oscillator (LOCO) 3, a real-time clock oscillator (RTC) 4, a frequency divider (Div) 5, and a clock selection circuit (CLK_SEL). ) 6, a clock generator (CPG) 7, a clock buffer (CPB) 8, and a control register (Reg) 9.

  The voltage controlled oscillator of the phase-locked loop 1 generates a clock signal from the reference frequency signal generated by the crystal oscillator XTAL outside the semiconductor chip 10 and supplies it to the first input terminal of the clock selection circuit 6. The high frequency clock signal generated from the high frequency oscillator 2, the low frequency clock signal generated from the low frequency oscillator 3, the real time clock signal having a frequency of 32 kHz from the real time clock oscillator 4, and the reference frequency signal generated by the crystal oscillator XTAL are separated. The other real-time clock signal having a frequency of 32 kHz generated by the frequency divider 5 and the external clock signal EXTCK generated outside the semiconductor chip 10 are the second input terminal and the third input terminal of the clock selection circuit 6. , The fourth input terminal, the fifth input terminal, and the sixth input terminal.

  One clock input signal is selected from the clock input signals from the first input terminal to the sixth input terminal of the clock selection circuit 6 by the 3-bit selection signal SEL <2: 0> of the output of the control register 9. This is transmitted to the output terminal of the clock selection circuit 6. The selected clock signal transmitted to the output terminal of the clock selection circuit 6 is supplied in common to the input terminals of the first, second and third frequency dividers 70, 71 and 72 of the clock generator 7, and the first divided signal is supplied. A system clock signal SYSCK used for a CPU (central processing unit) or the like is generated from the output terminal of the frequency divider 70, and a bus clock signal BUSCK supplied to the external bus is generated from the output terminal of the second frequency divider 71. From the output terminal of the third frequency divider 72, the peripheral clock signal PERICK used for the operation clock of the peripheral IP is generated. The peripheral clock signal PERICK is amplified by a plurality of buffer amplifiers 80 to 85 inside the clock buffer 8 and then distributed to a plurality of peripheral IPs.

  A clock selection circuit that selects one clock input signal from clock input signals from the first input terminal to the sixth input terminal in response to a 3-bit selection signal SEL <2: 0> output from the control register 9 ( Any of the clock selection circuits from the first embodiment to the eighth embodiment of the present invention described above is employed as (CLK_SEL) 6.

  Although the invention made by the present inventor has been specifically described based on various embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the scope of the invention. Yes.

  For example, the semiconductor integrated circuit of the present invention is not limited to a microcontroller or a system LSI, but can be widely used as a general-purpose semiconductor integrated circuit including a clock selection circuit that selects one clock input signal from a plurality of clock input signals. It is possible to adopt.

  Further, according to the present invention, when a plurality of clock signals are selected, it is possible to cope with various clock specifications, and it is possible to cope with glitch prevention and metastable failure probability reduction. As a result, more realistic operation reliability can be ensured.

DEC ... Decoder Cnt ... Control unit Mpx ... Multiplexer SEL ... Selection signal INV0 ... Inverter AND0, AND1 ... AND circuit D-FF0, 1, 2, 3 ... D-type flip-flop AND2, AND3 ... AND circuit OR0 ... OR circuit CKIN0, 1 ... Clock signal CKG0, 1 ... Clock output signal CKOUT ... Clock output signal FF0, 1 ... Latch

Claims (18)

A decoder to which a selection signal is supplied, a first clock signal and a second clock signal, a control unit to which at least a first selection output signal and a second selection output signal from the decoder are supplied, the first clock signal and the A semiconductor integrated circuit including a clock selection circuit having a second clock signal and a multiplexer to which at least a first selection control signal and a second selection control signal from the control unit are supplied;
The control unit has a first gate circuit to which the first selection output signal from the decoder is supplied to one input terminal, and the second selection output signal from the decoder to one input terminal. A second gate circuit,
The control unit includes first and second D-type flip-flops connected in series between an output terminal of the first gate circuit and the other input terminal of the second gate circuit, and the second A semiconductor integrated circuit comprising: a third and a fourth D-type flip-flop connected in series between an output terminal of a gate circuit and the other input terminal of the first gate circuit. A signal of a non-selection level of the output terminal of the first gate circuit is supplied to the other input terminal of the second gate circuit via the first and second D-type flip-flops connected in series. Thus, the second clock signal can be output as a clock output signal via the second gate circuit of the control unit and the multiplexer.
A signal of the non-selection level of the output terminal of the second gate circuit is supplied to the other input terminal of the first gate circuit via the third and fourth D-type flip-flops connected in series. The semiconductor integrated circuit according to claim 1, wherein the first clock signal can be output as the clock output signal via the first gate circuit and the multiplexer of the control unit. . Output data of the second D-type flip-flop on the rear stage side of the first and second D-type flip-flops connected in series is transmitted to the multiplexer as the first selection control signal and the second Is transmitted to the other input terminal of the gate circuit of
Output data of the fourth D-type flip-flop on the subsequent stage side of the third and fourth D-type flip-flops connected in series is transmitted to the multiplexer as the second selection control signal and the first The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is transmitted to the other input terminal of the gate circuit. The control unit further comprises first and second latches,
The data input terminal of the first latch and the data input terminal of the second D-type flip-flop are connected to the first D on the front side of the first and second D-type flip-flops connected in series. Output data of the type flip-flop is supplied in parallel, and output data of the first latch is transmitted to the multiplexer as the first selection control signal,
The data input terminal of the second latch and the data input terminal of the fourth D-type flip-flop are connected to the third D of the preceding stage of the third and fourth D-type flip-flops connected in series. 3. The semiconductor integrated circuit according to claim 2, wherein output data of the type flip-flop is supplied in parallel, and output data of the second latch is transmitted to the multiplexer as the second selection control signal. In response to the first clock signal, the gate control terminal of the first latch and both edge trigger terminals of the first and second D-type flip-flops connected in series are
5. The semiconductor integrated circuit according to claim 4, wherein a gate control terminal of the second latch and both edge trigger terminals of the third and fourth D-type flip-flops connected in series respond to the second clock signal. circuit. The control unit further comprises first and second delay circuits,
The input terminal of the first delay circuit is connected to the edge trigger terminal of the first D-type flip-flop on the front stage side, and the output terminal of the first delay circuit is the second D on the rear stage side. Connected to the edge trigger terminal of the flip-flop,
The input terminal of the second delay circuit is connected to the edge trigger terminal of the third D-type flip-flop on the front stage side, and the output terminal of the second delay circuit is the fourth D on the rear stage side. 6. The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is connected to the edge trigger terminal of a flip-flop. The gate control terminal of the first latch is connected to one of the input terminal and the output terminal of the first delay circuit;
The semiconductor integrated circuit according to claim 6, wherein the gate control terminal of the second latch is connected to one of the input terminal and the output terminal of the second delay circuit. The multiplexer comprises third, fourth and fifth gate circuits,
One input terminal and the other input terminal of the third gate circuit are respectively responsive to the first selection control signal and the first clock signal from the control unit,
One input terminal and the other input terminal of the fourth gate circuit are respectively responsive to the second selection control signal and the second clock signal from the control unit,
The first clock output signal generated from the third gate circuit and the second clock output signal generated from the fourth gate circuit are supplied to the fifth gate circuit, so that the first gate output signal is generated. The semiconductor integrated circuit according to claim 7, wherein the gate circuit 5 generates a clock output signal as a final output of the multiplexer. A first clock signal source for generating the first clock signal; and a second clock signal source for generating the second clock signal.
Either the first clock signal generated from the first clock signal source or the second clock signal generated from the second clock signal source is generated by the clock selection circuit in response to the selection signal. 9. The semiconductor integrated circuit according to claim 8, wherein the semiconductor integrated circuit is generated as the final output of the multiplexer. A decoder to which a selection signal is supplied, a first clock signal and a second clock signal, a control unit to which at least a first selection output signal and a second selection output signal from the decoder are supplied, the first clock signal and the A method of operating a semiconductor integrated circuit including a clock selection circuit having a second clock signal and a multiplexer to which at least a first selection control signal and a second selection control signal from the control unit are supplied,
The control unit has a first gate circuit to which the first selection output signal from the decoder is supplied to one input terminal, and the second selection output signal from the decoder to one input terminal. A second gate circuit,
The control unit includes first and second D-type flip-flops connected in series between an output terminal of the first gate circuit and the other input terminal of the second gate circuit, and the second A third and a fourth D-type flip-flop connected in series between the output terminal of the gate circuit and the other input terminal of the first gate circuit;
By setting the selection signal to the first state, the first clock signal can be output as a clock output signal from the output of the multiplexer,
The semiconductor integrated circuit characterized in that the second clock signal can be output from the output of the multiplexer as the clock output signal by setting the selection signal to a second state different from the first state. How the circuit works. A signal of a non-selection level of the output terminal of the first gate circuit is supplied to the other input terminal of the second gate circuit via the first and second D-type flip-flops connected in series. Thus, the second clock signal can be output as a clock output signal via the second gate circuit of the control unit and the multiplexer.
A signal of the non-selection level of the output terminal of the second gate circuit is supplied to the other input terminal of the first gate circuit via the third and fourth D-type flip-flops connected in series. 11. The semiconductor integrated circuit according to claim 10, wherein the first clock signal can be output as the clock output signal via the first gate circuit and the multiplexer of the control unit. How it works. Output data of the second D-type flip-flop on the subsequent stage side of the first and second D-type flip-flops connected in series is transmitted to the multiplexer as the first selection control signal and the second Is transmitted to the other input terminal of the gate circuit of
Output data of the fourth D-type flip-flop on the rear stage side of the third and fourth D-type flip-flops connected in series is transmitted to the multiplexer as the second selection control signal and the first The method of operating a semiconductor integrated circuit according to claim 11, wherein the operation is transmitted to the other input terminal of the gate circuit. The control unit further comprises first and second latches,
The data input terminal of the first latch and the data input terminal of the second D-type flip-flop are connected to the first D on the front side of the first and second D-type flip-flops connected in series. Output data of the type flip-flop is supplied in parallel, and output data of the first latch is transmitted to the multiplexer as the first selection control signal,
The data input terminal of the second latch and the data input terminal of the fourth D-type flip-flop are connected to the third D of the preceding stage of the third and fourth D-type flip-flops connected in series. 12. The method of operating a semiconductor integrated circuit according to claim 11, wherein output data of the type flip-flop is supplied in parallel, and output data of the second latch is transmitted to the multiplexer as the second selection control signal. In response to the first clock signal, the gate control terminal of the first latch and both edge trigger terminals of the first and second D-type flip-flops connected in series are
14. The semiconductor integrated circuit according to claim 13, wherein the gate control terminal of the second latch and the edge trigger terminals of the third and fourth D-type flip-flops connected in series are responsive to the second clock signal. How the circuit works. The control unit further comprises first and second delay circuits,
The input terminal of the first delay circuit is connected to the edge trigger terminal of the first D-type flip-flop on the front stage side, and the output terminal of the first delay circuit is the second D on the rear stage side. Connected to the edge trigger terminal of the flip-flop,
The input terminal of the second delay circuit is connected to the edge trigger terminal of the third D-type flip-flop on the front stage side, and the output terminal of the second delay circuit is the fourth D on the rear stage side. The method of operating a semiconductor integrated circuit according to claim 14, wherein the semiconductor integrated circuit is connected to the edge trigger terminal of a flip-flop. The gate control terminal of the first latch is connected to one of the input terminal and the output terminal of the first delay circuit;
16. The method of operating a semiconductor integrated circuit according to claim 15, wherein the gate control terminal of the second latch is connected to one of the input terminal and the output terminal of the second delay circuit. The multiplexer comprises third, fourth and fifth gate circuits,
One input terminal and the other input terminal of the third gate circuit are respectively responsive to the first selection control signal and the first clock signal from the control unit,
One input terminal and the other input terminal of the fourth gate circuit are respectively responsive to the second selection control signal and the second clock signal from the control unit,
The first clock output signal generated from the third gate circuit and the second clock output signal generated from the fourth gate circuit are supplied to the fifth gate circuit, so that the first gate output signal is generated. 17. The method of operating a semiconductor integrated circuit according to claim 16, wherein the gate circuit 5 generates a clock output signal as a final output of the multiplexer. A first clock signal source for generating the first clock signal; and a second clock signal source for generating the second clock signal;
Either the first clock signal generated from the first clock signal source or the second clock signal generated from the second clock signal source is generated by the clock selection circuit in response to the selection signal. The method of operating a semiconductor integrated circuit according to claim 17, wherein the semiconductor integrated circuit is generated as the final output of the multiplexer.

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