JP2013191932A - Data communication circuit and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data communication circuit and an electronic device that suppress an increase in peak power.SOLUTION: The data communication circuit includes: a phase-locked loop; a plurality of circuits for data transmission or data reception operable on the basis of a clock supplied from the phase-locked loop; and a phase adjustment section connected between the phase-locked loop and the plurality of circuits to shift the phase of the clock supplied to the plurality of circuits.

Description

  The present invention relates to a data communication circuit and an electronic device.

  Conventionally, from a plurality of input terminals, a plurality of holding circuits that respectively hold reception signals received by the plurality of input terminals, and a reception signal that is selectively connected to one of the plurality of input terminals. There has been a receiving circuit having a detection circuit that detects clock information and outputs a clock signal, and a clock circuit that is connected to the detection circuit and generates an internal clock signal.

  In this receiving circuit, the plurality of holding circuits commonly receive the internal clock signal and hold the corresponding received signal in synchronization with each other.

JP 2009-188489 A

  By the way, in the conventional receiving circuit, when signals are simultaneously input to a plurality of input terminals, the power consumption in the receiving circuit increases and the peak power increases. When the peak power increases, there arises a problem that the power supply voltage and the ground potential are temporarily changed, and the speeding up of the circuit operation is limited.

  The rate control for increasing the circuit operation speed by increasing the peak power is the same when a signal is simultaneously input to a plurality of output terminals in a transmission circuit having a plurality of output terminals.

  Accordingly, it is an object to provide a data communication circuit and an electronic device in which an increase in peak power is suppressed.

  A data communication circuit according to an embodiment of the present invention includes a phase synchronization circuit, a plurality of data transmission or data reception circuits that operate based on a clock supplied from the phase synchronization circuit, the phase synchronization circuit, A phase adjustment unit connected between the plurality of circuits and configured to shift a phase of a clock supplied to the plurality of circuits.

  A data communication circuit and an electronic device in which an increase in peak power is suppressed can be provided.

1 is a diagram illustrating an LSI including a data communication circuit according to a first embodiment. 1 is a diagram illustrating a data communication circuit 100 according to a first embodiment. 3 is a diagram illustrating a skew adjuster 123 of the data communication circuit 100 according to the first embodiment. FIG. 6 is a diagram illustrating operation waveforms of a clock CK and a clock CK_RETURN in the data communication circuit 100 according to the first embodiment. FIG. 6 is a diagram illustrating an example of operation waveforms of a clock and a signal at the time when adjustment of a delay amount is started in the data communication circuit 100 according to the first embodiment. FIG. 6 is a diagram illustrating an example of operation waveforms of a clock and a signal at the time when the adjustment of the delay amount is completed in the data communication circuit 100 according to the first embodiment. FIG. 6 is a diagram illustrating a data communication circuit 200 according to a second embodiment. FIG. 6 is a diagram illustrating a circuit configuration of a VDL included in a DLL 220 of the data communication circuit 200 according to the second embodiment. FIG. FIG. 10 is a diagram illustrating operation waveforms of clocks CK1 to CK4 in the data communication circuit 200 according to the second embodiment. FIG. 6 is a diagram illustrating a data communication circuit 300 according to a third embodiment. FIG. 10 is a diagram illustrating a skew adjuster 323 of the data communication circuit 300 according to the third embodiment. FIG. 11 is a diagram illustrating an example of operation waveforms of a clock and a signal at the time when adjustment of delay amount is started in the data communication circuit 300 according to the third embodiment. FIG. 10 is a diagram illustrating an example of operation waveforms of a clock and a signal at the time when the adjustment of the delay amount is completed in the data communication circuit 300 according to the third embodiment.

  Embodiments to which the data communication circuit and the electronic device of the present invention are applied will be described below.

<Embodiment 1>
FIG. 1 is a diagram illustrating an LSI (Large Scale Integrated circuit) including the data communication circuit according to the first embodiment.

  The LSI chip 10 includes a CPU (Central Processing Unit) 20, a controller 30, a transmitter 40, and a receiver 50. The LSI chip 10 is an example of an electronic device.

  The controller 30, the transmitter 40, and the receiver 50 included in the LSI chip 10 are examples of data communication circuits. The CPU 20 is an example of a processing unit that processes data transmitted and received by the data communication circuit (the controller 30, the transmitter 40, and the receiver 50).

There are four controllers 30, four transmitters 40, and four receivers 50, and each one is disposed along the four sides of the rectangular CPU 20 in plan view. CPU 20
Such an LSI chip 10 is disposed in an information processing apparatus such as a server or a PC (Personal Computer), for example, an external storage device such as a hard disk, a display unit such as a monitor, a mouse, a keyboard, or the like. Are connected to a device such as an input unit via a dedicated bus line.

  In the LSI chip 10, the transmitter 40 transmits data to a device outside the LSI chip 10, and the receiver 50 receives data from a device outside the LSI chip 10. Data transmission / reception by the transmitter 40 and the receiver 50 is performed by the controller 30.

  The controller 30 is a control unit that controls SERDES (SERializer / DESerializer).

  Here, each of the transmitter 40 and the receiver 50 includes n TX (transmission unit) and n RX (reception unit), and is an example of a plurality of circuits for data transmission or reception. It is. The transmitter 40 converts transmission data input from the controller 30 from parallel data to serial data and transmits the converted data. The receiver 50 converts the received data from serial data to parallel data and inputs the converted data to the controller 30.

  Although FIG. 1 illustrates a form in which the data communication circuit includes both the transmitter 40 and the receiver 50, the data communication circuit may include any one of the transmitter 40 and the receiver 50.

  1 shows the LSI chip 10 as an example of the electronic device, the electronic device may be, for example, a mobile phone terminal, a smartphone terminal, a PC (Personal Computer), a server, or the like.

  FIG. 2 is a diagram illustrating the data communication circuit 100 according to the first embodiment.

  The data communication circuit 100 includes a PLL (Phase Locked Loop) 110, a DLL (Delay Locked Loop) 120, a SERDES control unit 130, a transmitter 140, and a receiver 150.

  The PLL 110 is connected to a crystal oscillator TCXO, for example, and includes a loop circuit constructed by a VCO (Voltage Controlled Oscillator), a frequency divider, a phase detector, a charge pump, and an LPF (Low Pass Filter). Including. A reference clock (REF_CK (not shown)) output from the crystal oscillator TCXO is input to the phase detector via the frequency divider, and a clock output from the frequency divider included in the loop circuit is input to the phase detector. .

  The PLL 110 is an example of a clock output unit that performs control so that the phases of two input clocks to the phase detector are equal, and outputs a clock output from the VCO as an output of the PLL 110. In this way, the clock PLL_CK is output from the PLL 110 and input to the DLL 120. The clock PLL_CK is a clock having the same frequency as the clock used when the transmitter 140 and the receiver 150 perform normal operation. The normal operation refers to an operation performed by the data communication circuit 100 after the delay amount adjustment described later is completed.

  The DLL 120 is an example of a phase adjustment unit including a CP / LPF 121, VDLs 122 </ b> A to 122 </ b> H, and a skew adjuster 123.

  The CP / LPF 121 represents a charge pump (CP) and a low pass filter (LPF) as one block.

  The CP of the CP / LPF 121 receives the EARLY signal or the LATE signal from the skew adjuster 123, and the LPF integrates the current output from the CP and outputs a control voltage VCNTL representing the integration result. The control voltage VCNTL output by the LPF is a control voltage for controlling the delay amount given to the clocks CK1 to CK8 by the VDLs 122A to 122H, and is input to each of the VDLs 122A to 122H.

  When the EARLY signal is input from the skew adjuster 123, the CP / LPF 121 outputs a control voltage VCNTL for advancing the phase of the clock CK_RETURN with respect to the clock CK (decreasing the delay amount).

  On the other hand, when the LATE signal is input from the skew adjuster 123, the CP / LPF 121 outputs a control voltage VCNTL for delaying the phase of the clock CK_RETURN with respect to the clock CK (increasing the delay amount).

  Here, as an example, the voltage value of the control voltage VCNTL decreases when the delay amount is increased, and increases when the delay amount is decreased.

  VDLs (Variable Delay Lines) 122A to 122H are examples of delay elements that set a delay amount to be applied to the input clock CK based on the control voltage VCNTL input from the LPF of the CP / LPF 121 to the delay amount control terminals 122A1 to 122H1. .

  The VDLs 122A to 122H output clocks CK1 to CK8 by giving a predetermined delay amount to the input clock, respectively. The VDL 122A gives a delay amount to the clock CK input from the skew adjuster 123 and outputs the clock CK1.

  The VDLs 122B to 122H output clocks CK2 to CK8 by giving delay amounts to the clocks CK1 to CK7, respectively. The clock CK8 output from the VDL 122H is the same as the clock CK_RETURN.

  The VDLs 122A to 122H are constructed of, for example, a CMOS (Complementary Metal Oxide Semiconductor) inverter, and use a delay element that outputs a predetermined delay amount corresponding to the control voltage VCNTL to the input clock. it can.

  The clock input terminal of the VDL 122A is connected to the skew adjuster 123 and receives the clock CK.

  The clock output terminal of the VDL 122A, the clock input terminals and clock output terminals of the VDLs 122B to 122G, and the clock input terminal of the VDL 122H are connected in series as shown in FIG.

  The clock output terminals of the VDLs 122A to 122H are connected to TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150, respectively. Therefore, the clocks CK1 to CK8 output from the VDLs 122A to 122H are input as operation reference clocks to TX0 to TX3 and RX0 to RX3, respectively.

  The clock output terminal of the VDL 122H is connected to the skew adjuster 123, and the clock CK_RETURN output from the clock output terminal of the VDL 122H is input to the skew adjuster 123.

  In FIG. 2, the clock input terminals and the clock output terminals of the VDLs 122A to 122H are shown without reference numerals for the sake of easy viewing.

  The skew adjuster 123 receives the clock PLL_CK input from the PLL 110 and outputs a clock CK in which the number of pulses of the clock PLL_CK is 1/8.

  The skew adjuster 123 detects the phase difference between the clock CK and the clock CK_RETURN input from the VDL 122H, and sends the EARLY signal or the LATE signal to the CP of the CP / LPF 121 so that the phase difference becomes a predetermined phase difference. input. The skew adjuster 123 is an example of a phase detection unit.

  The skew adjuster 123 increases or decreases the output current of the CP of the CP / LPF 121 using the EARLY signal or the LATE signal so that the detected phase difference becomes a desired phase difference, thereby reducing the delay amount in the VDLs 122A to 122H. adjust.

  The skew adjuster 123 generates a pulse CK and outputs an EARLY signal or a LATE signal based on a signal input from the SERDES control unit 130. The skew adjuster 123 receives the skew adjustment start signal SKEW_ADJ_START and the DLL enable signal DLL_AFTER_LOCK_EN from the SERDES control unit 130. Further, the skew adjuster 123 inputs a skew adjustment end signal SKEW_ADJ_STOP to the SERDES control unit 130.

  The SERDES control unit 130 is a control unit corresponding to the controller 30 shown in FIG. The SERDES control unit 130 controls SERDES.

  In FIG. 2, N-bit transmission data transmitted from the SERDES control unit 130 to TX0 to TX3 of the transmitter 140 is indicated by TXPDT0 [N-1: 0] to TXPDT3 [N-1: 0], respectively. Further, N-bit received data received from RX0 to RX3 of the receiver 150 is indicated by RXPDT0 [N-1: 0] to RXPDT3 [N-1: 0]. Note that the number of bits N of transmission data and reception data is an integer of 2 or more.

  Further, the SERDES control unit 130 outputs a skew adjustment start signal SKEW_ADJ_START and a DLL enable signal DLL_AFTER_LOCK_EN to the skew adjuster 123. Further, the skew adjustment end signal SKEW_ADJ_STOP is input from the skew adjuster 123 to the SERDES control unit 130.

  Here, the skew adjustment start signal SKEW_ADJ_START is a signal output from the SERDES control unit 130 to the skew adjuster 123 when the delay amount setting process is started.

  The DLL enable signal DLL_AFTER_LOCK_EN is a signal output from the SERDES control unit 130 to the skew adjuster 123 when the delay amount can be continuously adjusted after the delay amount setting process is completed.

  The skew adjustment end signal SKEW_ADJ_STOP is a signal that is input from the skew adjuster 123 to the SERDES control unit 130 when the delay amount setting process is completed.

  Next, the skew adjuster 123 of the data communication circuit 100 according to the first embodiment will be described with reference to FIG.

  FIG. 3 is a diagram illustrating the skew adjuster 123 of the data communication circuit 100 according to the first embodiment.

  The skew adjuster 123 includes a selector 161, an FF (Flip Flop) 162, AND circuits 163 to 165, an OR circuit 166, an FF 167, a counter (CNTR) 168, and comparators (CMP) 169 and 170.

  The skew adjuster 123 further includes an AND circuit 171, an OR circuit 172, a determination unit 173, an EARLY / LATE controller 174, and an FF 175.

  Here, the FF 162, the counter 168, the determiner 173, the EARLY / LATE controller 174, and the FF 175 all operate with the clock PLL_CK output from the PLL 110 (see FIG. 2).

  In the selector 161, the clock PLL_CK is input from the PLL 110 (see FIG. 2) to one input terminal, and the fixed value 0 (zero) is input to the other input terminal. The selector 161 outputs the clock PLL_CK when the pulse enable signal PULSE_EN input from the OR circuit 172 to the selection signal input terminal is at H (High) level, and has a fixed value 0 when the pulse enable signal PULSE_EN is at L (Low). (Zero) is output. The output of the selector 161 is a clock CK, which corresponds to the clock CK output from the skew adjuster 123 shown in FIG.

  The input terminal of the FF 162 is connected to the SERDES control unit 130 and to one input terminal (the upper input terminal in FIG. 3) of the AND circuit 163. The output terminal of the FF 162 is connected to the other input terminal of the AND 163 (the lower input terminal in FIG. 3) via the inverting arithmetic element, and the other input terminal of the AND circuit 164 (in FIG. 3). Connected to the lower input terminal).

  A skew adjustment start signal SKEW_ADJ_START is input to the FF 162 from the SERDES control unit 130.

  In the AND circuit 163, one input terminal (the upper input terminal in FIG. 3) is connected to the SERDES control unit 130 (see FIG. 2), and the other input terminal (the lower input terminal in FIG. 3). Is connected to the output terminal of the FF 162 through an inversion operation element.

  The output terminal of the AND circuit 163 is connected to the set terminal S of the FF 167 and to the reset terminal R of the FF 175. The output of the AND circuit 163 is input to the reset terminal R of the FF 175 as the start signal START.

  In the AND circuit 164, one input terminal (the upper input terminal in FIG. 3) is connected to the PLL 110 (see FIG. 2) via an inversion operation element, and the other input terminal (the lower side in FIG. 3). Input terminal) is connected to the output terminal of FF162. The output terminal of the AND circuit 164 is connected to one input terminal (the upper input terminal in FIG. 3) of the OR circuit 166.

  One input terminal (the upper input terminal in FIG. 3) of the AND circuit 165 is connected to an output terminal that outputs the lock signal LOCK of the EARLY / LATE controller 174. The other input terminal (the lower input terminal in FIG. 3) of the AND circuit 165 is connected to the SERDES control unit 130 via an inverting arithmetic element, and receives the DLL enable signal DLL_AFTER_LOCK_EN. The output terminal of the AND circuit 165 is connected to the other input terminal of the OR circuit 166 (the lower input terminal in FIG. 3).

  One input terminal (the upper input terminal in FIG. 3) of the OR circuit 166 is connected to the output terminal of the AND circuit 164, and the other input terminal (the lower input terminal in FIG. 3) is connected to the AND circuit 164. The output terminal of the circuit 165 is connected. The output terminal of the OR circuit 166 is connected to the reset terminal R of the FF 167.

  In the FF 167, the set terminal S is connected to the output terminal of the AND circuit 163, the reset terminal R is connected to the output terminal of the OR circuit 166, the output terminal is input to the counter 168, and one input terminal of the AND circuit 171 ( 3 is connected to the upper input terminal in FIG. The output of the FF 167 is input to one input terminal (the upper input terminal in FIG. 3) of the AND circuit 171 as the counter enable signal CNTR_EN.

  The counter 168 is a 3-bit counter whose input terminal is connected to the output terminal of the FF 167 and whose output terminal is connected to the input terminals of the comparators 169 and 170. Therefore, the output of the counter 168 is a 3-bit count signal CNTR [2: 0].

  While the control enable signal CNTR_EN input from the FF 167 is at the H level, the counter 168 counts the clock PLL_CK input to the clock input terminal and outputs a 3-bit count signal CNTR [2: 0] indicating the count number. To do. When the counter 168 counts from 0 to 7, the counter 168 resets the count value and starts counting from 0 again.

  The comparator 169 has an input terminal connected to the output terminal of the counter 168, and an output terminal connected to the other input terminal (lower input terminal in FIG. 3) of the AND circuit 171 via an inverting arithmetic element.

  The comparator 169 outputs an H level signal when the value of the count signal CNTR [2: 0] output by the counter 168 is 1, and the value of the count signal CNTR [2: 0] output by the counter 168 is 1. Otherwise, an L level signal is output.

  The comparator 170 has an input terminal connected to the output terminal of the counter 168, and an output terminal connected to one input terminal (the upper input terminal in FIG. 3) of the determiner 173.

  The comparator 170 outputs an H level signal when the value of the count signal CNTR [2: 0] output by the counter 168 is 3, and the value of the count signal CNTR [2: 0] output by the counter 168 is 3. Otherwise, an L level signal is output.

  The output of the comparator 170 is input to one input terminal (the upper input terminal in FIG. 3) of the determination unit 173 as a determination enable signal JUDGE_EN.

  In the AND circuit 171, one input terminal (the upper input terminal in FIG. 3) is connected to the output terminal of the FF 167, and the other input terminal (the lower input terminal in FIG. 3) is connected via the inverting arithmetic element. The output terminal of the comparator 169 is connected. The output terminal of the AND circuit 171 is connected to one input terminal (the upper input terminal in FIG. 3) of the OR circuit 172 via an inverting operation element. The counter enable signal CNTR_EN is input from the FF 167 to one input terminal of the AND circuit 171 (the upper input terminal in FIG. 3).

  In the OR circuit 172, one input terminal (the upper input terminal in FIG. 3) is connected to the output terminal of the AND circuit 171 via an inverting operation element, and the other input terminal (the lower input terminal in FIG. 3). ) Is connected to the output terminal of FF175. The output terminal of the OR circuit 172 is connected to the selection signal input terminal of the selector 161, and the output of the OR circuit 172 is input to the selection signal input terminal of the selector 161 as the pulse enable signal PULSE_EN.

  In the determiner 173, one input terminal (the upper input terminal in FIG. 3) is connected to the output terminal of the comparator 170, and the other input terminal (the left input terminal in FIG. 3) is the VDL 122H (FIG. 2). Connected to the clock output terminal. The output terminal of the determiner 173 is connected to the input terminal of the EARLY / LATE controller 174.

  The determination enable signal JUDGE_EN is input from the comparator 170 to one input terminal (upper input terminal in FIG. 3) of the determination unit 173, and VDL 122H is input to the other input terminal (left input terminal in FIG. 3). From CK_RETURN.

  When the determination enable signal JUDGE_EN is input from the comparator 170, the determination unit 173 determines the signal level of the clock CK_RETURN input from the VDL 122H at the rising timing of the clock PLL_CK, and outputs the data determination signal JUDGE_DT representing the determination result To do.

  The determination unit 173 outputs an H level data determination signal JUDGE_DT when the signal level of the clock CK_RETURN is H level, and outputs an L level data determination signal JUDGE_DT when the signal level of the clock CK_RETURN is L level. Output.

  The data determination signal JUDGE_DT output from the determiner 173 is input to the input terminal of the EARLY / LATE controller 174.

  The EARLY / LATE controller 174 has an input terminal connected to the output terminal of the determiner 173 and an output terminal on the right side in FIG. 3 connected to one input terminal of the AND circuit 165 (an upper input terminal in FIG. 3). At the same time, it is connected to the set terminal S of the FF 175.

  The output of the output terminal on the right side of the EARLY / LATE controller 174 in FIG. 3 is input to one input terminal of the AND circuit 165 (the upper input terminal in FIG. 3) and the set terminal S of the FF 175 as the lock signal LOCK. Is done.

  The EARLY / LATE controller 174 outputs an EARLY signal or a LATE signal to the CP of the CP / LPF 121 in order to adjust the phase of the clock CK_RETURN with respect to the clock CK.

  The EARLY signal is a signal for advancing the phase of the clock CK_RETURN with respect to the clock CK (decreasing the delay amount), and the LATE signal is for delaying the phase of the clock CK_RETURN with respect to the clock CK (increasing the delay amount). Signal.

  Here, if a 1-bit data width of the clock PLL_CK is described as 1 UI (Unit Interval), the clock CK is a clock having one pulse in 8 UI.

  In the first embodiment, a case where the delay amount setting process is performed from a state (initial state) where the phase difference of the clock CK_RETURN from the clock CK does not reach 3 UI will be described. That is, in the initial state, the sum of the delay amounts by the VDLs 122A to 122H does not reach 3 UI, and the phase of the clock CK_RETURN is delayed from this state.

  Here, when the phase of the clock CK_RETURN is delayed, the output level of the data determination signal JUDGE_DT changes from the L level to the H level because the determiner 173 first detects the falling edge of the clock CK_RETURN. Then, the next change in the output level of the data determination signal JUDGE_DT from the H level to the L level corresponds to the rising edge of the clock CK_RETURN.

  The EARLY / LATE controller 174 outputs a LATE signal so as to delay the phase of the clock CK_RETURN until the rising edge of the clock CK_RETURN is detected.

  That is, in the EARLY / LATE controller 174, the determination unit 173 first detects the falling edge of the clock CK_RETURN, the data determination signal JUDGE_DT changes from L level to H level, and the data determination signal JUDGE_DT changes from H level to L level. The LATE signal is output until the rising edge of the clock CK_RETURN is detected.

  The EARLY / LATE controller 174 outputs an EARLY signal when the data determination signal JUDGE_DT changes from the H level to the L level and the rising edge of the clock CK_RETURN is detected. As a result, the phase of the clock CK_RETURN is advanced, and if the rising edge of the clock CK_RETURN is correctly detected, the determiner 173 detects a section where the clock CK_RETURN rises to the H level.

  The EARLY / LATE controller 174 outputs the LATE signal when the determiner 173 detects the H level of the clock CK_RETURN again after outputting the EARLY signal.

  The EARLY / LATE controller 174 causes the determiner 173 to detect before and after the rising edge of the clock CK_RETURN by repeatedly outputting the LATE signal and the EARLY signal in this way.

  That is, if the determiner 173 detects the rise of the clock CK_RETURN before the rising edge of the clock CK_RETURN, the data decision signal JUDGE_DT is at the L level. is there.

  The EARLY / LATE controller 174 outputs the LOCK signal after repeatedly outputting the LATE signal and the EARLY signal four times in this manner.

  The LOCK signal is a signal that is set to the H level when setting (locking) the delay amount after the setting of the delay amount of the clock CK_RETURN with respect to the clock CK is completed.

  As described above, when the output of the LATE signal and the EARLY signal is repeated four times, the LOCK signal is output because it is correctly detected that the phase difference between the clock CK_RETURN and the clock CK has reached 3 UI. This is for verification.

  The LOCK signal is input to one input terminal (the upper input terminal in FIG. 3) of the AND circuit 165 and the set terminal S of the FF 175.

  The EARLY / LATE controller 174 that performs such an operation can be realized by a sequencer, for example.

  In this example, the LOCK signal is output after the EARLY / LATE controller 174 repeatedly outputs the LATE signal and the EARLY signal four times. However, the number of repetitions is not limited to four, but can be set to any number. May be. Alternatively, the LOCK signal may be output when the EARLY signal is output after the LATE signal (that is, when the rising edge of the clock CK_RETURN is first detected).

  In the FF 175, the set terminal S is connected to the output terminal on the right side of the EARLY / LATE controller 174 in FIG. 3, the reset terminal R is connected to the output terminal of the AND circuit 163, and the output terminal is the other input of the OR circuit 172. The terminal (the lower input terminal in FIG. 3) and the SERDES control unit 130 are connected. The output of the FF 175 is input as a skew adjustment end signal SKEW_ADJ_STOP to the other input terminal (the lower input terminal in FIG. 3) of the OR circuit 172 and the SERDES control unit 130.

  Next, operation waveforms of the clock CK and the clock CK_RETURN in the data communication circuit 100 according to the first embodiment will be described with reference to FIG.

  4A and 4B are diagrams illustrating operation waveforms of the clock CK and the clock CK_RETURN in the data communication circuit 100 according to the first embodiment. FIG. 4A illustrates an operation waveform during adjustment of the delay amount, and FIG. 4B illustrates the delay amount. The operation waveform at the time of normal operation after the adjustment is completed is shown.

  As shown in FIG. 4A, the data communication circuit 100 according to the first embodiment is configured to reduce the number of pulses of the clock PLL_CK input from the PLL 110 in the skew adjuster 123 to 1/8 during the adjustment of the delay amount. CK is output. Such a clock CK is generated by using a pulse enable signal PULSE_EN that is input to the selection signal input terminal of the selector 161 of the skew adjuster 123.

  Here, assuming that the 1-bit data width of the clock PLL_CK is 1 UI, the clock CK is a clock having one pulse in 8 UI.

  For such a clock CK, by setting the pulse enable signal PULSE_EN input to the selection signal input terminal of the selector 161 to the H level at a rate of once every 8 UI, only one pulse is generated from the 8 pulses corresponding to 8 UI of the clock PLL_CK. It is generated by extracting.

  Therefore, the pulse width of the clock CK is the same as the pulse width of the clock PLL_CK. Details will be described later with reference to the timing chart of FIG.

  In the data communication circuit 100 of the first embodiment, the clock CK input to the VDL 122A is used to shift the phase of the clock signal input to each of the TX0 to TX3 of the transmitter 140 and the RX0 to RX3 of the receiver 150. And a control so that the phase difference from the clock CK_RETURN output from the VDL 122H is 3 UI.

  Therefore, when the phase adjustment is completed, the phase of the clock CK_RETURN is delayed by 3 UI with respect to the clock CK, as shown in FIG.

  Here, the phase difference between the clock CK and the clock CK_RETURN is set to 3 UI because the phases of the clocks CK1 to CK8 input to each of the eight circuits TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150 are set. This is to make all the phases different.

  In other words, the phase difference between the clocks CK1 to CK8 input to each of the eight circuits TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150 is a non-integer without having an integer multiple relationship. This is to have a double relationship.

  If the phase difference between the clock CK and the clock CK_RETURN is set to 3UI, the phases of the clocks CK1 to CK8 input to the VDLs 122A to 122H as operation reference clocks are all different by 3UI / 8, and the transmitter 140 receives the TX0 to TX3. The circuit operation timings of the eight circuits RX0 to RX3 of the device 150 can be shifted.

  Thus, by shifting the timing of the circuit operation, the data communication circuit 100 according to the first embodiment realizes suppression of an increase in peak power.

  After the setting of the delay amount is completed, the clock enable signal PULSE_EN input to the selection signal input terminal of the selector 161 (see FIG. 3) is always fixed to the H level, so that the clock PLL_CK input from the PLL 110 is set. As shown in FIG. 4B, it is output as a clock CK. In this case, the phases of the clock PLL_CK and the clock CK are the same.

  As a result, the clock CK_RETURN output from the VDL 122H is a clock having a 3UI phase delayed from the clock CK. This is due to the delay amount adjustment described above.

  Next, the operation waveforms of each clock and each signal in the data communication circuit 100 according to the first embodiment will be described with reference to timing charts of FIGS.

  FIG. 5 is a diagram illustrating an example of operation waveforms of the clock and the signal at the time when the adjustment of the delay amount is started in the data communication circuit 100 according to the first embodiment.

  FIG. 6 is a diagram illustrating an example of operation waveforms of the clock and the signal at the time when the adjustment of the delay amount is completed in the data communication circuit 100 according to the first embodiment.

  5 and 6, the H and L level notations of the clock and signal are omitted, but a section where the clock and signal levels are high represents an H level section, and a section where the level is low is an L level section. Represents.

  FIG. 5 illustrates a case where the delay amount setting process is performed from a state (initial state) where the phase difference of the clock CK_RETURN relative to the clock CK does not reach 3 UI. That is, in the initial state, the sum of the delay amounts by the VDLs 122A to 122H has not reached 3 UI, and the case where the delay amount setting process for delaying the phase of the clock CK_RETURN is performed from this state will be described.

  In the first embodiment, when increasing the delay amount, the voltage value of the control voltage VCNTL is decreased, and when decreasing the delay amount, the voltage value of the control voltage VCNTL is increased.

  Therefore, in the initial state, the control voltage VCNTL output from the CP / LPF 121 is assumed to be set to the maximum value in order to delay the phase of the clock CK_RETURN.

  First, as shown in FIG. 5, at the start of the delay amount setting process, at time t1, the skew adjustment start signal SKEW_ADJ_START output from the SERDES control unit 130 transitions from the L level to the H level.

  As a result, the start signal START output from the AND circuit 163 becomes H level at the next rising time t2 of the clock PLL_CK.

  Furthermore, since the H level is inverted and input to the AND circuit 163 via the FF 162 at time t3 after one cycle of the clock PLL_CK, the start signal START changes to the L level.

  At time t3, the counter enable signal CNTR_EN output from the FF 167 becomes H level in response to the rising edge of the start signal START at time t2. As a result, the counter 168 starts counting the clock PLL_CK.

  Further, when the counter enable signal CNTR_EN becomes H level at time t3, the output of the AND circuit 171 becomes “1”, is inverted by the inversion operation element, and is input to the OR circuit 172, so that the OR circuit 172 outputs. The pulse enable signal PULSE_EN to be turned becomes “0” (L level). Therefore, the selector 161 reflects the fixed value 0 (zero) in the clock CK.

  Next, at time t4 after one cycle of the clock PLL_CK, the value of the count signal CNTR [2: 0] becomes 1, and the output signal of the comparator 169 becomes H level. 0 ”.

  Since the output of the AND circuit 171 is inverted by the inversion operation element and input to the OR circuit 172, the output of the OR circuit 172 becomes H level.

  That is, at time t4, the pulse enable signal PULSE_EN becomes H level.

  As a result, since the selector 161 selects the clock PLL_CK and outputs it as the clock CK, the clock CK reflects the pulse of the clock PLL_CK at time t4.

  Next, at the time t5 after one cycle of the clock PLL_CK, the value of the count signal CNTR [2: 0] becomes 2, so that the output signal of the comparator 169 becomes L level. Therefore, at time t5, the pulse enable signal PULSE_EN output from the OR circuit 172 becomes the L level (“0”). Thereby, the selector 161 selects the fixed value 0 (zero) and reflects it in the clock CK. That is, at time t5, the clock CK does not rise and is held at the L level.

  Thereafter, the counter 168 counts the clock PLL_CK, whereby the value of the count signal CNTR [2: 0] increases from 3 to 7. During this period, the output signal of the comparator 169 is at the L level, so that the OR circuit 172 The pulse enable signal PULSE_EN to be output is at L level.

  Therefore, while the count signal CNTR [2: 0] takes a value from 3 to 7, the clock CK does not rise and is held at the L level.

  As described above, when the pulse enable signal PULSE_EN input to the selection signal input terminal of the selector 161 is set to the H level at a rate of once in 8 UI of the clock PLL_CK, one pulse from 8 pulses corresponding to 8 UI of the clock PLL_CK. A clock CK is generated by extracting only.

  At time t6 when the value of the count signal CNTR [2: 0] becomes 3, the determination enable signal JUDGE_EN output from the comparator 170 becomes H level.

  At time t7 when the determination enable signal JUDGE_EN becomes H level and the clock PLL_CK next rises, the clock CK_RETURN is at L level, so the data determination signal JUDGE_DT output from the determiner 173 is at L level.

  The EARLY / LATE controller 174 outputs a LATE signal to the CP / LPF 121 in order to delay the phase of the clock CK_RETURN.

  Then, after time t8 when the value of the count signal CNTR [2: 0] becomes 1 again, the same operation as that after time t1 is repeated with the phase of the clock CK_RETURN slightly delayed.

  Even at time t9 when the value of the count signal CNTR [2: 0] becomes 3 again, the phase difference between the clock CK_RETURN and the clock CK does not reach 3UI, so that the clock CK_RETURN is the CP of the CP / LPF 121 at the time t10. It is further delayed by the output LATE signal.

  It should be noted that the time from when the count value of the counter 168 reaches 3 and the phase is compared by the determiner 173 until the count becomes 4 to 7 is provided as a time for stabilizing the control voltage VCNTL. Yes.

  Therefore, when taking a longer time for stabilizing the control voltage VCNTL, the maximum number of counts may be increased by increasing the number of bits of the counter 168.

  Next, the operation at the time when the adjustment of the delay amount is completed in the data communication circuit 100 according to the first embodiment will be described with reference to FIG.

  The operation shown in FIG. 6 is an operation after the output of the LATE signal and the EARLY signal by the EARLY / LATE controller 174 is repeated three times.

  First, at time t11 after the value of the count signal CNTR [2: 0] becomes 3 and the determination enable signal JUDGE_EN output from the comparator 170 becomes H level, the clock CK_RETURN is at H level. Outputs an H level data determination signal JUDGE_DT.

  At time t11, the EARLY / LATE controller 174 outputs a LATE signal to the CP / LPF 121 in order to detect the rising edge of the clock CK_RETURN. As a result, the control voltage VCNTL output by the LPF of the CP / LPF 121 decreases.

  At time t12, which is one cycle after the clock PLL_CK from time t11, the data determination signal JUDGE_DT and the LATE signal become L level.

  Then, at time t13 when the value of the count signal CNTR [2: 0] becomes 1, similarly to the time t4 in FIG. 5, since the output signal of the comparator 169 becomes H level, the output of the AND circuit 171 is It becomes “0”.

  As a result, the output of the OR circuit 172 becomes H level, and the pulse enable signal PULSE_EN becomes H level.

  Since the selector 161 selects the clock PLL_CK and outputs it as the clock CK, the clock CK reflects the pulse of the clock PLL_CK at time t13.

  Since the value of the count signal CNTR [2: 0] becomes 2 at time t14 after one cycle of the clock PLL_CK from time t13, the output signal of the comparator 169 becomes L level. Therefore, at time t13, the pulse enable signal PULSE_EN output from the OR circuit 172 becomes L level (“0”), and the clock CK does not rise and is held at L level.

  Then, at time t15 when the value of the count signal CNTR [2: 0] becomes 3, the determination enable signal JUDGE_EN output from the comparator 170 becomes H level.

  At time t16, which is one cycle after the clock PLL_CK from time t15, since the clock CK_RETURN is at L level, the determiner 173 outputs an L level data determination signal JUDGE_DT.

  Further, the EARLY / LATE controller 174 to which the L level data determination signal JUDGE_DT is input outputs the EARLY signal to the CP / LPF 121 in order to advance the phase of the clock CK_RETURN at time t16.

  The EARLY / LATE controller 174 determines that the phase difference of the clock CK_RETURN with respect to the clock CK has reached 3 UI because the output of the LATE signal and the EARLY signal has been repeated four times, and that the delay amount setting process has ended, and the lock signal LOCK To H level.

  When the lock signal LOCK becomes H level, the skew adjustment end signal SKEW_ADJ_STOP is output from the FF 175 to the SERDES control unit 130 and the OR circuit 172 by inputting the H level lock signal LOCK to the set terminal S of the FF 175.

  When the skew adjustment end signal SKEW_ADJ_STOP at the H level is input, the SERDES control unit 130 ends the delay amount setting process.

  The skew adjustment end signal SKEW_ADJ_STOP is a signal input from the skew adjuster 123 to the SERDES control unit 130 when the delay amount setting process is completed.

  Further, when the skew adjustment end signal SKEW_ADJ_STOP at the H level is input to the OR circuit 172, the output of the OR circuit 172 is clipped to “1”. Thereafter, the selector 161 selects the PLL_CK input from the PLL 110. Output as clock CK.

  Therefore, after time t17, which is one cycle after the clock PLL_CK from time t16, the clock CK has a waveform reflecting the clock PLL_CK.

  Further, at time t17, the output of the AND circuit 165 becomes “1” by the lock signal LOCK which becomes H level at t16, and thereby the output of the OR circuit 166 becomes “1”, so that the FF 167 is reset, The counter enable signal CNTR_EN output from the FF 167 becomes L level. When the counter enable signal CNTR_EN becomes L level, the counter 168 stops counting.

  When the counter enable signal CNTR_EN becomes L level, the output of the AND circuit 171 becomes “0” and the output of the OR circuit 172 becomes “1”. At time t17, the selector 161 also selects PLL_CK input from the PLL 110 and outputs it as the clock CK.

  After time t17, the data communication circuit 100 performs a normal operation using the delay amount set by time t16.

  When the delay amount setting process is completed as described above, if it is desired to continue setting the delay amount, the H level DLL enable signal DLL_AFTER_LOCK_EN may be output from the SERDES control unit 130 to the skew adjuster 123.

  The DLL enable signal DLL_AFTER_LOCK_EN is a signal output from the SERDES control unit 130 to the skew adjuster 123 when the delay amount can be continuously adjusted after the delay amount setting process is completed.

  When the DLL enable signal DLL_AFTER_LOCK_EN becomes H level, the outputs of the AND circuits 164 and 165 become “0” and the output of the OR circuit 166 becomes 0. Therefore, the FF 167 is not reset and the counter enable signal CNTR_EN becomes H level. be able to. Thereby, the data communication circuit 100 is in a state where the phase can be continuously adjusted.

  After time t17 when the delay amount setting process described above is completed and the normal operation is started, the clock CK input to the VDL 122A and the clock CK_RETURN output from the VDL 122H have a phase difference of 3 UI.

  At this time, the clock CK input to the VDL 122A and the clock CK_RETURN output from the VDL 122H have a phase difference of 3 UI as shown in FIG.

  The 3UI phase difference is equally allocated to the clocks CK1 to CK8 output from the VDLs 122A to 122H, respectively.

  That is, the clocks CK1 to CK8 are input to TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150 in a state having a phase difference of 3 UI / 8 in order.

  For this reason, TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150 operate using the clocks CK1 to CK8 having different phases by 3 UI / 8 as operation reference clocks, respectively.

  Therefore, according to the data communication circuit 100 of the first embodiment, the operation timings of TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150 can be shifted, so that TX0 to TX3 and reception of the transmitter 140 can be shifted. The increase in peak power accompanying the operation of RX0 to RX3 of the device 150 can be suppressed.

  In this way, shifting the timing of the operations of TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150 is realized by providing a non-integer multiple relationship to the phase difference between the clocks CK1 to CK8. It is.

  As described above, according to the first embodiment, it is possible to provide the data communication circuit 100 in which an increase in peak power is suppressed.

  Further, as described above, in the data communication circuit 100 according to the first embodiment, the signal path through which the clock PLL_CK output from the PLL 110 is converted into the clock CK when performing the delay amount setting process, and the normal operation The signal path through which the clock PLL_CK output from the PLL 110 after shifting to is the same.

  This signal path is a signal path through which the clock PLL_CK input from the PLL 110 shown in FIG. 2 to the DLL 120 is input to the VDLs 122A to 122H via the selector 161 shown in FIG.

  Here, if the signal path in the delay amount setting process is different from the signal path in the normal operation, the delay amount set in the delay amount setting process may not be an accurate value in the signal path in the normal operation. Strictly speaking, the delay time differs depending on the signal path, because the path length is different or the circuit element is included in a different part of the signal path. Such a difference in signal path becomes more prominent as the frequency of the clock PLL_CK increases.

  On the other hand, according to the data communication circuit 100 of the first embodiment, since the signal path for setting the delay amount is the same as the signal path after the shift to the normal operation, an accurate delay amount can be obtained. The increase in peak power can be effectively suppressed.

  In the above description, the mode in which the phase difference between the clock CK and the clock CK_RETURN is set to 3 UI has been described so that the phase difference between the clocks CK1 to CK8 has a non-integer multiple relationship.

  However, the phase difference between the clock CK and the clock CK_RETURN is not limited to 3 UI, and may be set to 5 UI, 6 UI, or 7 UI. In these cases, the clocks CK1 to CK8 have a phase difference of 5UI / 8, 6UI / 8, or 7UI / 8, respectively, and the clocks CK1 to CK8 all have different phases.

  Therefore, even when the phase difference between the clock CK and the clock CK_RETURN is set to 5 UI, 6 UI, or 7 UI, data communication in which the increase in peak power is suppressed is the same as when the phase difference is set to 3 UI as described above. A circuit 100 can be provided.

  Further, the phase difference between the clock CK and the clock CK_RETURN may be set to 2 UI. In this case, the timing of circuit operation is the same for four sets of TX0 and RX0, TX1 and RX1, TX2 and RX2, and TX3 and RX3, respectively, but compared to the case where the circuit operation of the eight circuits is the same, data communication The peak power in the circuit 100 can be suppressed to ¼.

  Further, the phase difference between the clock CK and the clock CK_RETURN may be set to 4 UI. In this case, the timing of circuit operation is the same for two sets of TX0, TX2, RX0, and RX2 and TX1, TX3, RX1, and RX3, respectively, but compared to the case where the circuit operation of eight circuits is the same. For example, the peak power in the data communication circuit 100 can be reduced to ½.

  In the above description, the mode in which the clocks CK1 to CK8 are supplied to the eight transmission and reception circuits (TX0 to TX3 and RX0 to RX3) has been described. However, the number of circuits is not limited to eight, and two or more circuits are provided. I just need it. In this case, the phase difference between the clock CK and the clock CK_RETURN is such that the clock supplied to at least some of the circuits is supplied to other circuits so that the phases of the clocks supplied to all the circuits are not the same. And should be different.

  In the above description, the data communication circuit 100 has been described as including both transmission and reception circuits (TX0 to TX3 and RX0 to RX3). However, the data communication circuit 100 includes a plurality of either transmission or reception circuits. Form may be sufficient.

  In the above description, the form in which the VDLs 122A to 122H set the delay amounts of the clocks CK1 to CK8 according to the control voltage VCNTL input from the LPF of the CP / LPF 121 has been described. Such VDLs 122A to 122H are circuits that adjust the phases of the clocks CK1 to CK8 in an analog manner based on the control voltage VCNTL.

  However, as the VDLs 122A to 122H, for example, delay elements in which a plurality of inverters and a plurality of selectors are alternately connected in series may be used. In this case, the delay amount can be set by converting the control voltage VCNTL into digital data and selecting the number of inverters and selectors through which the clock CK passes by the digitally converted control voltage VCNTL.

<Embodiment 2>
The data communication circuit 200 according to the second embodiment is different from the data communication circuit 100 according to the first embodiment in the delay amount setting processing technique. Accordingly, the data communication circuit 200 according to the second embodiment is partly different from the data communication circuit 100 according to the first embodiment in circuit configuration.

  Hereinafter, the same components as those of the data communication circuit 100 according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 7 is a diagram illustrating the data communication circuit 200 according to the second embodiment.

  The data communication circuit 200 includes a crystal oscillator (TCXO) 210, a DLL 220, a SERDES control unit 230, and a transmitter 240. FIG. 8 is a diagram illustrating a circuit configuration of the VDL included in the DLL 220 of the data communication circuit 200 according to the second embodiment.

  The crystal oscillator (TCXO) 210 is an example of a clock output unit.

  The DLL 220 includes a CP / LPF 121, VDLs 222A to 222H, and a PD (Phase Detector) 223.

  The control voltages VCNTL are input from the CP / LPF 121 (see FIG. 7) to the delay amount control terminals 222A1 to 222H1, and the skew adjustment shift signal SKEW_ADJ_SFT is input from the SERDES control unit to the VDLs 222A to 222H.

  The VDLs 222A to 222H are connected in series and propagate while sequentially delaying the clock CK input to the VDL 222A. Among the VDLs 222A to 222H, the VDLs 222A to 222D output clocks CK1 to CK4 according to the skew adjustment shift signal SKEW_ADJ_SFT, respectively.

  As illustrated in FIG. 8, the VDLs 222 </ b> A to 222 </ b> H include inverters 501 to 504, a selector 511, an input terminal 520, and output terminals 521 and 522. The inverters 501 to 504 are connected in series between the input terminal 520 and the output terminal 521. The output terminals of the inverters 501 to 503 are connected to the input terminals of the next-stage inverters 502 to 504 and to the input terminal of the selector 511, respectively. The output terminal of the inverter 504 is connected to the output terminal 521 and the input terminal of the selector 511.

  The inverters 501 to 504 receive the control voltage VCNTL from the CP / LPF 121 (see FIG. 7), and the delay amount in the inverters 501 to 504 is determined according to the control voltage VCNTL.

  A delay amount in the inverters 501 to 504 (a delay amount generated between the input terminal 520 and the output terminal 521) is set to 1 UI. Since the delay amounts of the inverters 501 to 504 are the same, each has a delay amount of UI / 4.

  The selector 511 has an input terminal connected to the output terminals of the inverters 501 to 504, a selection signal input terminal connected to the SERDES control unit 230, and an output terminal connected to the output terminal 522.

  The selector 511 selects one of the outputs of the inverters 501 to 504 according to the skew adjustment shift signal SKEW_ADJ_SFT input to the selection signal input terminal, and outputs the selected output to the output terminal 522.

  The clock CK is input to the input terminal 520 of the VDL 222A. A clock delayed by VDL in the previous stage is input to input terminals 520 of VDLs 222B to 222H.

  The output terminals 521 of the VDLs 222A to 222G are connected to the input terminal 520 of the next-stage VDL. The output terminal 521 of the VDL 222H outputs a clock CK_RETURN to the PD 223.

  The output terminals 522 of the VDLs 222A to 222D input the clocks CK1 to CK4 to the transmitter 240 (TX0 to TX3), respectively. The output terminals 522 of the VDLs 222E to 222H are open.

  The skew adjustment shift signal SKEW_ADJ_SFT input from the SERDES control unit 230 to the selection signal input terminal of the selector 511 is a 2-bit signal. The selector 511 selects the output of the inverter 501 when the value of the skew adjustment shift signal SKEW_ADJ_SFT is “00”. The selector 511 selects the output of the inverter 502 when the value of the skew adjustment shift signal SKEW_ADJ_SFT is “01”. The selector 511 selects the output of the inverter 502 when the value of the skew adjustment shift signal SKEW_ADJ_SFT is “10”. The selector 511 selects the output of the inverter 504 when the value of the skew adjustment shift signal SKEW_ADJ_SFT is “11”.

  When the skew adjustment shift signal SKEW_ADJ_SFT is input, the selector 511 selects and outputs the output of the inverter (any one of 501 to 504) determined by the skew adjustment shift signal SKEW_ADJ_SFT.

  The PD 223 receives the reference clock REF_CK output from the crystal oscillator (TCXO) 210 and the clock CK_RETURN output from the VDL 222H, and outputs signals UP and DN corresponding to the phase difference between the reference clock REF_CK and the clock CK_RETURN.

  The PD 223 performs a delay amount setting process based on the skew adjustment start signal SKEW_ADJ_START and the DLL enable signal DLL_AFTER_LOCK_EN.

  The SERDES control unit 230 is a control unit that controls SERDES.

  The CP / LPF 121 converts the signals UP and DN input from the PD 223 into currents by a charge pump, integrates the currents to convert them into voltages, and outputs a control voltage VCNTL.

  In FIG. 7, N-bit transmission data transmitted from the SERDES control unit 230 to TX0 to TX3 of the transmitter 140 is denoted by TXPDT0 [N-1: 0] to TXPDT3 [N-1: 0], respectively.

  The SERDES control unit 230 outputs a skew adjustment start signal SKEW_ADJ_START and a DLL enable signal DLL_AFTER_LOCK_EN to the PD 223 of the DLL 220. In addition, the SERDES control unit 230 outputs the skew adjustment shift signal SKEW_ADJ_SFT to the VDLs 222A to 222H.

  Here, the skew adjustment start signal SKEW_ADJ_START is a signal output from the SERDES control unit 230 to the PD 223 when the delay amount setting process is started.

  The DLL enable signal DLL_AFTER_LOCK_EN is a signal output from the SERDES control unit 230 to the PD 223 when the delay amount can be continuously adjusted after the delay amount setting process is completed.

  The skew adjustment shift signal SKEW_ADJ_SFT is a 2-bit signal and is used by the selector 511 to select one of the outputs of the inverters 501 to 504.

  In the data communication circuit 200 of the second embodiment, the transmitter 240 includes VCOs (Voltage Controlled Oscillators) 241 to 244. The VCOs 241 to 244 operate using the clocks CK1 to CK4 input from the VDLs 222A to 222D as reference clocks, and oscillate at a frequency eight times that of the clocks CK1 to CK4.

  In the second embodiment, the VDLs 222A to 222H have the crystal oscillator (TCXO) 210 assuming that the data width of 1 bit of the clock output from the VCOs 241 to 244 included in TX0 to TX3 of the transmitter 240 is 1 UI (Unit Interval). The output reference clock REF_CK is delayed by 1 UI and output.

  TX0 to TX3 of the transmitter 240 operate based on a clock oscillated by the VCOs 241 to 244.

  In the data communication circuit 200 of the second embodiment, no receiver is connected to the VDLs 222E to 222H of the DLL 220, but a receiver may be connected in the same manner as the data communication circuit 100 of the first embodiment.

  9A and 9B are diagrams illustrating operation waveforms of the clocks CK1 to CK4 in the data communication circuit 200 according to the second embodiment. FIG. 9A illustrates an operation waveform before adjustment of the delay amount, and FIG. 9B illustrates adjustment of the delay amount. The operation waveform at the time of normal operation after ending is shown.

  As shown in FIG. 9A, before the delay amount is adjusted, the clocks CK1 to CK4 input to TX0 to TX3 of the transmitter 240 are set to the reference clock REF_CK output from the crystal oscillator (TCXO) 210 by 1 UI. It has a delayed waveform.

  When the skew adjustment start signal SKEW_ADJ_START is input to the PD 223 from the SERDES control unit 230, the PD 223 and the CP / LPF 121 output a control voltage VCNTL whose voltage value is adjusted so as to delay the phase by 1 UI. At this time, the skew adjustment shift signal SKEW_ADJ_SFT is “00”, and the selector 511 selects the output of the inverter 501 among the VDLs 222A to 222H.

  In this state, the data communication circuit 200 according to the second embodiment is once locked.

  After entering the locked state, the SERDES control unit 230 sets the value of the skew adjustment shift signal SKEW_ADJ_SFT input to the VDLs 222A to 222D to “00”, “01”, “10”, and “11”. Note that the value of the skew adjustment shift signal SKEW_ADJ_SFT input to the VDLs 222E to 222H remains “00”.

  Thereby, the selectors 511 in the VDLs 222A to 222D select the outputs of the inverters 501, 502, 503, and 504, respectively.

  Therefore, as shown in FIG. 9B, the waveforms of the clocks CK1 to CK4 are delayed by 1/4 of 1 UI (by UI / 4).

  Thereafter, the delay amounts in the VDLs 222A to 222H are fixed, and CK1 to CK4 shown in FIG. 9B are input to the VCOs 241 to 244 of TX0 to TX3 of the transmitter 240, and the VCOs 241 to 244 are out of phase by UI / 4. Output the clock.

  Therefore, according to the data communication circuit 200 of the second embodiment, the operation timing of TX0 to TX3 of the transmitter 240 can be shifted, so that an increase in peak power accompanying the operation of TX0 to TX3 of the transmitter 240 is suppressed. can do.

  Thus, shifting the timing of the operations of TX0 to TX3 of the transmitter 240 is realized by providing a non-integer multiple relationship to the phase difference between the clocks CK1 to CK4.

  As described above, according to the second embodiment, it is possible to provide the data communication circuit 200 in which an increase in peak power is suppressed.

  In the second embodiment, the frequency of the reference clock REF_CK output from the TCXO is divided into the frequency of 1/8 of the frequency of the VCOs 241 to 244 for operating the TX0 to TX3, and the delay amount is set using the clock CK and CK_RETURN. By performing the setting process, the power consumption during the delay amount setting process can be reduced.

  In addition, although the form using TCXO was demonstrated above, you may use an injection-type VCO instead of TCXO.

<Embodiment 3>
FIG. 10 is a diagram illustrating a data communication circuit 300 according to the third embodiment.

  The data communication circuit 300 includes a PLL 110, a DLL 320, a SERDES control unit 130, a transmitter 140, and a receiver 150.

  The DLL 320 includes a CP / LPF 121, VDLs 122A to 122H, and a skew adjuster 323.

  In the data communication circuit 300 according to the third embodiment, the configuration of the skew adjuster 323 of the DLL 320 is different from the skew adjuster 123 of the DLL 120 of the data communication circuit 100 according to the first embodiment.

  Since the other components are the same as those of the data communication circuit 100 according to the first embodiment, the same components are denoted by the same reference numerals and the description thereof is omitted.

  The skew adjuster 323 receives the clock PLL_CK input from the PLL 110 and outputs a clock CK in which the frequency of the clock PLL_CK is 1/8.

  The skew adjuster 323 detects the phase difference between the clock CK and the clock CK_RETURN input from the VDL 122H, and sends the EARLY signal or the LATE signal to the CP of the CP / LPF 121 so that the phase difference becomes a predetermined phase difference. input.

  The skew adjuster 323 generates a pulse CK and outputs an EARLY signal or a LATE signal based on a signal input from the SERDES control unit 130. The skew adjuster 323 receives a skew adjustment start signal SKEW_ADJ_START and a DLL enable signal DLL_AFTER_LOCK_EN from the SERDES control unit 130. Further, the skew adjuster 323 inputs a skew adjustment end signal SKEW_ADJ_STOP to the SERDES control unit 130.

  Next, the skew adjuster 323 of the data communication circuit 300 according to the third embodiment will be described with reference to FIG.

  FIG. 11 is a diagram illustrating the skew adjuster 323 of the data communication circuit 300 according to the third embodiment.

  The skew adjuster 323 includes FF 361, FF 162, AND circuits 163, 164, FF 367, a counter (CNTR) 168, comparators 369 and 170, an AND circuit 371, a determiner 173, an EARLY / LATE controller 174, and an FF 175.

  Here, the FF 162, the counter 168, the determiner 173, the EARLY / LATE controller 174, and the FF 175 all operate by receiving the clock PLL_CK output from the PLL 110 (see FIG. 10).

  The skew adjuster 323 of the third embodiment is different from the skew adjuster 123 of the first embodiment in that a clock obtained by dividing the clock PLL_CK input from the PLL 110 by 8 is input to the VDL 122A as the clock CK. Further, the circuit configuration is different in relation to this difference.

  Hereinafter, the difference from the skew adjuster 123 of the first embodiment will be mainly described.

  The FF 361 has an input terminal connected to the output terminal of the AND circuit 371, and an output terminal connected to the VDL 122A. The FF 361 outputs the clock CK when the clock PLL_CK is input to the clock input terminal. The output of the FF 361 corresponds to the clock CK output from the skew adjuster 323 shown in FIG.

  The input terminal of the FF 162 is connected to the SERDES control unit 130 and to one input terminal (the upper input terminal in FIG. 11) of the AND circuit 163. Further, the output terminal of the FF 162 is connected to the other input terminal of the AND 163 (lower input terminal in FIG. 11) through the inverting arithmetic element, and the other input terminal (in FIG. 11) of the AND circuit 164. Connected to the lower input terminal).

  A skew adjustment start signal SKEW_ADJ_START is input to the FF 162 from the SERDES control unit 130.

  In the AND circuit 163, one input terminal (the upper input terminal in FIG. 11) is connected to the SERDES control unit 130 (see FIG. 10), and the other input terminal (the lower input terminal in FIG. 11). Is connected to the output terminal of the FF 162 through an inversion operation element.

  The output terminal of the AND circuit 163 is connected to the set terminal S of the FF 367 and to the reset terminal R of the FF 175. The output of the AND circuit 163 is input to the reset terminal R of the FF 175 as the start signal START.

  In the AND circuit 164, one input terminal (the upper input terminal in FIG. 11) is connected to the PLL 110 (see FIG. 10) via an inverting operation element, and the other input terminal (the lower side in FIG. 11). Input terminal) is connected to the output terminal of FF162. The output terminal of the AND circuit 164 is connected to the reset terminal R of the FF367.

  In the FF 367, the set terminal S is connected to the output terminal of the AND circuit 163, the reset terminal R is connected to the output terminal of the AND circuit 164, the output terminal is the input terminal of the counter 168, and one input terminal of the AND circuit 371 ( 11 is connected to the upper input terminal in FIG. The output of the FF 367 is input to one input terminal (the upper input terminal in FIG. 11) of the AND circuit 371 as the counter enable signal CNTR_EN.

  The counter 168 is a 3-bit counter whose input terminal is connected to the output terminal of the FF 367 and whose output terminal is connected to the input terminals of the comparators 369 and 170.

  While the control enable signal CNTR_EN input from the FF 367 is at the H level, the counter 168 counts the clock PLL_CK input to the clock input terminal and outputs a 3-bit count signal CNTR [2: 0] representing the count number. To do. When the counter 168 counts from 0 to 7, the counter 168 resets the count value and starts counting from 0 again.

  The comparator 369 has an input terminal connected to the output terminal of the counter 168 and an output terminal connected to the other input terminal of the AND circuit 371 (lower input terminal in FIG. 11).

  The comparator 369 outputs an H level (“1”) when the value of the second bit of the count signal CNTR [2: 0] output from the counter 168 is 0, and the count signal CNTR [2: 0] is 2 When the value of the bit is 1, L level (“0”) is output.

  That is, the comparator 369 outputs an H level (“1”) because the value of the second bit is 0 while the value of the count signal CNTR [2: 0] of the counter 168 is 0 to 3, and the counter 168 When the value of the count signal CNTR [2: 0] is between 4 and 7, since the value of the second bit is 1, the L level (“0”) is output.

  The comparator 170 has an input terminal connected to the output terminal of the counter 168, and an output terminal connected to one input terminal (the upper input terminal in FIG. 11) of the determiner 173.

  The output of the comparator 170 is input to one input terminal (the upper input terminal in FIG. 11) of the determination unit 173 as the determination enable signal JUDGE_EN.

  In the AND circuit 371, one input terminal (the upper input terminal in FIG. 11) is connected to the output terminal of the FF 367, and the other input terminal (the lower input terminal in FIG. 11) is connected to the output terminal of the comparator 369. It is connected. The output terminal of the AND circuit 371 is connected to the input terminal of the FF 361. The counter enable signal CNTR_EN is input from the FF 367 to one input terminal of the AND circuit 371 (the upper input terminal in FIG. 11).

  In the AND circuit 371, when the H level counter enable signal CNTR_EN is input from the FF 367, the value of the count signal CNTR [2: 0] of the counter 168 is 0 to 3, and the comparator 369 is at the H level (“1”). ) Is output, 1 is output.

  In addition, when the H level counter enable signal CNTR_EN is input from the FF 367, the AND circuit 371 sets the count signal CNTR [2: 0] of the counter 168 to 4 to 7 and sets the comparator 369 to the L level (“ While 0 ") is output, 0 is output.

  The output of the AND circuit 371 is reflected in the output of the FF 361 at a timing delayed by one cycle of the clock PLL_CK. Since the output of the FF 361 is output from the skew adjuster 323 as the clock CK, the frequency of the clock CK during the delay amount setting process is 1/8 of the clock PLL_CK.

  In the determination device 173, one input terminal (the upper input terminal in FIG. 11) is connected to the output terminal of the comparator 170, and the other input terminal (the left input terminal in FIG. 11) is VDL 122H (FIG. 10). Connected to the clock output terminal. The output terminal of the determiner 173 is connected to the input terminal of the EARLY / LATE controller 174.

  The EARLY / LATE controller 174 has an input terminal connected to the output terminal of the determiner 173, and an output terminal on the right side in FIG. 11 connected to the set terminal S of the FF 175.

  The output of the output terminal on the right side in FIG. 11 of the EARLY / LATE controller 174 is input to the set terminal S of the FF 175 as the lock signal LOCK.

  In the FF 175, the set terminal S is connected to the output terminal on the right side of the EARLY / LATE controller 174 in FIG. 11, the reset terminal R is connected to the output terminal of the AND circuit 163, and the output terminal is connected to the SERDES control unit 130. ing. The output of the FF 175 is input to the SERDES control unit 130 as a skew adjustment end signal SKEW_ADJ_STOP.

  Next, operation waveforms of each clock and each signal in the data communication circuit 300 according to the third embodiment will be described with reference to timing charts of FIGS.

  FIG. 12 is a diagram illustrating an example of operation waveforms of a clock and a signal at the time when adjustment of the delay amount is started in the data communication circuit 300 according to the third embodiment.

  FIG. 13 is a diagram illustrating an example of operation waveforms of the clock and the signal at the time when the adjustment of the delay amount is completed in the data communication circuit 300 according to the third embodiment.

  In FIG. 12 and FIG. 13, the clock and signal H level and L level are not shown, but the section where the clock and signal levels are high represents the H level section, and the section where the level is low is the L level section. Represents.

  FIG. 12 illustrates a case where the delay amount setting process is performed from a state (initial state) where the phase of the clock CK_RETURN is delayed with respect to the clock CK. In this initial state, it is assumed that the control voltage VCNTL output from the CP / LPF 121 is set to the maximum value.

  First, as shown in FIG. 12, at the start of the delay amount setting process, at time t21, the skew adjustment start signal SKEW_ADJ_START output from the SERDES control unit 130 transitions from the L level to the H level.

  As a result, the start signal START output from the AND circuit 163 becomes H level at the next rising time t22 of the clock PLL_CK.

  Furthermore, since the H level is inverted and input to the AND circuit 163 via the FF 162 at time t23 after one cycle of the clock PLL_CK, the start signal START changes to the L level.

  At time t23, the counter enable signal CNTR_EN output from the FF 367 becomes H level in response to the rising edge of the start signal START at time t2. As a result, the counter 168 starts counting the clock PLL_CK.

  When the counter enable signal CNTR_EN becomes H level at time t23, the value of the count signal CNTR [2: 0] is 0 and the output of the counter 369 is H level (“1”). The output of 371 becomes “1”.

  Since the output of the AND circuit 371 is input to the FF 361, the clock CK becomes H level at time t24, which is one cycle after the clock PLL_CK from time t23. The clock CK is at the H level until it becomes the L level at time t27 after one cycle of the clock PLL_CK from the timing when the value of the count signal CNTR [2: 0] becomes 4 thereafter.

  Further, from time t24, counting by the counter 168 is started.

  At time t25 when the value of the count signal CNTR [2: 0] becomes 3, the determination enable signal JUDGE_EN output from the comparator 170 becomes H level.

  At time t26 when the determination enable signal JUDGE_EN becomes H level and the clock PLL_CK next rises, the clock CK_RETURN is at H level, so the data determination signal JUDGE_DT output from the determiner 173 is at L level.

  The EARLY / LATE controller 174 outputs a LATE signal to the CP / LPF 121 in order to delay the phase of the clock CK_RETURN.

  Further, at time t26, the value of the count signal CNTR [2: 0] becomes 4.

  At time t27, which is one cycle after the clock PLL_CK from time t26, the value of the count signal CNTR [2: 0] becomes 4 at time t26, so that the clock CK becomes L level. The clock CK is at the L level until it becomes H level at time t28 one cycle after the clock PLL_CK after the timing when the value of the count signal CNTR [2: 0] becomes 0 again.

  Then, at time t28 after the value of the count signal CNTR [2: 0] becomes 0 again, the same operation as that after time t1 is repeatedly performed.

  Even at time t29 when the value of the count signal CNTR [2: 0] becomes 3 again, the phase difference between the clock CK_RETURN and the clock CK has not reached 3UI, so that the clock CK_RETURN is the CP of the CP / LPF 121 at the time t30. It is further delayed by the output LATE signal.

  It should be noted that the time from when the count value of the counter 168 reaches 3 and the phase is compared by the determiner 173 until the count becomes 4 to 7 is provided as a time for stabilizing the control voltage VCNTL. Yes.

  Therefore, when taking a longer time for stabilizing the control voltage VCNTL, the maximum number of counts may be increased by increasing the number of bits of the counter 168.

  Next, the operation at the time when the adjustment of the delay amount is completed in the data communication circuit 300 according to the third embodiment will be described with reference to FIG.

  The operation shown in FIG. 13 is an operation after the output of the LATE signal and the EARLY signal by the EARLY / LATE controller 174 is repeated three times.

  First, at time t31 after the value of the count signal CNTR [2: 0] becomes 3 and the determination enable signal JUDGE_EN output from the comparator 170 becomes H level, the clock CK_RETURN is at H level. Outputs an H level data determination signal JUDGE_DT.

  At time t31, the EARLY / LATE controller 174 outputs a LATE signal to the CP / LPF 121 in order to detect the rising edge of the clock CK_RETURN. As a result, the control voltage VCNTL output by the LPF of the CP / LPF 121 decreases.

  At time t32, which is one cycle after the clock PLL_CK from time t31, the data determination signal JUDGE_DT and the LATE signal become L level.

  Then, at time t33 after the value of the count signal CNTR [2: 0] becomes 0, the clock CK becomes H level.

  Then, at time t34 when the value of the count signal CNTR [2: 0] becomes 3, the determination enable signal JUDGE_EN output from the comparator 170 becomes H level.

  At time t35, which is one cycle after the clock PLL_CK from time t34, since the clock CK_RETURN is at L level, the determiner 173 outputs an L level data determination signal JUDGE_DT.

  Further, the EARLY / LATE controller 174 to which the L level data determination signal JUDGE_DT is input outputs the EARLY signal to the CP / LPF 121 in order to advance the phase of the clock CK_RETURN at time t35.

  The EARLY / LATE controller 174 determines that the phase difference of the clock CK_RETURN with respect to the clock CK has reached 3 UI because the output of the LATE signal and the EARLY signal has been repeated four times, and that the delay amount setting process has ended, and the lock signal LOCK To H level.

  When the lock signal LOCK becomes H level, the H level lock signal LOCK is input to the set terminal S of the FF 175, so that the skew adjustment end signal SKEW_ADJ_STOP at H level is output from the FF 175 to the SERDES control unit 130 at time t36. .

  When the skew adjustment end signal SKEW_ADJ_STOP at the H level is input, the SERDES control unit 130 ends the delay amount setting process.

  After time t36, the data communication circuit 300 performs a normal operation using the delay amount set by time t35.

  After time t36 when the delay amount setting process described above is completed and the normal operation is started, the clock CK input to the VDL 122A and the clock CK_RETURN output from the VDL 122H have a phase difference of 3 UI.

  At this time, the clock CK input to the VDL 122A and the clock CK_RETURN output from the VDL 122H have a phase difference of 3 UI as shown in FIG.

  The 3UI phase difference is equally allocated to the clocks CK1 to CK8 output from the VDLs 122A to 122H, respectively.

  That is, the clocks CK1 to CK8 are input to TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150 in a state having a phase difference of 3 UI / 8 in order.

  For this reason, TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150 operate using the clocks CK1 to CK8 having different phases by 3 UI / 8 as operation reference clocks, respectively.

  Therefore, according to the data communication circuit 300 of the third embodiment, the operation timings of TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150 can be shifted, so that TX0 to TX3 and reception of the transmitter 140 can be shifted. The increase in peak power accompanying the operation of RX0 to RX3 of the device 150 can be suppressed.

  In this way, shifting the timing of the operations of TX0 to TX3 of the transmitter 140 and RX0 to RX3 of the receiver 150 is realized by providing a non-integer multiple relationship to the phase difference between the clocks CK1 to CK8. It is.

  As described above, according to the third embodiment, it is possible to provide the data communication circuit 300 in which an increase in peak power is suppressed.

  In the third embodiment, the delay amount setting process is performed by using the clock CK and CK_RETURN obtained by dividing the clock PLL_CK supplied from the PLL 110 into a frequency of 1/8, thereby consuming the delay amount during the delay amount setting process. Electric power can be reduced.

  Further, as described above, in the data communication circuit 300 according to the third embodiment, the signal path through which the clock PLL_CK output from the PLL 110 is converted to the clock CK when performing the delay amount setting process, and the normal operation The signal path through which the clock PLL_CK output from the PLL 110 after shifting to is the same.

  This signal path is a signal path through which the clock PLL_CK input from the PLL 110 illustrated in FIG. 10 to the DLL 320 is input to the VDLs 122A to 122H via the FF 361 illustrated in FIG.

  Here, if the signal path in the delay amount setting process is different from the signal path in the normal operation, the delay amount set in the delay amount setting process may not be an accurate value in the signal path in the normal operation. Strictly speaking, the delay time differs depending on the signal path, because the path length is different or the circuit element is included in a different part of the signal path. Such a difference in signal path becomes more prominent as the frequency of the clock PLL_CK increases.

  On the other hand, according to the data communication circuit 300 of the third embodiment, since the signal path for setting the delay amount is the same as the signal path after the shift to the normal operation, an accurate delay amount can be obtained. The increase in peak power can be effectively suppressed.

The data communication circuits and electronic devices according to the exemplary embodiments 1 to 3 of the present invention have been described above. However, the present invention is not limited to the specifically disclosed embodiments, and is not limited to patents. Various modifications and changes can be made without departing from the scope of the claims.
Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1)
A clock output section;
A plurality of circuits for data transmission or data reception that operate based on a clock supplied from the clock output unit;
A data communication circuit comprising: a phase adjustment unit that is connected between the clock output unit and the plurality of circuits and shifts a phase of a clock supplied to the plurality of circuits.
(Appendix 2)
The phase adjusting unit is
A delay element for delaying a phase of a clock input to the plurality of circuits;
A phase detector that detects a phase difference between an input clock and an output clock of the delay element;
A charge pump that outputs a current representing the phase difference detected by the phase detector;
The data communication circuit according to appendix 1, further comprising: an integrator that inputs a voltage obtained by integrating the output current of the charge pump to a delay amount control terminal of the delay element.
(Appendix 3)
The data communication according to appendix 2, wherein the phase detector adjusts a delay amount in the delay element by increasing or decreasing an output current of the charge pump so that a detected phase difference becomes a desired phase difference. circuit.
(Appendix 4)
4. The data communication circuit according to appendix 2 or 3, wherein a plurality of the delay elements are provided, one for each of the plurality of circuits.
(Appendix 5)
When adjusting the delay amount in the phase adjustment unit, the phase adjustment unit uses a clock with a reduced number of clock pulses used during normal operation or a clock obtained by dividing the clock used during normal operation. 5. The data communication circuit according to any one of 4.
(Appendix 6)
An oscillator that is disposed in each of the plurality of circuits and outputs a clock having a frequency multiplied by the clock based on the clock supplied from the clock output unit;
There are a plurality of the delay elements, one for each of the plurality of circuits,
The phase of the clock supplied to the plurality of circuits is shifted by shifting the delay amount of each of the plurality of delay elements in the lock state after the locked state by the delay lock loop is obtained. Data communication circuit.
(Appendix 7)
The data communication circuit according to any one of appendices 4 to 6, wherein the plurality of delay elements are connected in series.
(Appendix 8)
The phase adjustment unit is configured such that a phase difference between a clock supplied to the plurality of circuits and a clock output from the clock output unit is a non-integer multiple of one cycle of a clock output from the clock output unit. The data communication circuit according to any one of appendices 1 to 7, wherein a phase of a clock supplied to the plurality of circuits is shifted.
(Appendix 9)
The data communication circuit according to any one of appendices 1 to 8, and
And a processing unit that processes data transmitted or received by the data communication circuit.

10 LSI chip 20 CPU
30 Controller 40 Transmitter 50 Receiver 100 Data Communication Circuit 110 PLL
120 DLL
121 CP / LPF
122A-122H VDL
123 Skew adjuster 130 SERDES control unit 140 Transmitter 150 Receiver 161 Selector 162 FF
163 to 165 AND circuit 166 OR circuit 167 FF
168 Counter (CNTR)
169, 170 Comparator (CMP)
200 Data communication circuit 220 DLL
230 SERDES control unit 240 transmitter 223 PD
241-244 VCO
300 Data communication circuit 320 DLL
323 Skew Adjuster 361 FF
367 FF
369 Comparator 371 AND circuit

Claims (9)

A clock output section;
A plurality of circuits for data transmission or data reception that operate based on a clock supplied from the clock output unit;
A data communication circuit comprising: a phase adjustment unit that is connected between the clock output unit and the plurality of circuits and shifts a phase of a clock supplied to the plurality of circuits. The phase adjusting unit is
A delay element for delaying a phase of a clock input to the plurality of circuits;
A phase detector that detects a phase difference between an input clock and an output clock of the delay element;
A charge pump that outputs a current representing the phase difference detected by the phase detector;
The data communication circuit according to claim 1, further comprising: an integrator that inputs a voltage obtained by integrating the output current of the charge pump to a delay amount control terminal of the delay element.   The data according to claim 2, wherein the phase detection unit adjusts a delay amount in the delay element by increasing or decreasing an output current of the charge pump so that a detected phase difference becomes a desired phase difference. Communication circuit.   The data communication circuit according to claim 2, wherein there are a plurality of the delay elements, and one delay element is provided for each of the plurality of circuits.   The said phase adjustment part uses the clock which reduced the pulse number of the clock used at the time of a normal operation, or the clock which divided the clock used at the time of a normal operation, when adjusting the delay amount in the said phase adjustment part. The data communication circuit according to any one of claims 1 to 4. An oscillator that is disposed in each of the plurality of circuits and outputs a clock having a frequency multiplied by the clock based on the clock supplied from the clock output unit;
There are a plurality of the delay elements, one for each of the plurality of circuits,
The phase of a clock supplied to the plurality of circuits is shifted by shifting a delay amount of each of the plurality of delay elements in the lock state after the locked state by the delay lock loop is obtained. Data communication circuit.   The data communication circuit according to claim 4, wherein the plurality of delay elements are connected in series.   The phase adjustment unit is configured such that a phase difference between a clock supplied to the plurality of circuits and a clock output from the clock output unit is a non-integer multiple of one cycle of a clock output from the clock output unit. The data communication circuit according to claim 1, wherein phases of clocks supplied to the plurality of circuits are shifted. A data communication circuit according to any one of claims 1 to 8,
And a processing unit that processes data transmitted or received by the data communication circuit.

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