JP2013190301A - Phase detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase detector capable of stably detecting a phase.SOLUTION: A phase detector 10 comprises an oscillation circuit 9 that oscillates a phase θi to be synchronized with an AC system voltage V1, generates a waveform V2 with a phase φ obtained by delaying an AC system voltage V1 on the basis of a discrete system first-order lag operation expression using an arithmetic period ts, generates a sine wave Vb that becomes sinθi and a sin wave Va that becomes cosθi on the basis of the phase θi, and synchronizes a phase φi with the AC system voltage V1 on the basis of a waveform of the AC system voltage V1, the waveform V2, the sine wave Vb and the sine wave Va.

Description

  The present invention relates to a phase detector that detects the phase of a single-phase alternating current.

  In general, a phase detector is used for phase control for synchronizing output power to the voltage of an AC power system in a power electronics device or the like. In addition, a phase detector that detects a phase of a single-phase AC using a phase shift circuit that generates a signal having a phase different from that of the AC system voltage is disclosed (see Patent Document 1).

JP-A-2005-3530

  However, in the case of a phase detector using a phase shift circuit, the value being processed may oscillate depending on the accuracy of the phase shift circuit. Therefore, there is a need for a phase detector that can stably detect the phase.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a phase detector that can stably detect a phase.

  A phase detector according to an aspect of the present invention includes an oscillating means for oscillating a phase synchronized with an input waveform, and an input waveform and a first frequency based on an arithmetic expression of a discrete first-order lag using an operation period. Shift waveform generation means for generating a shift waveform having a phase difference, first sine wave generation means for generating a first sine wave based on the phase oscillated from the oscillation means, and the first sine wave The first sine wave generated by the generating means and the second sine wave generating means for generating a second sine wave having a second phase difference, and the input waveform and the shift waveform generating means Based on the shift waveform, the first sine wave generated by the first sine wave generation unit, and the second sine wave generated by the second sine wave generation unit, from the oscillation unit The oscillated phase is the phase of the input waveform And control means for controlling so as to synchronize.

  ADVANTAGE OF THE INVENTION According to this invention, the phase detector which can detect a phase stably can be provided.

The block diagram which shows the structure of the phase detector which concerns on the 1st Embodiment of this invention. 1 is a configuration diagram showing a configuration of a phase shift circuit according to a first embodiment. FIG. The vector diagram which shows the calculation in the phase shift circuit which concerns on 1st Embodiment. The block diagram which shows the structure of the phase detector which concerns on the 2nd Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a configuration diagram showing the configuration of a phase detector 10 according to the first embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the same part in subsequent figures, the detailed description is abbreviate | omitted, and a different part is mainly described. In the following embodiments, the same description is omitted.

  The phase detector 10 is a digital phase detector that detects a phase by arithmetic processing by a computer such as a microcomputer. The phase detector 10 detects the phase of the input single-phase AC system voltage V1. The phase detector 10 outputs the phase θi controlled so as to be synchronized with the phase of the AC system voltage V1. The phase θi output from the phase detector 10 is used to control the phase of an alternating current or the like output from a power electronics device or the like so as to be synchronized with the AC system voltage V1.

  The phase detector 10 includes a phase shift circuit 1, a first waveform generation circuit 2, a second waveform generation circuit 3, two multipliers 4 and 5, a subtractor 6, a controller 7, and an addition And an oscillation circuit 9.

  The phase shift circuit 1 generates a waveform V2 obtained by delaying the phase of the waveform indicating the input AC system voltage V1 by φ (π / 2 [rad]). That is, the phase shift circuit 1 shifts the phase of the AC grid voltage V1 in a direction delayed by the phase (shift phase) φ. The phase shift circuit 1 generates a waveform V2 based on an arithmetic expression obtained by discretizing a first-order lag transfer function of a continuous system using an arithmetic cycle ts. The phase shift circuit 1 outputs the generated waveform V2 to the multiplier 4.

  The first waveform generation circuit 2 generates a sine wave Vb that becomes sin θi based on the phase θi oscillated from the oscillation circuit 9. The first waveform generation circuit 2 outputs the generated sine wave Vb to the multiplier 4. Here, the phase θi oscillated from the oscillation circuit 9 is a phase controlled so as to be synchronized with the phase of the AC system voltage V1.

  The second waveform generation circuit 3 generates a sine wave Va that becomes cos θi based on the phase θi oscillated from the oscillation circuit 9. The second waveform generation circuit 3 outputs the generated sine wave Va to the multiplier 5.

  The multiplier 4 receives the waveform V2 generated by the phase shift circuit 1 and the sine wave Vb generated by the first waveform generation circuit 2. The multiplier 4 multiplies the waveform V2 and the sine wave Vb. The multiplier 4 outputs the multiplied operation result to the subtracter 6.

  The multiplier 5 receives the AC system voltage V 1 and the sine wave Va generated by the second waveform generation circuit 3. The multiplier 5 multiplies the AC system voltage V1 and the sine wave Va. The multiplier 5 outputs the multiplied operation result to the subtracter 6.

  The subtracter 6 subtracts the calculation result from the multiplier 5 from the calculation result from the multiplier 4. By this calculation, the subtractor 6 obtains the phase difference Δθ. The phase difference Δθ calculated in this way is substantially equal to the phase difference between the phase θ of the AC system voltage V1 and the phase θi oscillated from the oscillation circuit 9. The subtractor 6 outputs the calculated phase difference Δθ to the controller 7.

  The controller 7 controls the phase θi oscillated from the oscillation circuit 9 based on the phase difference Δθ input from the subtractor 6. The controller 7 amplifies the phase difference Δθ as necessary. The controller 7 controls the oscillation frequency of the oscillation circuit 9 to be increased when the phase θ of the AC system voltage V1 is ahead of the phase θi oscillated from the oscillation circuit 9. Thus, when the frequency of the oscillation circuit 9 is increased, the phase of the oscillated phase θi advances. When the phase θ of the AC system voltage V1 is delayed from the phase θi oscillated from the oscillation circuit 9, the controller 7 controls the oscillation frequency of the oscillation circuit 9 to be decreased. Thereby, when the frequency of the oscillation circuit 9 is lowered, the phase of the oscillated phase θi is delayed. The controller 7 outputs a frequency for controlling the phase to the adder 8.

  The adder 8 receives the reference phase frequency θr and the frequency for controlling the phase calculated by the controller 7. The adder 8 adds the frequency input from the controller 7 to the reference phase frequency θr. The adder 8 outputs the calculated frequency to the oscillation circuit 9.

  The oscillation circuit 9 oscillates the phase θi controlled to be synchronized with the phase of the AC system voltage V1 based on the frequency input from the adder 8. The phase θi oscillated from the oscillation circuit 9 becomes the output of the phase detector 10.

  Next, the operation of the phase detector 10 will be described.

  Here, for convenience of explanation, it is assumed that AC system voltage V1 is represented by a sine wave having an amplitude of 1. In this case, the waveform V2 in which the phase of the AC system voltage V1 is shifted by the AC system voltage V1 and the phase shift circuit 1 is expressed as follows.

V1 = sin θ, V2 = sin (θ−φ) Equation (1)
Here, φ is π / 2 [rad].

  The sine wave Va generated by the second waveform generation circuit 3 and the sine wave Vb generated by the first waveform generation circuit 2 are expressed as follows using the phase θi oscillated from the oscillation circuit 9. The

Va = sin (θi−φi), Vb = sinθi (2)
Here, φi is π / 2 [rad].

  The phase difference Δθ calculated by the subtractor 6 is expressed as follows.

Δθ = −V1 * Va + V2 * Vb Equation (3)
Formula (3) becomes as follows when Formula (1) and Formula (2) are used.

Δθ = −sin θ * sin (θi−φi) + sin (θ−φ) * sin θi
= −sinθsinθicosφi + sinθcosθisinφi
+ Sinθsinθicosφ−cosθsinθisinφ (4)
The second and fourth terms, and the first and third terms in equation (4) are summarized as follows.

Δθ = (sin θ cos θ isin φi−cos θ sin θ isin φ)
− (Sin θsin θicosφi−sinθsinθicosφ)
= Sinφ (sinθcosθi−cosθsinθi)
− (Sinφ−sinφi) sinθcosθi
-Sinθsinθi (cosφi-cosφ)
= Sinφsin (θ−θi) − (sinφ−sinφi) sinθcosθi
− (Cos φi−cos φ) sin θsin θi (5)
The second term and the third term in Expression (5) are terms that vary with the frequency of the AC system voltage V1. Here, the phase φ shifted by the phase shift circuit 1 and the phase difference φi between the sine wave Vb generated by the first waveform generation circuit 2 and the sine wave Va generated by the second waveform generation circuit 3 are: Both are the same at π / 2. Therefore, the second and third terms of Equation (5) are zero.

  If the difference between the phase θ of the AC system voltage V1 and the phase θi oscillated from the oscillation circuit 9 is small and constant, the direct current signal proportional to the difference between θ and θi is Is obtained as follows.

Δθ = sinφsin (θ−θi) ≈sinφ (θ−θi) (6)
Here, as described above, the phase φ shifted by the phase shift circuit 1 and the phase difference φi between the sine wave Va and the sine wave Vb are both π / 2. For this reason, sinφ = 1. Therefore, Formula (6) becomes as follows.

Δθ≈θ−θi (7)
Therefore, the phase difference Δθ output from the subtractor 6 is positive when the phase θ of the AC system voltage V1 is ahead of the phase θi oscillated from the oscillation circuit 9. Further, the phase difference Δθ is negative when the phase θ of the AC system voltage V1 is delayed from the phase θi oscillated from the oscillation circuit 9.

  The controller 7 performs arithmetic processing such as amplifying the phase difference Δθ input from the subtractor 6 to control the phase θi oscillated from the oscillation circuit 9 so as to synchronize with the phase of the AC system voltage V1. .

  FIG. 2 is a configuration diagram showing the configuration of the phase shift circuit 1 according to the present embodiment.

  The phase shift circuit 1 includes a first-order lag circuit 21, a correction gain 22, three gains 23, 24, and 26, and a subtracter 25.

  The first-order lag circuit 21 generates a waveform of a first-order lag that is delayed in phase (shift phase) φd from the input AC system voltage V1 based on an arithmetic expression obtained by discretizing a first-order lag transfer function of a continuous system using an operation cycle ts. Generate. The amplitude of the first-order lag waveform generated here is not the same as the amplitude of the AC system voltage V1. The shift phase φd is π / 4 [rad]. The primary delay circuit 21 outputs the generated primary delay waveform to the correction gain 22.

  The correction gain 22 multiplies the waveform generated by the first-order lag circuit 21 by a gain correction value for correcting a gain shift caused by discretizing the first-order lag transfer function of the continuous system. The correction gain 22 outputs a waveform multiplied by the gain correction value to the gain 23.

  The gain 23 multiplies the gain 1 / K for making the amplitude of the waveform input from the correction gain 22 the same as the amplitude of the AC system voltage V1. The gain 1 / K is the reciprocal of the gain K when the primary delay transfer function used in the primary delay circuit 21 is a continuous system. The waveform multiplied by the gain 1 / K by the gain 23 has the same amplitude as the AC system voltage V1 and is delayed by the phase φd. The gain 23 outputs a waveform multiplied by the gain 1 / K to the subtracter 25.

  The gain 24 multiplies the waveform of the input AC system voltage V1 by a gain cosφd. The gain 24 outputs a waveform multiplied by the gain cosφd to the subtracter 25.

  The subtracter 25 subtracts the waveform input from the gain 24 from the waveform input from the gain 23. The subtracter 25 outputs the subtracted waveform to the gain 26.

  The gain 26 multiplies the waveform input from the subtractor 25 by a gain 1 / sin φd. The gain 1 / sinφd is a value for making the amplitude of the waveform input by the subtractor 25 the same as the waveform of the AC system voltage V1. As a result, the gain 26 generates a waveform V2 that is the output of the phase shift circuit 1.

  FIG. 3 is a vector diagram showing the calculation in the phase shift circuit 1 according to the present embodiment. A vector V1 represents the AC system voltage V1. A vector V2 represents the output waveform of the phase shift circuit 1. A vector Vφd indicates a waveform output from the gain 23.

The calculation in the phase shift circuit 1 is expressed by the following equation.

  Next, calculation in the phase shift circuit 1 will be described.

The first-order lag transfer function of the continuous system is expressed as follows.

  Here, T is a time constant, s is a Laplace operator, X (s) is an input, and Y (s) is an output.

The shift phase φd and gain K of the first-order lag transfer function of the continuous system represented by Expression (9) are expressed as follows.

  Here, ω is an angular frequency of the AC system voltage V1.

  When the shift phase φd is π / 4 [rad] and the AC frequency is 60 [Hz], the time constant T = 0.00265, the gain K = 1 / √2, the sin φd = 1 / √2, cosφd = 1 / √2.

Next, when the first-order lag transfer function of the continuous system represented by Expression (9) is discretized by difference approximation, the following expression is obtained.

  Here, ts is a calculation cycle.

  The calculation using the first-order lag transfer function of the discrete system represented by Expression (12) is executed by the first-order lag circuit 21.

When formula (12) is arranged by Y (z), the following formula is obtained.

Arranging by Y (z) / X (z) gives the following equation.

Thereby, the gain of the discrete system becomes the following equation.

Also, the shift phase of the discrete system is given by

From this equation, in order to accurately set the shift phase to π / 4 [rad], the following equation should be established.

At this time, the gain of the discrete system of Expression (15) is expressed by the following expression.

Here, since the gain K when the shift phase φd of the continuous system is π / 4 [rad] is 1 / √2, the gain correction value of the correction gain 22 is expressed by the following equation.

  Therefore, when the shift phase φd is π / 4 [rad], the AC frequency is 60 [Hz], and the calculation cycle ts is 5 degrees (ts = 231 [μs]), the discrete time constant T = 0.00278, the gain Correction value = 1.046. A discrete time constant T is set in the first-order lag circuit 21. The gain correction value is set to the correction gain 22.

  According to the present embodiment, the phase lag (shift phase φd) and the gain can be precisely matched by discretizing the first-order lag in the phase shift circuit 1 and solving the transfer function considering the calculation cycle ts.

  Thereby, since the accuracy of the phase shift circuit 1 is improved, the phase difference Δθ (sin Δθ) calculated by the subtracter 6 does not vibrate, and stable phase detection can be performed.

  In addition, since the calculation of the primary delay of the primary delay circuit 21 may be simple, the calculation load on the computer can be reduced.

  Furthermore, when compared with a system in which the AC system voltage V1 is stored in a memory and the phase is shifted, the amount of memory used can be reduced.

  In addition, by setting the calculation cycle ts so as to be synchronized with the AC grid voltage V1 to be phase-detected, the phase delay and gain of the phase shift circuit 1 can be accurately maintained even if the grid frequency varies. Thereby, the phase shift circuit 1 can perform an exact phase shift.

(Second Embodiment)
FIG. 4 is a block diagram showing a configuration of a phase detector 10A according to the second embodiment of the present invention.

  In the phase detector 10A according to the first embodiment shown in FIG. 1, the phase detector 10A replaces the second waveform generation circuit 3 with the phase shift circuit 1A. Others are the same as in the first embodiment.

  The phase shift circuit 1A generates the sine wave Va by delaying the phase of the sine wave Vb generated by the first waveform generation circuit 2 by π / 2 [rad]. The configuration of the phase shift circuit 1A is the same as that of the phase shift circuit 1.

  According to the present embodiment, the phase shift circuit 1 that shifts the phase of the AC grid voltage V1 and the phase shift circuit 1A for generating the sine wave Va have the same configuration, so that the two phase shift circuits 1, It is possible to equalize the characteristics for calculating the shift phases φ and φi of 1A more accurately. Thereby, the accuracy of phase detection of the phase detector 10A can be improved.

  In each embodiment, the configuration in which the waveform generated by the first-order lag circuit 21 is multiplied by two gains with the correction gain 22 and the gain 23 has been described. A gain corresponding to the product of the gains may be multiplied. Further, the configuration for performing calculations such as addition, subtraction, multiplication, and division may be any configuration as long as the obtained calculation results are equivalent.

  In each embodiment, a filter such as a low-pass filter, a high-pass filter, or a band-pass filter may be provided as appropriate to remove noise and the like. For example, stable and accurate phase detection can be performed by calculating the AC system voltage V1 with a value through a filter that reduces harmonic components. Similarly, by providing a low-pass filter after the phase difference Δθ output from the subtractor 6, stable and accurate phase detection can be performed.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  DESCRIPTION OF SYMBOLS 1 ... Phase shift circuit, 2 ... 1st waveform generation circuit, 3 ... 2nd waveform generation circuit, 4, 5 ... Multiplier, 6 ... Subtractor, 7 ... Controller, 8 ... Adder, 9 ... Oscillation circuit 10: Phase detector.

Claims (7)

An oscillation means for oscillating a phase synchronized with the input waveform;
Shift waveform generating means for generating a shift waveform having a first phase difference from the input waveform, based on an arithmetic expression of a discrete system first-order lag using an operation period;
First sine wave generating means for generating a first sine wave based on the phase oscillated from the oscillating means;
Second sine wave generating means for generating a second sine wave having a second phase difference from the first sine wave generated by the first sine wave generating means;
The input waveform, the shift waveform generated by the shift waveform generation means, the first sine wave generated by the first sine wave generation means, and the second sine wave generation means generated by the second sine wave generation means A phase detector comprising: control means for controlling the phase oscillated from the oscillating means to synchronize with the phase of the input waveform based on a second sine wave. The shift waveform generating means includes
First-order lag calculation means for calculating a first-order lag waveform of the input waveform based on the discrete-form first-order lag calculation formula;
A gain for multiplying the waveform of the primary delay calculated by the primary delay calculating means by a gain value of a discrete primary delay based on the discrete primary delay computing equation;
2. The phase detector according to claim 1, further comprising shift waveform calculation means for calculating the shift waveform based on the first-order lag waveform multiplied by the discrete first-order lag gain value. The second sine wave generating means uses the discrete system first-order lag calculation formula using the calculation period in the shift waveform generating means and the first sine wave generated by the first sine wave generating means. The phase detector according to claim 1, wherein the second sine wave is generated based on the phase detector. The phase detector according to any one of claims 1 to 3, wherein the calculation cycle is set to be synchronized with a frequency of the input waveform. The first phase difference in the shift waveform generation means and the second phase difference in the second sine wave generation means are the same. The phase detector according to 1. 6. The phase according to claim 5, wherein the first phase difference in the shift waveform generation means and the second phase difference in the second sine wave generation means are π / 2 [rad]. Detector. A phase detector that oscillates in phase with an input waveform,
Based on an arithmetic expression of a discrete system first-order lag using an arithmetic cycle, a shift waveform having a first phase difference with the input waveform is generated,
Based on the oscillated phase, a first sine wave is generated,
Generating a second sine wave having a second phase difference from the generated first sine wave;
Based on the input waveform, the generated shift waveform, the generated first sine wave, and the generated second sine wave, control is performed to synchronize the oscillating phase with the phase of the input waveform. A phase detection method comprising:

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