JPH09326690A - Digital pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a digital PLL circuit of constitution capable of obtaining phase signal output equivalent to analog phase signal output from the digital PLL circuit of H/W constitution and not damaging the synchronous sampling function of a conventional digital PLL circuit. SOLUTION: The output of a low-pass filter 4 for extracting fundamental wave component signals from AC input signals 2 is continuously A/D converted based on synchronous pulses, phase comparison is performed in a phase comparison operation part 22 by using obtained digital signal data and synchronous phase signals, an obtained phase deviation is integrated in a loop filter operation part 30 and a phase change portion is outputted. An H/W counter 10 for counting a pulse number corresponding to the phase change portion and outputting the phase signal output equivalent to analog output, the synchronous pulses and synchronous phase signals is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL circuit for sampling and phase detection of a system voltage and a system current in a power control protection device, a system observation device and the like.

[0002]

2. Description of the Related Art FIG. 10 shows, for example, JP-A-2-212775.
It is a figure which shows the conventional digital PLL circuit shown by the publication. In the figure, 2 is an AC input signal, 4 is a low-pass filter, 6 is an A / D converter that performs sampling based on the synchronization pulse from the sample timer 116, and 118 is a synchronization phase that counts the synchronization pulses from the sample timer 116. A sample counter 22 that outputs a signal is a phase comparison calculation unit that inputs the synchronous phase signal from the sample counter 118 and the instantaneous value digital signal from the A / D conversion unit 6 and outputs a phase deviation.

Reference numeral 30 denotes a loop filter calculation unit which receives the phase deviation from the phase comparison calculation unit 22 and outputs the phase change amount,
Reference numeral 130 denotes a sample period calculation unit that calculates a modified sampling period based on the phase change amount from the loop filter calculation unit 30 and outputs it to the sample timer 116.

The phase comparison calculation unit 22, the loop filter calculation unit 30, and the sample period calculation unit 130 are the CPU 20.
Is composed.

Next, the operation will be described. The AC input signal 2 has its harmonic components removed by the low-pass filter 4, and is input to the A / D conversion unit 6. The A / D conversion unit 6
Sampling is performed in synchronization with the waveform of the AC input signal 2 based on the synchronization pulse from the sample timer 116. On the other hand, the sample counter 118 has the sample timer 116.
The sync pulse from is counted and a sync phase signal is output. The phase comparison calculation unit 22 obtains a phase deviation from the A / D converted instantaneous value digital signal and the synchronization phase signal.

The loop filter calculation unit 30 outputs a phase change amount from this phase deviation. Sample period calculation unit 13
For 0, the modified sampling period is calculated based on this phase change amount and is set in the sample timer 116 every time. As a result, the synchronization pulse output from the sample timer 116 performs sampling in synchronization with the waveform of the AC input signal 2.

[0007]

DISCLOSURE OF THE INVENTION Conventional digital PL
Since the L circuit is configured as described above, when using the phase signal of the digital PLL circuit output, only the synchronous phase signal of the sampling period for sampling the AC input signal can be obtained. For example, when a system that requires an analog phase signal is used together in the same system, there is a problem that a separate digital PLL circuit having an H / W structure that can output the analog phase signal must be provided.

The present invention has been made in order to solve the above problems, and has a digital PL having an H / W structure.
An object of the present invention is to obtain a digital PLL circuit which can obtain a phase signal output equivalent to the analog phase signal output from the L circuit and which does not impair the synchronous sampling function of the conventional digital PLL circuit.

[0009]

According to a first aspect of the present invention, there is provided a digital PLL circuit which outputs a high-frequency pulse signal that follows a system frequency based on a phase change output from a loop filter operation section. An arithmetic unit and an H / W counter unit for outputting a synchronous pulse, a synchronous phase signal, and a phase signal equivalent to the analog phase signal output from the high-frequency pulse signal are provided.

A digital PL according to a second aspect of the invention.
The L circuit includes an AC voltage drop detector that detects that the AC voltage has dropped significantly and outputs a signal, and a switch that switches the input of the loop filter calculation unit to 0 by the output of this AC voltage drop detector. It is a thing.

A digital PL according to a third aspect of the invention.
The L circuit inputs the phase signal output from the H / W counter section, monitors the frequency, and outputs a signal when the frequency exceeds a set allowable frequency, and a frequency rise decrease detector. And a switch for switching the input of the loop filter calculation unit to 0 according to the AND condition of the AC voltage drop detector.

A digital PL according to a fourth aspect of the invention.
The L circuit detects an AC voltage greatly decreased and outputs an AC voltage drop detector, two loop filter arithmetic units having different time constants, and outputs of the two loop filter arithmetic units. A switch for switching to a loop filter arithmetic unit having a fast time constant according to the output of the AC voltage drop detector is provided.

A digital PL according to a fifth aspect of the invention.
The L circuit detects an AC voltage greatly decreased and outputs a signal, an AC voltage drop detector, two loop filter arithmetic units having different time constants, and outputs of the respective loop filter arithmetic units to the AC voltage. A limiter for limiting the output of the voltage drop detector and an adder for adding the outputs of the limiters are provided.

A digital PL according to the invention of claim 6
The L circuit includes two loop filter arithmetic units having different time constants, a switch for switching the output of the loop filter arithmetic unit according to the output of the AC voltage drop detector, an AND condition of the frequency rise decrease detector and the AC voltage drop detector. , And a switch for setting the input of the loop filter calculation unit to 0.

The digital PL according to the invention of claim 7
The L circuit is a switch that switches the input of the loop filter calculation unit to 0 by the output of the AC voltage drop detector, and a hysteresis width setting that outputs a constant hysteresis width when the AC voltage drop detector detects a drop in the AC voltage. And an adder for adding the output of the hysteresis width setting device to the input of the AC voltage drop detector.

A digital PL according to the invention of claim 8
The L circuit includes a switch that cuts off the output from the PI control calculation unit in the loop filter calculation unit by the output of the AC voltage drop detector.

The digital PL according to the invention of claim 9
The L circuit is a counter that counts the number of pulses from the pulse oscillation calculation unit and outputs a phase signal equivalent to an analog output, and a sample period counter that counts the number of pulses from the pulse oscillation calculation unit and outputs a synchronization pulse. And a counter that counts the sync pulse and outputs the sync phase signal.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1. 1 is a connection diagram showing a digital PLL circuit according to Embodiment 1 of the present invention.
2 is an AC input signal, 4 is a low-pass filter, 6 is H / W
An A / D conversion unit that performs sampling based on the synchronization pulse from the counter unit 10, a sample period counter 12 that outputs a synchronization pulse, and a sample period counter 12
It is a counter that counts the sync pulses from and outputs a sync phase signal.

Reference numeral 22 is a phase comparison operation unit for inputting the synchronous phase signal from the counter 14 and the instantaneous value digital signal from the A / D conversion unit 6 and outputting a phase deviation. Reference numeral 32 is a phase deviation operation from the phase comparison operation unit 22. Is input to output a phase deviation integral value, 34 is a reference frequency unit that outputs a set reference frequency phase component, and 36 is a PI control calculation unit 32.
Is added and the reference frequency phase component from the reference frequency unit 34 is added, and an addition operation unit that outputs the phase change amount is denoted by 38. First-order delay operation 38 is performed to remove harmonic noise included in the input signal. It is a department.

A pulse oscillation calculation unit 40 outputs a high frequency pulse signal that follows the system frequency based on the phase change from the loop filter calculation unit 30, and inputs the high frequency pulse signal to the sample period counter 12. The sample period counter calculates a modified sampling period based on the input high frequency pulse signal and outputs a synchronization pulse.

Reference numeral 16 is a counter for inputting a high frequency pulse signal from the pulse oscillation calculation section 40, and is constituted by a counter for outputting a phase signal equivalent to an analog phase output output by a digital PLL circuit constituted by H / W. There is.

The sample period counter 12, counters 14 and 16 constitute the H / W counter section 10, and P
I control calculation unit 32, reference frequency unit 34, addition calculation unit 3
The 6th and 1st-order delay calculation units 38 form a loop filter calculation unit 30. Then, this loop filter calculation unit 3
0, the phase comparison calculation unit 22, and the pulse oscillation calculation unit 40 are CP
It is provided in U20.

Next, the operation will be described. In the digital PLL circuit configured as described above, the AC input signal 2 is input to the A / D conversion unit 6 after the harmonics are removed by the low pass filter 4. The A / D conversion unit 6
Based on the synchronization pulse shown in FIG. 2B from the sample period counter 12, sampling is performed in synchronization with the waveform of the AC input signal 2 shown in FIG.

On the other hand, the counter 14 counts the sync pulse from the sample period counter 12 and outputs a sync phase signal as shown in FIG. 2 (c). Phase comparison calculation unit 22
Calculates the phase deviation from the A / D converted instantaneous value digital signal and the synchronous phase signal. The PI control calculator 32 outputs a phase deviation integrated value from this phase deviation. Addition calculation unit 3
Reference numeral 6 adds the reference frequency phase component output from the reference frequency unit 34 and the phase deviation integral value output from the PI control calculation unit 32, and outputs the phase change component. First-order delay calculation unit 38
Removes the harmonic component contained in the phase change component.

The pulse oscillation calculation unit 40 outputs a high frequency pulse signal that follows the system frequency based on the phase change amount from the first-order delay calculation unit 38. Sample period counter 1
Reference numeral 2 corrects the sampling period based on the high frequency pulse output from the pulse oscillation calculation unit 40 to generate a synchronization pulse. As a result, FIG. 2 (a) and FIG.
Sampling can be performed in synchronization with the AC input signal 2 as shown in (b).

The counter 16 also counts the high frequency pulses from the pulse oscillation calculator 40 and outputs a phase signal. As a result, a phase signal equivalent to the analog phase signal output by the digital PLL circuit configured by H / W as shown in FIG. 2D can be obtained.

Embodiment 2. FIG. 3 is a connection diagram showing a digital PLL circuit according to a second embodiment of the present invention. In the embodiment shown in FIG. 1, an AC voltage drop for detecting a decrease in AC voltage and outputting a signal is output. Detector 6
0 and a switch 62 for receiving the output of the AC voltage drop detector 60 and setting the input of the loop filter calculation unit 30 to 0 are added.

Next, the operation will be described. The AC voltage drop detector 60 monitors the AC input signal 2, detects that the AC voltage has dropped, and outputs a signal. The switch 62 is
When receiving the signal from the AC voltage drop detector 60, the input of the loop filter calculation unit 30 is switched from the output side of the phase comparison calculation unit 22 to the 0 side. As a result, it is possible to prevent the digital PLL circuit from having a large detection error due to the phase fluctuation of the AC input voltage signal during the accident period when the AC voltage greatly decreases.

Embodiment 3 FIG. 4 is a connection diagram showing a digital PLL circuit according to a third embodiment of the present invention. The phase signal output 50 from the H / W counter section 10 is input to the embodiment shown in FIG. Of the frequency rise drop detector 64 that outputs a signal when this frequency exceeds the set allowable frequency, and the AND condition of the output of this frequency rise drop detector 64 and the output of the AC voltage drop detector 60 An AND circuit 66 for switching the switch 62 from the output side of the phase comparison calculation unit 22 to the 0 side is added.

Next, the operation will be described. The frequency rise decrease detector 64 monitors the phase signal output 50 and outputs a signal when the detected frequency exceeds the allowable frequency. AND circuit 6
6 outputs a signal according to the AND condition of the signals of the AC voltage drop detector 60 and the frequency rise drop detector 64. Upon receiving the signal from the AND circuit 66, the switch 62 switches the input of the loop filter calculation unit 30 from the output side of the phase comparison calculation unit 22 to the 0 side.

As a result, during the accident period, if a large detection error occurs in the digital PLL circuit due to the phase fluctuation of the AC input voltage signal, the digital PLL circuit is held at the set maximum frequency value or minimum frequency value. It is possible to prevent the frequency from being held with a large detection error.

Embodiment 4 FIG. FIG. 5 is a connection diagram showing a digital PLL circuit according to a fourth embodiment of the present invention. In the embodiment shown in FIG. 1, an AC voltage drop detecting a decrease in AC voltage and outputting a signal is performed. Detector 6
0, a loop filter calculation unit 30B other than the loop filter calculation unit 30A, and a switch 76 that receives the output of the AC voltage drop detector 60 and switches the output of the two loop filter calculation units 30A and 30B. Is.

The loop filter arithmetic unit 30A receives the phase deviation from the phase comparison arithmetic unit 22 and outputs the phase deviation integral value, and the PI control arithmetic unit 32.
In order to remove the harmonic noise included in the output signal of the addition calculation unit 36 and the addition calculation unit 36 that adds the phase deviation integral value from the reference frequency phase from the reference frequency unit 34 and outputs the phase change amount. And the first-order delay calculation unit 38.

The loop filter arithmetic unit 30B receives the phase deviation from the phase comparison arithmetic unit 22 and outputs the phase deviation integrated value, and the PI control arithmetic unit 70.
In order to remove the harmonic noise included in the output signal of the addition calculation unit 72 and the addition calculation unit 72 that adds the phase deviation integrated value from the reference frequency phase from the reference frequency unit 34 and outputs the phase change amount. And the time constant of the output of the loop filter calculation unit 30B is set faster than the time constant of the output of the loop filter calculation unit 30A.

Next, the operation will be described. The AC voltage drop detector 60 monitors the AC input signal 2, detects that the AC voltage has dropped, and outputs a signal. Switch 76
When receiving the signal from the AC voltage drop detector 60, the outputs of the loop filter calculation units 30A and 30B are switched to the side of the faster time constant. As a result, during an accident period in which the AC voltage drops significantly, it is possible to follow the phase fluctuation of the AC input voltage signal and reduce the detection error of the digital PLL circuit.

Embodiment 5 6 is a connection diagram showing a digital PLL circuit according to a fifth embodiment of the present invention. In the embodiment shown in FIG. 1, an AC voltage drop detecting a decrease in AC voltage and outputting a signal is performed. Detector 6
0, a loop filter calculation unit 30B other than the loop filter calculation unit 30A, a limiter 80 that limits the output of the loop filter calculation unit 30A by the output of the AC voltage drop detector 60, and the output of the loop filter calculation unit 30B. The limiter 82 and the addition operation unit 84 for adding the outputs of the limiters 80 and 82 are added. The operations of the limiters 80 and 82 are such that when the output of the AC voltage drop detector 60 is received, the limiter value of the limiter 80 is opened → closed, and the limiter value of the limiter 82 is closed → opened. Further, the opening / closing operation of the limiter value is, for example, 1
This is performed with the next delay. This is to reduce the amount of overshoot that occurs, as compared with the case of switching to the loop filter calculation unit 30B having a fast time constant.

The loop filter arithmetic unit 30A receives the phase deviation from the phase comparison arithmetic unit 22 and outputs the phase deviation integrated value, and the PI control arithmetic unit 32.
In order to remove the harmonic noise included in the output signal of the addition calculation unit 36 and the addition calculation unit 36 that adds the phase deviation integral value from the reference frequency phase from the reference frequency unit 34 and outputs the phase change amount. And the first-order delay calculation unit 38.

The loop filter arithmetic unit 30B receives the phase deviation from the phase comparison arithmetic unit 22 and outputs the phase deviation integral value, and the PI control arithmetic unit 70.
In order to remove the harmonic noise included in the output signal of the addition calculation unit 72 and the addition calculation unit 72 that adds the phase deviation integrated value from the reference frequency phase from the reference frequency unit 34 and outputs the phase change amount. And the time constant of the output of the loop filter calculation unit 30B is set faster than the time constant of the output of the loop filter calculation unit 30A.

Next, the operation will be described. The AC voltage drop detector 60 monitors the AC input signal 2, detects that the AC voltage has dropped, and outputs a signal. Upon receiving the signal from the AC voltage drop detector 60, the limiter 80 outputs the output of the first-order delay calculation unit 38, that is, the loop filter calculation unit 30A.
Of the first-order delay calculation unit 74, that is, the loop filter calculation unit 30.
It operates so as to remove the limitation of the output of B. When the signal from the AC voltage drop detector 60 disappears,
The limiter 80 and the limiter 82 operate in reverse to the above.

As a result, during the accident period when the AC voltage drops significantly, it is possible to follow the phase fluctuation of the AC input voltage signal and reduce the detection error of the digital PLL circuit. In addition, by switching the output of the loop filter calculation unit with a limiter, the transition to the selected loop filter calculation unit is performed smoothly, so the amount of overshoot that occurs at the time of switching can be reduced compared to the case of a switch. You can

Embodiment 6 FIG. FIG. 7 is a connection diagram showing a digital PLL circuit according to a sixth embodiment of the present invention. In the embodiment shown in FIG. 1, an AC voltage drop detection for detecting a drop in AC voltage and outputting a signal is detected. Bowl 60
And a switch 62 for switching the inputs of the loop filter calculation units 30A and 30B between the output side and the 0 side of the phase comparison calculation unit 22 and the phase signal output from the H / W counter unit 10 to monitor the frequency, Frequency rise / fall detector 64 that outputs a signal when this frequency exceeds the set allowable frequency
And an AND circuit 66 that switches the switch 62 from the output side of the phase comparison calculation unit 22 to the 0 side according to the AND condition of the output of the frequency rise drop detector 64 and the output of the AC voltage drop detector 60, and a loop filter. A loop filter computing unit 30B different from the computing unit 30A and a switch 76 for receiving the output of the AC voltage drop detector 60 when the AC voltage drops and switching the output of the loop filter computing units 30A and 30B. Is.

The loop filter arithmetic unit 30A receives the phase deviation from the phase comparison arithmetic unit 22 and outputs the phase deviation integral value, and the PI control arithmetic unit 32.
In order to remove the harmonic noise included in the output signal of the addition calculation unit 36 and the addition calculation unit 36 that adds the phase deviation integral value from the reference frequency phase from the reference frequency unit 34 and outputs the phase change amount. And the first-order delay calculation unit 38.

The loop filter arithmetic unit 30B receives the phase deviation from the phase comparison arithmetic unit 22 and outputs the phase deviation integrated value, and the PI control arithmetic unit 70.
In order to remove the harmonic noise included in the output signal of the addition calculation unit 72 and the addition calculation unit 72 that adds the phase deviation integrated value from the reference frequency phase from the reference frequency unit 34 and outputs the phase change amount. And the time constant of the output of the loop filter calculation unit 30B is set faster than the time constant of the output of the loop filter calculation unit 30A.

Next, the operation will be described. Switch 76
When receiving the signal from the AC voltage drop detector 60, switches the output of the loop filter calculation unit 30A to the output side of the loop filter calculation unit 30B having a fast time constant. As a result, during an accident period in which the AC voltage drops significantly, it is possible to follow the phase fluctuation of the AC input voltage signal and reduce the detection error of the digital PLL circuit. For example, even if the digital PLL circuit causes a large detection error due to the phase variation of the AC input voltage signal, the digital PLL circuit is held at the set maximum frequency value or minimum frequency value.
It is possible to prevent the LL circuit from being frequency-held with a large detection error.

Embodiment 7. 8 is a connection diagram showing a digital PLL circuit according to a seventh embodiment of the present invention. In the embodiment shown in FIG. 3, when the AC voltage drop detector 60 operates, a constant hysteresis width is output. Hysteresis width setting device 86 and hysteresis width setting device 8
An adder 88 for adding the output of 6 to the input of the AC voltage drop detector 60 is added.

Next, the operation will be described. Upon receiving the signal from the AC voltage drop detector 60, the hysteresis width setting device 86 outputs a constant hysteresis width value. The adder 88 adds the output from the hysteresis width setting unit 86 and the AC input signal 2 and outputs the result to the AC voltage drop detector 60. As a result, the chattering of the switch 62 due to the operation / non-operation of the AC voltage drop detector 60 is prevented.

Embodiment 8 FIG. FIG. 9 is a connection diagram showing a digital PLL circuit according to an eighth embodiment of the present invention. In the embodiment shown in FIG. 1, an AC voltage drop detection that detects that the AC voltage has dropped and outputs a signal is detected. Bowl 60
Then, a switch 90 for cutting off the output from the PI control calculation unit 32 in the loop filter calculation unit 30 in response to the output of the AC voltage drop detector 60 is added.

Next, the operation will be described. The AC voltage drop detector 60 monitors the AC input signal 2, detects that the AC voltage has dropped, and outputs a signal. The switch 90 is
When the signal from the AC voltage drop detector 60 is received, the output side of the PI control calculation unit 32 is switched to the 0 side. As a result, during the accident period when the AC voltage drops significantly, only the reference frequency phase from the reference frequency unit 34 becomes the input to the first-order delay calculation unit 38, and the digital PLL circuit becomes large due to the phase fluctuation of the AC input voltage signal. It is possible to avoid having a detection error and to operate at a preset reference frequency.

[0049]

As described above, according to the first aspect of the present invention, the A / D conversion unit performs A / D conversion using the synchronization pulse generated by the H / W counter unit, and H / W conversion is performed. Since the phase comparison calculation is performed using the synchronous phase signal in synchronization with the sampling from the W counter unit, the AC instantaneous value sampling data synchronized with the frequency and phase of the AC input signal can be taken in very accurately. Further, since the high frequency pulse signal generated from the pulse oscillation calculation unit is configured to be counted by the H / W counter unit, a phase signal equivalent to the analog phase signal output by the digital PLL circuit configured by H / W is obtained. There is an effect that can be.

According to the second aspect of the present invention, when the AC voltage drops, the switch switches from the output side of the phase comparison calculation unit to the 0 side by the signal from the AC voltage drop detector, and the AC voltage drop detection. Since the frequency is held at the immediately preceding frequency, during the accident period when the AC voltage drops significantly, the digital P
This has an effect of preventing the LL circuit from having a large detection error.

According to the third aspect of the present invention, the output of the AC voltage drop detector and the output of the frequency rise drop detector are ANDed.
Depending on the conditions, the switch may be set to 0 from the output side of the phase comparison calculation unit.
Since it is configured to switch to the side, if a large detection error occurs in the PLL circuit due to the phase fluctuation of the AC input voltage signal during the accident period, it is held at the set maximum frequency value or minimum frequency value, and the digital PLL circuit operates. There is an effect that it is possible to prevent the frequency from being held with a large detection error.

According to the fourth aspect of the invention, when the signal from the AC voltage drop detector is received, the switch switches the output of the loop filter arithmetic unit to the output side of the loop filter arithmetic unit having a fast time constant. Therefore, during the accident period in which the AC voltage greatly drops, there is an effect that the phase fluctuation of the AC input voltage signal is followed and the detection error of the digital PLL circuit can be reduced.

According to the fifth aspect of the present invention, when the signal from the AC voltage drop detector is received, the operation of the limiter switches the output of the loop filter arithmetic unit to the output side of the loop filter arithmetic unit having a fast time constant. Since it is configured, the transition to the selected loop filter arithmetic unit is performed smoothly,
As compared with the case of switching by the switch, there is an effect that the amount of overshoot generated at the time of switching can be reduced.

According to the sixth aspect of the present invention, during the accident period when the AC voltage greatly decreases, the loop filter operation unit is configured to operate with a fast time constant, so that the phase fluctuation of the AC input voltage signal is prevented. This can be followed, and the detection error of the digital PLL circuit can be reduced. Further, even if a large detection error occurs in the digital PLL circuit due to the phase fluctuation of the AC input voltage signal, it is held at the set maximum frequency value or minimum frequency value.
There is an effect that it is possible to prevent the LL circuit from being frequency-held with a large detection error.

According to the invention described in claim 7, when the hysteresis width setting device receives a signal from the AC voltage drop detector, the hysteresis width setting device outputs a constant hysteresis width value, and the output and the AC input signal are added. Since the value is output to the AC voltage drop detector, there is an effect that the chattering of the switch due to the operation / non-operation of the AC voltage drop detector can be prevented.

According to the eighth aspect of the present invention, when the signal from the AC voltage drop detector is received, the switch is configured to switch from the output side of the PI control calculation section to the 0 side. During the accident period, the digital PLL circuit can be prevented from having a large detection error due to the phase fluctuation of the AC input voltage signal, and the digital PLL circuit can be operated at the preset reference frequency.

According to the ninth aspect of the present invention, the H / W counter section includes a counter that counts the number of pulses from the pulse oscillation calculation section and outputs a phase signal equivalent to an analog output, and the pulse oscillation calculation section. Since a sample period counter that counts the number of pulses from and outputs a sync pulse and a counter that counts this sync pulse and outputs the sync phase signal are provided, a sync phase signal and an analog phase used in the CPU are provided. There is an effect that a phase signal output equivalent to a signal can be reliably obtained separately and independently.

[Brief description of drawings]

FIG. 1 is a digital P according to the first embodiment of the present invention.
It is a connection diagram showing an LL circuit.

FIG. 2 is a signal waveform diagram showing the operation of the H / W counter unit in the first embodiment.

FIG. 3 is a digital P according to the second embodiment of the present invention.
It is a connection diagram showing an LL circuit.

FIG. 4 is a digital P according to the third embodiment of the present invention.
It is a connection diagram showing an LL circuit.

FIG. 5 is a digital P according to the fourth embodiment of the present invention.
It is a connection diagram showing an LL circuit.

FIG. 6 is a digital P according to a fifth embodiment of the present invention.
It is a connection diagram showing an LL circuit.

FIG. 7 is a digital P according to the sixth embodiment of the present invention.
It is a connection diagram showing an LL circuit.

FIG. 8 is a digital P according to Embodiment 7 of the present invention.
It is a connection diagram showing an LL circuit.

FIG. 9 is a digital P according to the eighth embodiment of the present invention.
It is a connection diagram showing an LL circuit.

FIG. 10 is a connection diagram showing a conventional digital PLL circuit.

[Explanation of symbols]

2 AC input signal, 4 low pass filter, 6 A / D
Conversion unit, 10 H / W counter unit, 12 sample period counter, 14, 16 counter, 22 phase comparison operation unit, 30, 30A, 30B loop filter operation unit, 4
0 pulse oscillation calculation unit, 50 phase signal output, 60 AC voltage drop detector, 62, 76, 90 switch, 64
Frequency rise decrease detector, 80, 82 limiter, 86
Hysteresis width setting device, 88 adder

Claims (9)

[Claims] 1. A low-pass filter for extracting a fundamental wave component signal from an AC input signal, and continuous A / D conversion of an output from the low-pass filter based on a synchronizing pulse to obtain digital signal data of the AC input signal. A / D conversion unit, a phase comparison calculation unit that performs phase comparison using the digital signal data and the synchronous phase signal, and outputs a phase deviation, and a loop filter that integrates the phase deviation and outputs a phase change amount An arithmetic unit, a pulse oscillation arithmetic unit that outputs the number of pulses according to the phase change amount, a phase signal output that is equivalent to an analog output by counting the number of pulses and the synchronization pulse, and this synchronization pulse is counted. A digital PLL circuit comprising an H / W counter section for outputting the synchronous phase signal. 2. An AC voltage drop detector that detects that the AC voltage has dropped significantly and outputs a signal, and a switch that sets the input of the loop filter calculation unit to 0 by the output of this AC voltage drop detector. Claim 1 characterized by the above.
The described digital PLL circuit. 3. A frequency rise decrease detector for inputting a phase signal output from an H / W counter unit to monitor the frequency and outputting a signal when this frequency exceeds a set allowable frequency, and this frequency rise decrease. 3. The digital PLL circuit according to claim 2, further comprising a switch for setting the input of the loop filter arithmetic unit to 0 according to an AND condition between the output of the detector and the output of the AC voltage drop detector. 4. An AC voltage drop detector for detecting a significant decrease in AC voltage and outputting a signal, two loop filter arithmetic units having different time constants, and outputs of the two loop filter arithmetic units. 2. The digital PLL circuit according to claim 1, further comprising a switch for switching to a loop filter arithmetic unit having a fast time constant according to the output of the AC voltage drop detector. 5. An AC voltage drop detector that detects a significant decrease in AC voltage and outputs a signal, two loop filter arithmetic units having different time constants, and outputs of the respective loop filter arithmetic units. 2. The digital PLL circuit according to claim 1, further comprising a limiter for limiting the output of the AC voltage drop detector and an adder for adding the outputs of the limiters. 6. A frequency rise decrease detector for inputting a phase signal output from an H / W counter section to monitor the frequency and outputting a signal when the frequency exceeds a set allowable frequency, and this frequency rise decrease detection. 5. A switch for setting the input of the loop filter calculation unit to 0 according to the AND condition between the output of the voltage regulator and the output of the AC voltage drop detector.
The described digital PLL circuit. 7. A hysteresis width setting device that outputs a constant hysteresis width when the AC voltage drop detector operates by detecting a drop in the AC voltage, and an output of this hysteresis width setting device is the AC voltage drop detector. 3. The digital PLL circuit according to claim 2, further comprising an adder for adding to the input of the. 8. An AC voltage drop detector that detects that the AC voltage has dropped and outputs a signal, and an output from the PI control operation unit in the loop filter operation unit is cut off by the output of this AC voltage drop detector. The digital PLL circuit according to claim 1, further comprising a switch. 9. The H / W counter section counts the number of pulses from the pulse oscillation calculation section and outputs a phase signal equivalent to an analog output, and the H / W counter section counts the number of pulses from the pulse oscillation calculation section. 9. The digital PLL circuit according to claim 1, further comprising a sample period counter that outputs a synchronization pulse and a counter that counts the synchronization pulse and outputs the synchronization phase signal.