JP2013187247A - Interposer and method for manufacturing the same - Google Patents
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本発明はインターポーザおよびその製造方法に係り、特に、対応する端子間を直線状の電路で接続したインターポーザおよびその製造方法に関する。 The present invention relates to an interposer and a method for manufacturing the interposer, and more particularly to an interposer in which corresponding terminals are connected by a linear electric circuit and a method for manufacturing the interposer.
近年半導体集積回路(IC)は一層小型化、高集積化が進んでおり、外部接続端子も高密度化してきている。 In recent years, semiconductor integrated circuits (ICs) have been further miniaturized and highly integrated, and external connection terminals have also been increased in density.
ICの外部接続端子の高密度化に対応して実装基板上に形成する端子を高密度化することは、製作費の上昇を招くだけでなく、実装技術も高度となる。 Increasing the density of the terminals formed on the mounting substrate in response to the increase in the density of the external connection terminals of the IC not only increases the manufacturing cost, but also increases the mounting technology.
このため、ICと実装基板の間に設置し、ICの端子ピッチを実装基板の端子ピッチに変換するインターポーザがすでに開発されている(例えば、特許文献1参照)。 For this reason, an interposer that is installed between an IC and a mounting board and converts the terminal pitch of the IC into the terminal pitch of the mounting board has already been developed (see, for example, Patent Document 1).
なお、インターポーザは、IC自体を積層するPoP(パッケージ・オン・パッケージ)あるいはPiP(パッケージ・イン・パッケージ)にも使用されている。 The interposer is also used for PoP (package on package) or PiP (package in package) for stacking ICs themselves.
しかしながら、既存のインターポーザは、基板両面の端子間を水平方向の電路と基板を貫通する垂直方向のビアとで接続する構造であり、ピッチの変換率を大きくするためには、基板を複数枚積層し階段状に端子間を接続する必要があった。 However, the existing interposer has a structure in which the terminals on both sides of the board are connected by a horizontal electric circuit and a vertical via that penetrates the board. To increase the pitch conversion rate, multiple boards are stacked. It was necessary to connect the terminals in a staircase pattern.
このため、インターポーザの構造が複雑となるだけでなく、ICの端子と実装基板(または他のIC)の端子を結ぶ電路の長さが長くなるという課題があった。 For this reason, there is a problem that not only the structure of the interposer becomes complicated, but also the length of the electric circuit connecting the terminal of the IC and the terminal of the mounting substrate (or other IC) becomes long.
本発明は上記課題に鑑みなされたものであって、端子間を最短長の電路で接続することのできるインターポーザを提供することを目的とする。 This invention is made | formed in view of the said subject, Comprising: It aims at providing the interposer which can connect between terminals with the shortest electric circuit.
本発明に係るインターポーザは、平板状の透明絶縁体と、前記透明絶縁体の第1の面上に配置される複数個の電極群である第1の電極群と、前記透明絶縁体の前記第1の面の裏面である第2の面上に配置される前記第1の電極群と同数の電極群である第2の電極群と、前記透明絶縁体を貫通し、前記第1の電極群と前記第2の電極群の対応する電極間を最短距離で接続する電路群とを具備する。 An interposer according to the present invention includes a flat transparent insulator, a first electrode group that is a plurality of electrode groups disposed on a first surface of the transparent insulator, and the first electrode of the transparent insulator. A second electrode group which is the same number of electrode groups as the first electrode group disposed on the second surface which is the back surface of the first surface; and the first electrode group which penetrates the transparent insulator. And an electric circuit group connecting the corresponding electrodes of the second electrode group with the shortest distance.
この構成により、インターポーザ両面の端子を直線的に接続して構造を簡略化することができる。 With this configuration, the terminals on both sides of the interposer can be linearly connected to simplify the structure.
本発明に係るインターポーザは、前記電路群が、前記透明絶縁体にフェムト秒レーザアシストエッチングにより前記透明絶縁体内に形成された貫通孔の内壁に形成される電路で構成される。 In the interposer according to the present invention, the electric circuit group is configured by an electric circuit formed on an inner wall of a through hole formed in the transparent insulator by femtosecond laser-assisted etching.
この構成により、透明絶縁体に直線状の電路を形成することができる。 With this configuration, a linear electric circuit can be formed in the transparent insulator.
本発明に係るインターポーザは、前記電路が、めっきまたはCVDにより前記貫通孔内部に形成されたものである。 In the interposer according to the present invention, the electric circuit is formed in the through hole by plating or CVD.
この構成により、高アスペクト比の貫通孔内に電路を形成することができる。 With this configuration, an electric circuit can be formed in the through hole having a high aspect ratio.
本発明に係るインターポーザの製造方法は、平板状の透明絶縁体の第1の面上の複数の位置と前記平板状絶縁体の前記第1の面の裏面である第2の面上の前記第1の面上の複数の位置に対応する位置との最短経路に沿ってフェムト秒レーザにより前記透明絶縁体の内部に改質部を形成する改質部形成段階と、前記改質部をエッチングにより削除して前記透明絶縁体に貫通孔を穿孔する穿孔段階と、前記貫通孔の内部に電路を形成する電路形成段階と、前記平板状絶縁体の第1の面および第2の面の前記貫通孔の開口位置に前記電路と電気的に接続する電極群を形成する電極群形成段階と、を含む。 The method of manufacturing an interposer according to the present invention includes a plurality of positions on the first surface of the flat transparent insulator and the second surface on the second surface which is the back surface of the first surface of the flat insulator. A modified portion forming step of forming a modified portion in the transparent insulator by a femtosecond laser along a shortest path with positions corresponding to a plurality of positions on one surface; and etching the modified portion by etching A drilling step of removing and drilling a through hole in the transparent insulator, an electric circuit forming step of forming an electric circuit inside the through hole, and the penetration of the first surface and the second surface of the flat insulator And an electrode group forming step of forming an electrode group electrically connected to the electric circuit at the opening position of the hole.
本発明によれば、インターポーザ両面の端子が直線的に接続されるため、インターポーザの構造を簡略化することができる。 According to the present invention, since the terminals on both sides of the interposer are linearly connected, the structure of the interposer can be simplified.
以下本発明に係るインターポーザの実施例について説明する。 Examples of interposers according to the present invention will be described below.
図1は本発明に係るインターポーザの上面図(a)、下面図(c)およびX−X断面図(b)である。 FIG. 1 is a top view (a), a bottom view (c), and an XX sectional view (b) of an interposer according to the present invention.
インターポーザ1は、平面状の透明絶縁体11であり、上面11aに第1の電極群12が、下面11bに第2の電極群13が形成されている。
The interposer 1 is a planar
なお、第1の電極群12の電極間ピッチと第2の電極群13の電極間ピッチは相違しており、第1の電極群12を構成する電極数と第2の電極群13を構成する電極数は同一である。
The interelectrode pitch of the
図1の実施例は、第2の電極群13の電極間ピッチは第1の電極群12の電極間ピッチの倍である場合、すなわちピッチ変換率が"2"である場合を示しているが、これは本発明を限定するものではなく、ピッチ変換率は任意の倍率(>0)であってよく、均等である必要もない。さらに、各電極群の電極間ピッチは同一でなくてもよい。
The embodiment of FIG. 1 shows a case where the interelectrode pitch of the
そして、透明絶縁体11の内部には、第1の電極群12と第2の電極群13の対応する電極間を最短距離で接続する電路群14が設けられている。
In the
図2はインターポーザの使用状況を示す模式図であって、インターポーザ1の上面11a上には第1のIC21が搭載され、第1の電極群12は第1のIC21の外部端子と接触している。
FIG. 2 is a schematic diagram showing the use situation of the interposer. The
インターポーザ1の下面11bの下には第2のIC(またはプリント基板)22が配置され、第2の電極群13は第2のIC22の外部端子と接触している。
A second IC (or printed circuit board) 22 is disposed under the
したがって、第1のIC21の外部端子と第2のIC22の外部端子とは第1の電極群12、電路群14および第2の電極群13を介して電気的に接続されることとなる。
Therefore, the external terminal of the
図3は、本発明に係るインターポーザの製造方法を示すフローチャートであって、まず第1段階として、例えば合成石英である透明絶縁体11にフェムト秒レーザを使用して改質部を形成する(ステップ1)。
FIG. 3 is a flowchart showing a method for manufacturing an interposer according to the present invention. First, as a first step, a modified portion is formed using a femtosecond laser on a
すなわち、透明絶縁体11の所定箇所にフェムト秒レーザ光31を照射すると、レーザ光の集光部には構造改質部32が形成される。
That is, when the
レーザ光としては、波長800ナノメートル、パルス幅260〜300フェムト秒、繰り返し周波数200キロヘルツのチタン・サファイアレーザより発射されるレーザ光を開口比0.5の対物レンズで集光したものが適当である。 As the laser beam, a laser beam emitted from a titanium / sapphire laser having a wavelength of 800 nanometers, a pulse width of 260 to 300 femtoseconds, and a repetition frequency of 200 kilohertz is condensed with an objective lens having an aperture ratio of 0.5. is there.
なお、レーザパルスのエネルギは透明絶縁体のアブレーション閾値以下とし、改質中に集光部近傍が溶融等の損傷を受けないようにする必要がある。 The energy of the laser pulse needs to be less than the ablation threshold of the transparent insulator so that the vicinity of the light condensing part is not damaged such as melting during the modification.
レーザを毎秒1ミリメートルの速度で透明絶縁体11内を走査することにより、透明絶縁体11の内部に任意の形状の改質部を形成することができる。
By scanning the inside of the
図4は、透明絶縁体11の中央部から垂直上方に向かって改質層を形成する場合の模式図であり、レーザを中央部からZ軸方向に走査することとなる。
FIG. 4 is a schematic view when a modified layer is formed vertically upward from the central portion of the
なお、改質は透明絶縁体11の表面から離れた位置から表面に向かって形成することが望ましいので、透明絶縁体11の上面11aから下面11bまでを貫通する貫通孔を形成するには、まず透明絶縁体11の中央部から上面11aまでの改質部を形成し、透明絶縁体11を裏返し、中央部から下面11bまでに改質部を形成する。
In addition, since it is desirable to form the modification from a position away from the surface of the
また、透明絶縁体11の上面11aから下面11bまでを斜めに貫通する貫通孔を形成するときは、レーザをZ軸方向だけでなく、X軸およびY軸の少なくとも1つの軸方向に走査すればよい。
Further, when forming a through hole that obliquely penetrates from the
図3に戻って、改質部の形成が完了すると、エッチングにより改質部を除去し、透明絶縁材11に貫通孔を穿孔する(ステップ2)。 Returning to FIG. 3, when the formation of the modified portion is completed, the modified portion is removed by etching, and a through hole is formed in the transparent insulating material 11 (step 2).
エッチングは、ウエットエッチングよりもドライエッチングの方が貫通孔の形状を維持する観点から望ましい。 Etching is preferably dry etching rather than wet etching from the viewpoint of maintaining the shape of the through hole.
上記方法によれば、孔径がサブミクロンで、長さが数十〜数百ミクロンである高アスペクト比の貫通孔を形成することが可能となる。 According to the above method, it is possible to form a high aspect ratio through-hole having a hole diameter of submicron and a length of several tens to several hundreds of microns.
なお、上記したフェムト秒レーザとエッチングにより高アスペクト比の貫通孔を形成する技術は、フェムト秒レーザアシストエッチング法として既に公知である(例えば、http://www.nedo.go.jp/content/100116677.pdfを参照)。 The above-described technique for forming a high aspect ratio through-hole by etching with a femtosecond laser is already known as a femtosecond laser-assisted etching method (for example, http://www.nedo.go.jp/content/ 100116677.pdf).
次に、貫通孔の内部に電路を形成するが、貫通孔の内壁に導電層を形成することが現実的である(ステップ3)。 Next, although an electric circuit is formed inside the through hole, it is practical to form a conductive layer on the inner wall of the through hole (step 3).
導電層の形成方法としては、電解めっき、無電解めっき、CVD(化学気相成長)を適用することができる。 As a method for forming the conductive layer, electrolytic plating, electroless plating, or CVD (chemical vapor deposition) can be applied.
最後に、透明絶縁体11の上面11aおよび下面11bに貫通孔内の電路と接続する第1の電極群12および第2の電極群13を形成して(ステップ4)、インターポーザが完成する。
Finally, the
なお、本発明に係るインターポーザでは、電路を上面の電極群と下面の電極群を最短距離で結ぶように形成しているが、ギガヘルツ以上の高周波信号を対象とする回路に適用する場合には、電路長を等しくしたいという要求もある。 In the interposer according to the present invention, the electric circuit is formed so as to connect the upper electrode group and the lower electrode group at the shortest distance, but when applied to a circuit targeting a high frequency signal of gigahertz or more, There is also a demand to make the circuit lengths equal.
上記のフェムト秒レーザアシストエッチング法によれば、透明絶縁体中に3次元的に改質部を形成することが可能であるため、等しい電路長を有するインターポーザの製造にも本発明を適用可能である。 According to the femtosecond laser assisted etching method described above, the modified portion can be formed three-dimensionally in the transparent insulator. Therefore, the present invention can be applied to the manufacture of an interposer having an equal circuit length. is there.
本発明に係るインターポーザは、裏面照射型撮像素子と半導体メモリを使用した超高速度撮像装置に適用することができる。
従来提案されている超高速撮像装置には、主に画素周辺記録型撮像素子(In Situ Storage Image Sensor、以下ISIS)が使用されていた。
The interposer according to the present invention can be applied to an ultra high-speed imaging device using a backside illumination type imaging device and a semiconductor memory.
Conventionally proposed ultra-high-speed imaging devices mainly use a pixel peripheral recording type imaging device (In Situ Storage Image Sensor, hereinafter referred to as ISIS).
しかし、ISISはフォトダイオードと記憶素子がウエハの同一面に形成されるため、実際の受光面積が小さくなり、感度が抑制されていた。
そこで、ウエハ表面全体で受光を可能とするために、裏面照射型撮像素子が実用化されている。
However, in the ISIS, since the photodiode and the storage element are formed on the same surface of the wafer, the actual light receiving area is reduced and the sensitivity is suppressed.
Therefore, in order to enable light reception over the entire wafer surface, a back-illuminated image sensor has been put into practical use.
裏面照射型撮像素子は、ウエハの裏面全体に撮像素子を形成し、ウエハ内を貫通する電路により撮像信号をウエハ表面に伝送し、ウエハ表面に形成された電極から撮像素子を外部に出力する構造となっている。
そこで、裏面照射型撮像素子の表面と本発明に係るインターボーザ1の上面11aとを接触させ、下面11bとメモリを接触させることにより、撮像素子から出力される撮像信号を連続的に記憶することが可能となる。
The backside-illuminated image sensor has a structure in which an image sensor is formed on the entire back surface of the wafer, an image signal is transmitted to the wafer surface through an electric path penetrating the wafer, and the image sensor is output to the outside from an electrode formed on the wafer surface. It has become.
Therefore, the imaging signal output from the imaging device is continuously stored by bringing the surface of the back-illuminated imaging device into contact with the
図5は、裏面照射型撮像素子と本発明に係るインターボーザを適用した超高速撮像装置の構成図であって、(d)は1個の裏面照射型撮像素子41と1個のメモリ42をインターポーザ1で接続した構成であり、(e)は1個の裏面照射型撮像素子41と複数個のメモリ42、43・・・をインターポーザ1で接続した構成である。
FIG. 5 is a configuration diagram of an ultra-high-speed imaging device to which the backside illumination type imaging device and the interposer according to the present invention are applied. FIG. 5D shows one backside illumination
本発明は、端子間を最短長の電路で接続することのできるインターポーザを提供するものであり、産業上有用である。 INDUSTRIAL APPLICABILITY The present invention provides an interposer that can connect terminals with a shortest electric path, and is industrially useful.
1 インターポーザ
11 透明絶縁体
11a 上面(第1の面)
11b 下面(第2の面)
12 第1の電極群
13 第2の電極群
14 電路群
21 第1のIC
22 第2のIC
31 フェムト秒レーザ光
32 構造改質部
41 裏面照射型撮像素子
42、43 メモリ
1
11b Lower surface (second surface)
12
22 Second IC
31
Claims (4)
前記透明絶縁体の第1の面上に配置される複数個の電極群である第1の電極群と、
前記透明絶縁体の前記第1の面の裏面である第2の面上に配置される前記第1の電極群と同数の電極群である第2の電極群と、
前記透明絶縁体を貫通し、前記第1の電極群と前記第2の電極群の対応する電極間を最短距離で接続する電路群とを具備するインターポーザ。 A flat transparent insulator;
A first electrode group that is a plurality of electrode groups disposed on the first surface of the transparent insulator;
A second electrode group which is the same number of electrode groups as the first electrode group disposed on a second surface which is the back surface of the first surface of the transparent insulator;
An interposer comprising an electric path group penetrating the transparent insulator and connecting the corresponding electrodes of the first electrode group and the second electrode group at a shortest distance.
前記改質部をエッチングにより削除して前記透明絶縁体に貫通孔を穿孔する穿孔段階と、
前記貫通孔の内部に電路を形成する電路形成段階と、
前記平板状絶縁体の第1の面および第2の面の前記貫通孔の開口位置に、前記電路と電気的に接続する電極群を形成する電極群形成段階と、を含むインターポーザの製造方法。 Corresponding to a plurality of positions on the first surface of the flat transparent insulator and a plurality of positions on the first surface on the second surface which is the back surface of the first surface of the flat insulator. A modified part forming step of forming a modified part in the transparent insulator by a femtosecond laser along the shortest path to the position to be
A drilling step of removing the modified portion by etching and drilling a through hole in the transparent insulator;
An electric circuit forming step of forming an electric circuit inside the through hole;
An interposer manufacturing method comprising: an electrode group forming step of forming an electrode group electrically connected to the electric path at the opening positions of the through holes on the first surface and the second surface of the flat insulator.
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