JP2013183411A - Inspection circuit of ad converter and inspection method of ad converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that inspection accuracy deteriorates when evaluating the conversion results of a plurality of AD converters while time-sharing, and inspection circuit and method of an AD converter for inspecting AD converters including multiple channels in parallel while reducing the inspection time are wanted.SOLUTION: The inspection circuit of an AD converter includes a conversion results verification circuit which receives digital signals output from a plurality of AD converters, generates expectations to be output from the plurality of AD converters on the basis of a count up signal being output from a tester, and outputs the conversion results most deviated from the expectation, out of the conversion results output from the plurality of AD converters, to the tester.

Description

  The present invention relates to an AD converter inspection circuit and an AD converter inspection method. In particular, the present invention relates to an AD converter inspection circuit including a plurality of channels and an AD converter inspection method.

  An AD converter that converts an analog signal into a digital signal is used in various circuits. As such an AD converter, a multi-channel AD converter capable of AD converting a plurality of analog signals is often used. This is because a circuit that requires an AD converter often converts a plurality of analog signals into digital signals.

  In the AD converter manufacturing process, it is necessary to inspect whether the manufactured AD converter satisfies a predetermined standard. The AD converter is inspected by connecting the AD converter and the tester, inputting various test signals and control signals from the tester, and inputting digital signals output from the AD converter into the tester (see FIG. 2). The tester inspects characteristics such as the linearity of the AD converter based on the received digital signal, and determines whether the AD converter is good or bad.

  Here, if the multi-channel AD converter is an AD converter to be inspected, it is necessary to inspect all the channels. However, if all channels are inspected serially, it takes a long time to inspect the AD converter.

  Therefore, Patent Document 1 discloses a technique for inspecting AD converters in parallel by selecting output signals of a plurality of AD converters in an arbitrary order using a digital signal selector circuit.

JP 2004-333249 A

  The disclosure of the above prior art document is incorporated herein by reference. The following analysis has been made from the viewpoint of the present invention.

  As described above, according to the technique disclosed in Patent Document 1, a plurality of AD converters can be inspected in parallel. However, in the inspection circuit disclosed in Patent Document 1, a digital signal selected from a plurality of channels of conversion results is input to a tester using a digital signal selector circuit. That is, the conversion results are compared in a time division manner using a digital signal selector circuit. FIG. 3 is FIG. 7 of Patent Document 1. In FIG. As is clear from FIG. 3 (f), the inspection circuit disclosed in Patent Document 1 time-divides the conversion results of AD converters A and B, and inspects the time-division conversion results by taking them into a tester. .

  However, in such a method of comparing the conversion results in a time division manner, focusing on a specific AD converter, only a part of the conversion results are inspected. As a result, the inspection accuracy decreases.

  As described above, there is a problem to be solved in the inspection of the AD converter having a plurality of channels. Therefore, an AD converter inspection circuit and an AD converter inspection method that inspect AD converters having a plurality of channels in parallel without reducing inspection accuracy and reduce the inspection time are desired.

  According to the first aspect of the present invention, the digital signals output from the plurality of AD converters are received, and the expected value to be output by the plurality of AD converters is determined based on the count UP signal output from the tester. An AD converter test circuit is provided that includes a conversion result verification circuit that generates and outputs, to the tester, a conversion result that deviates most from the expected value among the conversion results generated and output from the plurality of AD converters.

  According to a second aspect of the present invention, a step of outputting an analog signal serving as a test signal for a plurality of AD converters and a count UP signal synchronized with the analog signal, and from the count UP signal, the plurality of AD An AD conversion comprising: generating an expected value to be output by the converter; and performing a pass / fail judgment of the plurality of AD converters based on a conversion result of the plurality of AD converters and the expected value. A test method for a vessel is provided.

  According to each aspect of the present invention, an AD converter inspection circuit and an AD converter inspection method for inspecting AD converters having a plurality of channels in parallel without reducing inspection accuracy and reducing inspection time, Provided.

It is a figure for demonstrating the outline | summary of one Embodiment of this invention. It is a figure for demonstrating the relationship between AD converter and its tester. FIG. 7 of Patent Document 1. It is a figure which shows an example of the system configuration | structure containing the test | inspection circuit 1 of the AD converter which concerns on the 1st Embodiment of this invention. FIG. 5 is a diagram illustrating an example of an internal configuration of a conversion result verification circuit 30 illustrated in FIG. 4. It is a flowchart which shows an example of operation | movement of the system containing the test | inspection circuit 1 of the AD converter which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the relationship between the analog ramp signal which the tester 2 outputs, and a count UP signal.

  First, an outline of an embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, when a plurality of AD converters are inspected serially, the inspection time becomes long. On the other hand, when the conversion result of the AD converter is evaluated in a time division manner, the inspection accuracy is lowered. Therefore, an AD converter inspection circuit and an AD converter inspection method that inspect AD converters having a plurality of channels in parallel without reducing inspection accuracy and reduce the inspection time are desired.

  Therefore, an inspection circuit for the AD converter shown in FIG. 1 is provided as an example. The AD converter inspection circuit shown in FIG. 1 accepts digital signals output from a plurality of AD converters, and determines an expected value to be output by the plurality of AD converters based on a count UP signal output from a tester. A conversion result verification circuit is provided that outputs, to the tester, a conversion result that is most deviated from an expected value among the conversion results generated and output from the plurality of AD converters.

  The tester outputs an analog signal for inspecting the AD converter and outputs a count UP signal synchronized with the analog signal. The count UP signal is output at a timing at which the analog signal changes by a voltage corresponding to 1 LSB (Least Significant Bit) of the AD converter to be inspected. As a result, the value obtained by counting the count UP signal is equal to the value (expected value) to be output by the AD converter to be inspected.

  Here, when inspecting the AD converter, a plurality of AD converters are operated simultaneously (in parallel), and a conversion result of each AD converter is obtained. The conversion result is compared with the expected value, and the AD converter is judged to be good or bad by using the conversion result most deviated from the expected value.

  If the conversion result that deviates most from the expected value satisfies the required standard, the conversion result output by other AD converters is guaranteed to be a good product without having to make a pass / fail judgment. it can. As a result, it is possible to inspect AD converters having a plurality of channels in parallel without reducing inspection accuracy, and to reduce inspection time.

  In the present invention, the following modes are possible.

  [Mode 1] As in the test circuit of the AD converter according to the first aspect.

  [Mode 2] Preferably, the test circuit of the AD converter further includes an analog signal distributor that distributes the analog signal output from the tester to the plurality of AD converters.

  [Mode 3] The test circuit of the AD converter constitutes one multi-channel AD converter by the plurality of AD converters, and the tester is based on the conversion result output from the conversion result verification circuit. It is preferable to perform pass / fail judgment of the multi-channel AD converter.

  [Mode 4] The conversion result verification circuit includes a plurality of registers that hold conversion results of the plurality of AD converters, a counter that counts the count UP signal and generates the expected value, and the plurality of registers. A selector that selects one conversion result from conversion results held by the plurality of registers, and the expected value based on an absolute value of a difference between the plurality of conversion results held in the plurality of registers and the expected value. A difference calculation determination unit that determines a conversion result that is most deviated from a value and instructs the selector to output a conversion result of a register that holds a conversion result that is most deviated from the expected value from the plurality of registers. Is preferred.

  [Mode 5] According to the AD converter inspection method according to the second aspect.

  Hereinafter, specific embodiments will be described in more detail with reference to the drawings.

[First Embodiment]
The first embodiment of the present invention will be described in more detail with reference to the drawings.

  FIG. 4 is a diagram illustrating an example of a system configuration including the test circuit 1 of the AD converter according to the present embodiment.

  The AD converter inspection system shown in FIG. 4 includes an AD converter inspection circuit 1 and a tester 2. Further, the AD converter inspection circuit 1 includes an AD converter 10, an analog signal distributor 20, and a conversion result verification circuit 30.

  The AD converter 10 is a multi-channel AD converter. The AD converter 10 is an AD converter corresponding to m (where m is an integer of 2 or more, and so on). Therefore, the AD converter 10 includes m AD converters ADC1 to ADCm. Further, each of the AD converters ADC1 to ADCm included in the AD converter 10 is an AD converter having a resolution of n (where n is an integer equal to or larger than 2; hereinafter the same).

  The analog signal distributor 20 receives an analog signal output from the tester 2. The analog signal distributor 20 distributes the analog signal output from the tester 2 to the AD converters ADC1 to ADCm. More specifically, the analog signal distributor 20 samples the input analog signal and then holds the sampled analog signal to generate m analog signals from one analog signal, Distribution to the AD converters ADC1 to ADCm.

  The conversion result verification circuit 30 receives the result of digital conversion by the AD converters ADC1 to ADCm. The conversion result verification circuit 30 selects one conversion result from a plurality of conversion results output from the AD converters ADC <b> 1 to ADCm and outputs it to the tester 2. The configuration of the conversion result verification circuit 30 will be described later.

  The tester 2 receives the conversion result selected by the conversion result verification circuit 30. The tester 2 outputs an analog signal for inspecting the characteristics of the AD converter 10 to the analog signal distributor 20. The tester 2 outputs a count UP signal to the conversion result verification circuit 30.

  Next, the configuration of the conversion result verification circuit 30 will be described.

  FIG. 5 is a diagram illustrating an example of the internal configuration of the conversion result verification circuit 30.

  The conversion result verification circuit 30 includes a plurality of registers R1 to Rm, a counter 301, a selector 302, a difference calculation determination unit 303, and an output circuit 304.

  The registers R1 to Rm receive the conversion results (digital signals) of the AD converters ADC1 to ADCm, respectively, and hold the values.

  The counter 301 counts the count UP signal.

  The selector 302 selects one conversion result from the registers R1 to Rm and outputs it to the output circuit 304.

  The difference calculation determination unit 303 evaluates the difference between the conversion result held in the registers R1 to Rm and the count value of the counter 301. The difference calculation determination unit 303 instructs the selector 302 on the conversion result to be output from the selector 302 based on the conversion result held in the registers R1 to Rm and the evaluation result of the count value of the counter 301.

  Next, the operation of the system including the test circuit 1 for the AD converter according to the present embodiment will be described.

  FIG. 6 is a flowchart showing an example of the operation of the system including the test circuit 1 of the AD converter according to the present embodiment.

  In step S01, the analog ramp signal output from the tester 2 is input to the AD converter 10 via the analog signal distributor 20.

  In step S02, the AD converters ADC1 to ADCm perform digital conversion. The digital signal converted by the AD converters ADC1 to ADCm is output to the conversion result verification circuit 30 and held in the registers R1 to Rm.

  In step S03, the counter 301 counts the count UP signal.

  Here, it is assumed that the count-up signal is output in synchronization with the analog ramp signal output from the tester 2. More specifically, the period of the count up signal is changed according to the slope of the analog ramp signal.

  FIG. 7 is a diagram illustrating an example of the relationship between the analog ramp signal output from the tester 2 and the count UP signal. The tester 2 outputs the count-up signal at a timing when the analog ramp signal changes by a voltage corresponding to 1LSB of the AD converters ADC1 to ADCm. Since the analog ramp signal and the count up signal are both signals generated by the tester 2, both signals can be output in synchronization. Based on the count UP signal thus generated, the counted value corresponds to a value to be output by the AD converters ADC1 to ADCm, that is, an expected value at the time of AD conversion.

  In step S04, the difference calculation determination unit 303 calculates the difference between the conversion result held in the registers R1 to Rm and the count value of the counter 301. Furthermore, based on the calculated difference, a register that holds the conversion result having the largest absolute value of the difference from the count value is specified (determined).

  In step S <b> 05, the difference calculation determination unit 303 instructs the selector 302 to output the conversion result held by the specified register.

  In step S06, the selector 302 outputs the conversion result held by the designated register to the tester 2 via the output circuit 304.

  In step S07, the tester 2 determines whether or not the accepted conversion result is acceptable. When it is determined that the conversion result does not satisfy the standard required for the AD converter 10, a failure is determined. The tester 2 determines that the entire AD converter 10 is defective if one of the plurality of AD converters ADC1 to ADCm included in the AD converter 10 is defective.

  The above is the description of the operation of the system including the AD converter inspection circuit 1 according to the present embodiment.

  As described above, the difference calculation determination unit 303 performs pass / fail determination of the AD converter 10 using the conversion result that is the most deviated from the expected value (count value of the counter 301) among the conversion results of the AD converters ADC1 to ADCm. . If the conversion result most deviated from the expected value satisfies the inspection standard, it can be ensured that the conversion results of other AD converters also satisfy the inspection standard (inspection accuracy does not decrease). As a result, it is possible to inspect AD converters having a plurality of channels in parallel without reducing inspection accuracy, and to reduce inspection time.

  In a semiconductor integrated circuit that incorporates an AD converter and operates as a CPU (Central Processing Unit), the AD converter 10 can be inspected by a program executed by the CPU. In that case, the AD converter 10 can be inspected without adding a new logic circuit.

  As described above, by performing the inspection of the multi-channel AD converter in parallel, it is possible to inspect the multi-channel AD converter by the inspection substantially equivalent to one channel. Therefore, the inspection time can be reduced and the inspection cost can be reduced.

  Moreover, unlike the inspection method disclosed in Patent Document 1, the conversion results are not compared in a time division manner, so that the inspection accuracy does not deteriorate.

  Further, the tester 2 can use an existing tester. That is, when the tester 2 is operated, there is no need to be aware of whether the AD converter to be inspected is a one-channel AD converter or a multi-channel AD converter. More specifically, the tester 2 only needs to be equipped with an analog inspection unit corresponding to one channel, and units for a plurality of channels are unnecessary. Therefore, it is unnecessary to invest in developing a new tester in order to inspect a multi-channel AD converter (existing tester can be used), which contributes to a reduction in inspection cost.

  Furthermore, the additional circuit necessary for the AD converter inspection circuit 1 according to the present embodiment is only required to realize functions such as difference calculation, size comparison, and signal selection, and can be realized with a small-scale configuration. Therefore, these circuits can be included in a single AD converter.

  The disclosure of the cited patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the scope of the claims of the present invention, Selection is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1 Test circuit of AD converter 2 Tester 10, ADC1 to ADCm AD converter 20 Analog signal distributor 30 Conversion result verification circuit 301 Counter 302 Selector 303 Difference calculation determination unit 304 Output circuit R1 to Rm register

Claims (5)

  Receives digital signals output from a plurality of AD converters, generates expected values to be output from the plurality of AD converters based on a count UP signal output from a tester, and outputs the plurality of AD converters. An AD converter inspection circuit comprising: a conversion result verification circuit that outputs a conversion result that is most deviated from the expected value to the tester.   The AD converter test circuit according to claim 1, further comprising an analog signal distributor that distributes the analog signal output by the tester to the plurality of AD converters.   The plurality of AD converters constitute one multi-channel AD converter, and the tester determines the quality of the multi-channel AD converter based on the conversion result output from the conversion result verification circuit. A test circuit for an AD converter according to claim 1 or 2 to be performed. The conversion result verification circuit includes:
A plurality of registers for holding the conversion results of the plurality of AD converters;
A counter that counts the count-up signal and generates the expected value;
A selector connected to the plurality of registers and selecting one conversion result from the conversion results held by the plurality of registers;
Based on the absolute value of the difference between the plurality of conversion results held in the plurality of registers and the expected value, a conversion result that is most deviated from the expected value is determined, and the most deviated from the expected value from the plurality of registers. A difference calculation determination unit that instructs the selector to output a conversion result of a register that holds the conversion result to be
A test circuit for an AD converter according to claim 1, comprising: Outputting an analog signal as a test signal for a plurality of AD converters and a count UP signal synchronized with the analog signal;
Generating an expected value to be output from the plurality of AD converters from the count-up signal;
A step of determining pass / fail of the plurality of AD converters based on a conversion result of the plurality of AD converters and the expected value;
A method for inspecting an AD converter, comprising:

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