JP2013183194A - Processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processing circuit that suppresses an effect of an offset voltage of an operational amplifier.SOLUTION: In an input period, one terminal of a first reference voltage capacitor Csa is connected to a second input terminal IN2 of an operational amplifier AMP and the other terminal thereof is connected to a first input terminal IN1 of the operational amplifier AMP, and one terminal of a second reference voltage capacitor Csb is connected to the first input terminal IN1 of the operational amplifier AMP and the other terminal thereof is connected to the second input terminal IN2 of the operational amplifier AMP. In an output period, the one terminal of the first reference voltage capacitor Csa is fed with a first reference voltage DAP and the other terminal thereof is connected to the first input terminal IN1 of the operational amplifier AMP, and the one terminal of the second reference voltage capacitor Csb is fed with a second reference voltage DAM and the other terminal thereof is connected to the second input terminal IN2 of the operational amplifier AMP.

Description

  The technology disclosed in this specification relates to a processing circuit that adds and outputs a reference voltage.

  As an example of a processing circuit, a processing circuit that amplifies a differential input signal and adds a reference voltage to output a differential output signal is known. This type of processing circuit is required in various situations. For example, in a unit conversion circuit included in a pipeline type AD converter or a cyclic type AD converter, a differential input signal is amplified and a reference voltage is added to provide a differential output signal to the next stage unit conversion circuit. A processing circuit is needed.

  Patent Document 1 discloses an example of this type of processing circuit. The processing circuit of Patent Document 1 includes an amplifier circuit and an adder circuit. The amplifier circuit includes an operational amplifier and a capacitor, accumulates electric charge corresponding to the differential voltage of the differential input signal in the capacitor, and connects the capacitor between the input terminal and the output terminal of the operational amplifier. The adder circuit provides a charge corresponding to the reference voltage to the capacitor of the amplifier circuit. As a result, the processing circuit can amplify the differential input signal twice and output a differential output signal to which the reference voltage is added.

JP 2010-283773 A

  Usually, an operational amplifier has an offset voltage. In the technique of Patent Document 1, an offset voltage is superimposed on a differential output signal, and an offset error occurs in the differential output signal.

  An object of the technology disclosed in this specification is to provide a processing circuit in which the influence of an offset voltage of an operational amplifier is suppressed.

  The processing circuit disclosed in this specification includes a first input voltage terminal, a second input voltage terminal, an operational amplifier, a first capacitor, a second capacitor, a first reference voltage capacitor, and a second reference voltage capacitor. . The first input voltage terminal is configured to receive a first input voltage. The second input voltage terminal is configured to receive a second input voltage. The operational amplifier has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first capacitor has a first terminal and a second terminal. The second capacitor has a third terminal and a fourth terminal. The first reference voltage capacitor has a fifth terminal and a sixth terminal. The second reference voltage capacitor has a seventh terminal and an eighth terminal. In the processing circuit disclosed in this specification, in the first period, the first input terminal is connected to the first output terminal, the second input terminal is connected to the second output terminal, and the first terminal is the first input voltage. A second terminal connected to the second input voltage terminal, a third terminal connected to the second input voltage terminal, a fourth terminal connected to the first input voltage terminal, and a fifth terminal connected to the second input voltage terminal. The sixth terminal is connected to the first input terminal, the seventh terminal is connected to the first input terminal, and the eighth terminal is connected to the second input terminal. In the processing circuit disclosed in this specification, in a second period different from the first period, the first terminal is connected to the first output terminal, the second terminal is connected to the first input terminal, and the third terminal is Connected to two output terminals, the fourth terminal is connected to the second input terminal, the first reference voltage is applied to the fifth terminal, the sixth terminal is connected to the first input terminal, and the second reference is connected to the seventh terminal. A voltage is applied and the eighth terminal is connected to the second input terminal.

  In the first period, in the first capacitor, the first input voltage is applied to the first terminal and the second input voltage is applied to the second terminal, and the difference voltage between the first input voltage and the second input voltage. Are sampled. Similarly, in the second capacitor, the second input voltage is applied to the third terminal and the first input voltage is applied to the fourth terminal, and the difference voltage between the second input voltage and the first input voltage is sampled. Is done. In the first period, the first reference voltage capacitor has a fifth input terminal connected to the second input terminal of the operational amplifier and a sixth terminal connected to the first input terminal of the operational amplifier. The offset voltage is sampled. Similarly, in the second reference voltage capacitor, the first input terminal of the operational amplifier is connected to the seventh terminal and the second input terminal of the operational amplifier is connected to the eighth terminal, and the offset voltage of the operational amplifier is sampled. The In the second period, the first capacitor is connected between the first input terminal and the first output terminal of the operational amplifier, and the second capacitor is connected between the second input terminal and the second output terminal of the operational amplifier. As a result, the operational amplifier amplifies the sampled differential voltage. At this time, in the first reference voltage capacitor, the first reference voltage is applied to the fifth terminal and the sixth terminal is connected to the first input terminal of the operational amplifier. In the second reference voltage capacitor, the seventh terminal is connected to the seventh terminal. A second reference voltage is applied and the eighth terminal is connected to the second input terminal of the operational amplifier. Thereby, the reference voltage is added to the amplified differential voltage. In the first period, the offset voltage on the second input terminal side is sampled in the first reference voltage capacitor with reference to the potential of the first input terminal of the operational amplifier, and the second reference voltage capacitor is sampled in the operational amplifier. The offset voltage on the first input terminal side is sampled with reference to the potential of the second input terminal. For this reason, the offset voltage appearing at each of the first output terminal and the second output terminal output from the operational amplifier is only the in-phase component. As a result, the influence of the offset voltage does not appear in the difference between the voltage at the first output terminal and the voltage at the second output terminal.

FIG. 1 shows an example of a schematic block diagram of a pipelined AD converter. FIG. 2 shows an example of a timing chart of each unit conversion circuit of the pipeline type AD converter. FIG. 3 shows an example of a schematic block diagram of the unit conversion circuit. FIG. 4 shows input / output characteristics of the unit conversion circuit. FIG. 5 shows an example of a circuit diagram of the unit conversion circuit. FIG. 6 shows a conduction state in the unit conversion circuit of FIG. 5 during the input period. FIG. 7 shows a conduction state in the unit conversion circuit of FIG. 5 during the output period. FIG. 8 shows a conduction state during the output period in the unit conversion circuit of the comparative example. FIG. 9 shows an example of a modification of the unit conversion circuit of FIG. FIG. 10 shows a conduction state during the input period in the unit conversion circuit of the modification of FIG. FIG. 11 shows a conduction state during the output period in the unit conversion circuit of the modification of FIG. FIG. 12 shows an example of a schematic block diagram of a cyclic AD converter. FIG. 13 shows an example of a circuit diagram of the unit conversion circuit. FIG. 14 shows an example of a timing chart of the unit conversion circuit of the cyclic AD converter. FIG. 15 shows a conduction state in the unit conversion circuit of FIG. 13 during the 0th period. FIG. 16 shows a conduction state in the unit conversion circuit of FIG. 13 during the initialization period. FIG. 17 shows a conduction state in the unit conversion circuit of FIG. 13 during the first input / output period. FIG. 18 shows a conduction state in the unit conversion circuit of FIG. 13 during the second input / output period.

The features of the technology disclosed in this specification will be summarized. The items described below have technical usefulness independently.
(First Feature) A processing circuit disclosed in the present specification amplifies a differential input signal composed of a first input voltage and a second input voltage, and is composed of a first reference voltage and a second reference voltage. The reference voltage is added to output a differential output signal composed of the first output voltage and the second output voltage. The processing circuit disclosed in this specification can be used for a circuit that requires power-of-two multiplication, such as a pipelined AD converter and a cyclic AD converter.
(Second Feature) A processing circuit disclosed in this specification includes a first input voltage terminal, a second input voltage terminal, an amplifier circuit, an adder circuit, a first output voltage terminal, and a second output voltage terminal. And may be provided.
(Third feature) The first input voltage terminal may be configured to receive the first input voltage. The second input voltage terminal may be configured to receive a second input voltage.
(Fourth feature) The amplifier circuit may include an operational amplifier, a first capacitor, and a second capacitor.
(Fifth feature) The operational amplifier has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The operational amplifier may be configured such that, in the first period, the first input terminal and the first output terminal are connected, and the second input terminal and the second output terminal are connected. Thereby, in the operational amplifier, full feedback is applied in the first period, and the potentials of the first input terminal and the second input terminal become the offset voltage.
(Sixth feature) The first capacitor has a first terminal and a second terminal. The first capacitor may be configured such that, in the first period, the first terminal is connected to the first input voltage terminal and the second terminal is connected to the second input voltage terminal. Thereby, the first capacitor can sample the difference voltage between the first input voltage and the second input voltage in the first period. The first capacitor may be configured such that, in the second period, the first terminal is connected to the first output terminal of the operational amplifier, and the second terminal is connected to the first input terminal of the operational amplifier. Accordingly, the first capacitor can form a feedback path between the first input terminal and the first output terminal of the operational amplifier in the second period.
(Seventh feature) The second capacitor has a third terminal and a fourth terminal. In the second capacitor, the third terminal may be connected to the second input voltage terminal and the fourth terminal may be connected to the first input voltage terminal in the first period. Accordingly, the second capacitor can sample the difference voltage between the first input voltage and the second input voltage in the first period. The second capacitor may be configured such that, in the second period, the third terminal is connected to the second output terminal of the operational amplifier and the fourth terminal is connected to the second input terminal of the operational amplifier. Accordingly, the second capacitor can form a feedback path between the second input terminal and the second output terminal of the operational amplifier in the second period.
(Eighth feature) The addition circuit may include a reference voltage generation circuit, a first reference voltage capacitor, and a second reference voltage capacitor.
(Ninth Feature) The reference voltage generation unit may be configured to generate a first reference voltage and a second reference voltage. The first reference voltage and the second reference voltage may be set based on the voltage range of the differential input signal. The first reference voltage capacitor has a fifth terminal and a sixth terminal. In the first reference voltage capacitor, the fifth terminal is connected to the second input terminal of the operational amplifier in the first period, the sixth terminal is connected to the first input terminal of the operational amplifier, and the fifth terminal is connected to the fifth terminal in the second period. One reference voltage may be applied, and the sixth terminal may be connected to the first input terminal of the operational amplifier. The second reference voltage capacitor has a seventh terminal and an eighth terminal. The second reference voltage capacitor has a seventh terminal connected to the first input terminal of the operational amplifier in the first period, an eighth terminal connected to the second input terminal of the operational amplifier, and the seventh terminal connected to the seventh terminal in the second period. The second reference voltage may be applied and the eighth terminal may be connected to the second input terminal of the operational amplifier.
(Tenth feature) The first output voltage terminal may be connected to the first output terminal of the operational amplifier, and may be configured to output the first output voltage. The second output voltage terminal is connected to the second output terminal of the operational amplifier, and may be configured to output the second output voltage.
(Eleventh feature) The technique disclosed in this specification may be embodied in an AD conversion circuit that corrects a plurality of sub-digital signals output from a unit conversion circuit to generate a digital signal. This AD converter includes a pipeline type or a cyclic type. The unit conversion circuit may include a sub AD converter and the processing circuit described above. The sub AD converter may be configured to compare the differential input signal with a plurality of thresholds and generate a sub digital signal corresponding to the voltage range of the differential input signal. The reference voltage generation unit of the processing circuit may include a DA converter, and may be configured to generate the first reference voltage and the second reference voltage based on the sub digital signal of the sub AD converter.

  As shown in FIG. 1, a pipelined AD converter 1 converts an analog differential input signal AIN into a multi-bit digital output signal DOUT and outputs it. An AD converter 3 and an encoder 4 are provided.

  The plurality of unit conversion circuits 2 are connected in multiple stages, and are configured such that the differential input signal AIN is input to the unit conversion circuit 2 corresponding to the first stage. The unit conversion circuit 2 in the first stage generates a sub-digital signal D1 [1: 0] corresponding to the most significant bit, and differentially amplifies the differential input signal AIN twice and adds a predetermined reference voltage. The output signal AOUT is output toward the unit conversion circuit 2 of the second stage. The second stage unit conversion circuit 2 receives the differential output signal AOUT output from the first stage unit conversion circuit 2 as a differential input signal AIN, and corresponds to a sub-digital corresponding to a bit one digit lower than the most significant bit. The signal D2 [1: 0] is generated, and the differential output signal AOUT obtained by amplifying the received differential input signal AIN twice and adding a predetermined reference voltage is provided to the unit conversion circuit 2 of the third stage.

  As described above, in the pipelined AD converter 1, the plurality of unit conversion circuits 2 connected in multiple stages perform the pipeline operation, detect the differential input signal AIN in order from the upper bit, and thereby detect the plurality of sub-digital signals. Convert to The flash AD converter 3 converts the output of the unit conversion circuit 2 at the final stage into the sub-digital signal Dm + 1 [n: 0] of the least significant bit. The encoder 4 encodes the sub-digital signal generated by each unit conversion circuit 2 and the flash AD converter 3 with a predetermined arithmetic expression, and generates a digital output signal DOUT corresponding to the analog differential input signal AIN.

  FIG. 2 shows a timing chart of the unit conversion circuit 2 from the first stage to the third stage. As shown in FIG. 2, the unit conversion circuit 2 of each stage is synchronized with the clock CLK and repeats the input period and the output period alternately.

  As shown in FIG. 2, at time T1, the unit conversion circuit 2 of the first stage is in the input period, and the differential input signal AIN is input and sampled. At time T2, the unit conversion circuit 2 of the first stage becomes an output period, and the unit conversion circuit 2 of the second stage becomes an input period. At this time T2, the unit conversion circuit 2 of the first stage generates the sub-digital signal D1 [1: 0] and outputs the differential output signal AOUT to the unit conversion circuit 2 of the second stage. The conversion circuit 2 inputs the differential output signal AOUT as the differential input signal AIN and samples it.

  Similarly, at time T3, the unit conversion circuit 2 of the first stage is in the input period, and the next differential input signal AIN is input and sampled. At time T3, the second stage unit conversion circuit 2 is in the output period, and the third stage unit conversion circuit 2 is in the input period. At this time T3, the second stage unit conversion circuit 2 generates the sub-digital signal D2 [1: 0] and outputs the differential output signal AOUT to the third stage unit conversion circuit 2 to generate the third stage unit. The conversion circuit 2 inputs the differential output signal AOUT as the differential input signal AIN and samples it. At time T4, the unit conversion circuits 2 in the first stage and the third stage are in the output period, and the unit conversion circuit 2 in the second stage is in the input period. That is, the odd-stage unit conversion circuit 2 and the even-stage unit conversion circuit 2 are controlled alternately in the state of the input period and the output period. Finally, the m-th stage unit conversion circuit 2 outputs the digital signal Dm [1: 0], and at the same time, the flash AD converter 3 outputs the least significant digital signal Dm + 1 [n: 0]. The encoder 4 calculates those digital signals and generates a digital output signal DOUT.

  As shown in FIG. 3, the unit conversion circuit 2 includes a 1.5-bit sub AD converter 5 and a processing circuit 8. The processing circuit 8 includes an adder circuit 6 and an amplifier circuit 7. The adder circuit 6 includes a 1.5-bit DA converter 6a and an adder 6b. The amplifier circuit 7 includes a sample hold unit 7a and an amplifier unit 7b. The sub AD converter 5 converts the differential input signal AIN into a 1.5-bit sub digital signal D [1: 0]. The DA converter 6a generates reference voltages DAP and DAM based on the 1.5-bit sub-digital signal D [1: 0]. The sample hold unit 7a and the amplification unit 7b of the amplifier circuit 7 sample and hold the differential input signal AIN, and amplify the sampled and held differential input signal AIN twice. The adder 6b adds the reference voltages DAP and DAM generated by the AD converter 6 to the differential input signal AIN amplified twice, and provides an analog differential output signal AOUT to the unit conversion circuit 2 in the next stage. To do.

  Here, the differential input signal AIN is composed of a first input voltage Vinp and a second input voltage Vinm, and these voltages have a reverse phase relationship. The differential output signal AOUT is also composed of a first output voltage Voutp and a second output voltage Voutm, and these voltages have a reverse phase relationship. The reference voltages DAP and DAM include any one of a positive reference voltage (+ Vref), a negative reference voltage (−Vref), and a common voltage (a center voltage (0 V) between the positive reference voltage and the negative reference voltage). Is selected. The positive reference voltage (+ Vref) and the negative reference voltage (−Vref) correspond to the upper limit value and lower limit value of the amplitude of the first input voltage Vinp and the second input voltage Vinm. Therefore, the differential input signal AIN corresponding to the difference voltage between the first input voltage Vinp and the second input voltage Vinm has an amplitude between + 2Vref and −2Vref. Similarly, the differential output signal AOUT corresponding to the difference voltage between the first output voltage Voutp and the second output voltage Voutm also has an amplitude between + 2Vref and −2Vref.

  The sub AD converter 5 compares the differential input signal AIN with two threshold values (−Vref / 2, Vref / 2), detects in which voltage range the differential input signal AIN exists, Based on this, the sub-digital signal D [1: 0] is generated. For example, when the sub AD converter 5 detects that the differential input signal AIN is in a voltage range lower than −Vref / 2, it outputs the sub digital signal D [1: 0] that becomes “00”. The sub A / D converter 5 outputs a sub digital signal D [1: 0] which is “01” when it is detected that the differential input signal AIN is in the voltage range of −Vref / 2 to Vref / 2. The sub A / D converter 5 outputs a sub digital signal D [1: 0] which is “10” when it is detected that the differential input signal AIN is in a voltage range exceeding Vref / 2. The DA converter 6a selects the positive reference voltage (+ Vref) as the reference voltages DAP and DAM when the sub-digital signal D [1: 0] is “00”. For this reason, in the adder circuit 8, the positive reference voltage (+ Vref) is added to the differential input signal AIN amplified twice, so that the differential output signal AOUT becomes 2AIN + Vref. The DA converter 6a selects the common voltage (0V) as the reference voltages DAP and DAM when the sub-digital signal D [1: 0] is “01”. Therefore, the differential output signal AOUT is 2AIN. The DA converter 6a selects the negative reference voltage (−Vref) as the reference voltages DAP and DAM when the sub-digital signal D [1: 0] is “10”. For this reason, in the adder circuit 8, the negative reference voltage (-Vref) is added to the differential input signal AIN amplified twice, so that the differential output signal AOUT becomes 2AIN-Vref.

  As shown in the input / output characteristic diagram of FIG. 4, when the differential input signal AIN is in a voltage range lower than −Vref / 2, the differential output signal AOUT is 2AIN + Vref, and the differential input signal AIN is −Vref / When the voltage range is 2 to Vref / 2, the differential output signal AOUT is 2AIN, and when the differential input signal AIN is in a voltage range exceeding + Vref / 2, the differential output signal AOUT is 2AIN−Vref. .

  FIG. 5 shows a circuit diagram of the unit conversion circuit 2. The unit conversion circuit 2 includes a first input voltage terminal Tinp, a second input voltage terminal Tinm, a 1.5-bit sub AD converter 5, a 1.5-bit DA converter 6a, and a first reference voltage capacitor Csa. A second reference voltage capacitor Csb, an operational amplifier AMP, a first capacitor Cf1a, a second capacitor Cf1b, a plurality of switches SW, a first output voltage terminal Toutp, and a second output voltage terminal Toutm. I have.

  The first input voltage terminal Tinp is configured to receive the first input voltage Vinp of the differential input signal AIN. The second input voltage terminal Tinm is configured to receive the second input voltage Vinm of the differential input signal AIN.

  The sub AD converter 5 is connected to the first input voltage terminal Tinp and the second input voltage terminal Tinm. As described above, the sub A / D converter 5 compares the differential input signal AIN with two threshold values (−Vref / 2, Vref / 2), and based on the voltage range of the differential input signal AIN, the sub digital signal D [ 1: 0] is output. The DA converter 6a is configured to be able to input a sub-digital signal D [1: 0], and based on the sub-digital signal D [1: 0], a positive reference voltage (+ Vref) and a negative reference voltage (− Vref) or common voltage (0 V) is selected. For example, when the positive side reference voltage (+ Vref) is selected, the DA converter 6a controls the first reference voltage DAP to −Vref / 2 and the second reference voltage DAM to Vref / 2. When the negative reference voltage (-Vref) is selected, the DA converter 6a controls the first reference voltage DAP to Vref / 2 and the second reference voltage DAM to -Vref / 2. When the common voltage (0V) is selected, the DA converter 6a controls the first reference voltage DAP and the second reference voltage DAM to 0V.

  The first reference voltage capacitor Csa has one terminal (corresponding to the fifth terminal recited in the claims) connected to the first offset compensation switch SW4a, and the other terminal (the sixth terminal recited in the claims). Corresponding to the terminal) is connected to the first input terminal IN1 of the operational amplifier AMP. The first offset compensation switch SW4a connects one terminal of the first reference voltage capacitor Csa to the second input terminal IN2 of the operational amplifier AMP in the input period, and one terminal of the first reference voltage capacitor Csa in the output period. Can be connected to the DA converter 6a. The second reference voltage capacitor Csb has one terminal (corresponding to the seventh terminal recited in the claims) connected to the second offset compensation switch SW4b, and the other terminal (the eighth terminal recited in the claims). Corresponding to the terminal) is connected to the second input terminal IN2 of the operational amplifier AMP. The second offset compensation switch SW4b connects one terminal of the second reference voltage capacitor Csb to the first input terminal IN1 of the operational amplifier AMP in the input period, and one terminal of the second reference voltage capacitor Csb in the output period. Can be connected to the DA converter 6a.

  The first capacitor Cf1a has one terminal (corresponding to the first terminal recited in the claims) connected to the capacitor switch SW2a and the other terminal (corresponding to the second terminal recited in the claims). The capacitor switch SW1a is connected. The first capacitor Cf1a is connected between the first input voltage terminal Tinp and the second input voltage terminal Tinm in the input period by switching the capacitor switches SW1a and SW2a, and is connected to the first input terminal IN1 of the operational amplifier AMP in the output period. The first output terminal OUT1 is connectable. Similarly, the second capacitor Cf1b has one terminal (corresponding to the third terminal recited in the claims) connected to the capacitor switch SW2b and the other terminal (corresponding to the fourth terminal recited in the claims). Is connected to the capacitor switch SW1b. The second capacitor Cf1b is connected between the first input voltage terminal Tinp and the second input voltage terminal Tinm in the input period by switching the capacitor switches SW1b and SW2b, and is connected to the second input terminal IN2 of the operational amplifier AMP in the output period. The second output terminal OUT2 can be connected.

  A first initialization switch SW3a is provided between the first input terminal IN1 and the first output terminal OUT1 of the operational amplifier AMP. The first initialization switch SW3a is conductive during the input period and insulated during the output period. Further, a second initialization switch SW3b is provided between the second input terminal IN2 and the second output terminal OUT2 of the operational amplifier AMP. The second initialization switch SW3b is conductive during the input period and insulated during the output period.

  The first output voltage terminal Toutp is connected to the first output terminal OUT1 of the operational amplifier AMP, and is configured to output the first output voltage Voutp. The second output voltage terminal Toutm is connected to the second output terminal OUT2 of the operational amplifier AMP and is configured to output the second output voltage Voutm.

  Next, the operation of the unit conversion circuit 2 will be described. First, the conduction state when the unit conversion circuit 2 is in the input period will be described. As shown in FIG. 6, in the input period, the first capacitor Cf1a is connected between the first input voltage terminal Tinp and the second input voltage terminal Tinm, and the first input voltage Vinp and the first input voltage Vinp are connected to the first capacitor Cf1a. A differential voltage of the two input voltages Vinm is applied, and the differential input signal is sampled. Similarly, in the input period, the second capacitor Cf1b is connected between the first input voltage terminal Tinp and the second input voltage terminal Tinm, and the first input voltage Vinp and the second input voltage Vinm are connected to the second capacitor Cf1b. A differential voltage is applied and the differential input signal is sampled.

  Here, if the capacitance of the first capacitor Cf1a is Cf1a and the capacitance of the second capacitor is Cf1b, the amount of charge Q1 (Cf1a) accumulated in the capacitor switch SW1a side terminal of the first capacitor Cf1a in the first period. The charge amount Q1 (Cf1b) accumulated at the terminal on the capacitor switch SW1b side of the second capacitor Cf1b is expressed by the following Equation 1.

  Further, as shown in FIG. 6, in the input period, the first initialization switch 3a short-circuits between the first input terminal IN1 and the first output terminal OUT1 of the operational amplifier AMP, and the second initialization switch 3b The second input terminal IN2 and the second output terminal OUT2 of the operational amplifier AMP are short-circuited. Here, as shown in FIG. 6, in the input period, the first offset voltage Vosm is output to the first output terminal OUT1 of the operational amplifier AMP, and the second offset voltage Vosp is output to the second output terminal OUT2 of the operational amplifier AMP. Let's say. In the input period, the first initialization switch 3a short-circuits between the first input terminal IN1 and the first output terminal OUT1 of the operational amplifier AMP so that full feedback is applied. Therefore, the potential of the first input terminal IN1 of the operational amplifier AMP is the first potential. 2 offset voltage Vosm. Similarly, in the input period, since the second initialization switch 3b short-circuits between the second input terminal IN2 and the second output terminal OUT2 of the operational amplifier AMP, full feedback is applied, so that the second input terminal IN2 of the operational amplifier AMP The potential becomes the first offset voltage Vosp.

  In the input period, the first offset compensation switch SW4a is connected to the second input terminal IN2 of the operational amplifier AMP. Therefore, the first offset voltage Vosp and the second offset voltage Vosm are applied to both ends of the first reference voltage capacitor Csa, and charges corresponding to the voltage difference are accumulated. Similarly, in the input period, the second offset compensation switch SW4b is connected to the first input terminal IN1 of the operational amplifier AMP. Therefore, the first offset voltage Vosp and the second offset voltage Vosm are applied to both ends of the second reference voltage capacitor Csb, and charges corresponding to the voltage difference are accumulated. Here, if the capacitance of the first reference voltage capacitor Csa is Csa and the capacitance of the second reference voltage capacitor Csb is Csb, the first reference voltage capacitor Csa is accumulated in the terminal on the operational amplifier AMP side in the input period. The charge amount Q1 (Csb) and the charge amount Q1 (Csb) accumulated at the terminal on the operational amplifier AMP side of the second reference voltage capacitor Csb are expressed by the following Equation 2.

  Next, the conduction state when the unit conversion circuit 2 is in the output period will be described. As shown in FIG. 7, in the output period, the first capacitor Cf1a is connected between the first input terminal IN1 and the first output terminal OUT1 of the operational amplifier AMP, and between the first input terminal IN1 and the first output terminal OUT1. A feedback connection is formed. Similarly, in the output period, the second capacitor Cf1b is connected between the second input terminal IN2 and the second output terminal OUT2 of the operational amplifier AMP, and a feedback connection is formed between the second input terminal IN2 and the second output terminal OUT2. Is done. By this feedback connection, the potential of the first input terminal IN1 of the operational amplifier AMP is maintained at the second offset voltage Vosm, and the potential of the second input terminal IN2 of the operational amplifier AMP is maintained at the first offset voltage Vosp.

  In the output period, the sub AD converter 5 generates the sub digital signal D [1: 0]. The DA converter 6a generates reference voltages DAP and DAM based on the sub-digital signal D [1: 0]. Since the first offset compensation switch SW4a is connected to the DA converter 6a, the first reference voltage DAP is applied to one terminal of the first reference voltage capacitor Csa. Therefore, the second offset voltage Vosm and the first reference voltage DAP are applied to both ends of the first reference voltage capacitor Csa, and charges corresponding to the voltage difference are accumulated. Similarly, since the second offset compensation switch SW4b is connected to the DA converter 6a, the second reference voltage DAM is applied to one terminal of the second reference voltage capacitor Csb. Therefore, the first offset voltage Vosp and the second reference voltage DAM are applied to both ends of the second reference voltage capacitor Csb, and charges corresponding to the voltage difference are accumulated. In the output period, the charge amount Q2 (Csa) accumulated at the terminal on the operational amplifier AMP side of the first reference voltage capacitor Csa and the charge amount Q2 (Csb) accumulated at the terminal on the operational amplifier AMP side of the second reference voltage capacitor Csb ) Is expressed by Equation 3 below.

  Here, FIG. 8 shows a conduction state in the output period in the comparative example. The comparative example is an example in which the offset compensation switches SW4a and SW4b are not provided. For this reason, in the comparative example, the offset voltage is not sampled in the reference voltage capacitors Csa and Csb in the input period, and no charge is accumulated. In the connection state in the output period, the wiring connecting the first input terminal IN1, the first reference voltage capacitor Csa, and the first capacitor Cf1a of the operational amplifier AMP is closed. Therefore, in this closed wiring, according to the law of charge conservation, the charge accumulated in the first capacitor Cf1a in the input period and the charge accumulated in the first capacitor Cf1a and the first reference voltage capacitor Csa in the output period match. Assuming that the amount of charge accumulated at the terminal on the capacitor switch SW1a side of the first capacitor Cf1a in the output period is Q2 (Cf1a), the following expression 4 is obtained.

  When Formula 4 is arranged with respect to Q2 (Cf1a), it is expressed by Formula 5 below.

  Similarly, in the connection state in the output period, the wiring connecting the second input terminal IN2, the second reference voltage capacitor Csb, and the second capacitor Cf1b of the operational amplifier AMP is closed. Therefore, in this closed wiring, according to the law of charge conservation, the charge accumulated in the second capacitor Cf1b in the input period and the charge accumulated in the second capacitor Cf1b and the second reference voltage capacitor Csb in the output period coincide. If the amount of charge accumulated at the terminal on the capacitor switch SW1b side of the second capacitor Cf1b in the output period is Q2 (Cf1b), it is expressed by the following Equation 6.

  When formula 6 is arranged with respect to Q2 (Cf1b), it is expressed by formula 7 below.

  Since the potential of the first input terminal IN1 of the operational amplifier AMP is the second offset voltage Vosm, the voltage of the first output voltage Voutp is obtained by adding the second offset voltage Vosm to the potential difference of the first capacitor Cf1a. The potential difference of the first capacitor Cf1a is obtained by dividing the amount of charge accumulated in the first capacitor Cf1a by the capacitance Cf1a of the first capacitor Cf1a. That is, when the second offset voltage Vosm is added to the result obtained by dividing Formula 5 by the capacitance Cf1a of the first capacitor Cf1a and reversing the positive and negative, the first output voltage Voutp is obtained. Similarly, since the potential of the second input terminal IN2 of the operational amplifier AMP is the first offset voltage Vosp, the voltage of the second output voltage Voutm is obtained by adding the first offset voltage Vosp to the potential difference of the second capacitor Cf1b. The potential difference of the second capacitor Cf1b is obtained by dividing the amount of charge accumulated in the second capacitor Cf1b by the capacitance of the second capacitor Cf1b. That is, when the first offset voltage Vosp is added to the expression 7 divided by the capacitance Cf1b of the second capacitor Cf1b and reversed in polarity, the second output voltage Voutm is obtained. The first output voltage Voutp and the second output voltage Voutm are expressed by Equation 8 below.

Here, assuming that the capacitance of each of the capacitors Cf1a, Cf1b, Csa, and Csb is “Cf1a = Cf1b = Csa = Csb = C”, the differential output signal AOUT is expressed by Equation 9 below.

  As shown in Equation 9, in the case of the comparative example, an offset error of 2 (Vosm−Vosp) is superimposed on the differential output signal Vout based on the offset voltage of the operational amplifier AMP.

  On the other hand, in this embodiment, as shown in FIG. 7, offset compensation switches SW4a and SW4b are provided, and charges corresponding to the offset voltage are stored in the reference voltage capacitors Csa and Csb in the input period. Is done. Accordingly, when the law of conservation of electric charge is applied, Expressions 4 and 6 are expressed by Expression 10 below.

  For this reason, Formula 5 and 7 are also represented by the following Formula 11.

  Further, the first output voltage Voutp and the second output voltage Voutm are also expressed by Equation 12 below.

When the capacitances of the capacitors Cf1a, Cf1b, Csa, and Csb are “Cf1a = Cf1b = Csa = Csb = C”, the differential output signal AOUT is expressed by the following Expression 13.

  As shown in Formula 13, in this embodiment, the offset error of 2 (Vosm−Vosp) that appears in the comparative example disappears. In this embodiment, during the input period, the offset voltage on the second input terminal IN2 side is sampled in the first reference voltage capacitor Csa on the basis of the potential of the first input terminal IN1 of the operational amplifier AMP, and the second reference voltage capacitor is sampled. The offset voltage on the first input terminal IN1 side is sampled at Csb with reference to the potential of the second input terminal IN2 of the operational amplifier AMP. As a result, the offset voltage appearing in each of the first output voltage Voutp and the second output voltage Voutm output from the operational amplifier AMP becomes only the in-phase component (see Expression 12). As a result, in this embodiment, the influence of the offset voltage does not appear in the operation output signal AOUT. In this embodiment, the influence of the offset voltage of the operational amplifier AMP is suppressed, and the accuracy of the double amplification is improved.

(Modification)
The unit conversion circuit 12 of the modification shown in FIG. 9 is characterized in that measures are taken against the parasitic capacitances of the capacitor switches SW1a and SW1b. The unit conversion circuit 12 includes charge compensation units 9A and 9B and adjustment capacitors Cca and Ccb.

  The first charge compensation unit 9A includes a first charge compensation capacitor Ca and a first charge compensation switch SW5a. The first charge compensation capacitor Ca has one terminal connected to the first capacitor Cf1a and the other terminal connected to the first charge compensation switch SW5a. The first charge compensation switch SW5a is configured to be connected to the second input voltage terminal Tinm in the input period and connectable to the second input terminal IN2 of the operational amplifier AMP in the output period. The second charge compensation unit 9B includes a second charge compensation capacitor Cb and a second charge compensation switch SW5b. The second charge compensation capacitor Cb has one terminal connected to the second capacitor Cf1b and the other terminal connected to the second charge compensation switch SW5b. The second charge compensation switch SW5b is configured to be connected to the first input voltage terminal Tinp in the input period and connectable to the first input terminal IN1 of the operational amplifier in the output period.

  One terminal of the first adjustment capacitor Cca is connected to the first input terminal IN1 of the operational amplifier AMP, and the other terminal is connected to the first adjustment switch SW6a. The first adjustment switch SW6a connects the other terminal of the first adjustment capacitor Cca to the second input terminal IN2 of the operational amplifier AMP in the input period, and connects the other terminal of the first adjustment capacitor Cca to the ground potential in the output period. It can be connected to (0V). The second adjustment capacitor Ccb has one terminal connected to the second input terminal IN2 of the operational amplifier AMP and the other terminal connected to the second adjustment switch SW6b. The second adjustment switch SW6b connects the other terminal of the second adjustment capacitor Ccb to the first input terminal IN1 of the operational amplifier AMP during the input period, and connects one terminal of the second adjustment capacitor Ccb to the ground potential during the output period. It can be connected to (0V).

  Next, the operation of the unit conversion circuit 2 of the modification will be described. Note that a description of portions common to the above-described embodiments is omitted. First, a conduction state when the unit conversion circuit 12 of the modification is in the input period will be described.

  As shown in FIG. 10, in the input period, the first charge compensation switch SW5a of the first charge compensation unit 9A is connected to the second input voltage terminal Tinm. At this time, since the second input voltage Vinm is applied to both ends of the first charge compensation capacitor Ca, there is no potential difference between both ends of the first charge compensation capacitor Ca. Therefore, no charge is accumulated in the first charge compensation capacitor Ca during the input period. Similarly, in the input period, the second charge compensation switch SW5b of the second charge compensation unit 9B is connected to the first input voltage terminal Tinp. At this time, since the first input voltage Vinp is applied to both ends of the second charge compensation capacitor Cb, there is no potential difference between both ends of the second charge compensation capacitor Cb. For this reason, in the input period, no charge is accumulated in the second charge compensation capacitor Cb.

  In the input period, the first adjustment switch SW6a is connected to the second input terminal IN2 of the operational amplifier AMP. Therefore, the first offset voltage Vosp and the second offset voltage Vosm are applied to both ends of the first adjustment capacitor Cca, and charges corresponding to the voltage difference are accumulated. Similarly, in the input period, the second adjustment switch SW6b is connected to the first input terminal IN1 of the operational amplifier AMP. Therefore, the first offset voltage Vosp and the second offset voltage Vosm are applied to both ends of the second adjustment capacitor Ccb, and charges corresponding to the voltage difference are accumulated. If the capacitance of the first adjustment capacitor Cca is Cca and the capacitance of the second adjustment capacitor Ccb is Ccb, the first adjustment capacitor Cca is stored in the terminal on the first input terminal IN1 side of the operational amplifier AMP of the first adjustment capacitor Cca in the input period. The amount of charge Q1 (Cca) and the amount of charge Q1 (Ccb) accumulated at the terminal on the second input terminal IN2 side of the operational amplifier AMP of the second adjustment capacitor Ccb are expressed by Equation 14 below.

  Here, the switches SW1a, 1b, 5a, 5b are considered. Since these switches SW1a, 1b, 5a, 5b are composed of transistors, they have parasitic capacitances. Further, the first input voltage Vinp or the second input voltage Vinm is applied to these switches SW1a, 1b, 5a, 5b during the input period. For this reason, electric charges are accumulated in these switches SW1a, 1b, 5a, 5b according to the parasitic capacitance and the input voltages Vinp, Vinm. As shown in FIG. 10, the parasitic capacitance of the capacitor switch SW1a is Cpxa, the parasitic capacitance of the capacitor switch SW1b is Cpxb, the parasitic capacitance of the first charge compensation switch SW5a is Cpya, and the second charge compensation switch. If the parasitic capacitance of SW5b is Cpyb, the charge amount Q1 (SW1a) stored in the capacitor switch SW1a, the charge amount Q1 (SW1b) stored in the capacitor switch SW1b, and the first charge compensation switch SW5a are stored in the input period. The charge amount Q1 (SW5a) to be stored and the charge amount Q1 (SW5b) stored in the second charge compensation switch SW5b are expressed by the following Expression 15.

  Next, a conduction state when the unit conversion circuit 12 of the modified example is in the output period will be described. As shown in FIG. 11, in the output period, the capacitor switch SW1a is connected to the first input terminal IN1 of the operational amplifier AMP, and the first charge compensation switch SW5a is connected to the second input terminal IN2 of the operational amplifier AMP. Therefore, the first offset voltage Vosp and the second offset voltage Vosm are applied to both ends of the first charge compensation capacitor Ca, and charges corresponding to the voltage difference are accumulated. Similarly, in the output period, the capacitor switch SW1b is connected to the second input terminal IN2 of the operational amplifier AMP, and the second charge compensation switch SW5b is connected to the first input terminal IN1 of the operational amplifier AMP. Therefore, the first offset voltage Vosp and the second offset voltage Vosm are applied to both ends of the second charge compensation capacitor Cb, and charges corresponding to the voltage difference are accumulated.

  In the output period, the charge amount Q2 (Ca) stored in the terminal connected to the first input terminal IN1 of the operational amplifier AMP of the first charge compensation capacitor Ca and the terminal connected to the second input terminal IN2 are stored. The charge amount Q′2 (Ca) and the charge amount Q2 (Cb) accumulated in the terminal connected to the second input terminal IN2 of the operational amplifier AMP of the second charge compensation capacitor Cb are connected to the first input terminal IN1. The amount of charge Q′2 (Cb) stored in the terminal is expressed by the following Expression 16.

  In the output period, the first adjustment switch SW6a is connected to the ground potential (0 V). Therefore, the second offset voltage Vosm and the ground potential (0 V) are applied to both ends of the first adjustment capacitor Cca, and charges corresponding to the voltage difference are accumulated. Similarly, the second adjustment switch SW6b is connected to the ground potential (0 V). Therefore, the first offset voltage Vosp and the ground potential (0 V) are applied to both ends of the second adjustment capacitor Ccb, and charges corresponding to the voltage difference are accumulated. In the output period, the amount of charge Q2 (Cca) accumulated at the terminal on the operational amplifier AMP side of the first adjustment capacitor Cca and the amount of charge Q2 (Ccb) accumulated at the terminal on the operational amplifier AMP side of the second adjustment capacitor Ccb are: And expressed by the following Equation 17.

  In the output period, the second offset voltage Vosm is applied to the capacitor switch SW1a and the second charge compensation switch SW5b, and the first offset voltage Vosp is applied to the capacitor switch SW1b and the first charge compensation switch SW5a. Is applied. In the output period, the charge amount Q2 (SW1a) accumulated in the capacitor switch SW1a, the charge amount Q2 (SW1b) accumulated in the capacitor switch SW1b, the charge amount Q2 (SW5a) accumulated in the first charge compensation switch SW5a, and the first The charge amount Q2 (SW5b) accumulated in the two-charge compensation switch SW5b is expressed by the following Expression 18.

  Here, in the closed wiring connected to the first input terminal IN1 of the operational amplifier AMP, the law of charge conservation is applied to the input period and the output period. Assuming that the amount of charge accumulated at the terminal on the capacitor switch SW1a side of the first capacitor Cf1a in the output period is Q2 (Cf1a), the following equation 19 is obtained.

  When formula 19 is arranged with respect to Q2 (Cf1a), it is expressed by the following formula 20.

  Similarly, in the closed wiring connected to the second input terminal IN2 of the operational amplifier AMP, the law of charge conservation is applied to the input period and the output period. Assuming that the amount of charge accumulated at the terminal on the capacitor switch SW1b side of the second capacitor Cf1b in the output period is Q2 (Cf1b), the following expression 21 is obtained.

  When formula 21 is arranged with respect to Q2 (Cf1b), it is expressed by the following formula 22.

  The voltage of the first output voltage Voutp is obtained by adding the second offset voltage Vosm to the potential difference of the first capacitor Cf1a. The potential difference of the first capacitor Cf1a is obtained by dividing the amount of charge accumulated in the first capacitor Cf1a by the capacitance Cf1a of the first capacitor Cf1a. That is, when the second offset voltage Vosm is added to a value obtained by dividing Equation 20 by the capacitance Cf1a of the first capacitor Cf1a and reversing the positive and negative values, the first output voltage Voutp is obtained. Similarly, the voltage of the second output voltage Voutm is obtained by adding the first offset voltage Vosp to the potential difference of the second capacitor Cf1b. The potential difference of the second capacitor Cf1b is obtained by dividing the amount of charge accumulated in the second capacitor Cf1b by the capacitance of the second capacitor Cf1b. That is, when the first offset voltage Voutp is added to the equation 22 divided by the capacitance Cf1b of the second capacitor Cf1b and reversed in polarity, the second output voltage Voutm is obtained. The first output voltage Voutp and the second output voltage Voutm are expressed by Equation 23 below.

Here, the capacitances of the capacitors Cf1a, Cf1b, Csa, and Csb are “Cf1a = Cf1b = Csa = Csb = C”, and the parasitic capacitances of the capacitors switches SW1a, SW1b, SW4a, and SW4b are “Cpxa = Cpxb = Cpya = When Cpyb = Cp ”and the adjustment capacitors Cca and Ccb and the compensation capacitors Ca and Cb are“ Cca = Ccb = 4Ca + 2Cp = 4Cb + 2Cp ”, the first output voltage Voutp and the second output voltage Voutm are expressed by the following Expression 24. expressed.

The differential output signal AOUT is expressed by Equation 25 below.

  As shown in Expression 25, in this embodiment, the influence of the offset voltage does not appear in the differential output signal AOUT. Furthermore, in the case of the present embodiment, charge compensation units 9A and 9B are provided, and in the output period, the first charge compensation switch SW4a of the first charge compensation unit 9A is closed including the second input terminal IN2 of the operational amplifier AMP. The second charge compensation switch SW4b of the second charge compensation unit 9B is connected to a closed line including the first input terminal IN1 of the operational amplifier AMP. As a result, the charge accumulated in the parasitic capacitance of the first charge compensation switch SW4a of the first charge compensation unit 9A is discharged to the closed wiring including the second input terminal IN2 of the operational amplifier AMP, and the second charge compensation unit 9B The charge accumulated in the parasitic capacitance of the two-charge compensation switch 4b is discharged to the closed wiring including the first input terminal IN1 of the operational amplifier AMP. Specifically, the charge accumulated in the parasitic capacitance of the first charge compensation switch SW4a of the first charge compensation unit 9A is equal to the charge accumulated in the parasitic capacitance of the capacitor switch SW1a. For this reason, when the first charge compensator 9A is provided, the influence of these charges becomes an in-phase component with respect to the output of the operational amplifier AMP, and the influence of the parasitic capacitance disappears by canceling them. Similarly, the charge accumulated in the parasitic capacitance of the second charge compensation switch SW4b of the second charge compensation unit 9B is equal to the charge accumulated in the parasitic capacitance of the capacitor switch SW1b. For this reason, when the second charge compensator 9B is provided, the influence of these charges becomes an in-phase component with respect to the output of the operational amplifier AMP, and the influence of the parasitic capacitance disappears by canceling them. In this embodiment, the influence of the parasitic capacitance is suppressed, and the accuracy of the double amplification is improved.

  As shown in FIG. 12, the cyclic AD converter 100 converts an analog differential input signal AIN into a multi-bit digital output signal DOUT and outputs it, and includes a unit conversion circuit 102 and an encoder 104. ing.

  The unit conversion circuit 102 is configured to receive a differential input signal AIN and is configured to circulate using the output as an input. The unit conversion circuit 102 first generates a sub-digital signal D1 [1: 0] corresponding to the most significant bit, and doubles the differential input signal AIN and adds a predetermined reference voltage to the differential output signal AOUT. Is output. The unit conversion circuit 102 circulates the differential output signal AOUT and receives it as a differential input signal AIN, and generates a sub-digital signal D2 [1: 0] corresponding to a bit one digit lower than the most significant bit. Then, the received differential input signal AIN is amplified twice, and a differential output signal AOUT obtained by adding a predetermined reference voltage is output.

  In this way, in the cyclic AD converter 100, the unit conversion circuit 102 performs a cyclic operation, and the differential input signal AIN is detected in order from the upper bits and converted into a plurality of sub-digital signals. The encoder 4 encodes the sub-digital signal output from the unit conversion circuit 102 with a predetermined arithmetic expression, and generates a digital output signal DOUT corresponding to the analog differential input signal AIN.

  FIG. 13 shows a circuit diagram of the unit conversion circuit 102. In addition, about the component which is common in the unit conversion circuit 2 of 1st Example, a common code | symbol is attached | subjected and the description is abbreviate | omitted. The unit conversion circuit 102 includes a third capacitor Cf2a, a fourth capacitor Cf2b, and a plurality of switches SW.

  The third capacitor Cf2a has one terminal connected to the first output terminal OUT1 of the operational amplifier AMP and the other terminal connected to the switch SW7a. The third capacitor Cf2a is either between the first input terminal IN1 and the first output terminal OUT1 of the operational amplifier AMP or between the first output terminal OUT1 and the second output terminal OUT2 of the operational amplifier AMP by switching the switch SW7a. It is configured to be connectable to. Similarly, the fourth capacitor Cf2b has one terminal connected to the second output terminal OUT2 of the operational amplifier AMP and the other terminal connected to the switch SW7b. The fourth capacitor Cf2b is either between the second input terminal IN2 and the second output terminal OUT2 of the operational amplifier AMP or between the first output terminal OUT1 and the second output terminal OUT2 of the operational amplifier AMP by switching the switch SW7b. It is configured to be connectable to.

  In the unit conversion circuit 102, the first capacitor Cf1a is switched between the first input voltage terminal Tinp and the second input voltage terminal by switching the capacitor switches SW1a and SW2a as compared to the unit conversion circuit 2 of the first embodiment. During Tinm, in addition to being connected between the first input terminal IN1 and the first output terminal OUT1 of the operational amplifier AMP, it can be connected to either the first output terminal OUT1 or the second output terminal OUT2 of the operational amplifier AMP. Yes. Similarly, the second capacitor Cf1b is connected between the first input voltage terminal Tinp and the second input voltage terminal Tinm between the second input terminal IN2 and the second output terminal OUT2 of the operational amplifier AMP by switching the capacitor switches SW1b and SW2b. In addition, it is configured to be connectable between the first output terminal OUT1 and the second output terminal OUT2 of the operational amplifier AMP.

  FIG. 14 shows a timing chart of the unit conversion circuit 102. The unit conversion circuit 102 is synchronized with the clock CLK and performs a plurality of cycles with three periods as one cycle. As shown in FIG. 14, the unit conversion circuit 102 can distinguish between odd cycles and even cycles. The first capacitor Cf1a and the second capacitor Cf1b operate corresponding to odd cycles, and the third capacitor Cf2a and the fourth capacitor Cf2b operate corresponding to even cycles.

  First, the conduction state when the unit conversion circuit 102 is in the 0th period (see FIG. 14) will be described. As shown in FIG. 15, in the 0th period, the first capacitor Cf1a is connected between the first input voltage terminal Tinp and the second input voltage terminal Tinm, and the first input voltage Vinp is connected to the first capacitor Cf1a. A differential voltage of the second input voltage Vinm is applied, and the differential input signal is sampled. Similarly, in the 0th period, the second capacitor Cf1b is connected between the first input voltage terminal Tinp and the second input voltage terminal Tinm, and the first input voltage Vinp and the second input voltage Vinm are connected to the second capacitor Cf1b. Are applied, and the differential input signal is sampled. Further, in the 0th period, the first input voltage Vinp and the second input voltage Vinm are input to the sub A / D converter 5, and the sub A / D converter 5 generates the sub digital signal D [1: 0]. The DA converter 6a stores the sub-digital signal D [1: 0].

  Next, a conduction state when the unit conversion circuit 102 is in the initialization period (see FIG. 14) will be described. As shown in FIG. 16, in the initialization period, the first initialization switch 3a shorts between the first input terminal IN1 and the first output terminal OUT1 of the operational amplifier AMP, and the second initialization switch 3b is the operational amplifier. The second input terminal IN2 and the second output terminal OUT2 of the AMP are short-circuited. At this time, the first offset compensation switch S4a is connected to the second input terminal IN2 of the operational amplifier AMP, and the second offset compensation switch 4b is connected to the first input terminal IN1 of the operational amplifier AMP. As a result, the offset voltage is sampled in the first reference voltage capacitor Csa and the second reference voltage capacitor Csb.

  Next, a conduction state when the unit conversion circuit 102 is in the first input / output period (see FIG. 14) will be described. As shown in FIG. 17, in the first input / output period, the first capacitor Cf1a is connected between the first input terminal IN1 and the first output terminal OUT1 of the operational amplifier AMP, and the first input terminal IN1 and the first output terminal. A feedback connection is formed between OUT1. Similarly, in the first input / output period, the second capacitor Cf1b is connected between the second input terminal IN2 and the second output terminal OUT2 of the operational amplifier AMP, and is fed back between the second input terminal IN2 and the second output terminal OUT2. A connection is formed.

  The DA converter 6a generates reference voltages DAP and DAM based on the stored sub-digital signal D [1: 0], and applies the reference voltages DAP and DAM to the reference voltage capacitors Csa and Csb. . This conduction state is the same as in the first embodiment. Thus, in the first input / output period, the differential in which the influence of the offset voltage of the operational amplifier AMP is suppressed by the first capacitor Cf1a, the second capacitor Cf1b, the first reference voltage capacitor Csa, and the second reference voltage capacitor Csb. An output signal AOUT is output.

  Further, in the first input / output period, the third capacitor Cf2a is connected between the first output terminal OUT1 and the second output terminal OUT2 of the operational amplifier AMP, and the first output voltage Voutp and the second output are supplied to the third capacitor Cf2a. A differential voltage of the voltage Voutm is applied, and the differential output signal (which is also the differential input signal of the next cycle) is sampled. Similarly, in the first input / output period, the fourth capacitor Cf2b is connected between the first output terminal OUT1 and the second output terminal OUT2 of the operational amplifier AMP, and the first output voltage Voutp and the second output voltage are applied to the fourth capacitor Cf2b. A differential voltage of the output voltage Voutm is applied, and the differential output signal (which is also the differential input signal of the next cycle) is sampled.

  Further, in the first input / output period, the first output voltage Voutp and the second output voltage Voutm are input to the sub AD converter 5, and the sub AD converter 5 generates the sub digital signal D [1: 0]. The DA converter 6a stores the sub-digital signal D [1: 0].

  Next, the unit conversion circuit 102 enters an initialization period (see FIG. 14). The conduction state at this time is shown in FIG. 16 described above, and thereby, the offset voltage is sampled in the first reference voltage capacitor Csa and the second reference voltage capacitor Csb.

  Next, a conduction state when the unit conversion circuit 102 is in the second input / output period (see FIG. 14) will be described. As shown in FIG. 18, in the second input / output period, the third capacitor Cf2a is connected between the first input terminal IN1 and the first output terminal OUT1 of the operational amplifier AMP, and the first input terminal IN1 and the first output terminal. A feedback connection is formed between OUT1. Similarly, in the second input / output period, the fourth capacitor Cf2b is connected between the second input terminal IN2 and the second output terminal OUT2 of the operational amplifier AMP, and is fed back between the second input terminal IN2 and the second output terminal OUT2. A connection is formed.

  The DA converter 6a generates reference voltages DAP and DAM based on the stored sub-digital signal D [1: 0], and applies the reference voltages DAP and DAM to the reference voltage capacitors Csa and Csb. . This conduction state is the same as in the first embodiment. Thus, in the second input / output period, the differential in which the influence of the offset voltage of the operational amplifier AMP is suppressed by the third capacitor Cf2a, the fourth capacitor Cf2b, the first reference voltage capacitor Csa, and the second reference voltage capacitor Csb. An output signal AOUT is output.

  Further, in the second input / output period, the first capacitor Cf1a is connected between the first output terminal OUT1 and the second output terminal OUT2 of the operational amplifier AMP, and the first output voltage Voutp and the second output are supplied to the second capacitor Cf1a. A differential voltage of the voltage Voutm is applied, and the differential output signal (which is also the differential input signal of the next cycle) is sampled. Similarly, in the second input / output period, the second capacitor Cf1b is connected between the first output terminal OUT1 and the second output terminal OUT2 of the operational amplifier AMP, and the first output voltage Voutp and the second output voltage are applied to the second capacitor Cf1b. A differential voltage of the output voltage Voutm is applied, and the differential output signal (which is also the differential input signal of the next cycle) is sampled.

  Further, in the second input / output period, the first output voltage Voutp and the second output voltage Voutm are input to the sub AD converter 5, and the sub AD converter 5 generates the sub digital signal D [1: 0]. The DA converter 6a stores the sub-digital signal D [1: 0].

  As described above, in the unit conversion circuit 102 of the cyclic AD converter 100, the first capacitor Cf1a and the second capacitor Cf1b generate the differential input signal and generate the differential output signal corresponding to the odd cycle, and the even number Corresponding to the cycle, the third capacitor Cf2a and the fourth capacitor Cf2b generate the differential input signal and generate the differential output signal. The cyclic AD converter 100 repeats these cycles to convert the differential input signal AIN into a digital signal DOUT and output it.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

Tinp: first input voltage terminal Tinm: second input voltage terminal Toutp: first output voltage terminal Toutm: second output voltage terminal AMP: operational amplifier Cf1a: first capacitor Cf1b: second capacitor Csa: first reference voltage capacitor Csb : Second reference voltage capacitor 6a: DA converter

Claims (4)

A first input voltage terminal to which a first input voltage is input;
A second input voltage terminal to which a second input voltage is input;
An operational amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
A first capacitor having a first terminal and a second terminal;
A second capacitor having a third terminal and a fourth terminal;
A first reference voltage capacitor having a fifth terminal and a sixth terminal;
A second reference voltage capacitor having a seventh terminal and an eighth terminal;
In the first period,
The first input terminal is connected to the first output terminal;
The second input terminal is connected to the second output terminal;
The first terminal is connected to the first input voltage terminal;
The second terminal is connected to the second input voltage terminal;
The third terminal is connected to the second input voltage terminal;
The fourth terminal is connected to the first input voltage terminal;
The fifth terminal is connected to the second input terminal;
The sixth terminal is connected to the first input terminal;
The seventh terminal is connected to the first input terminal;
The eighth terminal is connected to the second input terminal;
In a second period different from the first period,
The first terminal is connected to the first output terminal;
The second terminal is connected to the first input terminal;
The third terminal is connected to the second output terminal;
The fourth terminal is connected to the second input terminal;
A first reference voltage is applied to the fifth terminal;
The sixth terminal is connected to the first input terminal;
A second reference voltage is applied to the seventh terminal;
The eighth terminal is a processing circuit connected to the second input terminal.   The processing circuit according to claim 1, further comprising a reference voltage generation unit that generates the first reference voltage and the second reference voltage. A sub AD converter;
A processing circuit according to claim 2,
The sub A / D converter compares the differential input signal and a plurality of threshold values, and generates a sub digital signal corresponding to the voltage range of the differential input signal,
The reference voltage generation unit including a DA converter generates the first reference voltage and the second reference voltage based on the sub-digital signal,
The differential input signal is an AD conversion circuit including the first input voltage and the second input voltage. An AD conversion circuit that generates a digital signal by correcting a plurality of sub-digital signals output from a unit conversion circuit,
The unit conversion circuit includes a sub AD converter and the processing circuit according to claim 2,
The sub A / D converter compares the differential input signal and a plurality of threshold values, and generates the sub digital signal according to a voltage range of the differential input signal,
The reference voltage generation unit including a DA converter generates the first reference voltage and the second reference voltage based on the sub-digital signal,
The differential input signal is an AD conversion circuit including the first input voltage and the second input voltage.

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