JP2013182930A - Laminated composite electronic component - Google Patents

Laminated composite electronic component Download PDF

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JP2013182930A
JP2013182930A JP2012044090A JP2012044090A JP2013182930A JP 2013182930 A JP2013182930 A JP 2013182930A JP 2012044090 A JP2012044090 A JP 2012044090A JP 2012044090 A JP2012044090 A JP 2012044090A JP 2013182930 A JP2013182930 A JP 2013182930A
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external terminal
laminated
internal electrode
electronic component
multilayer
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Kazuhiko Ito
和彦 伊藤
Takashi Kajino
隆 楫野
Teiichi Tanaka
禎一 田中
Masaki Tomita
将来 冨田
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TDK Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a laminated composite electronic component which can integrally laminate a ceramic PTC thermistor and a ceramic capacitor without requiring a complicated manufacturing process and can achieve both countermeasures against overcurrent and removal of a high-frequency noise for a power supply line simultaneously.SOLUTION: A laminated composite electronic component includes: an element body in which a PTC thermistor part that has a semiconductor ceramic layer mainly composed of BaTiOand an internal electrode layer alternately laminated and a capacitor part that has an insulator layer mainly composed of BaTiOand the internal electrode layer alternately laminated are mutually laminated; signal external terminal electrodes 8a and 8b which are electrically connected to one end of an internal electrode layer 3 of the PTC thermistor part 4 and provided on both end parts of the element body 11; and a ground external terminal electrode 8c which is electrically connected to one end of an internal electrode layer 6 of the capacitor part 7 and formed over the bottom surface and side surface of the laminated capacitor part in the element body 11.

Description

本発明は、電子機器等を過電流やノイズなどから防御する保護素子に関する。より詳細には、積層PTCサーミスタと積層コンデンサを一体化した積層型複合電子部品に関する。   The present invention relates to a protective element that protects an electronic device or the like from overcurrent, noise, and the like. More specifically, the present invention relates to a multilayer composite electronic component in which a multilayer PTC thermistor and a multilayer capacitor are integrated.

サーミスタとして、正の抵抗温度特性を有するPTC(Positive Temperature Coefficient)サーミスタが知られている。このPTCサーミスタは、温度の上昇に対して抵抗が増加する。このPTCサーミスタは、自己制御型発熱体、過電流保護素子、温度センサ等として利用されている。従来、このようなPTCサーミスタとして、主成分のチタン酸バリウム(BaTiO)に微量の希土類元素等を添加して導電性をもたせた半導体セラミック層と、半導体セラミック層を挟む一対の外部端子電極とを備えた単板型のPTCサーミスタが用いられてきた。 As a thermistor, a PTC (Positive Temperature Coefficient) thermistor having a positive resistance temperature characteristic is known. This PTC thermistor increases in resistance to an increase in temperature. This PTC thermistor is used as a self-control heating element, an overcurrent protection element, a temperature sensor, and the like. Conventionally, as such a PTC thermistor, a semiconductor ceramic layer which is made conductive by adding a trace amount of rare earth elements to barium titanate (BaTiO 3 ) as a main component, and a pair of external terminal electrodes sandwiching the semiconductor ceramic layer, A single plate type PTC thermistor provided with has been used.

近年、特に電源回路の過電流保護用途のPTCサーミスタに対しては、消費電力を抑制するため、非作動時の常温における抵抗(以下、便宜上「室温抵抗」という)が十分に小さいことが強く望まれている。PTCサーミスタの室温抵抗は電極面積に反比例するため、電極面積が大きいほど室温抵抗を低減することができる。   In recent years, especially for PTC thermistors used for overcurrent protection of power supply circuits, in order to reduce power consumption, it is strongly desired that the resistance at room temperature during non-operation (hereinafter referred to as “room temperature resistance” for convenience) be sufficiently small. It is rare. Since the room temperature resistance of the PTC thermistor is inversely proportional to the electrode area, the room temperature resistance can be reduced as the electrode area increases.

そこで、従来の単板型のPTCサーミスタに代わるものとして、複数の半導体セラミック層と複数の内部電極層とが交互に積層された積層型PTCサーミスタが提案されている。積層型PTCサーミスタでは、内部電極層を複数積層することによって電極面積を大幅に増やすことができるため、室温抵抗を低減させることができる。   In view of this, a multilayer PTC thermistor in which a plurality of semiconductor ceramic layers and a plurality of internal electrode layers are alternately stacked has been proposed as an alternative to the conventional single-plate PTC thermistor. In the stacked PTC thermistor, the electrode area can be greatly increased by stacking a plurality of internal electrode layers, so that the room temperature resistance can be reduced.

また電源回路においては、電源ラインやグランドに存在するインピーダンスによって、電源ラインでの電圧変動が大きくなると、駆動する回路の動作が不安定になったり、電源回路を経由して回路間の干渉が起こったりすることがある。よって通常は、電源ラインとグランドの間にデカップリングコンデンサが接続されている。   Also, in a power supply circuit, if the voltage fluctuation in the power supply line becomes large due to the impedance existing in the power supply line or ground, the operation of the driving circuit becomes unstable or interference occurs between the circuits via the power supply circuit. Sometimes. Therefore, usually, a decoupling capacitor is connected between the power supply line and the ground.

近年、携帯電話などの通信機器やパーソナルコンピュータなどの情報処理機器では、大量の情報を処理するために信号の高速化が進んでおり、使用されるICのクロック周波数も高周波化が進んでいる。
このため、高周波成分を多く含むノイズが発生しやすくなり、IC電源回路においては通常、デカップリング効果の高い積層セラミックコンデンサを使って高周波ノイズを吸収している。
In recent years, in communication devices such as mobile phones and information processing devices such as personal computers, the speed of signals has been increased in order to process a large amount of information, and the clock frequency of ICs used has been increased.
For this reason, noise containing a large amount of high frequency components is likely to occur, and in an IC power supply circuit, high frequency noise is usually absorbed using a multilayer ceramic capacitor having a high decoupling effect.

このように電源ラインには、過電流保護やノイズ対策など様々な対策が必要であり、各々の機能毎にそれぞれ個別の対策部品が必要となる。   As described above, the power supply line needs various countermeasures such as overcurrent protection and noise countermeasures, and requires separate countermeasure parts for each function.

下記特許文献1には、積層セラミックコンデンサの対向する一側面に設けられた一対の外部端子電極の一方にPTC特性を有する素子を電気的に直列接続して過電流・過熱保護機能を付与した積層セラミックコンデンサが開示されている。   In the following Patent Document 1, a multilayer ceramic capacitor is provided with an overcurrent / overheat protection function by electrically connecting elements having PTC characteristics in series to one of a pair of external terminal electrodes provided on opposite side surfaces of the multilayer ceramic capacitor. A ceramic capacitor is disclosed.

しかしながら、本発明者等が検討を行ったところ、従来の特許文献1に示すような積層型複合素子では、確かに短絡等による過電流時や過熱時にはPTC素子が発熱して抵抗が増大し、積層セラミックコンデンサを保護することができるが、積層セラミックコンデンサの外部端子の一方にPTC素子を直列に接続して金属端子で覆っているので、製造工程が複雑となり、コストがかかるという問題がある。また、この構造では、積層セラミックコンデンサとPTC素子を直列接続以外の構成に接続することは困難であるため、積層セラミックコンデンサで信号ラインあるいは電源ラインにおける高周波ノイズの吸収を行いつつ、PTC素子で過電流保護を行う、といったような回路構成は実現できない。   However, as a result of studies by the present inventors, in the multilayer composite element as shown in Patent Document 1 of the prior art, the PTC element surely generates heat during overcurrent or overheating due to a short circuit or the like, and the resistance increases. Although the multilayer ceramic capacitor can be protected, since the PTC element is connected in series to one of the external terminals of the multilayer ceramic capacitor and covered with the metal terminal, there is a problem that the manufacturing process becomes complicated and costs increase. In addition, with this structure, it is difficult to connect the multilayer ceramic capacitor and the PTC element to a configuration other than the series connection. Therefore, the multilayer ceramic capacitor absorbs high-frequency noise in the signal line or the power line, and the PTC element does A circuit configuration such as current protection cannot be realized.

特開平11−176695号公報Japanese Patent Laid-Open No. 11-176695

本発明は、このような実状に鑑みてなされ、その目的は、複雑かつ高コストな製造工程を必要とせずに積層PTCサーミスタと積層コンデンサを一体積層化し、電子機器等を過電流やノイズなどから防御する積層型複合電子部品を提供することを目的とする。   The present invention has been made in view of such a situation, and an object thereof is to integrally laminate a multilayer PTC thermistor and a multilayer capacitor without requiring a complicated and expensive manufacturing process, and to prevent electronic devices and the like from overcurrent and noise. An object of the present invention is to provide a laminated composite electronic component that protects.

上記目的を達成するために、本発明に係る積層型複合電子部品は、BaTiOを主成分とする半導体セラミック層と内部電極層とが交互に積層されている積層PTCサーミスタ部と、BaTiOを主成分とする絶縁体層と内部電極層とが交互に積層されている積層コンデンサ部とが積層された素子本体と、前記積層PTCサーミスタ部の内部電極層の一方が、素子本体の対向する端面に形成された外部端子電極の一方と電気的に接続され、前記積層PTCサーミスタ部の内部電極層の他方が、素子本体の前記対向する端面に形成された外部端子電極の他方と電気的に接続され、前記積層コンデンサ部の内部電極層の一方が前記素子本体の対向する端面に形成された外部電子電極のいずれか一方と電気的に接続され、前記積層コンデンサ部の内部電極層の他方が、前記素子本体の対向する端面と直交する方向の少なくとも底面に形成された外部端子電極と電気的に接続された構成であることを特徴とする積層型複合電子部品を提供する。 In order to achieve the above object, a multilayer composite electronic component according to the present invention includes a multilayer PTC thermistor portion in which a semiconductor ceramic layer mainly composed of BaTiO 3 and internal electrode layers are alternately laminated, and BaTiO 3 . One of the element main body in which the multilayer capacitor part in which the insulator layers as main components and the internal electrode layers are alternately laminated, and the internal electrode layer of the multilayer PTC thermistor part are opposite end faces of the element main body. And the other of the internal electrode layers of the laminated PTC thermistor portion is electrically connected to the other of the external terminal electrodes formed on the opposing end surface of the element body. One of the internal electrode layers of the multilayer capacitor portion is electrically connected to any one of the external electronic electrodes formed on the opposing end surfaces of the element body, and the multilayer capacitor A multilayer composite electronic component comprising: the other internal electrode layer electrically connected to an external terminal electrode formed on at least a bottom surface in a direction orthogonal to an opposing end surface of the element body. provide.

本発明に係る積層型複合電子部品は、前記積層コンデンサ部の内部電極層の他方が、前記素子本体の対向する端面に直交する方向の底面及び側面に跨るように形成された外部端子電極に電気的に接続されていても良い。   In the multilayer composite electronic component according to the present invention, the other of the internal electrode layers of the multilayer capacitor portion is electrically connected to the external terminal electrode formed so as to straddle the bottom surface and the side surface in the direction orthogonal to the opposing end surface of the element body. May be connected.

さらに、本発明に係る積層型複合電子部品は、前記素子本体の対向する端面に形成される外部端子電極が、信号用外部端子電極であって良い。   Furthermore, in the multilayer composite electronic component according to the present invention, the external terminal electrode formed on the opposing end surface of the element body may be a signal external terminal electrode.

さらに、本発明に係る積層型複合電子部品は、前記素子本体の対向する端面と直交する方向の少なくとも底面に形成される外部端子電極が、接地用外部端子電極であってよい。   Furthermore, in the multilayer composite electronic component according to the present invention, the external terminal electrode formed on at least the bottom surface in the direction orthogonal to the opposing end surface of the element body may be a grounding external terminal electrode.

なお、前記積層PTCサーミスタ部とグランド間の絶縁を確保するために、前記接地用外部端子電極は、前記半導体セラミック層の側面には接触しないように形成する必要がある。   In order to secure insulation between the laminated PTC thermistor portion and the ground, the grounding external terminal electrode needs to be formed so as not to contact the side surface of the semiconductor ceramic layer.

本発明に係る積層型複合電子部品を、前記の構造とすることで、積層PTCサーミスタと積層コンデンサを並設し、かつ電気的にはL字状に接続をし、電源ラインに対して、積層PTCサーミスタを直列に配置すると同時に、電源ラインとグランドの間に積層コンデンサを配置することができるので、電子機器等を過電流から防御しつつ、高周波ノイズを低減することができる。また、本発明に係る積層型複合電子部品は、三端子構造を有することで、異常時に過電流が素子に流れ込み、素子が発熱した場合の熱を効率良く実装基板に逃がすことができるので、熱暴走しにくくなり、結果として積層型複合電子部品の耐電圧が向上する。   The multilayer composite electronic component according to the present invention has the above-described structure, so that the multilayer PTC thermistor and the multilayer capacitor are juxtaposed and electrically connected in an L shape, and the multilayer is formed with respect to the power line. Since the PTC thermistor is arranged in series and the multilayer capacitor can be arranged between the power supply line and the ground, it is possible to reduce high frequency noise while protecting the electronic device and the like from overcurrent. In addition, since the multilayer composite electronic component according to the present invention has a three-terminal structure, an overcurrent flows into the element at the time of abnormality, and heat generated when the element generates heat can be efficiently released to the mounting board. As a result, the withstand voltage of the multilayer composite electronic component is improved.

本発明の一実施形態に係る積層型複合電子部品の説明図であり、(a)は、斜視図、(b)は、L1断面図、(c)は、W1断面図である。It is explanatory drawing of the multilayer composite electronic component which concerns on one Embodiment of this invention, (a) is a perspective view, (b) is L1 sectional drawing, (c) is W1 sectional drawing. 本発明の一実施形態に係る積層型複合電子部品の電気回路図である。1 is an electric circuit diagram of a multilayer composite electronic component according to an embodiment of the present invention. 本発明の一実施形態に係る積層型複合電子部品の積層PTCサーミスタ部の構造を示す分解斜視図である。It is a disassembled perspective view which shows the structure of the lamination | stacking PTC thermistor part of the lamination | stacking type | mold composite electronic component which concerns on one Embodiment of this invention. 本発明の一実施形態に係る積層型複合電子部品の積層コンデンサ部の構造を示す分解斜視図である。It is a disassembled perspective view which shows the structure of the multilayer capacitor part of the multilayer composite electronic component which concerns on one Embodiment of this invention. (A)は、本発明の一実施形態に係る積層型複合電子部品の表面側斜視図、(B)は(A)に示す積層型複合電子部品の背面(裏面)側斜視図である。(A) is the surface side perspective view of the multilayer composite electronic component which concerns on one Embodiment of this invention, (B) is the back surface (back surface) side perspective view of the multilayer composite electronic component shown to (A). 本発明の比較例に係る単体の積層PTCサーミスタの説明図であり、(a)は、斜視図、(b)は、L2断面図、(c)は、W2断面図である。It is explanatory drawing of the single laminated PTC thermistor which concerns on the comparative example of this invention, (a) is a perspective view, (b) is L2 sectional drawing, (c) is W2 sectional drawing. (A)は、本発明の一実施形態に係る積層型複合電子部品を電源ラインに接続したときの電圧波形、(B)は単体のPTCサーミスタを電源ラインに接続したときの電圧波形である。(A) is a voltage waveform when the multilayer composite electronic component according to one embodiment of the present invention is connected to the power supply line, and (B) is a voltage waveform when a single PTC thermistor is connected to the power supply line.

以下、本発明を、図面に示す実施形態に基づき説明する。   Hereinafter, the present invention will be described based on embodiments shown in the drawings.

図1に示すように、本発明の一実施形態に係る積層型複合電子部品1は、BaTiOを主成分とする半導体セラミック層2と第1の内部電極層3(図1(b)、図1(c))とが交互に積層されている積層PTCサーミスタ部4(図1(b)、図1(c))と、BaTiOを主成分とし、前記半導体セラミック層と同等の空隙率を有する絶縁体層5(図1(b)、図1(c))と第2の内部電極層6(図1(b)、図1(c))とが交互に積層されている積層コンデンサ部7(図1(b)、図1(c))とが互いに積層された素子本体11と、該素子本体11の両端面部に設けられた一対の信号用外部端子電極8a、8b(図1(a)、図1(b))と、前記積層コンデンサ部7の底面と側面にわたって形成されている接地用外部端子電極8c(図1(a)、図1(b))を有する構造である。図1(b)は、積層型複合電子部品の長手方向の断面図であり、図1(c)は積層型複合電子部品の短手方向の断面図である。
また、積層PTCサーミスタ部4と積層コンデンサ部7は、図2に示すような電気回路を成しており、図5(A)および図5(B)に示すような信号用外部端子電極8a、8b、および接地用外部端子電極8cから成る三端子構造を有する。
As shown in FIG. 1, a multilayer composite electronic component 1 according to one embodiment of the present invention includes a semiconductor ceramic layer 2 mainly composed of BaTiO 3 and a first internal electrode layer 3 (FIG. 1B, FIG. 1 (c)) alternately laminated PTC thermistor portions 4 (FIG. 1 (b), FIG. 1 (c)), and BaTiO 3 as a main component, and a porosity equivalent to that of the semiconductor ceramic layer. Multilayer capacitor portion in which insulator layers 5 (FIGS. 1B and 1C) and second internal electrode layers 6 (FIGS. 1B and 1C) are alternately stacked 7 (FIG. 1 (b), FIG. 1 (c)) and a pair of signal external terminal electrodes 8a, 8b provided on both end surfaces of the element body 11 (FIG. 1 (1)). a), FIG. 1 (b)), and an external terminal for grounding formed over the bottom surface and side surface of the multilayer capacitor section 7 Electrode 8c (FIG. 1 (a), to FIG. 1 (b)) is a structure with. FIG. 1B is a cross-sectional view in the longitudinal direction of the multilayer composite electronic component, and FIG. 1C is a cross-sectional view in the short direction of the multilayer composite electronic component.
The multilayer PTC thermistor section 4 and the multilayer capacitor section 7 form an electric circuit as shown in FIG. 2, and the signal external terminal electrodes 8a as shown in FIGS. 5 (A) and 5 (B), 8b, and a three-terminal structure including an external terminal electrode 8c for grounding.

半導体セラミック層2および絶縁体層5は、BaTiOを主成分とする材料で構成される。積層PTCサーミスタ部4の第1の内部電極層3および積層コンデンサ部7の第2の内部電極層6は、たとえばニッケル、パラジウム、これらの金属の少なくとも一種を含む合金などで構成される。 The semiconductor ceramic layer 2 and the insulator layer 5 are made of a material mainly composed of BaTiO 3 . The first internal electrode layer 3 of the multilayer PTC thermistor portion 4 and the second internal electrode layer 6 of the multilayer capacitor portion 7 are made of, for example, nickel, palladium, an alloy containing at least one of these metals, or the like.

半導体セラミック層2の厚みは、特に限定されないが、例えば5〜200μm程度、第1の内部電極層3の厚みは、特に限定されないが、例えば1〜5μm程度とすればよい。   Although the thickness of the semiconductor ceramic layer 2 is not specifically limited, For example, about 5-200 micrometers and the thickness of the 1st internal electrode layer 3 are not specifically limited, For example, what is necessary is just about 1-5 micrometers.

また絶縁体層5の厚みは、特に限定されないが、例えば5〜200μm程度、第2の内部電極層6の厚みは、特に限定されないが、例えば1〜5μm程度である。   The thickness of the insulator layer 5 is not particularly limited, but is about 5 to 200 μm, for example, and the thickness of the second internal electrode layer 6 is not particularly limited, but is about 1 to 5 μm, for example.

素子本体11の相互に向き合う端面には、それぞれ信号用外部端子電極8aおよび8bが形成してあり、積層PTCサーミスタ部において、それぞれ交互に引き出される第1の内部電極層3がそれぞれの信号用外部端子電極8a、8bに接続される。さらに前記信号用外部端子電極8a、8bのいずれか一方と、積層コンデンサ部7の第2の内部電極6のいずれか一方とが接続してある。一方、接地用外部端子電極8cは、素子本体11の積層コンデンサ部7の底面と側面に跨り、積層コンデンサ部7の第2の内部電極6の他方に接続してある。信号用外部端子電極8a、8bおよび接地用外部端子電極8cは、たとえばAg、Pd、Cu、Ni、Zn、Al、Sn、これらの金属の少なくとも一種を含む合金などで構成され、その厚みは、特に限定されないが、例えば5〜30μm程度である。信号用外部端子電極8a、8bおよび接地用外部端子電極8cは、単層でも良いが、複数の層の積層膜であっても良い。   External end electrodes 8a and 8b for signals are formed on the end faces of the element body 11 that face each other. In the laminated PTC thermistor section, the first internal electrode layers 3 that are alternately drawn out are respectively connected to the signal external terminals. It is connected to the terminal electrodes 8a and 8b. Furthermore, either one of the signal external terminal electrodes 8 a and 8 b is connected to one of the second internal electrodes 6 of the multilayer capacitor unit 7. On the other hand, the grounding external terminal electrode 8 c extends across the bottom surface and the side surface of the multilayer capacitor portion 7 of the element body 11 and is connected to the other of the second internal electrodes 6 of the multilayer capacitor portion 7. The signal external terminal electrodes 8a and 8b and the ground external terminal electrode 8c are made of, for example, Ag, Pd, Cu, Ni, Zn, Al, Sn, an alloy containing at least one of these metals, and the thickness thereof. Although it does not specifically limit, For example, it is about 5-30 micrometers. The signal external terminal electrodes 8a and 8b and the ground external terminal electrode 8c may be a single layer or may be a laminated film of a plurality of layers.

次に、積層型複合電子部品1の製造方法について説明する。
まず、図1に示す半導体セラミック層2の原料を含む半導体セラミック層形成用スラリーを準備する。次に、半導体セラミック層形成用スラリーをペット(PET)フィルム上にドクターブレード法などで塗布、乾燥してグリーンシートを作製する。
Next, a method for manufacturing the multilayer composite electronic component 1 will be described.
First, the slurry for semiconductor ceramic layer formation containing the raw material of the semiconductor ceramic layer 2 shown in FIG. 1 is prepared. Next, a slurry for forming a semiconductor ceramic layer is applied onto a PET (PET) film by a doctor blade method or the like and dried to produce a green sheet.

同様にして、図1に示す絶縁体層5の原料を含む絶縁体層形成用スラリーを準備する。次に、絶縁体層形成用スラリーをペットフィルムの上にドクターブレード法などで塗布、乾燥してグリーンシートを作製する。   Similarly, a slurry for forming an insulator layer containing a raw material for the insulator layer 5 shown in FIG. 1 is prepared. Next, the insulator layer forming slurry is applied onto a pet film by a doctor blade method or the like and dried to prepare a green sheet.

この半導体セラミック層グリーンシートの表面に、図1に示す積層PTCサーミスタ部4の第1の内部電極層3を、および絶縁体層グリーンシートの表面に、図1に示す積層コンデンサ部7の第2の内部電極層6を形成するための内部電極用ペーストをスクリーン印刷などで印刷する。次に、図3に示すように、第1の内部電極用ペーストが印刷された半導体セラミック層グリーンシートを必要枚数で積層し、さらにこの積層体の上面,下面に内部電極用ペーストが印刷されていない半導体セラミック層グリーンシートを複数枚重ねた第1のカバーシート9を重ねて、積層PTCサーミスタ部4を形成する。   The first internal electrode layer 3 of the multilayer PTC thermistor section 4 shown in FIG. 1 is formed on the surface of the semiconductor ceramic layer green sheet, and the second of the multilayer capacitor section 7 shown in FIG. The internal electrode paste for forming the internal electrode layer 6 is printed by screen printing or the like. Next, as shown in FIG. 3, the required number of semiconductor ceramic layer green sheets printed with the first internal electrode paste are laminated, and the internal electrode paste is printed on the upper and lower surfaces of the laminate. The laminated PTC thermistor portion 4 is formed by stacking the first cover sheets 9 each including a plurality of non-conducting ceramic ceramic green sheets.

同様に、図4に示すように、第2の内部電極用ペーストが印刷された絶縁体層グリーンシートを必要枚数で積層し、さらにこの積層体の上面,下面に内部電極用ペーストが印刷されていない絶縁体層グリーンシートを複数枚重ねた第2のカバーシート10を重ねて、積層コンデンサ部7を形成する。   Similarly, as shown in FIG. 4, the required number of insulating layer green sheets printed with the second internal electrode paste are laminated, and the internal electrode paste is printed on the upper and lower surfaces of the laminate. The multilayer capacitor portion 7 is formed by stacking the second cover sheets 10 each including a plurality of non-insulator layer green sheets.

次いで、積層PTCサーミスタ部4と積層コンデンサ部7とを積層し、一体化した積層体を、プレス機で積層方向に加圧、圧着して圧着体を得る。この圧着体をカッターなどで切断し、図1に示す素子本体11に対応するサイズの積層チップを得る。   Next, the laminated PTC thermistor part 4 and the laminated capacitor part 7 are laminated and the integrated laminated body is pressed and pressure-bonded in the laminating direction with a press to obtain a pressure-bonded body. The pressure-bonded body is cut with a cutter or the like to obtain a laminated chip having a size corresponding to the element body 11 shown in FIG.

次に、積層チップを、大気中、250〜400℃で1〜10時間加熱保持してバインダを除去した後、H/N雰囲気中、1150〜1250℃で0.5〜4時間、積層チップを焼結し、素子本体(焼結体)11を得る。 Next, the laminated chip was heated and held in the atmosphere at 250 to 400 ° C. for 1 to 10 hours to remove the binder, and then laminated in an H 2 / N 2 atmosphere at 1150 to 1250 ° C. for 0.5 to 4 hours. The chip is sintered to obtain an element body (sintered body) 11.

続いて得られた素子本体11を、大気中で、500〜800℃で0.5〜6時間加熱保持することにより、再酸化処理を行う。再酸化処理により、半導体セラミック層2のPTC特性を発現させる。   Subsequently, the element body 11 obtained is re-oxidized by heating and holding at 500 to 800 ° C. for 0.5 to 6 hours in the air. The PTC characteristic of the semiconductor ceramic layer 2 is expressed by the reoxidation treatment.


続いて得られた素子本体11の両端面に、信号用外部端子電極8aおよび8bを形成するために、外部端子電極用ペーストをディップにより形成する。また接地用外部端子電極8cを形成するためにコンデンサ部の底面と側面に外部端子電極用ペーストをスクリーン印刷により形成する。

Subsequently, in order to form the signal external terminal electrodes 8a and 8b on both end faces of the obtained element body 11, an external terminal electrode paste is formed by dipping. Further, in order to form the grounding external terminal electrode 8c, an external terminal electrode paste is formed by screen printing on the bottom and side surfaces of the capacitor portion.

続いて外部端子電極用ペーストが形成された素子本体11を、大気中500〜700℃で焼き付けた後、はんだめっきを行い、図1に示すような積層型複合電子部品1が得られる。   Subsequently, the element body 11 on which the external terminal electrode paste is formed is baked at 500 to 700 ° C. in the atmosphere, and then solder plating is performed to obtain the multilayer composite electronic component 1 as shown in FIG.

なお、信号用外部端子電極8a、8bおよび接地用外部端子電極8cは、スパッタリングなどの成膜法により形成しても良い。   The signal external terminal electrodes 8a and 8b and the ground external terminal electrode 8c may be formed by a film forming method such as sputtering.

本実施形態の積層型複合電子部品1は、複雑かつ高コストな製造工程を必要とせずに積層PTCサーミスタと積層コンデンサを一体積層化することができる。また本積層型複合電子部品1は、積層PTCサーミスタと積層コンデンサを並設しかつ電気的にはL字状に接続をし、三端子構造とすることで、電源ラインに対して、積層PTCサーミスタを直列に配置すると同時に電源ラインとグランドの間に積層コンデンサを配置することができるので、電子機器等を過電流から防御しつつ、高周波ノイズを低減することができ、結果として電気回路の部品点数の削減および省スペース化、低コスト化が図られる。更に、本積層型複合電子部品に過電流が流れ込み、積層PTCサーミスタ素子が発熱した場合、熱を効率良く実装基板に逃がすことができるので、単体のPTCサーミスタを使う場合と比較して、より熱暴走しにくくなり、結果として積層型複合電子部品の耐電圧が向上する。   The multilayer composite electronic component 1 of the present embodiment can integrally laminate a multilayer PTC thermistor and a multilayer capacitor without requiring a complicated and expensive manufacturing process. In addition, the multilayer composite electronic component 1 includes a multilayer PTC thermistor and a multilayer capacitor connected in parallel and electrically connected in an L shape to form a three-terminal structure. Since a multilayer capacitor can be placed between the power supply line and ground at the same time, high frequency noise can be reduced while protecting electronic equipment from overcurrent, resulting in the number of electrical circuit components. Reduction, space saving, and cost reduction. Furthermore, when an overcurrent flows into this multilayer composite electronic component and the multilayer PTC thermistor element generates heat, the heat can be efficiently released to the mounting board, so that it is more heated than when using a single PTC thermistor. As a result, the withstand voltage of the multilayer composite electronic component is improved.

以下、実施例及び比較例に基づき本発明をさらに具体的に説明するが、本発明は以下の実施例に何ら限定されるものではない。   EXAMPLES Hereinafter, although this invention is demonstrated more concretely based on an Example and a comparative example, this invention is not limited to a following example at all.

積層PTCサーミスタ部において、焼結して得られるチタン酸バリウム系化合物が下記式(A)の組成になるように、BaCO、TiO、Gd及びSiOをそれぞれ秤量した後、純水ならびに粉砕用ボールとともにナイロン製ポット内に入れて6時間混合し、乾燥させて混合粉末を得た。
(Ba0.997Gd0.0031.02TiO+0.05SiO・・・(A)
In the laminated PTC thermistor part, BaCO 3 , TiO 2 , Gd 2 O 3 and SiO 2 were weighed so that the barium titanate compound obtained by sintering had the composition of the following formula (A), The mixture was placed in a nylon pot together with water and grinding balls, mixed for 6 hours, and dried to obtain a mixed powder.
(Ba 0.997 Gd 0.003 ) 1.02 TiO 3 + 0.05SiO 2 (A)

得られた混合粉末を仮成形し、これを1150℃の大気中に4時間保持して仮焼して、仮焼体を得た。次いで、この仮焼体を解砕して得た仮焼粉末を溶剤ならびに粉砕用ボールとともにナイロン製ポットに入れ、これにバインダ及び可塑剤を添加してボールミルにて20時間混合し、半導体セラミック層形成用スラリーを得た。   The obtained mixed powder was temporarily molded, and this was held in the atmosphere at 1150 ° C. for 4 hours and calcined to obtain a calcined body. Next, the calcined powder obtained by pulverizing the calcined body is put into a nylon pot together with a solvent and a grinding ball, and a binder and a plasticizer are added thereto and mixed in a ball mill for 20 hours. A forming slurry was obtained.

得られた半導体セラミック層形成用スラリーをペットフィルムの上にドクターブレード法で塗布、乾燥してグリーンシートを作製した。このグリーンシートの表面に第1の内部電極層用Niペーストをスクリーン印刷で印刷してNi内部電極を形成した。   The obtained slurry for forming a semiconductor ceramic layer was applied onto a pet film by a doctor blade method and dried to prepare a green sheet. A Ni internal electrode was formed by printing the first internal electrode layer Ni paste on the surface of the green sheet by screen printing.

一方、積層コンデンサ部において、焼結して得られるチタン酸バリウム系化合物が下記式(B)の組成になるように、BaCO、TiO及びSiOをそれぞれ秤量した後、純水ならびに粉砕用ボールとともにナイロン製ポット内に入れて6時間混合し、乾燥させて混合粉末を得た。
Ba1.02TiO+0.05SiO・・・(B)
On the other hand, in the multilayer capacitor part, BaCO 3 , TiO 2 and SiO 2 were weighed so that the barium titanate compound obtained by sintering had the composition of the following formula (B), and then purified water and pulverized The mixture was put in a nylon pot together with the balls, mixed for 6 hours, and dried to obtain a mixed powder.
Ba 1.02 TiO 3 + 0.05SiO 2 (B)

得られた混合粉末を仮成形し、これを1150℃の大気中に4時間保持して仮焼して、仮焼体を得た。次いで、この仮焼体を解砕して得た仮焼粉末を溶剤ならびに粉砕用ボールとともにナイロン製ポットに入れ、これにバインダ及び可塑剤を添加してボールミルにて20時間混合し、絶縁体層形成用スラリーを得た。   The obtained mixed powder was temporarily molded, and this was held in the atmosphere at 1150 ° C. for 4 hours and calcined to obtain a calcined body. Next, the calcined powder obtained by pulverizing this calcined body is put into a nylon pot together with a solvent and a grinding ball, and a binder and a plasticizer are added thereto and mixed in a ball mill for 20 hours. A forming slurry was obtained.

得られた絶縁体層形成用スラリーをペットフィルムの上にドクターブレード法で塗布、乾燥してグリーンシートを作製した。このグリーンシートの表面に第2の内部電極用Niペーストをスクリーン印刷で印刷してNi内部電極を形成した。   The obtained insulator layer forming slurry was applied onto a pet film by a doctor blade method and dried to prepare a green sheet. A second internal electrode Ni paste was printed on the surface of the green sheet by screen printing to form a Ni internal electrode.

積層PTCサーミスタ部においては、図3に示すように、交互に積層される第1の内部電極層の一端面が半導体セラミック層の左端部、他方が右端部にと、交互に露出するようグリーンシートを積層した。一方、積層コンデンサ部においては、図4に示すように、第2の内部電極層の一端面が絶縁体層の左端部、他方がこれと直交する側面部にと、交互に露出するようグリーンシートを積層した。更に積層PTCサーミスタ部と積層コンデンサ部を積層し、これをプレスで積層方向に加圧、圧着した。圧着体をカッターで切断し、2.0mm×1.2mm×1.2mmの複合積層チップを得た。   In the laminated PTC thermistor portion, as shown in FIG. 3, the green sheets are alternately exposed such that one end face of the alternately laminated first internal electrode layers is exposed at the left end portion of the semiconductor ceramic layer and the other is at the right end portion. Were laminated. On the other hand, in the multilayer capacitor portion, as shown in FIG. 4, one end surface of the second internal electrode layer is alternately exposed to the left end portion of the insulator layer, and the other is exposed to the side surface portion orthogonal thereto. Were laminated. Furthermore, the laminated PTC thermistor part and the laminated capacitor part were laminated, and this was pressed and pressure-bonded in the laminating direction with a press. The pressure-bonded body was cut with a cutter to obtain a 2.0 mm × 1.2 mm × 1.2 mm composite laminated chip.

積層体を大気中、300℃で8時間加熱保持してバインダを除去した後、H/N雰囲気中、1200℃で2時間、積層体を焼結し、素子本体(焼結体)を得た。続いて得られた素子本体を大気中、700℃で2時間加熱保持することにより、再酸化処理を行った。 The laminated body was heated and held at 300 ° C. for 8 hours in the air to remove the binder, and then the laminated body was sintered at 1200 ° C. for 2 hours in an H 2 / N 2 atmosphere to obtain the element body (sintered body). Obtained. Subsequently, the obtained device main body was heated and maintained at 700 ° C. for 2 hours in the atmosphere to perform reoxidation treatment.

続いて、素子本体の両端面およびコンデンサ部の底面と前記両端面と直交する側面に跨ってAgペーストを塗布した後、大気中600℃で焼き付けて外部端子電極(信号用外部端子電極及び接地用外部端子電極)を形成した。このようにして得られた図1に示す構成の積層型複合電子部品1について、25℃における抵抗値(R25℃、単位:Ω)、及び200℃における抵抗値(R200℃、単位:Ω)、をそれぞれデジタルマルチメータにて測定した。さらに、25℃における抵抗値(R25℃)、200℃における抵抗値(R200℃)の各測定値から、PTCジャンプ{[log10(R200℃/R25℃)]、単位:桁}を求めた。また、プリント基板上にはんだ付けした積層型複合電子部品1を25℃の恒温槽内に入れ、両端面の信号用外部端子電極間に直流電源を接続して0Vより徐々に印加電圧を上昇させ、積層型複合電子部品1が破壊するまで昇圧し、破壊直前の電圧を耐電圧として求めた。なお、測定に用いたサンプル数はそれぞれ20個とし、表1には測定結果の平均値について示す。 Subsequently, an Ag paste is applied across the both end faces of the element body, the bottom face of the capacitor portion, and the side face perpendicular to the both end faces, and then baked at 600 ° C. in the atmosphere to external terminal electrodes (signal external terminal electrodes and grounding terminals). External terminal electrode) was formed. About the multilayer composite electronic component 1 having the structure shown in FIG. 1 thus obtained, a resistance value at 25 ° C. (R25 ° C., unit: Ω) and a resistance value at 200 ° C. (R200 ° C., unit: Ω) Each was measured with a digital multimeter. Furthermore, PTC jump {[log 10 (R200 ° C / R25 ° C)], unit: digit} was determined from the measured values of the resistance value at 25 ° C (R25 ° C) and the resistance value at 200 ° C (R200 ° C). Also, the multilayer composite electronic component 1 soldered on the printed circuit board is placed in a thermostatic chamber at 25 ° C., a DC power supply is connected between the signal external terminal electrodes on both end faces, and the applied voltage is gradually increased from 0V. The voltage was increased until the multilayer composite electronic component 1 was destroyed, and the voltage immediately before the destruction was determined as the withstand voltage. In addition, the number of samples used for the measurement is 20 each, and Table 1 shows an average value of the measurement results.

比較例
実施例に示した方法にて、図5に示すように、積層PTCサーミスタを単体で作製し、同様の評価を行った。外部端子は、両端面の信号用外部電端子電極のみの二端子構造である。ここで、図5(a)は単体の積層PTCサーミスタ斜視図、図5(b)は単体の積層PTCサーミスタ長手方向断面図、図5(c)は単体の積層PTCサーミスタ短手方向断面図である。

Figure 2013182930
By the method shown in the comparative example, a laminated PTC thermistor was produced by itself as shown in FIG. 5, and the same evaluation was performed. The external terminal has a two-terminal structure having only signal external electric terminal electrodes on both end faces. 5A is a perspective view of a single laminated PTC thermistor, FIG. 5B is a longitudinal sectional view of the single laminated PTC thermistor, and FIG. 5C is a short sectional view of the single laminated PTC thermistor. is there.
Figure 2013182930

表1に示す測定結果から明らかなように、両者のR25℃とPTCジャンプは、いずれも同じ値であるにもかかわらず、実施例に示す積層型複合電子部品のほうが、比較例に示す単体の積層PTCサーミスタよりも耐電圧が高かった。これは、積層型複合電子部品のほうが、電圧印加により発生したジュール熱を効率良く実装基板に逃がすことができ、熱暴走に至る電圧を高くすることができたためであると推測される。   As is clear from the measurement results shown in Table 1, the R25 ° C. and the PTC jump of both are the same value, but the multilayer composite electronic component shown in the example is more single unit shown in the comparative example. The withstand voltage was higher than that of the laminated PTC thermistor. This is presumably because the laminated composite electronic component was able to efficiently release Joule heat generated by voltage application to the mounting substrate and to increase the voltage leading to thermal runaway.

また、実施例に示す積層型複合電子部品と、比較例に示す単体の積層PTCサーミスタを電源ラインに接続して通電し、電気信号をオシロスコープにて観察したところ、図7に示すように、積層型複合電子部品の信号波形は、単体のPTCサーミスタを電源ラインに接続した場合と比較して、スパイクノイズが低減されていることがわかる。   Further, when the laminated composite electronic component shown in the example and the single laminated PTC thermistor shown in the comparative example were connected to the power supply line and energized and the electric signal was observed with an oscilloscope, the laminated composite electronic component shown in FIG. The signal waveform of the type composite electronic component shows that the spike noise is reduced as compared with the case where a single PTC thermistor is connected to the power supply line.

1 積層型複合電子部品
2 半導体セラミック層
3 第1の内部電極
4 積層PTCサーミスタ部
5 絶縁体層
6 第2の内部電極
7 積層コンデンサ部
8a,8b 信号用外部端子電極
8c 接地用外部端子電極
9 第1のカバーシート
10 第2のカバーシート
11 素子本体
12 単体の積層PTCサーミスタ
DESCRIPTION OF SYMBOLS 1 Laminated composite electronic component 2 Semiconductor ceramic layer 3 1st internal electrode 4 Laminated PTC thermistor part 5 Insulator layer 6 2nd internal electrode 7 Laminated capacitor part 8a, 8b Signal external terminal electrode 8c Grounding external terminal electrode 9 First cover sheet 10 Second cover sheet 11 Element body 12 Single layered PTC thermistor

Claims (4)

BaTiOを主成分とする半導体セラミック層と内部電極層とが交互に積層されている積層PTCサーミスタ部と、BaTiOを主成分とする絶縁体層と内部電極層とが交互に積層されている積層コンデンサ部とが積層された素子本体と、前記積層PTCサーミスタ部の内部電極層の一方が、素子本体の対向する端面に形成された外部端子電極の一方と電気的に接続され、前記積層PTCサーミスタ部の内部電極層の他方が、素子本体の前記対向する端面に形成された外部端子電極の他方と電気的に接続され、前記積層コンデンサ部の内部電極層の一方が前記素子本体の対向する端面に形成された外部端子電極のいずれか一方と電気的に接続され、前記積層コンデンサ部の内部電極層の他方が、前記素子本体の対向する端面と直交する方向の少なくとも底面に形成された外部端子電極と電気的に接続された構成であることを特徴とする積層型複合電子部品。 A laminated PTC thermistor portion in which semiconductor ceramic layers mainly composed of BaTiO 3 and internal electrode layers are alternately laminated, and an insulator layer and internal electrode layers mainly composed of BaTiO 3 are alternately laminated. One of the element body in which the multilayer capacitor part is laminated and one of the internal electrode layers of the multilayer PTC thermistor part is electrically connected to one of the external terminal electrodes formed on the opposing end surfaces of the element body, and the laminated PTC The other of the internal electrode layers of the thermistor part is electrically connected to the other of the external terminal electrodes formed on the opposing end face of the element body, and one of the internal electrode layers of the multilayer capacitor part faces the element body. One of the external terminal electrodes formed on the end face is electrically connected, and the other of the internal electrode layers of the multilayer capacitor section is orthogonal to the opposing end face of the element body At least the multilayer composite electronic component, which is a bottom surface formed external terminal electrodes electrically connected to each of the direction. 前記積層コンデンサ部の内部電極層の他方が、前記素子本体の対向する端面に直交する方向の底面及び側面に跨るように形成された外部端子電極に電気的に接続されていることを特徴とする、請求項1に記載の積層型複合電子部品。   The other of the internal electrode layers of the multilayer capacitor portion is electrically connected to an external terminal electrode formed so as to straddle a bottom surface and a side surface in a direction orthogonal to the opposing end surface of the element body. The multilayer composite electronic component according to claim 1. 前記素子本体の対向する端面に形成される外部端子電極が、信号用外部端子電極であることを特徴とする、請求項1に記載の積層型複合電子部品。   2. The multilayer composite electronic component according to claim 1, wherein the external terminal electrodes formed on opposing end faces of the element body are signal external terminal electrodes. 3. 前記素子本体の対向する端面と直交する方向の少なくとも底面に形成される外部端子電極が、接地用外部端子電極であることを特徴とする、請求項1に記載の積層型複合電子部品。   2. The multilayer composite electronic component according to claim 1, wherein the external terminal electrode formed on at least the bottom surface in a direction orthogonal to the opposing end surface of the element body is a grounding external terminal electrode.
JP2012044090A 2012-02-29 2012-02-29 Laminated composite electronic component Pending JP2013182930A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107068404A (en) * 2015-10-08 2017-08-18 Tdk株式会社 Electronic unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107068404A (en) * 2015-10-08 2017-08-18 Tdk株式会社 Electronic unit
CN107068404B (en) * 2015-10-08 2019-03-19 Tdk株式会社 Electronic component

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