JP2013175908A - Gate monitor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a through current from appearing and both MOS transistors from turning off without using delay circuits.SOLUTION: A PMOS transistor M3 is disposed to configure a current mirror circuit together with a PMOS transistor M1, and a size ratio is n:1. The PMOS transistor M3 and a PMOS transistor M4 are connected to a current source Cs1. A PMOS transistor M5 is disposed to configure a current mirror circuit together with the PMOS transistor M4 and is connected to a gate terminal of an NMOS transistor M2. An NMOS transistor M3' is disposed to configure a current mirror circuit together with the NMOS transistor M2, and a size ratio is n:1. The NMOS transistor M3' and an NMOS transistor M4' are connected to a current source Cs2. An NMOS transistor M5' is disposed to configure a current mirror circuit together with the NMOS transistor M4' and is connected to a gate terminal of the PMOS transistor M1.

Description

  The present invention relates to a technique of a gate monitor circuit in a class D amplifier circuit or the like.

The class D amplifier circuit converts an input signal into a pulse width modulation signal having a constant amplitude and amplifies the power, and is used for power amplification of an audio signal, for example. Since the class D amplifier circuit operates with two values, the loss of the transistor can be significantly reduced. Furthermore, there is an advantage that the efficiency is higher than that of the linear amplifier regardless of the amplitude of the input signal.
This type of class D amplifier circuit includes an integration circuit that integrates an input signal, a comparison circuit that compares the output signal of the integration circuit with a predetermined triangular wave signal, and a pulse width modulation signal that is pulse width modulated based on the comparison circuit. A pulse width amplifier for outputting, and an output signal of the pulse width amplifier is fed back to the input side of the integrating circuit. The output signal of the pulse width amplifier becomes an analog signal for driving a load such as a speaker via the output buffer circuit.

The output buffer circuit includes a PMOS transistor and an NMOS transistor, and it is necessary to prevent both the PMOS transistor and the NMOS transistor from being turned on and causing a through current to flow.
Therefore, conventionally, a delay circuit is used to cause a deviation between the input signal to the PMOS transistor and the input signal to the NMOS transistor (see, for example, Patent Document 1).

FIG. 2 is a diagram showing an example of such a conventional gate monitor circuit. In FIG. 2, the output terminal of the NAND circuit 52 is connected to the gate terminal PG of the PMOS transistor 50. An input terminal IN and an output terminal of the delay circuit 56 are connected to the input terminal of the NAND circuit 52. The gate terminal NG of the NMOS transistor 51 is connected to the input terminal of the delay circuit 56 via the NOT circuit 57.
On the other hand, the output terminal of the NOR circuit 53 is connected to the gate terminal NG of the NMOS transistor 51. An input terminal IN and an output terminal of the delay circuit 54 are connected to the input terminal of the NOR circuit 53. The gate terminal PG of the PMOS transistor 50 is connected to the input terminal of the delay circuit 54 via the NOT circuit 55.

FIG. 3 is a timing chart showing the operation of the conventional gate monitor circuit of FIG. As shown in FIG. 3, when the signal Vin rising from L to H is input to the input terminal IN, the signal Vin rising from L to H is also input to the input terminal of the NAND circuit 52. The other input terminal 52 receives the signal 56 a delayed by the delay circuit 56 for the period Td.
Therefore, after the signal Vin rising from L to H is input to the input terminal IN, the H level signal is input to both input terminals of the NAND circuit 52 after the period Td. As a result, the output of the NAND circuit 52 becomes a signal falling from H to L, and the PMOS transistor 50 is turned on. At this time, since an H level signal is inputted to the input terminal of the NOR circuit 53 connected to the input terminal IN, the output of the NOR circuit 53 becomes L level, and the NMOS transistor 51 is turned off. ing.

Next, when the signal Vin falling from H to L is input to the input terminal IN, the output of the NAND circuit 52 becomes H level and the gate terminal PG of the PMOS transistor 50 becomes H level. Turns off. The H level signal at the gate terminal PG is input to the NOR circuit 53 through the NOT circuit 55 as a signal 54a delayed by the delay circuit 54 by the period Td.
As a result, the NOR circuit 53 receives an L level signal at both the input terminal connected to the input terminal IN and the input terminal connected to the delay circuit 54. Accordingly, the output of the NOR circuit 53 becomes an H level signal after a period Td after the signal Vin falling from H to L is input to the input terminal IN, and the NMOS transistor 51 is turned on. At this time, since an L level signal is input to the terminal connected to the input terminal IN of the NAND circuit 52, the output of the NAND circuit 52 becomes an H level signal, and the PMOS transistor 50 is turned off. It has become.

  As described above, conventionally, a delay circuit is connected to the gate terminal of each transistor to prevent both transistors from being turned on at the same time and to prevent a through current from flowing.

JP 2009-21903 A

However, in the conventional gate monitor circuit, the delay time Td of the delay circuits 54 and 56 varies depending on the power supply voltage, the characteristics of the MOS transistor, and the like. As a result, when the delay time Td becomes small, there is a problem that both MOS transistors are turned on and a through current flows. Even when the delay time Td varies, if the delay time Td is set large so that no through current flows, there is a problem that the time during which both MOS transistors are off increases.
The present invention has been made in view of the above circumstances, and an object thereof is to solve the problem of preventing the generation of a through current and the both MOS transistors from being turned off without using a delay circuit.

  In order to solve the above problems, a gate monitor circuit according to the present invention is provided as a first transistor that discharges current from an output terminal, a second transistor that sinks current from an output terminal, and a replica circuit of the first transistor. A third transistor, a fourth transistor provided as a replica circuit of the second transistor, a first current detecting means for detecting a current flowing through the first transistor based on a current flowing through the third transistor, A second current detecting means for detecting a current flowing through the second transistor based on a current flowing through the four transistors; and when the current of the first transistor detected by the first current detecting means falls below a predetermined value. First gate charging means for charging the gate terminal of the second transistor, and the second current detecting means When the current of the second transistor detected is below a predetermined value by, and a second gate charging means for charging the gate terminal of the first transistor.

  According to the present invention, when the first transistor shifts from the on state to the off state and the gate voltage of the first transistor becomes lower than the threshold value, the current flowing between the source and the drain of the first transistor decreases. Therefore, a current based on this current also flows between the source and drain of the third transistor provided as a replica circuit. The first current detection means detects the current flowing in the first transistor based on the current flowing between the source and drain of the third transistor, and the first gate charging means shared with the first current detection means When the measured current becomes a certain value or less, the gate terminal of the second transistor is charged. Therefore, an allowable through current can be set by adjusting a constant value. In addition, since the second transistor is turned on before the first transistor is completely turned off, both the first transistor and the second transistor are not turned off at the same time.

  Further, when the second transistor shifts from the on state to the off state and the gate voltage of the second transistor becomes lower than the threshold value, the current flowing between the drain and source of the second transistor decreases. A current based on this current also flows between the drain and source of the fourth transistor provided as a replica circuit. The second current detection means detects the current flowing in the second transistor based on the current flowing between the drain and source of the fourth transistor, and the second gate charging means shared with the second current detection means When the measured current becomes a certain value or less, the gate terminal of the first transistor is charged. Therefore, an allowable through current can be set by adjusting the constant value. In addition, since the first transistor is turned on before the second transistor is completely turned off, both the first transistor and the second transistor are not turned off at the same time.

  In a preferred aspect of the present invention, the replica circuit is a current mirror circuit, and the size ratio between the first transistor and the third transistor and the size ratio between the second transistor and the fourth transistor are both set to n: 1. ing. In this case, a current 1 / n of the saturation current flows between the drain and source of the third transistor and the fourth transistor. Therefore, by appropriately setting the value of n, the timing at which one of the first transistor and the second transistor is completely turned off and the timing at which the other transistor is turned on can be adjusted. A through current can be set.

  As another aspect, the third transistor and the first current detection means, and the fourth transistor and the second current detection means are each connected to a current source. In this case, the current detected by the first current detection means or the second current detection means is a value obtained by subtracting the current flowing between the drain and source of the third transistor or the fourth transistor from the current value of the current source. Become. Therefore, by appropriately setting the current value of the current source, the timing at which one of the first transistor and the second transistor is completely turned off and the timing at which the other transistor is turned on can be adjusted. Allowable through current can be set.

  The first gate charging unit and the first current detection unit may be configured by a current mirror circuit, and the second gate charging unit and the second current detection unit may be configured by a current mirror circuit. . According to the present invention, the current detected by the first current detection means or the second current detection means becomes the current flowing through the first gate charging means or the second gate charging means, and the first transistor and the second transistor can be configured with a simple configuration. The timing at which the other transistor is turned on can be adjusted by the saturation current flowing through one of the two transistors.

It is a circuit diagram which shows the structure of the gate monitor circuit which concerns on one Embodiment of this invention. It is a circuit diagram which shows the structure of the conventional gate monitor circuit. It is a timing chart which shows operation | movement of the conventional gate monitor circuit.

  With reference to FIG. 1, the configuration of a gate monitor circuit according to an embodiment of the present invention will be described. The gate monitor circuit 100 is a circuit that controls the ON state and the OFF state of the PMOS transistor M1 and the NMOS transistor M2 by monitoring the saturation currents flowing through the gates of the PMOS transistor M1 and the NMOS transistor M2. The PMOS transistor M1 discharges current to the output terminal OUT, and the NMOS transistor M2 is a transistor that sucks current from the output terminal OUT.

  The gate monitor circuit 100 includes a PMOS transistor M3 as a replica circuit for the PMOS transistor M1. The replica circuit is a transistor that operates in the same manner as the operation of a target transistor (M1 in this example). The PMOS transistor M1 and the PMOS transistor M3 are formed by the same manufacturing process and have the same electrical characteristics. However, the transistor sizes are different from the viewpoint of reducing current consumption. The PMOS transistor M3 and the PMOS transistor M1 constitute a current mirror circuit. In the present embodiment, the size ratio of the PMOS transistor M1 and the PMOS transistor M3 is set to n: 1.

  The drain terminal of the PMOS transistor M3 is connected to the drain terminal of the PMOS transistor M4 and the current source Cs1. Since the current Ibp flows through the current source Cs1, if the current flowing between the source and drain of the PMOS transistor M3 is Ids, the current flowing between the source and drain of the PMOS transistor M4 is Ibp-Ids. .

  The gate terminal of the PMOS transistor M4 is connected to the drain terminal of the PMOS transistor M4 and the gate terminal of the PMOS transistor M5, and the PMOS transistors M4 and M5 constitute a current mirror circuit. The drain terminal of the PMOS transistor M5 is connected to the gate terminal NG of the NMOS transistor M2. Therefore, when a current flows between the source and drain of the PMOS transistor M4, a current also flows between the source and drain of the PMOS transistor M5, and the gate terminal NG of the NMOS transistor M2 is charged. That is, the PMOS transistor M4 functions as first current detection means for detecting the saturation current of the PMOS transistor M1 based on the current flowing between the source and drain of the PMOS transistor M3, and the PMOS transistor M5 is the detected PMOS transistor M1. Functions as first gate charging means for charging the gate terminal of the NMOS transistor M2 when the saturation current of the NMOS transistor M2 becomes equal to or less than a predetermined value.

  The drain terminal of the PMOS transistor M5 is connected to the drain terminal of the NMOS transistor M7 and the gate terminal NG of the NMOS transistor M2. Since the PWM input terminal IN is connected to the gate terminal of the NMOS transistor M7, when the PWM input rising from L to H is input to the PWM input terminal IN, the NMOS transistor M7 is turned on, and the NMOS transistor M2 Is turned off.

Further, the drain terminal of the PMOS transistor M6 is connected to the gate terminals of the PMOS transistor M4 and the PMOS transistor M5. The gate terminal of the PMOS transistor M6 is connected to the PWM input terminal IN through the NOT circuit 10.
Accordingly, when a PWM input rising from L to H is input to the PWM input terminal IN, the PMOS transistor M6 is turned on, and the PMOS transistor M4 connected to the drain terminal of the PMOS transistor M6 and the gate terminals of the PMOS transistor M5 are connected. The potential at the terminal A is equal to Vdd.
The sizes of the PMOS transistors M3, M4, M5, M6, and M7 can be set as appropriate, but they may all be equal.

  On the other hand, the gate monitor circuit 100 includes an NMOS transistor M3 'as a replica circuit for the NMOS transistor M2. The NMOS transistor M3 'and the NMOS transistor M2 constitute a current mirror circuit. In the present embodiment, the size ratio between the NMOS transistor M2 and the NMOS transistor M3 'is set to n: 1.

  The drain terminal of the NMOS transistor M3 'is connected to the drain terminal of the NMOS transistor M4' and the current source Cs2. Since the current Ibn flows through the current source Cs2, if the current flowing between the drain and source of the NMOS transistor M3 ′ is Ids, the current flowing between the drain and source of the NMOS transistor M4 ′ is Ibn−Ids. It becomes.

  The gate terminal of the NMOS transistor M4 'is connected to the drain terminal of the NMOS transistor M4' and the gate terminal of the NMOS transistor M5 ', and the NMOS transistors M4' and M5 'constitute a current mirror circuit. The drain terminal of the NMOS transistor M5 'is connected to the gate terminal PG of the PMOS transistor M1. Accordingly, when a current flows between the drain and source of the NMOS transistor M4 ', a current also flows between the drain and source of the NMOS transistor M5', and the gate terminal of the PMOS transistor M1 is charged. That is, the NMOS transistor M4 ′ functions as a second current detection unit that detects the saturation current of the NMOS transistor M2 based on the current flowing between the drain and source of the NMOS transistor M4 ′, and the NMOS transistor M5 ′ detects When the saturation current of the NMOS transistor M2 becomes a certain value or less, it functions as a second gate charging means for charging the gate terminal of the PMOS transistor M1.

  The drain terminal of the NMOS transistor M5 'is connected to the drain terminal of the PMOS transistor M7' and the gate terminal PG of the PMOS transistor M1. Since the PWM input terminal IN is connected to the gate terminal of the PMOS transistor M7 ′, when the PWM input falling from H to L is input to the PWM input terminal IN, the PMOS transistor M7 ′ is turned on and the PMOS transistor M7 ′ is turned on. The transistor M1 is turned off.

The drain terminal of the NMOS transistor M6 ′ is connected to the gate terminals of the NMOS transistor M4 ′ and the NMOS transistor M5 ′. The gate terminal of the NMOS transistor M6 ′ is connected to the PWM input terminal IN via the NOT circuit 20.
Accordingly, when a PWM input falling from H to L is input to the PWM input terminal IN, the NMOS transistor M6 ′ is turned on, and the NMOS transistor M4 ′ and the PMOS transistor M5 ′ connected to the drain terminal of the NMOS transistor M6 ′. The potential at the connection point B with the gate terminal is equal to GND. The sizes of the NMOS transistors M3 ′, M4 ′, M5 ′, M6 ′, and M7 ′ can be set as appropriate, but they may all be equal.

  Hereinafter, the operation of the gate monitor circuit 100 of this embodiment will be described with reference to FIG. First, a state where an L level PWM input is supplied to the PWM input terminal IN is assumed as an initial state. In this case, the NMOS transistor M7 is off and the PMOS transistor M7 'is on. As will be described later, the NMOS transistor M5 'is in an off state. For this reason, the potential of the gate terminal PG is substantially Vdd, and the PMOS transistor M1 is turned off.

  Next, since an H level signal is input to the gate terminal of the PMOS transistor M6 via the NOT circuit 10, the PMOS transistor M6 is in an OFF state. The PMOS transistor M1 and the PMOS transistor M3 constitute a current mirror circuit. However, since the PMOS transistor M1 is in an off state, no current flows through the PMOS transistor M3. In this case, a current having the same magnitude as the current value Ibp of the current source Cs1 flows through the PMOS transistor M4. Accordingly, the potential at the connection point A is substantially equal to GND, and the PMOS transistor M5 is turned on.

On the other hand, since an H level signal is input to the gate terminal of the NMOS transistor M6 ′ via the NOT circuit 20, the NMOS transistor M6 ′ is in an ON state. Accordingly, the potential at the connection point B becomes substantially equal to GND, and the NMOS transistor M5 ′ is turned off.
Since the NMOS transistor M7 is in the off state and the PMOS transistor M5 is in the on state, the potential of the gate terminal NG of the NMOS transistor M2 is approximately Vdd, and the NMOS transistor M2 is in the on state.

Next, a case where a PWM input rising from L to H is input to the PWM input terminal IN, the PMOS transistor M1 transitions from the off state to the on state, and the NMOS transistor M2 transitions from the on state to the off state will be described.
When a PWM input rising from L to H is input to the PWM input terminal IN, an H level signal is input to the gate terminal of the NMOS transistor M7, so that the NMOS transistor M7 transitions from the off state to the on state. Further, an L level signal is input to the gate terminal of the PMOS transistor M6 via the NOT circuit 10, and the PMOS transistor M6 is turned on. Therefore, the potential at the connection point A becomes substantially equal to Vdd, and the PMOS transistor M5 transitions from the on state to the off state. Then, the current flowing from the PMOS transistor M5 toward the gate terminal NG of the NMOS transistor M2 decreases and the current flowing from the gate terminal NG toward the NMOS transistor M7 increases. As a result, the potential of the gate terminal NG gradually decreases, and the NMOS transistor M2 transitions from the on state to the off state.

  In the present embodiment, the NMOS transistor M2 and the NMOS transistor M3 'constitute a current mirror circuit, and the size ratio of the NMOS transistor M2 and the NMOS transistor M3' is set to n: 1. Therefore, when the current Inmos flows between the drain and the source of the NMOS transistor M2, a current Imos / n flows between the drain and the source of the NMOS transistor M3 '.

  Since the drain terminal of the NMOS transistor M3 ′ is connected to the drain terminal of the NMOS transistor M4 ′ and the current source Cs2, if Imos / n> Ibn, no current is generated between the drain and source of the NMOS transistor M4 ′. Not flowing. In this case, no current flows between the drain and source of the NMOS transistor M5 'that forms a current mirror circuit with the NMOS transistor M4'.

  Here, when the current Inmos is the saturation current value Insat of the NMOS transistor M2, the output current value Ibn of the current source Cs2 is set to be Insat / n = Ibn. Therefore, when the NMOS transistor M2 is completely turned on, no current flows between the drain and source of the NMOS transistor M4 '. However, in the process in which the PWM input transitions from L to H and the NMOS transistor M7 changes from the on state to the off state, the potential of the gate terminal NG decreases toward GND, and accordingly, the current Imos increases. Decreases from the saturation current value Insat. In this process, Inmos / n <Ibn, and the current Ibn-Inmos / n flows through the NMOS transistor M4 'and the NMOS transistor M5'. As a result, the potential of the gate terminal PG of the PMOS transistor M1 gradually decreases from Vdd, and the PMOS transistor M1 transitions from the off state to the on state.

  On the other hand, the PMOS transistor M1 and the PMOS transistor M3 form a current mirror circuit, and the size ratio between the PMOS transistor M1 and the PMOS transistor M3 is set to n: 1. Therefore, when the current Ipmos flows between the source and drain of the PMOS transistor M1, a current of Ipmos / n flows between the source and drain of the PMOS transistor M3.

  Since the drain terminal of the PMOS transistor M3 is connected to the drain terminal of the PMOS transistor M4 and the current source Cs1, no current flows between the source and drain of the PMOS transistor M4 when Ipmos / n> Ibp. In this case, no current flows between the PMOS transistor M4 and the source and drain of the PMOS transistor M5 constituting the current mirror circuit.

  Here, when the current Ipmos is the saturation current value Ipsat of the PMOS transistor M1, the output current value Ibp of the current source Cs1 is set to be Ipsat / n = Ibp. Therefore, when the PMOS transistor M1 is completely turned on, no current flows between the source and drain of the PMOS transistor M4. However, in the process in which the PWM input changes from L to H and the PMOS transistor M1 changes from the OFF state to the ON state, the potential of the gate terminal PG decreases toward GND, and accordingly, the current Ipmos increases. Increases from zero toward the saturation current value Ipsat. In this process, Ipmos / n <Ibp, and the current Ibp-Ipmos / n flows through the PMOS transistor M4 and the PMOS transistor M5. As a result, the potential of the gate terminal NG of the MMOS transistor M1 gradually increases from GND, and the NMOS transistor M2 transitions from the off state to the on state. That is, the PMOS transistor M4 functions as first current detection means for detecting the current flowing through the PMOS transistor M1 based on the current flowing between the source and drain of the PMOS transistor M3, and the PMOS transistor M5 is connected to the gate − of the PMOS transistor M1. It functions as a first gate charging means for charging the gate terminal of the NMOS transistor M2 when the source-to-source voltage falls below the threshold voltage and the detected current of the PMOS transistor M1 becomes a certain value or less.

  When the PWM input rising from L to H is supplied to the PWM input terminal IN, the current flowing through the NMOS transistor M5 ′ gradually increases so as to lower the potential of the gate terminal PG of the PMOS transistor M1, and the NMOS transistor M2 The current flowing through the PMOS transistor M5 gradually decreases so as to lower the potential of the gate terminal NG. As described above, since the charging current supplied to each of the gate terminal PG and the gate terminal NG increases and decreases in the reverse direction, the NMOS transistor M2 is synchronized with the transition of the PMOS transistor M1 from the OFF state to the ON state. Transitions from the on state to the off state. As a result, it is possible to shorten the period in which the PMOS transistor M1 and the NMOS transistor M2 are simultaneously turned off while preventing the through current.

Next, a case where a PWM input falling from H to L is input to the PWM input terminal IN, the PMOS transistor M1 shifts from the on state to the off state, and the NMOS transistor M2 shifts from the off state to the on state will be described.
When a PWM input falling from H to L is input to the PWM input terminal IN, an L level signal is input to the gate terminal of the NMOS transistor M7, so that the NMOS transistor M7 changes from the on state to the off state. Further, the PMOS transistor M7 ′ transits from the off state to the on state. Further, an H level signal is input to the gate terminal of the NMOS transistor M6 ′ via the NOT circuit 20, and the NMOS transistor M6 ′ is turned on. Therefore, the potential at the connection point B between the drain terminal of the NMOS transistor M6 ′ and the gate terminals of the NMOS transistor M5 ′ and the NMOS transistor M4 ′ is substantially equal to GND, and the NMOS transistor M5 ′ transitions from the on state to the off state. To do. Then, the current flowing from the gate terminal PG of the PMOS transistor M1 toward the NMOS transistor M5 ′ decreases, and the current flowing from the PMOS transistor M7 ′ toward the gate terminal PG increases. As a result, the potential of the gate terminal PG gradually increases, and the PMOS transistor M1 transitions from the on state to the off state.

  In the present embodiment, the PMOS transistor M1 and the PMOS transistor M3 constitute a current mirror circuit, and the size ratio of the PMOS transistor M1 and the PMOS transistor M3 is set to n: 1. Therefore, when the current Ipmos flows between the source and drain of the PMOS transistor M1, a current of Ipmos / n flows between the source and drain of the PMOS transistor M3.

  Since the drain terminal of the PMOS transistor M3 is connected to the drain terminal of the PMOS transistor M4 and the current source Cs1, no current flows between the source and drain of the PMOS transistor M4 when Ipmos / n> Ibp. In this case, no current flows between the PMOS transistor M4 and the source and drain of the PMOS transistor M5 constituting the current mirror circuit.

  Here, when the current Ipmos is the saturation current value Ipsat of the PMOS transistor M2, the output current value Ibp of the current source Cs1 is set to be Ipsat / n = Ibp. Therefore, when the PMOS transistor M1 is completely turned on, no current flows between the source and drain of the PMOS transistor M4. However, in the process in which the PWM input changes from H to L and the PMOS transistor M7 ′ changes from the OFF state to the ON state, the potential of the gate terminal PG rises toward Vdd, and accordingly, the current Ipmos The magnitude decreases from the saturation current value Ipsat. In this process, Ipmos / n <Ibn, and the current Ibp-Ipmos / n flows through the PMOS transistor M4 and the PMOS transistor M5. As a result, the potential of the gate terminal NG of the NMOS transistor M2 gradually rises from GND, and the NMOS transistor M2 transitions from the off state to the on state.

  As described above, the NMOS transistor M2 and the NMOS transistor M3 'constitute a current mirror circuit, and the size ratio between the NMOS transistor M2 and the NMOS transistor M3' is set to n: 1. Therefore, when the current Inmos flows between the drain and the source of the NMOS transistor M2, a current Imos / n flows between the drain and the source of the NMOS transistor M3 '.

  Since the drain terminal of the NMOS transistor M3 ′ is connected to the drain terminal of the NMOS transistor M4 ′ and the current source Cs2, if Imos / n> Ibn, no current is generated between the drain and source of the NMOS transistor M4 ′. Not flowing. In this case, no current flows between the drain and source of the NMOS transistor M5 'that forms a current mirror circuit with the NMOS transistor M4'.

  Here, when the current Inmos is the saturation current value Insat of the NMOS transistor M2, the output current value Ibn of the current source Cs2 is set to be Insat / n = Ibn. Therefore, when the NMOS transistor M2 is completely turned on, no current flows between the drain and source of the NMOS transistor M4 '. However, in the process in which the PWM input changes from H to L and the NMOS transistor M2 changes from the off state to the on state, the potential of the gate terminal NG rises toward Vdd, and accordingly, the current Imos increases. Increases from zero toward the saturation current value Insat. In this process, Inmos / n <Ibn, and the current Ibn-Inmos / n flows through the NMOS transistor M4 'and the NMOS transistor M5'. As a result, the potential of the gate terminal PG of the PMOS transistor M1 gradually decreases from Vdd, and the PMOS transistor M1 transitions from the off state to the on state. That is, the NMOS transistor M4 ′ functions as second current detection means for detecting the current flowing through the NMOS transistor M2 based on the current flowing between the drain and source of the NMOS transistor M3 ′, and the NMOS transistor M5 ′ is the NMOS transistor M2 When the gate-source voltage of the NMOS transistor M2 falls below the threshold voltage and the detected current of the NMOS transistor M2 becomes a certain value or less, it functions as a second gate charging means for charging the gate terminal of the PMOS transistor M1.

  When the PWM input falling from H to L is supplied to the PWM input terminal IN, the current flowing through the NMOS transistor M5 ′ gradually decreases so as to increase the potential of the gate terminal PG of the PMOS transistor M1, and the NMOS transistor M2 The current flowing through the PMOS transistor M5 gradually increases so as to increase the potential of the gate terminal NG. As described above, since the charging current supplied to each of the gate terminal NG and the gate terminal PG decreases and increases in the opposite direction, the PMOS transistor M1 is synchronized with the transition of the NMOS transistor M2 from the OFF state to the ON state. Transitions from the on state to the off state. As a result, it is possible to shorten the period in which the PMOS transistor M1 and the NMOS transistor M2 are simultaneously turned off while preventing the through current.

As described above, according to the present embodiment, the through current allowed by appropriately selecting the current value Ibp of the current source Cs1, the current value Ibn of the current source Cs2, the size of the PMOS transistor M1, and the size of the NMOS gate M2. Can be set freely.
Since the NMOS transistor M2 is turned on before the PMOS transistor M1 is completely turned off, and the PMOS transistor M1 is turned on before the NMOS transistor M2 is completely turned off, the NMOS transistor M2 is turned on. And the time for which the PMOS transistor M1 is simultaneously turned off can be almost eliminated.
Furthermore, since this embodiment does not require the use of a delay circuit, there are no inconveniences such as generation of a through current due to variations in delay time and an increase in OFF time of the NMOS transistor M2 and the PMOS transistor M1.

DESCRIPTION OF SYMBOLS 10 ... NOT circuit, 20 ... NOT circuit, 100 ... Gate monitor circuit, Cs1 ... Current source, Cs2 ... Current source, M1 ... PMOS transistor (first transistor), M2 ... NMOS transistor (second transistor) Transistor), M3... PMOS transistor (replica circuit), M3 ′... NMOS transistor (replica circuit), M4... PMOS transistor (first current detection means), M4 ′... NMOS transistor (second current detection means) M5... PMOS transistor (first gate charging means), M5 ′... NMOS transistor (second gate charging means), M6... PMOS transistor, M6 ′... NMOS transistor, M7. ... NMOS transistors.

Claims (4)

A first transistor for discharging current from the output terminal;
A second transistor that draws current from the output terminal;
A third transistor provided as a replica circuit of the first transistor;
A fourth transistor provided as a replica circuit of the second transistor;
First current detecting means for detecting a current flowing through the first transistor based on a current flowing through the third transistor;
Second current detection means for detecting a current flowing through the second transistor based on a current flowing through the fourth transistor;
First gate charging means for charging the gate terminal of the second transistor when the current of the first transistor detected by the first current detection means becomes a predetermined value or less;
Second gate charging means for charging the gate terminal of the first transistor when the current of the second transistor detected by the second current detection means becomes a predetermined value or less;
A gate monitor circuit comprising: The replica circuit is a current mirror circuit, and the size ratio between the first transistor and the third transistor and the size ratio between the second transistor and the fourth transistor are both set to n: 1.
The gate monitor circuit according to claim 1. The third transistor and the first current detection means, and the fourth transistor and the second current detection means are each connected to a current source,
The gate monitor circuit according to claim 1, wherein the gate monitor circuit is a gate monitor circuit. The first gate charging unit and the first current detection unit are formed of a current mirror circuit,
The second gate charging unit and the second current detection unit are formed of a current mirror circuit.
The gate monitor circuit according to claim 1, wherein the gate monitor circuit is a gate monitor circuit.

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