JP2013171773A - Relay drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a relay drive device capable of suppressing heat generation of a relay.SOLUTION: A relay drive circuit comprises: a transistor 156 operating depending on a DC power supply voltage from a DC-DC converter; a Zener diode 161 connected with an output terminal of the transistor 156; a transistor 159 operated by a Zener current; and a relay 20 whose relay coil 21 is connected with a pair of relay output terminals consisting of output terminals of the transistors 156 and 159. When an output voltage between the relay output terminals becomes larger than a predetermined value defined by the Zener diode 161 and the transistor 159, the transistors 159 and 158 are operated to adjust an output voltage of the transistor 156, and thereby, to keep the output voltage between the relay output terminals at the predetermined value.

Description

  The present invention relates to a relay drive circuit for performing an inrush current suppressing operation in an inverter device, for example.

FIG. 3 shows a main circuit of the inverter device provided with the relay drive circuit, and the operation thereof will be described below together with the configuration.
The AC voltage output from the AC power supply 11 is rectified by the converter unit 12 including a diode bridge and converted into a DC voltage. One end of an inrush current suppression circuit 13 made of a resistor or the like is connected to the positive output terminal of the converter unit 12 in order to prevent damage inside the inverter device due to excessive current flowing when power is turned on.
Further, a smoothing capacitor 16 made of an electrolytic capacitor or the like is connected between the other end of the inrush current suppression circuit 13 and the negative side output terminal of the converter unit 12.

Connected to both ends of the smoothing capacitor 16 is an inverter unit 17 for converting a DC voltage into an AC voltage having a predetermined magnitude and frequency by turning on and off the semiconductor switching element. It is connected.
The smoothing capacitor 16 is connected in parallel with a DC-DC converter 14 that converts the voltage between both ends into a DC voltage of a predetermined magnitude and outputs it as a DC power supply voltage. The DC power supply voltage output from the DC-DC converter 14 is supplied to the relay drive circuit 15 as shown, and is used as various control power supply voltages. Here, the relay drive circuit 15 is for driving a relay that operates the inrush current suppression circuit 13 as described later.

FIG. 4 shows a main circuit of an inverter device described in Patent Document 1 as a conventional technique configured in substantially the same manner as FIG.
4, components having the same functions as those in FIG. 3 are denoted by the same reference numerals, and the following description will focus on portions different from those in FIG.

The power supply circuit 14A in FIG. 4 corresponds to a drive signal generation circuit for the switching element of the inverter unit 17 integrated with the DC-DC converter 14 in FIG. The delay circuit 19 on the output side of the relay drive circuit 15 is for delaying the output signal of the relay drive circuit 15 by a predetermined time and outputting it to the relay 20.
The relay 20 includes a relay coil 21 and a relay contact 22 that are excited by the output current of the delay circuit 19, and operates to short-circuit both ends of the inrush current suppression circuit 13 when the relay contact 22 is turned on.

  In this prior art, since the relay contact 22 is normally off, when the AC power supply 11 is turned on, the charging current of the smoothing capacitor 16 flows while being limited by the inrush current suppression circuit 13. Thereafter, when the voltage of the smoothing capacitor 16 reaches a predetermined value, the relay drive circuit 15 operates via the power supply circuit 14A, and the relay coil 21 is excited after being delayed by a delay circuit 19 for a predetermined time. Therefore, the relay contact 22 can be turned on after the smoothing capacitor 16 is sufficiently charged and its voltage is set to a predetermined value, and an excessive excitation current is applied to the relay coil 21 due to insufficient voltage of the smoothing capacitor 16 for a long period of time. It can be prevented from flowing.

Next, FIG. 5 shows the configuration of the relay drive circuit 15 in FIG. 3 described above.
In FIG. 5, reference numeral 151 denotes a CPU as an energization control unit, and a pulse-like relay control signal output from the CPU 151 is applied to the light emitting diode 153 a in the photocoupler 153 via the current limiting resistor 152. The output current of the phototransistor 153b in the photocoupler 153 flows to the relay coil 21 via the current limiting resistor 154. Reference numeral 23 denotes a free-wheeling diode connected in parallel to the relay coil 21.
In the relay drive circuit of FIG. 5, the ratio (duty) of the period during which the relay control signal is turned on by finely controlling the relay control signal output from the CPU 151 in order to suppress the heat generation of the relay 20. A method of reducing the size is used.

  Under ideal conditions, the relay output voltage (the output voltage of the relay drive circuit) can be expressed by the output voltage of the DC-DC converter 14 x the duty of the relay control signal. If this duty is reduced and the average value of the relay output voltage is reduced, the exciting current of the relay 20 is reduced, so that the heat generation of the relay 20 can be suppressed as compared with the case where the relay control signal is always on.

  When the OFF period of the relay control signal becomes longer than a certain period inherent to the relay, the exciting force of the relay coil 21 is weakened, and the relay contact 22 is turned OFF. However, even after the relay control signal is turned off, the exciting current flowing in the relay coil 21 during the ON period of the relay control signal is recirculated through the reflux diode 23, so that the exciting force of the relay coil 21 is maintained. Thus, the relay contact 22 can be prevented from being turned off after a very short on-time.

JP-A-6-165520 (paragraphs [0010] to [0013], FIG. 1 and the like)

  In this type of inverter device, the output voltage of the DC-DC converter 14 may increase due to load fluctuations. In FIG. 5, when the relay output voltage rises due to the rise of the output voltage of the DC-DC converter, the excitation current of the relay coil 21 increases and the amount of heat generation increases, and the internal temperature of the inverter device is lowered by appropriate cooling means. If this measure is not taken, the relay 20 may not be usable.

  Here, FIG. 6A is a timing chart showing a relay control signal, a relay output voltage, and an average value thereof in the prior art. FIG. 6B is a timing chart according to an embodiment of the present invention described later, which will be described later.

  In the prior art of FIG. 6A, the relay control signal is continuously turned on for a certain period (all on period) in order to reliably turn on the relay contact 22 when the relay is activated. After the start-up, the relay control signal is controlled to be turned on / off at a predetermined duty (duty control period), thereby reducing the average value of the relay output voltage to reduce the exciting current of the relay coil 21, and the relay 20 The fever is suppressed.

  Since the average value of the relay output voltage in the duty control period of FIG. 6A is proportional to the duty, heat generation of the relay 20 can be suppressed as the duty is reduced. Note that the maximum value of the relay output voltage at the start of the relay and during the duty control period is a value obtained by subtracting the collector-emitter saturation voltage of the phototransistor 153b in the photocoupler 153 from the output voltage of the DC-DC converter 14. However, in FIG. 6A, the saturation voltage is ignored.

Here, as the control signals generated by the CPU 151 in FIG. 5, there are an upper signal L _{0 having} a short cycle (its cycle is T ₀ ) and a lower signal L _{1 having} a long cycle (its cycle is T ₁ ). If, in general, the higher the signal L ₀ is used for high-speed processing is required arithmetic operations, the relay control signal long lower signal L ₁ periodicity is used.

In FIG. 6A described above, the OFF period of the relay control signal needs to be shorter than a certain period unique to the relay so that the relay 20 is not erroneously turned OFF due to a decrease in the excitation current of the relay coil 21.
However, when the lower signal L ₁ having a long cycle is used as the relay control signal from the CPU 151, the upper signal L ₀ may interrupt the cycle T ₁ of the lower signal L ₁ as shown in FIG. For example, when the upper signal L ₀ interrupts at the end of the off period of the lower signal L ₁ having a duty of 50%, the maximum off period of the relay 20 is higher than the upper signal at T _1/2, which is the off period of the lower signal L _1. period _{T 0} of _T 1/2 + _{T 0} becomes plus of L _0, only _{T 0} is longer than the normal off period _T 1/2. With such a relay contact 22 after the erroneous OFF period of the relay _{20 (T 1/2 + T} 0) has passed are turned on, the relay contact 22 there is a risk that welded large load current flows.

As one method of solving the erroneous off of the above-mentioned relay 20 generates a relay control signal based on the upper signal L ₀ of CPU 151, there is a way to prevent interruption of the low-order signal L _1.
2 (a) is a conceptual diagram illustrating a method of generating a relay control signal in CPU 151, and selected by the switch means 151a as a selection means a higher signal L ₀ and the lower signal L _1, based on the selected signal Relay control signal generation means 151b generates and outputs a relay control signal.

Here, FIG. 8 is a diagram showing the relationship between the relay control signal and the operation of the photocoupler.
In general photocouplers, the off delay time _Tdoff from the fall of the relay control signal until the photocoupler is turned off is longer than the on delay time _Tdon from the rise of the relay control signal until the photocoupler is turned on. long. Accordingly, the shorter the period of the relay control signal, the longer the period during which the photocoupler is in the on state, the duty of the relay output voltage is increased, and the average value of the relay output voltage is increased.
Therefore, the period generates a relay control signal based on the short upper signal L _0, in case of driving the relay 20 is also the calorific value of the relay 20 is disadvantageously increased.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a relay drive circuit that suppresses heat generation of the relay and prevents the relay from being erroneously turned off to improve reliability.

In order to solve the above-described problem, the invention according to claim 1 includes a first transistor that operates according to a DC power supply voltage;
A constant voltage element connected to the output terminal of the first transistor;
A second transistor operated by a current flowing through the constant voltage element;
A relay in which a relay coil is connected between a pair of relay output terminals composed of an output terminal of the first transistor and an output terminal of the second transistor;
When the output voltage between the relay output terminals exceeds a predetermined value determined by the constant voltage element and the second transistor, the second transistor is operated to adjust the output voltage of the first transistor, and the relay output The output voltage between the terminals is maintained at the predetermined value.

The invention according to claim 2 is the relay drive circuit according to claim 1,
A third transistor that operates in response to a pulse-like relay control signal output from the energization control unit; operates the first transistor in conjunction with the third transistor; and operates in conjunction with the second transistor. The third transistor is operated.

The invention according to claim 3 is the relay drive circuit according to claim 2,
The output current of the second transistor is input to the base of the third transistor, and the output current of the third transistor is input to the base of the first transistor.

The invention according to claim 4 is the relay drive circuit according to claim 3,
The constant voltage element is a Zener diode, and a current flowing through the Zener diode flows to the base of the second transistor.

The invention according to claim 5 is the relay drive circuit according to claim 4,
The second transistor is operated by a current flowing through the Zener diode, and the third transistor and the first transistor are sequentially operated in conjunction with the second transistor, whereby an output voltage between the relay output terminals is obtained. Is to lower.

The invention according to claim 6 is the relay drive circuit according to any one of claims 2 to 5,
The energization control unit is configured to select either a high order signal that is a pulse signal having a constant period or a low order signal that is a pulse signal having a longer period than the high order signal, and a signal selected by the selection means. Relay control signal generating means for generating the relay control signal based on the above.

The invention according to claim 7 is the relay drive circuit according to claim 6,
The relay control signal generation means generates a pulse signal having a period of at least twice the period of the upper signal as the relay control signal when the upper signal is selected by the selection means.

According to the present invention, the relay output voltage can be stabilized and the heat generation of the relay can be suppressed regardless of the rise of the DC power supply voltage.
Further, by using a relay control signal based on a high-order signal having a short cycle, it is possible to prevent the relay contacts from being accidentally turned off and to prevent welding of the relay contacts, and to improve the reliability of the inverter device. Further, since a relay output voltage proportional to the duty of the relay control signal commanded from the energization control unit can be obtained, the relay can be driven with high accuracy.

It is a circuit diagram which shows the structure of embodiment of this invention. It is explanatory drawing which shows the production | generation means (FIG. 2 (a)) and production | generation operation | movement (FIG.2 (b)) of the relay control signal in CPU. It is a main circuit block diagram of the inverter apparatus provided with the relay drive circuit. It is a main circuit block diagram of the inverter apparatus described in patent document 1. FIG. It is a block diagram of the relay drive circuit in FIG. It is a wave form diagram of a relay control signal, relay output voltage, and its average value in a prior art (Drawing 6 (a)) and an embodiment (Drawing 6 (b)) of the present invention. In prior art, it is explanatory drawing of a relay control signal when the interruption of a high-order signal occurs. It is a figure which shows the relationship between a relay control signal and photocoupler operation.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a relay drive circuit according to an embodiment of the present invention. In FIG. 1, components having the same functions as those in FIG. 5 are given the same reference numerals, and the following description will focus on parts different from those in FIG.
The relay drive circuit shown in FIG. 1 is supplied with a DC power supply voltage from the DC-DC converter 14 as shown in FIG. 3, and energizes the relay coil 21 to turn on the relay contact 22 and thereby an inrush current suppression circuit. It operates so as to short-circuit both ends of 13.

In FIG. 1, a resistor 155 is connected between the emitter of the phototransistor 153b in the photocoupler 153 and the circuit ground. One end of the resistor 154 is connected to the emitter of the phototransistor 153b, and the other end is connected to the base of the third transistor 158 and the collector of the second transistor 159.
A first transistor 156 and a relay coil 21 are connected in series between the output terminals of the DC-DC converter 14, and a resistor 157 is connected between the base of the transistor 156 and the collector of the transistor 158. Yes.
The emitters of the transistors 158 and 159 are connected to the ground.

A Zener diode 161 as a constant voltage element and a resistor 162 are connected in series between the collector of the transistor 156 and the ground, and a resistor 160 is connected between the series connection point and the base of the transistor 159. Yes.
Here, the transistors 156, 158, and 159, the resistors 154, 155, 157, 160, and 162, and the Zener diode 161 constitute a voltage stabilizing circuit 163.
Note that the resistors 152, 154, 157, and 160 in FIG. 1 are for preventing an overcurrent from flowing through the relay drive circuit, and the resistors 155 and 162 are grounded so that the transistors 158 and 159 are not erroneously turned on by noise. It is for bypassing to the side.

Next, the operation of this embodiment will be described.
First, when the power of the inverter device is turned on, the DC power supply voltage output from the DC-DC converter 14 increases. On the other hand, the photocoupler 153 is turned on by the pulsed relay control signal generated by the CPU 151, and the base current of the transistor 158 increases via the resistor 154 due to the voltage drop of the resistor 155. As described above, at the time of start-up, the low-order signal L ₁ (cycle T ₁ ) having a long cycle is used as the relay control signal.
As the base current of the transistor 158 increases, the collector current increases. In other words, since the base current of the transistor 156 increases, the collector-emitter voltage decreases, and the relay output voltage is equal to the Zener voltage of the Zener diode 161 and the transistor. It rises to a total value of 159 with the base-emitter voltage.

The total value of the Zener voltage of the Zener diode 161 and the base-emitter voltage of the transistor 159 is substantially constant. However, when the relay output voltage exceeds this total value, the Zener diode 161 is turned on and the collector current of the transistor 159 is reduced. It increases and the base current of transistor 158 decreases. As a result, the base current of the transistor 156 also decreases, and the collector-emitter voltage increases, so that the relay output voltage decreases.
In this way, the collector-emitter voltage of the transistor 156 repeatedly increases and decreases, and the maximum value of the relay output voltage is the zener voltage of the zener diode 161 and the base-emitter of the transistor 159 as shown in the middle stage of FIG. It is limited to the total value with the inter-voltage. Actually, the maximum value of the relay output voltage includes a voltage drop due to the resistor 160, but this voltage drop can be ignored if it is assumed that the value of the resistor 160 is small.

6B, when the relay output voltage is limited to the total value of the Zener voltage of the Zener diode 161 and the base-emitter voltage of the transistor 159, the average value of the relay output voltage is as shown in FIG. As shown in the lower part of FIG. 6 (b), the entire ON period and the duty control period are constant at a low value independent of the DC power supply voltage by the DC-DC converter 14. The relay output voltage under ideal conditions is [the Zener voltage of Zener diode 161 + the base-emitter voltage of transistor 159] × duty. Therefore, when CPU 151 sets the duty of the relay control signal to an appropriate value, DC− Regardless of the fluctuation of the DC power supply voltage by the DC converter 14, the relay output voltage can be controlled with high accuracy and stability.
When the DC power supply voltage is lower than [the Zener voltage of Zener diode 161 + the base-emitter voltage of transistor 159] during normal operation, the relay output voltage is the collector voltage of transistor 159 from the output voltage of DC-DC converter 14. • The value obtained by subtracting the saturation voltage between emitters.

Normally, a three-terminal regulator is known as a voltage stabilization circuit for obtaining a stable DC voltage. However, in principle, a three-terminal regulator has a stable voltage unless the potential difference between input and output exceeds a certain value. Cannot be output. However, in order to increase the input voltage to the three-terminal regulator, it is necessary to provide a power supply for the relay drive circuit separately, so it is necessary to increase the output of the DC-DC converter, which increases the cost and the circuit size. Turn into.
On the other hand, according to the present embodiment, it is possible to output a stable voltage even if there is no potential difference between the input and output of the voltage stabilization circuit 163 in FIG. 1, which may increase the cost and increase the size. Absent.

In order to prevent the relay 20 from being erroneously turned off, a relay control signal is generated based on the upper signal L ₀ having a short cycle, and the period of the relay control signal in that case is twice the cycle T ₀ of the upper signal L _0. It is desirable to perform duty control so as to achieve the above.
For example, as shown in FIG. 2 (a), when the upper signal L ₀ (period T ₀ ) is selected by the switch means 151a, as shown in FIG. 2 (b), based on the upper signal L ₀ It is easy for the relay control signal generating means 151b to generate a signal having a double cycle 2T ₀ , and this signal may be output from the CPU 151 as a relay control signal.

Here, as described with reference to FIG. 7, since the interruption of the lower signal L ₁ is eliminated when using the higher signal L ₀ to the relay control signal, the maximum off-period of the relay control signal = T _1/2, and the relay control signal since shorter than the maximum off-period = T _1/2 + T ₀ when using the lower signal L _1, it is possible to prevent erroneous off relay 20. As a result, it is possible to prevent welding of the relay contacts and improve the reliability of the inverter device.

Furthermore, given the on-off operation, including the operation delay of the photo-coupler 153, when the period of the relay control signal outputted from the CPU151 to 2 times the period T ₀ (e.g., lower signal the period of the relay control signal and the period _{T 1,} when the T 1 = 2T _0), the oN period = oFF period _{= T} 1/2 duty relay control signal as a 50% on-delay time _{T don} photocoupler 153, the off delay time Is T _doff , the average on-period _{Ton1 (AVG)} of the photocoupler 153 can be expressed by Equation 1.
[Equation 1]
T _{on1 (AVG)} = (T ₁ / 2−T _don + T _doff ) / T ₁

Also, when the period of the relay control signal is made equal to the period T ₀ (when the upper signal L ₀ shown in the upper part of FIG. 2B is output as it is as a relay control signal), the duty of the relay control signal is turned on at 50%. period = When off period _{= T} 0/2, the average on-period _{T on0} photocoupler 153 _(AVG) can be represented by equation 2.
[Equation 2]
_{T on0 (AVG) = (T} 0/2-T don + T doff) / T 0

Here, if T ₀ = T _1/2 , T _{on0 (AVG)} can be expressed by Equation 3.
[Equation 3]
_{T on0 (AVG) = (T} 0/2-T don + T doff) / T 0 = (T 1/4-T don + T doff) / (T 1/2) = {T 1 / 2-2 × (T _don + T _doff )} / T ₁

As described above, when the cycle of the relay control signal is made equal to the cycle T ₀ of the upper signal L ₀ , the influence of the on / off delay of the photocoupler 153 is 2 when the cycle of the relay control signal is T _1. You can see that it doubles.
Since a general photocoupler has a larger off delay than an on delay, the shorter the period of the relay control signal, the longer the period during which the photocoupler is in the on state, and the average value of the relay output voltage increases. The amount of heat generated by the relay also increases. Accordingly, the high-order signal L _{0 of the} CPU 151 is selected as in the present embodiment, and the photocoupler 153 is driven by generating a relay control signal having a period twice or more of the period T ₀ and driving the photocoupler 153. It is possible to reduce the influence of the on / off delay. As a result, a relay output voltage proportional to the duty of the relay control signal commanded from the CPU 151 can be obtained, and the relay can be driven with high accuracy.

  INDUSTRIAL APPLICABILITY The present invention can be used not only as a relay for an inrush current suppression circuit of an inverter device but also as a relay drive circuit for various uses that require suppression of heat generation and prevention of erroneous OFF of relay contacts.

DESCRIPTION OF SYMBOLS 11 AC power supply 12 Converter part 13 Inrush current suppression circuit 14 DC-DC converter 15 Relay drive circuit 16 Smoothing capacitor 17 Inverter part 18 Motor 20 Relay 21 Relay coil 22 Relay contact 23 Reflux diode 151 CPU
151a switch unit 151b relay control signal generation unit 152, 154, 155, 157, 160, 162 resistor 153 photocoupler 153a light emitting diode 153b phototransistor 156, 158, 159 transistor 161 zener diode 163 voltage stabilization circuit

Claims (7)

A first transistor that operates in response to a DC power supply voltage;
A constant voltage element connected to the output terminal of the first transistor;
A second transistor operated by a current flowing through the constant voltage element;
A relay in which a relay coil is connected between a pair of relay output terminals composed of an output terminal of the first transistor and an output terminal of the second transistor;
With
When the output voltage between the relay output terminals exceeds a predetermined value determined by the constant voltage element and the second transistor, the second transistor is operated to adjust the output voltage of the first transistor, and the relay output A relay drive circuit characterized by maintaining an output voltage between terminals at the predetermined value. In the relay drive circuit according to claim 1,
A third transistor that operates in response to a pulsed relay control signal output from the energization control unit;
A relay driving circuit that operates the first transistor in conjunction with a third transistor and operates the third transistor in conjunction with the second transistor. In the relay drive circuit according to claim 2,
The relay drive circuit, wherein an output current of the second transistor is input to a base of the third transistor, and an output current of the third transistor is input to a base of the first transistor. In the relay drive circuit according to claim 3,
The relay driving circuit, wherein the constant voltage element is a Zener diode, and a current flowing through the Zener diode flows to a base of the second transistor. In the relay drive circuit according to claim 4,
The second transistor is operated by a current flowing through the Zener diode, and the third transistor and the first transistor are sequentially operated in conjunction with the second transistor, whereby an output voltage between the relay output terminals is obtained. A relay drive circuit characterized by lowering. In the relay drive circuit according to any one of claims 2 to 5,
The energization control unit
A selection means for selecting one of a higher order signal that is a pulse signal having a constant period and a lower order signal that is a pulse signal having a longer period than the higher order signal;
Relay control signal generation means for generating the relay control signal based on the signal selected by the selection means;
A relay drive circuit comprising: In the relay drive circuit according to claim 6,
The relay control signal generating means generates a pulse signal having a period of at least twice the period of the upper signal as the relay control signal when the upper signal is selected by the selecting means. Driving circuit.

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