JP2013165243A - Circuit board, method for manufacturing circuit board, and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board having an opening provided on an insulating film in which an opening ratio is sufficiently improved, and to provide a method for manufacturing a circuit board and a display device.SOLUTION: A circuit board includes a glass substrate and an insulating film. The insulating film has at least a first opening and a second opening. When a main surface of the substrate is viewed in plane, the circuit board includes a first conductor overlapping the first opening, a second conductor or a semiconductor which is electrically connected to the first conductor, a third conductor overlapping the second opening, and a fourth conductor electrically connected to the third conductor. A layer in which the second conductor or the semiconductor is provided is positioned closer to the glass substrate side than a layer in which the fourth conductor is provided, and the first conductor is a circuit board thicker than the third conductor.

Description

The present invention relates to a circuit board, a circuit board manufacturing method, and a display device. More specifically, the present invention relates to a circuit board used as a constituent member of a high-definition liquid crystal display device, a circuit board manufacturing method, and a display device.

A circuit board has an electronic circuit as a constituent element. For example, a circuit board including an element such as a thin film transistor (TFT) is a liquid crystal display device, an organic electroluminescence display device, and an electronic device such as a solar cell. Widely used as a component.

Hereinafter, the circuit configuration of the TFT array substrate constituting the TFT-driven liquid crystal display panel will be described as an example. The TFT array substrate usually has a pixel circuit including a structure in which a TFT as a switching element is provided at an intersection of an m × n matrix wiring composed of m rows of gate bus lines and n columns of source bus lines. Here, the TFT array substrate is provided with a contact hole for electrically connecting different layers, such as the drain wiring of the TFT being electrically connected to the pixel electrode through the contact hole. Yes.

In recent years, high-definition display devices such as smartphones, tablets, portable game machines, and car navigation systems have become widespread, so a circuit with a high aperture ratio that is suitable for high-definition display devices. Substrates are strongly desired.

As a conventional circuit board, for example, a circuit board in which a gate electrode and a source metal provided in different layers are respectively connected to a pixel electrode at a contact hole portion is disclosed (for example, see Patent Document 1). ).

International Publication No. 2011/104938

The contact hole portion in the conventional circuit board described above is formed through a step of forming an organic insulating film (resist) as a planarizing film at a location where two or more types of steps exist and opening the planarizing film. However, as will be described later, there is room for improvement to obtain a circuit board having a high aperture ratio while ensuring a sufficient manufacturing yield.

The present invention has been made in view of the above situation, and provides a circuit board having a sufficiently improved aperture ratio in a circuit board having an opening in an insulating film, a method for manufacturing the circuit board, and a display device. It is intended to do.

The inventor of the present invention has studied various circuit boards that have an improved aperture ratio of the circuit board and can be appropriately used for display devices and the like. Here, the present inventor has paid attention to the fact that the contact hole is usually shielded from light, and therefore the opening area of the circuit board is reduced (the opening ratio of the circuit board is reduced). In order to prevent this decrease in the aperture ratio, it has been studied to appropriately reduce the hole diameter by a technique that does not cause a problem in the function of the contact hole. When an organic insulating film (resist) that is a planarizing film is formed at a location where two or more types of steps exist, and the opening is made, focus at the time of patterning exposure is set at a location where the steps are low. When exposure is performed for an exposure time of Y milliseconds (Y is larger than X described later) so that the organic insulating film can be sufficiently removed up to a low point, the higher the step, the overexposed, and the contact hole portion opening. On the other hand (for example, the diameter W ₂ in FIG. 16), on the other hand, the exposure is performed by focusing on a portion having a high step, for example, the organic insulating film at a portion having a high step can be sufficiently removed. When only exposure with an exposure time of about X milliseconds is performed, an increase in the diameter of the opening of the contact hole portion where the step is high is prevented (for example, FIG. 17). Definitive diameter W _1), the step is left unexposed organic insulating film (resist) on the lower portion (e.g., focusing on the planarization film 136R) in FIG.

In the conventional circuit board, for example, there is a step between the source / gate contact portion and the source / Si contact portion or between the source / gate contact portion and the source / light shielding film contact portion. Here, first, when patterning the organic insulating film for patterning by exposure, this inventor paid attention to the advantageous effect of adjusting exposure time to the one where a level | step difference is low. In other words, when the exposure time is adjusted to the higher step, the contact portion with the lower step has an unexposed organic film left below the contact hole, thereby disconnecting the connection and preventing the electrical connection. It has been found that there is a risk that the manufacturing yield of the resin may decrease, or that cross-contamination may occur due to the resist residue being scattered in the next process. It was also found that such disconnection and cross-contamination can be sufficiently prevented by adjusting the exposure time to a lower step. However, for example, in the conventional circuit board, the source / gate contact portion and the source / Si contact portion have a step comparable to the gate electrode and the gate oxide film, and the exposure time is adjusted to the portion where the step is low. When the planarization film is opened, as described above, there is a tendency that the opening area where the level difference is high tends to increase the opening area, and thereby the opening ratio of the circuit board may be lowered. The present inventor has first found such a problem, and then has found that it is important to maintain a high aperture ratio, especially as the display device has higher definition.

The present inventor has recognized that it is important to have a process that does not impair the function of the contact hole portion and that does not increase the opening area of the planarization film, and has intensively studied this. Then, by filling the step with a conductor and making it small, the difference between the steps in the opening area of the planarized film to be manufactured can be reduced, for example, the first source metal is placed only in a place where the step is low. It has been found that the step can be reduced by patterning and arranged, and as a result, an increase in the opening area of the planarization film can be suppressed.

Further, in the conventional device structure, the level difference is the gate electrode and the gate oxide film, but recently, a light shielding film may be employed under the transistor. When the metal on the film (on the organic insulating film) and the light-shielding film are electrically connected in the contact hole portion, in the conventional structure, the conductor (source metal or the like) in the source / gate contact portion and the source / light-shielding film contact portion The level difference with the conductor (source metal or the like) is, for example, the lowermost insulating film (for example, about 300 nm) existing under the transistor and the semiconductor compared to the level difference between the source / gate contact portion and the source / Si contact portion described above. It further increases by the level difference of the layer (for example, about 1000 nm). In such a circuit board, the opening area of the opening tends to be particularly large. The present inventor has found that the present invention can be particularly suitably applied to such a circuit board, and has conceived that the above problems can be solved brilliantly, and has reached the present invention.

That is, the present invention is a circuit board having a glass substrate and an insulating film, wherein the insulating film has at least a first opening and a second opening, and the circuit board has a plan view of the main surface of the substrate. A first conductor overlapping with the first opening, a second conductor or semiconductor electrically connected to the first conductor, a third conductor overlapping with the second opening, and a third conductor The layer having the fourth conductor electrically connected to the body and provided with the second conductor or the semiconductor is closer to the glass substrate than the layer provided with the fourth conductor. The first conductor is a thicker circuit board than the third conductor. The circuit board of the present invention is usually a circuit board for a display device. The first conductor to the fourth conductor are made of, for example, a light-shielding metal and are not deposited on a flattening film described later.

The first conductor is usually electrically connected to the second conductor or the semiconductor on the lower side (glass substrate side) of the first conductor, and the third conductor is usually the lower side of the third conductor. To electrically connect to the fourth conductor. It is preferable that a 1st conductor and a 3rd conductor are comprised from the same electroconductive material. More preferably, it is made of source metal. Normally, the first conductor and the third conductor are separated separately and are not electrically connected.

The first conductor is thicker than the third conductor, and an amount corresponding to the difference between the upper surface of the first conductor (referred to as the surface opposite to the glass substrate side) and the upper surface of the third conductor. The step is smaller. The upper surface of the first conductor or the third conductor is the height of the lowest portion of the upper surface of the first conductor or the third conductor in the contact portion.

The first conductor is preferably a laminate of conductors. For example, when the third conductor is also a laminated body of conductors, it is preferable that the third conductor is laminated more than the third conductor. In addition, it is one of the preferred embodiments of the present invention that the first conductor includes a plurality of layers of source metal, and the third conductor includes a single layer of source metal. It is one of the preferable embodiments of the present invention that the first conductor further includes a gate metal.

The circuit board is an array substrate having a thin film transistor element, the thin film transistor element preferably includes a gate electrode, a source electrode, a drain electrode, and a semiconductor, and the fourth conductor is preferably a gate electrode.

In a preferred embodiment of the present invention, the second conductor or semiconductor is a semiconductor of the thin film transistor element.
Note that the thin film transistor element may be an amorphous Si TFT, a polycrystalline Si TFT, or the like, or may include an oxide semiconductor. For example, the semiconductor layer of the thin film transistor element is preferably an amorphous Si semiconductor layer.

The circuit board has at least a fourth conductor between the layer provided with the second conductor or the semiconductor and the layer provided with the third conductor when the circuit board is viewed in cross section. And a gate oxide film is preferably provided. The layer is a layer in contact with a common member (for example, an insulating layer) on the glass substrate side and / or on the side opposite to the glass substrate side.

The circuit board includes at least a fourth conductor and a gate between the layer provided with the second conductor and the layer provided with the third conductor when the circuit board is viewed in cross section. An oxide film, a semiconductor, and an insulating film are provided in one preferred form of the circuit board of the present invention. The second conductor is preferably a light shielding film. The gate oxide film and the light shielding film usually overlap with a gate electrode which is a fourth conductor when the main surface of the substrate is viewed in plan. By applying the present invention to such a circuit board, the effect of increasing the aperture ratio of the circuit board, such as sufficiently suppressing an increase in the area of the contact hole, can be exhibited remarkably.

Note that the thickness of the insulating film to be opened is preferably 2 μm or more. For example, it is preferably 10 μm or less.

The circuit board is further provided with a planarization film, and the planarization film has an opening provided so as to overlap the first opening when the substrate main surface is viewed in plan, and the second opening. It is preferable that an opening is provided so as to overlap with the portion. The flattening film usually refers to a film for flattening the surface of the circuit board opposite to the glass substrate. Further, the circuit board is further provided with a planarization film and a fifth conductor and a sixth conductor on the planarization film, and the planarization film has the circuit board when the substrate main surface is viewed in plan view. Includes a first contact hole for electrically connecting the fifth conductor on the planarization film and the first conductor through the opening of the planarization film overlapping the first opening, and the first contact hole, It is preferable that a second contact hole for electrically connecting the sixth conductor on the planarization film and the third conductor through the opening of the planarization film overlapping the two openings is suitable. It is mentioned as a thing. In other words, the circuit board further forms an organic insulating film (resist) which is a planarizing film, and opens the openings at positions overlapping with the first opening and the second opening, and the metal or transparent conductive film is formed. It may be deposited to form a contact hole. In addition, the said 5th conductor and 6th conductor should just be a metal or transparent conductor in which at least one part is provided on the planarization film | membrane.

The diameter of the opening of the planarizing film is preferably 8 μm or less. As one of the effects of the present invention, in the planarization film, the diameter of the opening overlapping with the second opening can be sufficiently reduced in addition to the diameter of the opening overlapping with the first opening. As a result, the aperture ratio of the circuit board can be made sufficiently higher. The diameter may be an average length of the diameter, but it is more preferable that the maximum diameter of the opening is within the upper limit. The maximum diameter is preferably 3 μm or more.

In one preferred embodiment of the present invention, the opening overlaps with the light shielding film. The opening may overlap with the light shielding film as long as the contact hole substantially overlaps with the second conductor.

In the circuit board of the present invention, as described above, for example, a pixel electrode is further disposed on the planarization film, and the pixel electrode, the first electrode, and the second electrode or the semiconductor are provided as contact holes. The pixel electrode and the third electrode and the fourth electrode are electrically connected through a first opening as a contact hole.

The present invention is also a method for manufacturing a circuit board having a glass substrate and an insulating film, the method for manufacturing the circuit board comprising a step of forming a second conductor or a semiconductor, a step of forming an insulating film, Forming a fourth conductor, forming a first conductor electrically connected to the second conductor or semiconductor, and forming a third conductor electrically connected to the fourth conductor, planarization Forming a film, and opening each of a region overlapping with the first conductor of the planarizing film and a region overlapping with the third conductor of the planarizing film by exposure. The conductor is thicker than the third conductor and has an exposure time for opening a region overlapping the first conductor of the planarizing film, and opening a region overlapping the third conductor of the planarizing film. The exposure time for doing this is also the same circuit board manufacturing method. It can be said that the same exposure time is substantially the same in the technical field of the present invention.

Here, the step of forming the first conductor electrically connected to the second conductor or the semiconductor and forming the third conductor electrically connected to the fourth conductor is, for example, the third conductor While the source metal is deposited once as the body (depositing the second source metal), the source metal can be deposited twice as the first conductor (depositing the first source metal and the second source metal). As a result, a step corresponding to the thickness of the first source metal film can be absorbed. As a result, overexposure of the opening at the highest step is suppressed, and as a result, an excessive increase in the opening area of the portion is prevented. It is possible to suppress the resist remaining at the portion where the level difference is low.

More specifically, the step of forming the first conductor that is electrically connected to the second conductor or the semiconductor and the third conductor that is electrically connected to the fourth conductor includes the following steps: Can be done. First, a first source metal is deposited. Next, a resist is applied. Next, first patterning exposure is performed. Next, wet etching is performed. Thus, the first source metal is formed only in the first region (region serving as the first opening when the substrate main surface is viewed in plan) so as to be electrically connected to the second conductor or the semiconductor. Then, the resist is peeled off. Next, a second source metal is deposited. Next, a resist is applied. Next, second patterning exposure is performed. Next, wet etching is performed. Thus, the second source metal is formed in the first region so as to be electrically connected to the second conductor or the semiconductor via the first source metal, and is also electrically connected to the fourth conductor. A second region (a region that becomes a second opening when the main surface of the substrate is viewed in plan) is formed in the second opening. Next, the resist is peeled off. As described above, patterning is completed.

In the method for manufacturing a circuit board according to the present invention, the pixel electrode is formed on the planarizing film, and at the same time, usually, the pixel electrode and the first electrode and the second electrode or the semiconductor are interposed through the first opening. The pixel electrode and the third electrode and the fourth electrode are electrically connected through the second opening. This also forms a contact hole.

In addition, the preferable form of the circuit board obtained by the manufacturing method of the circuit board of this invention is the same as the preferable form of the circuit board of this invention mentioned above.

The present invention is also a display device including the circuit board of the present invention or the circuit board obtained by the method for manufacturing a circuit board of the present invention. Examples of the display device include liquid crystal display devices, EL display devices such as organic EL display devices and inorganic EL display devices. Among them, a small-sized, high-definition display device such as a smartphone, a tablet, a portable game machine, and a car navigation is particularly preferable. As the display device, a liquid crystal display device is preferable.

The preferred form of the circuit board provided in the display device of the present invention is the same as the preferred form of the circuit board of the present invention described above or the circuit board obtained by the method for producing a circuit board of the present invention.

The circuit board of the present invention, the method of manufacturing the circuit board, and the configuration of the display device are not particularly limited by other components as long as the above-described components are essential. The circuit board manufacturing method and other configurations usually used in display devices can be applied as appropriate.

According to the present invention, in the circuit board in which the opening is provided in the insulating film, the aperture ratio of the circuit board can be sufficiently improved.

5 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 1. FIG. 5 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 1. FIG. 5 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 1. FIG. 5 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 1. FIG. 5 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 1. FIG. 5 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 1. FIG. 5 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 1. FIG. 5 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 1. FIG. 5 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 1. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 2. FIG. 12 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Embodiment 3. FIG. 12 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 1. FIG. 12 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 1. FIG. 12 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 1. FIG. 12 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 1. FIG. 12 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 1. FIG. 12 is a schematic cross-sectional view showing one alternative form of the circuit board manufacturing process of Comparative Example 1. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board of Comparative Example 2. FIG. 10 is a schematic plan view showing one of manufacturing steps of a circuit board of Comparative Example 2. FIG. 10 is a schematic plan view showing one of manufacturing steps of a circuit board of Comparative Example 2. FIG. 10 is a schematic plan view showing one of manufacturing steps of a circuit board of Comparative Example 2. FIG. 10 is a schematic plan view showing one of manufacturing steps of a circuit board of Comparative Example 2. FIG. 10 is a schematic plan view showing one of manufacturing steps of a circuit board of Comparative Example 2. FIG. 10 is a schematic plan view showing one of manufacturing steps of a circuit board of Comparative Example 2. FIG.

In this specification, a source metal refers to a source electrode, a source bus line in a TFT, or a metal made of the same material as these. The gate metal refers to a metal made of the same material as a gate electrode, a gate bus line, or these in a TFT. The circuit board is also referred to as a TFT substrate because it is a substrate on which TFTs are provided in the embodiment. In the liquid crystal display device including the circuit board of the present invention, the substrate facing the circuit board is also referred to as a CF substrate since the color filter (CF) is disposed in the embodiment. The aperture ratio of the circuit board is a ratio of the light-transmitting area to the total area of the light-transmitting area and the light-blocking area in the circuit board in the display area where an image is displayed when the circuit board is applied to a display device. Since the opening of the planarization film is usually shielded from the viewpoint of improving display quality, the opening area (opening ratio) of the circuit board can be increased by reducing the opening area of the planarization film. Further, in this specification, for convenience of explanation, even an opening (hole) that is not yet electrically connected during the manufacturing process may be referred to as a “contact hole portion”. Further, a component member made of a source metal and a gate metal that are electrically connected to each other is also referred to as a source / gate contact portion, and a contact hole in which the contact portion is formed is also referred to as a gate contact hole. A component member made of a source metal and a silicon (Si) semiconductor that are electrically connected to each other is also referred to as a source / Si contact portion, and a contact hole in which the contact portion is formed is also referred to as an active contact hole. A structure including a source metal and a light shielding film that are electrically connected to each other is also referred to as a source / light shielding film contact portion. These contact portions may be further electrically connected to a transparent electrode such as a metal on the planarizing film or a pixel electrode through a contact hole overlapping the contact portion. Further, even a substrate on which an electric circuit is not completely formed yet during the manufacturing process may be referred to as a “circuit substrate”.

Embodiments will be described below, and the present invention will be described in more detail with reference to the drawings. However, the present invention is not limited only to these embodiments. Moreover, in each embodiment etc., the same code | symbol is attached | subjected to the member and part which exhibit the same function.

(Embodiment 1)
The circuit board of Embodiment 1 has a source / gate contact portion and a source / Si contact portion. In this case, in the conventional circuit board, there is a step between the source metal of the source / gate contact portion and the source metal of the source / Si contact portion. As will be described later, the first source metal is applied to the source / Si contact portion. By leaving, the step can be reduced. That is, the step can be reduced by arranging a plurality of layers of source metal in the source / Si contact portion and arranging a single layer of source metal in the source / gate contact portion.
The circuit board according to the first embodiment is a TFT substrate provided with a thin film transistor (TFT), and includes a pixel electrode area (display area) and a region outside the pixel electrode area (non-display area). The layer thickness of the semiconductor layer is, for example, 5000 nm or less (several hundred nm when low-temperature polysilicon [LTPS] is used). The film thickness of the gate insulating film (gate oxide film) is, for example, 2000 nm or less (several hundred nm when LTPS is used).
Below, the formation process of the patterning film in TFT is demonstrated.

1 to 9 are schematic cross-sectional views showing one of the manufacturing steps of the circuit board according to the first embodiment. The circuit board according to the first embodiment can be manufactured by a combination of techniques usually used in the technical field of the present invention. Hereinafter, a manufacturing process particularly characteristic in the present invention will be described in detail.

Interlayer insulating film patterning step S1
FIG. 1 is a schematic cross-sectional view of the circuit board after the patterning process of the interlayer insulating film 20 is performed. The circuit board of Embodiment 1 has a glass substrate (not shown), and a barrier layer 11, a silicon (Si) semiconductor layer 14, a gate oxide film 16, a gate electrode 18, and an interlayer insulating film 20 are provided on the glass substrate. Have in order. In the active contact hole portion CH _A , the upper surface of the silicon (Si) semiconductor layer 14 is exposed. Further, the gate contact hole CH _G, the upper surface of the gate electrode 18 is exposed. The level difference between the upper surfaces corresponds to the thickness of the gate oxide film 16 and the gate electrode 18.

Barrier metal and first source metal deposition step S2
FIG. 2 is a schematic cross-sectional view of the circuit board after the step of depositing the barrier metal 21 and the first source metal 23 from the circuit board shown in FIG. The barrier metal 21 and the first source metal 23, in the active contact hole CH _A, is connected silicon (Si) and electrically the upper surface of the semiconductor layer 14. The barrier metal 21 and the first source metal 23, in the gate contact hole CH _G, are top and electrically connected to the gate electrode 18.

Photoresist coating process S3
FIG. 3 is a schematic cross-sectional view of the circuit board after a step of coating a photoresist 25 from the circuit board shown in FIG.

Exposure step S4
FIG. 4 is a schematic cross-sectional view of the circuit board after a step of patterning and exposing the photoresist 25 from the circuit board shown in FIG. Photoresist 26A after patterning is provided only to the active contact holes CH _A.
In the exposure process in Embodiment 1, a photomask is not used, but a photomask may be used.

First source metal and barrier metal wet etching step S5
FIG. 5 is a schematic cross-sectional view of the circuit board after the wet etching process of the first source metal 23 and the barrier metal 21 is further performed from the circuit board shown in FIG. The first source metal 24A and the barrier metal 22A after etching are provided only in the active contact hole portion CH _A and are electrically connected to the upper surface of the silicon (Si) semiconductor layer 14.

Photoresist stripping step S6 and barrier metal, second source metal and antireflection metal deposition step S7
FIG. 6 shows a circuit board after a step of removing the photoresist 26A from the circuit board shown in FIG. 5 and then a step of depositing a barrier metal 27, a second source metal 29 and an antireflection metal 31. FIG. The barrier metal 27, the second source metal 29 and the anti-reflective metal 31, in the active contact hole CH _A, upper and electricity through the first source metal 24A and the barrier metal 22A silicon (Si) semiconductor layer 14 connection is to, also, in the gate contact hole CH _G, are top and electrically connected to the gate electrode 18.

Photoresist coating and patterning step (exposure step) S8, and wet etching step S9 for antireflection metal, second source metal and barrier metal
In FIG. 7, a photoresist is further coated from the circuit board shown in FIG. 6, and this is patterned to form photoresists 34A and 34G. Then, the antireflection metal 31, the second source metal 29, and the barrier metal 27 are coated. It is a cross-sectional schematic diagram of the circuit board after performing the process of wet-etching. In the active contact hole portion CH _A , an antireflection metal 32A, a second source metal 30A, and a barrier metal 28A are formed, and these are silicon (Si) semiconductor layers via the first source metal 24A and the barrier metal 22A. 14 is electrically connected to the upper surface. In the gate contact hole CH _G, anti-reflective metal 32G, the second source metal 30G and barrier metal 28G are formed, they are top and electrically connected to the gate electrode 18.

Photoresist stripping step S10 and planarization film coating step S11
FIG. 8 is a schematic cross-sectional view of the circuit board after a step of further removing the photoresist 34A and the photoresist 34G and coating the planarizing film 35 from the circuit board shown in FIG.

Planarizing film exposure step S12
FIG. 9 is a schematic cross-sectional view of the circuit board after a step of patterning and exposing the planarizing film 35 from the circuit board shown in FIG. In FIG. 9, the planarizing film 36 subjected to patterning exposure is formed. And exposure time in active contact holes CH _A, the exposure time in the gate contact hole CH _G and is substantially the same.

Transparent electrode (pixel electrode) formation step S13
Further, a transparent electrode (not shown) is formed on the planarizing film 36 from the circuit board shown in FIG. The transparent electrode is in the active contact hole CH _A, silicon (Si) semiconductor layer 14 and are electrically connected, in the gate contact hole CH _G, is electrically connected to the gate electrode. The transparent electrode in the first embodiment is made of ITO (indium tin oxide), but may be made of other transparent electrodes such as IZO (indium zinc oxide) instead of ITO.

The diameter (maximum diameter) of the contact hole portion (opening portion) shown in FIG. 9 can be reduced to, for example, 8 μm. Here, by applying the present invention, the diameter of the opening having the higher step is less than 1 μm, for example, 0, compared to the case where the exposure time is adjusted to the lower step in the circuit board of Comparative Example 1 described later. It can be reduced by 5 μm. In the present embodiment, as the interlayer insulating film 20, for example, a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN _x ), a silicon nitride oxide film (SiNO), or the like is used.

The circuit board of Embodiment 1 is particularly suitable because the aperture ratio can be sufficiently improved even when applied to a high-definition liquid crystal display panel. In addition, even if it is the structure which uses a conductor layer instead of the semiconductor layer 14 in Embodiment 1, the effect similar to Embodiment 1 can be exhibited.

The circuit board of Embodiment 1 is provided with the first source metal 24A and the barrier metal 22A corresponding to the first conductor by the steps S2 to S6. Thereby, the step of the connecting portion between the contact hole portions is reduced when the planarizing film is coated without causing problems such as disconnection in the contact hole portions. As a result, when patterning exposure of the planarizing film, both contact hole portions can be appropriately exposed without excess and deficiency, and the resist residue in the active contact hole portion CH _A is sufficiently suppressed, yield resulting from disconnection or the like. in terms of deterioration of is sufficiently suppressed, it is possible to reduce the diameter of the gate contact hole CH _G, it is possible to heighten the aperture ratio of the circuit board.

In addition, as a source metal, what is used normally can be used, for example, metals, such as tantalum (Ta), aluminum (Al), tungsten (W), copper (Cu), nitrides of these metals, and aluminum It can be an alloy or the like. The same applies to the gate metal (gate electrode).

The circuit substrate of Embodiment 1 is preferably an active matrix substrate, whereby voltage application is controlled for each pixel due to the switching function of the TFT, and precise active matrix driving can be performed.

The circuit board of Embodiment 1 has a pixel circuit including a structure in which a TFT as a switching element is provided at an intersection of an m × n matrix wiring composed of m rows of gate bus lines and n columns of source bus lines. . In other words, a pixel electrode and a TFT are provided for each region surrounded by the gate bus line and the source bus line.

It is particularly preferable that the top surface of the first conductor in the first opening and the top surface of the third conductor in the second opening have substantially the same height from the glass substrate. Height refers to the distance in the direction perpendicular to the glass substrate surface. In the first embodiment, since the sum of the thickness of the gate electrode 18 and the thickness of the gate oxide film 16 is a step, the thickness of the first source metal (additionally disposed source metal) is 18 is preferably substantially the same as the total thickness of the gate oxide film 16.

(Embodiment 2)
FIG. 10 is a schematic cross-sectional view showing one of the manufacturing steps of the circuit board according to the second embodiment.
The circuit board of Embodiment 2 has a source / gate contact portion and a source / light shielding film contact portion. FIG. 10 shows the circuit board after a step corresponding to the photoresist peeling step S10 in the first embodiment. That is, in the circuit board of the second embodiment, an organic insulating film (resist) that is a planarizing film is further formed from the form shown in FIG. 10 to form a source / gate contact portion and a source / light shielding film contact portion. The opening is made at a location overlapping with and a conductor (metal or transparent conductive film) on the planarizing film is deposited, and a contact hole electrically connected to the conductor on the planarizing film is formed. Although not illustrated, the lower side of the illustrated member (the lower side of the light shielding film 10) is a glass substrate.

In the conventional circuit board, there is a step between the source metal of the source / gate contact portion and the source metal of the source / light shielding film contact portion. In the second embodiment, the first source metal 24S is provided in the source / light shielding film contact portion. By leaving, the step can be reduced and relaxed. That is, a plurality of layers of source metal (source metal 24S and source metal wiring 30S) are stacked in the source / light shielding film contact portion, and a single layer of source metal 30G is disposed in the source / gate contact portion, thereby reducing the step. be able to.
The light shielding film 10 deposits a metal (for example, molybdenum) as a material of the light shielding film 10, performs a photoresist formation process, and further performs etching (mainly wet etching is applied). Thus, it can be formed.

In the second embodiment, in order to minimize the photocurrent flowing in the transistor, the light shielding film 10 is employed in the lower part of the transistor, and the source metal wiring 30S on the planarization film and the light shielding film 10 are electrically connected by a contact hole. I am letting.

In the configuration of the second embodiment, the thickness of the first source metal 24S is the sum of the thickness of the gate electrode 18, the thickness of the gate oxide film 16, the thickness of the semiconductor layer 14, and the thickness of the insulating film (barrier layer) 11. In contrast, it is preferably 50% or more. The upper limit is preferably 150% or less. In order to achieve the effect of the present invention, the thickness of the first source metal 24 </ b> S is the thickness of the gate electrode 18, the thickness of the gate oxide film 16, the thickness of the semiconductor layer 14, and the thickness of the insulating film (barrier layer) 11. It is particularly preferred that the total is substantially the same. In addition, the other structural member of Embodiment 2 is the same as the structural member of Embodiment 1, and can be formed similarly to Embodiment 1.

Here, in the case of a conventional circuit board in which the first source metal (source metal 24S additionally disposed) is not provided, the thickness of the gate electrode 18, the thickness of the gate oxide film 16, and the thickness of the semiconductor layer 14 The total thickness of the insulating film (barrier layer) 11 is a step. In this way, with the conventional configuration, the level difference becomes larger. As a result, when exposure is performed to open the organic insulating film in accordance with the source / light-shielding film contact portion with the low level difference, the source / Although the area of the opening (contact hole) formed in the organic insulating film (planarization film) in the gate contact portion has increased and the aperture ratio of the circuit board has decreased, this is not the case in the circuit board of the second embodiment. By suppressing such an increase in area, the aperture ratio of the circuit board can be sufficiently increased.

(Embodiment 3)
FIG. 11 is a schematic cross-sectional view illustrating one of the manufacturing steps of the circuit board according to the third embodiment.
FIG. 11 shows the circuit board after a step corresponding to the photoresist peeling step S10 in the first embodiment, as in FIG. That is, in the circuit board of Embodiment 3, when the organic insulating film (resist) that is a planarizing film is further formed from the form shown in FIG. Openings are made in portions overlapping with the source and light source / light shielding film contact portions, and a conductor (metal or transparent conductive film) is deposited on the planarizing film to form contact holes.

As the third embodiment, the first source metal 24S is added to the source / light shielding film contact portion (the portion where the source metal wiring 30S on the interlayer insulating film 20 is electrically connected to the light shielding film 10) as in the second embodiment. Thus, a more preferable embodiment in which the gate metal 18S is added to the source / light-shielding film contact portion to further relax the step is shown. The gate metal 18S can be formed simultaneously in the step of forming the gate metal (gate electrode) 18G in the source / gate contact portion. In this case, opening of the gate oxide film 16 is necessary before the step of forming the gate metal 18S, but the opening can be performed by, for example, a photoresist forming step and a wet etching step.

The sum of the thickness of the gate metal 18S and the thickness of the first source metal 24S is the sum of the thickness of the gate metal 18G, the thickness of the gate oxide film 16, the thickness of the semiconductor layer 14, and the thickness of the insulating film (barrier layer) 11. In contrast, it is preferably 50% or more. More preferably, it is 70% or more. The upper limit is preferably 150% or less. Further, the total thickness of the gate metal 18S and the first source metal 24S is the thickness of the gate electrode 18G, the thickness of the gate oxide film 16, the thickness of the semiconductor layer 14, and the thickness of the insulating film (barrier layer) 11. It is particularly preferable that the total is substantially the same. Other configurations of the third embodiment are the same as those of the second embodiment described above.

In the circuit board according to the third embodiment, the increase in area when the main surface of the contact hole in the source / gate contact portion with the higher step is viewed in a plan view is suppressed, and the aperture ratio of the circuit board is further increased sufficiently. be able to.

As described above, the circuit boards of Embodiments 1 to 3 described above can be manufactured by a combination of methods usually used in the technical field of the present invention. For example, in the source metal formation method, after forming a source metal layer, a resist is formed by, for example, a mask process, wet etching is performed on the source metal layer, and the source bus line, the source electrode, and the source metal are formed. A drain electrode is formed. Next, the resist on the substrate is removed.
The contact hole can be formed by exposure patterning or the like after depositing a planarization film (organic insulating film) or the like as described above. Note that the inorganic insulating film can be etched by dry etching.

In addition, when the distance between the contact portion having a low step and the contact portion having a high step is separated by a centimeter when the main surface of the substrate is viewed in plan, an additional metal is deposited as in the above-described embodiment. In addition, it is conceivable to solve the problems of the present invention by making the exposure intensity for the higher step difference lower than the exposure intensity for the lower step difference. However, at this time, the exposure for the high opening and the exposure for the low opening are performed at least twice in total. Of course, two photomasks are used. On the other hand, this invention can make an exposure process not complicated.
Furthermore, in the case of the above-described first to third embodiments, when the main surface of the substrate is viewed in plan, the distance between the contact portion having a high step and the contact portion having a low step is several μm. Considering process variations such as thickness, it can be said that such double exposure is impossible in the first place. From this point of view, in the present invention, it is preferable that the distance between the opening having a high step and the opening having a low step is 1 mm or less when the main surface of the substrate is viewed in plan. More preferably, the distance is 10 μm or less.

In a circuit board and a display device (a liquid crystal television or the like), the configuration related to the circuit board and the display device of the present invention can be confirmed by analyzing the TFT substrate of the product.

(Other embodiments)
In the active contact hole portions according to the above-described first to third embodiments, the source metal is stacked, and it is preferable to stack the metal by adding the metal in this way, but the conductor of the active contact hole portion is used as the gate contact hole. The effect of the present invention can be obtained as long as it is thicker than the conductor of the portion.

Further, as in the first embodiment, in the active contact hole portion, the barrier metal 22A, the source metal 24A, the barrier metal 28A, the source metal 30A, and the antireflection metal 32A are laminated in this order from the glass substrate side, and thus laminated. For example, the barrier metal and the antireflection metal may be omitted.

The form of the contact hole according to the first to third embodiments described above can exert the effect of the present invention even when applied to a contact hole in a display region other than the above-described form. A form to which the configuration is applied is also included in the present invention. Further, the present invention is preferably applied to all contact holes in the picture element, but the present invention is applied to at least some of the contact holes in the picture element as long as the effect of increasing the aperture ratio of the circuit board can be exhibited. As long as is applied. Such a contact hole configuration according to the present invention is applicable to, for example, a contact hole in a non-display region such as a scan driver IC or a data driver IC as long as it is applied to at least a part of the contact hole in the display region. It doesn't matter.

As the semiconductor, an oxide semiconductor such as IGZO (In—Ga—Zn—O) can be preferably used in addition to the a-Si (amorphous silicon) semiconductor. Further, it is preferable to use a semiconductor in the contact hole portion according to the present invention, but instead of the semiconductor, a second conductor (metal or the like) may be used like the light shielding film illustrated in the second and third embodiments. The effect of this invention can be exhibited.

In addition, although the circuit board of Embodiments 1-3 can exhibit an advantageous effect when applied to a liquid crystal display device, the display device of the present invention is not limited to this and is organic. An advantageous effect can also be exhibited in EL display devices such as EL display devices and inorganic EL display devices.

In the other embodiments, the configurations other than those described above are the same as the configurations of the first or second embodiment.

(Comparative Example 1)
12 to 16 are schematic cross-sectional views showing one of the manufacturing steps of the circuit board of Comparative Example 1. FIG. 17 is a schematic cross-sectional view showing one alternative form of the circuit board manufacturing process of Comparative Example 1.
The configuration of Comparative Example 1 is that the unpatterned barrier metal 22A and the patterned source metal 24A in the first embodiment are not provided, in other words, the steps S2 to S6 in the first embodiment are not performed. These are the same as the configuration of the first embodiment. In Comparative Example 1, since the step of pre-planarization layer formed between the active contact hole CH _a gate contact hole CH _g is large, the contact holes of the gate contact hole CH _g when forming the contact hole Overexposure, the opening area of the contact hole increases (diameter W ₂ in FIG. 16), and _a resist residue (photoresist 136R in FIG. 17) is generated in the active contact hole portion CHa. Therefore, it is impossible to obtain a circuit board having a sufficiently high aperture ratio while ensuring a sufficient manufacturing yield.

(Comparative Example 2)
18 to 30 are schematic cross-sectional views showing one of the manufacturing steps of the circuit board of Comparative Example 2.

Formation process s1 of the light shielding film 210
FIG. 18 is a schematic cross-sectional view of the circuit board after the light shielding film 210 is formed on the glass substrate 200. In this step, the light shielding film 210 is formed in the photodiode portion. The circuit board after the light shielding film 210 is formed is as shown in FIG. 31 to be described later when the main surface of the board is viewed in plan.

Deposition step s2 of the barrier layer (insulating film layer) 211 and the silicon (Si) semiconductor layer 213
FIG. 19 is a schematic cross-sectional view of the circuit board after performing step s2 of depositing a barrier layer (insulating film layer) 211 and a semiconductor layer 213 from the circuit board shown in FIG.

Patterning step s3 of the semiconductor layer 213
FIG. 20 is a schematic cross-sectional view of the circuit board after the patterning step s3 of the semiconductor layer 213 is further performed from the circuit board shown in FIG. A semiconductor layer 214 is formed on the barrier layer (insulating film layer) 211. The circuit board after patterning the semiconductor layer 213 is as shown in FIG. 32 to be described later when the main surface of the board is viewed in plan.

Deposition step s4 of gate oxide film 216
FIG. 21 shows a step s4 in which a gate oxide film 216 is further deposited from the circuit substrate shown in FIG.
It is a cross-sectional schematic diagram of the circuit board after performing.

Deposition process s5 of gate metal 217
FIG. 22 is a schematic cross-sectional view of the circuit board after performing step s5 of further depositing gate metal 217 from the circuit board shown in FIG.

Patterning step s6 of the gate metal 217
FIG. 23 is a schematic cross-sectional view of the circuit board after performing step s6 of patterning the gate metal 217 from the circuit board shown in FIG. A gate metal 218 is formed on the gate oxide film 216. The circuit board after patterning the gate metal 217 is as shown in FIG. 33 to be described later when the main surface of the board is viewed in plan.

N-type impurity diffusion step s7 for TFT and diode
FIG. 24 shows a state in which a photoresist 226n is further coated from the circuit board shown in FIG. 23, and an N-type impurity is diffused into a part of the semiconductor layer 214 in the TFT and the photodiode portion to form N +. It is a cross-sectional schematic diagram of the circuit board. A portion where the N-type impurity is diffused in the semiconductor layer is denoted as 214n.

P-type impurity diffusion step s8 for TFT and diode
In FIG. 25, the photoresist 226n is further removed from the circuit board shown in FIG. 24, the photoresist 226p is coated, and P-type impurities are diffused in the TFT and the other part of the semiconductor layer 214 in the photodiode portion. It is a cross-sectional schematic diagram of the circuit board after performing process s8 made into P +. In the semiconductor layer, a portion where the P-type impurity is diffused is denoted as 214p. Note that the circuit board after these impurities are diffused is as shown in FIG. 34 to be described later when the main surface of the board is viewed in plan.

Contact hole forming step s9 on the light shielding film 210
FIG. 26 is a schematic cross-sectional view of the circuit board after the step s9 of further removing the photoresist 226p from the circuit board shown in FIG. 25 and forming the contact hole portion CH on the light shielding film 210.

Insulating film 219 deposition step s10
FIG. 27 is a schematic cross-sectional view of the circuit board after performing step s10 of further depositing an insulating film 219 from the circuit board shown in FIG.

Contact hole forming step s11
FIG. 28 is a diagram in which contact holes are further formed from the circuit board shown in FIG. That is, a part of the insulating film 219 on the light shielding film 210 is removed to form the contact hole part CH1, and a part of the insulating film 219 and the gate oxide film 216 on the semiconductor layer 214n is removed to form the contact part CH2n. Then, a part of the insulating film 219 and the gate oxide film 216 on the semiconductor layer 214p is removed to form a contact part CH2p, and a part of the insulating film 219 on the gate metal 218 is removed to form a contact part CH3. . The insulating film after these contact holes are formed is denoted as 220. The circuit board after the contact holes are formed is as shown in FIG. 35 described later when the main surface of the board is viewed in plan.

Source metal 229 deposition step s12
FIG. 29 is a schematic cross-sectional view of the circuit board after performing step s12 of further depositing source metal 229 from the circuit board shown in FIG.

Source metal 229 patterning step s13
FIG. 30 is a schematic cross-sectional view of the circuit board after performing step s12 of patterning the source metal 229 from the circuit board shown in FIG. A source metal 230 is formed on the insulating film 220. The patterned source metal 230 has a shape as shown in FIG. 36 described later when the substrate main surface is viewed in plan.

FIGS. 31 to 36 are schematic plan views illustrating one of the manufacturing steps of the circuit board of Comparative Example 2. FIGS. In addition, some drawings are abbreviate | omitted with respect to the cross-sectional schematic diagram mentioned above.
FIG. 31 is a schematic plan view after the formation process s1 of the light shielding film 210 is completed. FIG. 32 is a schematic plan view of the semiconductor layer 214 formed after the patterning step s3 of the semiconductor layer 213 is completed. FIG. 34 is a schematic plan view after the N-type impurity diffusion step s7 and the P-type impurity diffusion step s8 for the TFT and the diode are completed. FIG. 35 is a schematic plan view after the contact hole forming step s11 is completed. FIG. 36 is a schematic plan view on which the source metal 230 is formed after the patterning step s13 of the source metal 229 is completed.

Comparative Example 2 described above is also for explaining a conventional circuit board having a source / gate contact portion and a source / light-shielding film contact portion as shown in Embodiments 2 and 3 described above. In addition, the first source metal (additionally arranged source metal) and / or the gate metal is modified to provide an organic insulating film on the contact portion of the contact portion, and this is opened. As a result, the second embodiment has the same configuration as that of the first embodiment having the source / gate contact portion and the source / Si contact portion, and has the source / gate contact portion and the source / Si contact portion. 3 is the same configuration. Thereby, the effect similar to what was exhibited in the embodiment mentioned above can be exhibited, and it becomes one of the preferred embodiments of the present invention. Here, the “lower-level contact hole” in which the source metal and / or the gate metal is additionally disposed may be only the contact portion CH1 in the comparative example 2, for example. CH1, the contact part CH2n, and the contact part CH2p are preferable. Further, for example, both the first source metal and the gate metal are provided for the lowest contact portion CH1, and only one of the first source metal or the gate metal is provided for the contact portion CH2n and the contact portion CH2p. The step between the entire contact portions can be further reduced, which is a particularly preferable mode.

10, 210: light shielding films 11, 111, 211: barrier layers 14, 114, 213, 214, 214n, 214p: semiconductor layers 16, 116, 216: gate oxide films 18, 118: gate electrodes 18G, 18S, 217, 218 : Gate metal 20, 120: Interlayer insulating films 21, 22A, 27, 28A, 28G, 127, 128a, 128g: Barrier metal 23, 24A, 24S, 29, 30A, 30G, 130a, 130g: Source metal 25, 26A, 34A, 34G, 134a, 134g, 136R, 226n, 226p: Photoresist 30S: Source metal wiring 31, 32A, 32G: Antireflection metal 35, 36, 135, 136: Planarization film (organic insulating film)
200: Glass substrate 219: Insulating film 229, 230: Source metal CH _A , CH _a : Active contact hole part CH _G , CH _g : Gate contact hole part

Claims (12)

A circuit board having a glass substrate and an insulating film,
The insulating film has at least a first opening and a second opening,
The circuit board has a first conductor that overlaps the first opening, a second conductor or semiconductor that is electrically connected to the first conductor, and a second opening when the main surface of the board is viewed in plan A third conductor, and a fourth conductor electrically connected to the third conductor,
The layer provided with the second conductor or semiconductor is closer to the glass substrate than the layer provided with the fourth conductor,
The circuit board, wherein the first conductor is thicker than the third conductor. The circuit board according to claim 1, wherein the first conductor is laminated more than the third conductor. The first conductor includes a plurality of layers of source metal,
The circuit board according to claim 1, wherein the third conductor includes a single-layer source metal. The circuit board is an array substrate having thin film transistor elements,
The thin film transistor element includes a gate electrode, a source electrode, a drain electrode, and a semiconductor,
The circuit board according to claim 1, wherein the fourth conductor is a gate electrode. The circuit board has at least a fourth conductor between the layer provided with the second conductor or the semiconductor and the layer provided with the third conductor when the circuit board is viewed in cross section. 5. A circuit board according to claim 1, further comprising a gate oxide film. The circuit board includes at least a fourth conductor and a gate between the layer provided with the second conductor and the layer provided with the third conductor when the circuit board is viewed in cross section. The circuit board according to claim 5, wherein an oxide film, a semiconductor, and an insulating film are provided. The circuit board according to claim 1, wherein the second conductor is a light shielding film. The circuit board is further provided with a planarization film,
The planarization film is provided with an opening so as to overlap with the first opening when the main surface of the substrate is viewed in plan, and with an opening so as to overlap with the second opening. The circuit board according to claim 1, wherein the circuit board is characterized in that The circuit board according to claim 8, wherein a diameter of the opening of the planarizing film is 8 μm or less. The circuit board according to claim 4, wherein the second conductor or the semiconductor is a semiconductor of the thin film transistor element. A method of manufacturing a circuit board having a glass substrate and an insulating film,
The method of manufacturing the circuit board includes a step of forming a second conductor or a semiconductor,
Forming an insulating film;
Forming a fourth conductor;
Forming a first conductor electrically connected to the second conductor or the semiconductor and forming a third conductor electrically connected to the fourth conductor;
Forming a planarization film, and
A step of opening a region overlapping with the first conductor of the planarization film by exposure and a region overlapping with the third conductor of the planarization film,
The first conductor is thicker than the third conductor,
The exposure time for opening the region overlapping the first conductor of the planarization film is the same as the exposure time for opening the region overlapping the third conductor of the planarization film. A method for manufacturing a circuit board. A display device comprising the circuit board according to claim 1 or the circuit board obtained by the method for manufacturing a circuit board according to claim 11.

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