JP2013162391A - Multistage amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multistage amplifier that effectively suppresses a gain in a low frequency band and suppresses occurrence of oscillation by increasing a loss of a drain bias loop in the low frequency band.SOLUTION: A bias loop 17 is formed via output matching circuits 4, 6 that apply bias voltages to output terminals of amplification elements 1, 2. The output matching circuits 4, 6 each include: parallel circuits 25, 26 comprising inductors 18, 19 connected in series with the bias loop 17, and first capacitors 20, 21 connected in parallel with the inductors 18, 19; and a series circuit 24 comprising a resistance 22 and a second capacitor 23, and having one end connected to corresponding ends of the parallel circuits 25, 26 and the other end grounded. Values of the component elements 18, 19, 20, 21, 22, 23 are set such that a loss of the bias loop 17 is greater than a gain of the amplification elements 1, 2 in a frequency band lower than an operating frequency of the amplification elements 1, 2.

Description

  The present invention relates to a multistage amplifier used for amplification of a high-frequency signal.

  In conventional multi-stage amplifiers used for amplifying general high-frequency signals, the DC component is blocked so that the bias voltage to the field effect transistor (hereinafter abbreviated as FET), which is an amplifying element, does not leak to adjacent FETs. Are loaded in series between the input matching circuit and the output matching circuit.

  In recent years, newly developed wide bandgap semiconductor FETs such as GaN (gallium nitride) are compared to GaAs (gallium arsenide) FETs, which generally use a gain in the low frequency band (several hundred MHz or less). Therefore, an effective solution for increasing the loss of the drain bias loop in the low frequency band is desired.

  In general, in a multistage amplifier, a bias voltage is applied to the drain of an FET from a bias power supply common to each stage. At this time, a drain bias loop is formed between the drain and gate of the second and subsequent FETs via an output matching circuit for the FET, an output matching circuit for the previous FET, and a capacitor for blocking DC components. The When the loss of the drain bias loop is smaller than the gain of the FET, the signal leaked to the drain bias loop becomes infinitely large and may oscillate.

  The output matching circuit constituting the drain bias loop passes a low frequency band component including a DC bias voltage and cuts off a high frequency band component including an operating frequency of the FET. Therefore, the loss of the drain bias loop becomes large for this high frequency band component. On the other hand, since the fundamental wave of the pulse component on which the operating frequency of the FET is superimposed is sufficiently lower than the operating frequency of the FET, the loss of the drain bias loop becomes small for such a low frequency band component.

  As a technique for cutting off the low frequency band component, for example, an RC series circuit comprising a resistor having one end connected to a bias supply terminal and a capacitor having one end connected to the other end of the resistor and the other end grounded Discloses a technique for configuring a low-frequency band cutoff circuit (for example, Patent Document 1).

JP 2001-136035 A

  However, in the above prior art, the cutoff frequency of the low frequency band cutoff circuit cannot be arbitrarily set. Therefore, depending on the gain of the FET and its frequency characteristics, the loss of the drain bias loop is lower than the gain of the FET in the low frequency band. There is a problem that the frequency band component becomes small and the low frequency band component cannot be sufficiently attenuated, and the occurrence of oscillation cannot be sufficiently suppressed.

  The present invention has been made in view of the above, and it is possible to increase the loss of the drain bias loop in the low frequency band and effectively suppress the occurrence of oscillation by effectively suppressing the gain in the low frequency band. An object of the present invention is to provide a multistage amplifier.

  In order to solve the above-described problems and achieve the object, a multistage amplifier according to the present invention includes an output matching circuit in which a plurality of stages of amplification elements are connected in multiple stages and a bias voltage is applied to an output terminal of the amplification element, A multi-stage amplifier in which a bias loop is formed via the output matching circuit of each stage, wherein the output matching circuit includes an inductor connected in series to the bias loop and a first capacitor connected in parallel to the inductor. A parallel circuit including a resistor and a second capacitor, one end of which is connected to one end of the parallel circuit and the other end of which is grounded, and the parallel circuit forms a resonance circuit. , The inductance value of the inductor, the capacitance value of the first capacitor and the second capacitor, and the resistance value of the resistor, In frequency band lower than the operating frequency of the wide element, losses of the bias loop, characterized in that it is set to be larger than the gain of the amplifying element.

  According to the present invention, it is possible to increase the loss of the drain bias loop in the low frequency band, and effectively suppress the gain in the low frequency band to suppress the occurrence of oscillation.

FIG. 1 is a diagram of a configuration example of a multistage amplifier according to the first embodiment. FIG. 2 is a diagram illustrating an example of drain bias loop loss characteristics of the multistage amplifier according to the first embodiment. FIG. 3 is a diagram of a configuration example of the multistage amplifier according to the second embodiment. FIG. 4 is a diagram illustrating an example of drain bias loop loss characteristics of the multistage amplifier according to the second embodiment.

  A multistage amplifier according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In addition, this invention is not limited by embodiment shown below.

Embodiment 1 FIG.
FIG. 1 is a diagram of a configuration example of a multistage amplifier according to the first embodiment. As shown in FIG. 1, the multistage amplifier according to the first embodiment includes an amplification element 1, an amplification element 2, an input matching circuit 3 for the amplification element 1, an output matching circuit 4 for the amplification element 1, and an amplification element 2. Input matching circuit 5, output matching circuit 6 for amplifier 2, and DC component blocking capacitors 7, 8, 9. Note that GaAs (gallium arsenide) FETs are generally used as the amplifying elements 1 and 2, and in particular, GaN (gallium nitride) or the like having a higher gain in a low frequency band (several hundred MHz or less) than GaAs FETs. In the present embodiment, an effective solution for increasing the loss of the drain bias loop in the low frequency band is desired. In this embodiment, an example using the wide band gap semiconductor FET will be described. .

  The amplification element 1 has a source terminal (not shown) grounded, and the gate (input) terminal (G) of the amplification element 1 has an impedance when the amplification element 1 is viewed from the input terminal side of the multistage amplifier. Are connected to an input terminal of a multistage amplifier via a DC component blocking capacitor 7.

  The amplification element 2 has a source terminal (not shown) grounded in the same manner as the amplification element 1, and the drain (output) terminal (D) of the amplification element 2 is seen from the amplification element 2 to the output terminal side of the multistage amplifier. The output impedance matching circuit 6 is connected so as to optimize the impedance with respect to the amplifying element 2, and is connected to the output terminal of the multistage amplifier via the DC component blocking capacitor 9.

  The drain (output) terminal (D) of the amplifying element 1 and the gate (input) terminal (G) of the amplifying element 2 are connected via a DC component blocking capacitor 8, and the amplifying element 1 and the amplifying element 2 are connected to each other. The output matching circuit 4 is connected to the connection point between the drain (output) terminal (D) of the amplifying element 1 and the DC component blocking capacitor 8 so that the impedance relationship is optimal, and the gate (input) terminal ( An input matching circuit 5 is connected to a connection point between G) and the DC component blocking capacitor 8.

  Each input matching circuit 3, 5 also serves as a bias circuit to the gate (input) terminal (G) of each amplification element 1, 2, and one end is the gate (input) terminal (G) of each amplification element 1, 2. And a capacitor 11 having one end connected to the other end of the inductor 10 and the other end grounded. Connection points Vg1 and Vg2 between the inductor 10 and the capacitor 11 are gate power supplies (not shown). And a gate bias voltage is applied to each.

  Each of the output matching circuits 4 and 6 also serves as a bias circuit for the drain (output) terminal (D) of each of the amplifying elements 1 and 2, and one end is a gate (input) terminal ( G), the inductor 12 connected to the other end of the inductor 12, one end connected to the other end of the inductor 12, the other end grounded, and the one end connected to the connection point between the inductor 12 and the capacitor 13 in the low frequency band cutoff. A circuit 14 and a capacitor 15 having one end connected to the other end of the low-frequency band cutoff circuit 14 and the other end grounded, and the connection points Vd1 and Vd2 between the low-frequency band cutoff circuit 14 and the capacitor 15 are drain power supplies 16 and a drain bias voltage is applied to each.

  Next, the operation of each part of the multistage amplifier according to the embodiment will be described. Each of the input matching circuits 3 and 5 and each of the output matching circuits 4 and 6 allows a DC bias voltage from the drain power supply 16 or the gate power supply to pass therethrough, and the desired amplification element 1 or 2 to the drain power supply 16 or the gate power supply. Blocks high frequency band components including operating frequency.

  Here, paying attention to the amplifying element 2, the output matching circuit 6, the output matching circuit 4, and the DC component blocking capacitor are disposed between the drain (output) terminal (D) and the gate (input) terminal (G) of the amplifying element 2. 8, a drain bias loop (hereinafter simply referred to as “bias loop”) 17 is formed. As described above, when the loss of the bias loop 17 is smaller than the gain of the amplifying element 2, the low frequency band component leaked to the bias loop 17 may become infinite and oscillate. In particular, when a wide bandgap semiconductor FET such as GaN is used as each amplification element 1 or 2, the gain of the low frequency band (several hundred MHz or less) is large. There is a need for an effective solution to increase the bias loop loss in lower frequency bands.

  Therefore, in the present embodiment, the low frequency band cutoff circuit 14 is provided in the output matching circuits 4 and 6 forming the bias loop 17 as an effective solution for increasing the loss of the bias loop 17 in the low frequency band. Hereinafter, the low frequency band cutoff circuit 14 will be described.

  The low-frequency band cut-off circuit 14 includes two parallel circuits including inductors 18 and 19 connected in series to the bias loop 17 and first capacitors 20 and 21 connected in parallel to the two inductors 18 and 19, respectively. 25 and 26, and a series circuit 24 that includes a resistor 22 and a second capacitor 23, one end of which is connected to the connection point of the inductors 18 and 19 and the other end is grounded.

  In the present embodiment, the parallel circuits 25 and 26 are configured and function as a resonance circuit that resonates at an arbitrary low frequency. The equation for calculating the resonance frequency fc of the resonance circuit is expressed by the following equation (1), where L is the inductance value of the inductors 18 and 19 and C is the capacitance value of the first capacitors 20 and 21.

  fc = 1 / (2π (√LC)) (1)

  The inductance values of the inductors 18 and 19 and the first capacitors 20 and 21 are set so that the loss of the bias loop 17 in the low frequency band exceeds the gain of the amplification element 2 according to the frequency characteristics of the low frequency gain of the amplification element 2. , The capacitance value of the second capacitor 23, and the resistance value of the resistor 22 are set. As a result, the gain in the low frequency band of the entire multistage amplifier is effectively suppressed, and the occurrence of oscillation is suppressed.

  The capacitors 11 of the input matching circuits 3 and 5 may be arbitrarily set, for example, to suppress the high frequency band including a desired operating frequency. Each of the capacitors 13 and 15 may be arbitrarily set, for example, one of which is a value for suppressing a high frequency band including a desired operating frequency and the other is a value for suppressing a frequency band of several MHz or more. . The present invention is not limited by the method of setting the capacitance values of these capacitors 11, 13, and 15.

  FIG. 2 is a diagram illustrating an example of drain bias loop loss characteristics of the multistage amplifier according to the first embodiment. In FIG. 2, the horizontal axis indicates the frequency, and the vertical axis indicates the drain bias loop loss. In the example shown in FIG. 2, an example in which a wide band gap semiconductor FET is used as the amplifying elements 1 and 2 is shown. Further, in the example shown in FIG. 2, an example is shown in which the resonance points of the two parallel circuits 25 and 26 are set to different low frequencies. In FIG. 2, a hatched region above the dotted line in the drawing indicates a region where the drain bias loop loss is smaller than the gain of the amplifying element 2, that is, an oscillation region where oscillation occurs. The dotted line that separates this oscillation region from the region below it is hereinafter referred to as an “oscillation boundary line”.

  As shown in FIG. 2, when the configuration according to the present embodiment is applied, the drain bias loop loss can be made larger than the gain of the amplifying element 2 even in the low frequency band, and the drain bias loop loss characteristic line is Below the oscillation boundary.

  As described above, in the configuration according to the present embodiment, even when a wide band gap semiconductor FET is used, the drain bias loop loss in the low frequency band can be effectively increased, and the low frequency band of the entire multistage amplifier can be increased. Can effectively suppress the occurrence of oscillation.

  In the example shown in FIG. 1, two parallel circuits 25 and 26 are formed by the inductors 18 and 19 and the first capacitors 20 and 21 connected in parallel to the two inductors 18 and 19, respectively. The example in which each of the two parallel circuits 25 and 26 functions as a resonance circuit has been described. However, the number of parallel circuits that function as a resonance circuit is not limited to this, and according to the frequency characteristics of the low frequency gain of the amplifying element 2, 1 It may be one or more than two. In the example shown in FIG. 2, the example in which the resonance points of the two parallel circuits 25 and 26 are set to different low frequencies has been described. However, the resonance points of a plurality of parallel circuits can be the same, When three or more parallel circuits are provided, different low frequencies may be used as resonance points.

  As described above, according to the multistage amplifier of the first embodiment, when a bias loop is formed via an output matching circuit that applies a bias voltage to the output terminals of a plurality of amplifying elements, this output matching circuit A parallel circuit including an inductor connected in series to the bias loop and a first capacitor connected in parallel to the inductor, a resistor and a second capacitor, and one end connected to one end of the inductor. And a parallel circuit constituted by an inductor and a first capacitor function as a resonance circuit, and in a frequency band lower than the operating frequency of the amplifying element, the loss of the bias loop is larger than the gain of the amplifying element. So that the inductance value of the inductor, the capacity of the first capacitor and the second capacitor Drawers value, and since so as to set the resistance value of the resistor, the gain of the low frequency band of the overall multi-stage amplifier effectively suppressed to be able to suppress the occurrence of oscillation.

Embodiment 2. FIG.
FIG. 3 is a diagram of a configuration example of the multistage amplifier according to the second embodiment. In addition, the same code | symbol is attached | subjected to the component which is the same as that of Embodiment 1, or equivalent, and the detailed description is abbreviate | omitted.

  As shown in FIG. 3, in the multistage amplifier according to the second embodiment, the inductors 18 and 19 of the parallel circuits 25 and 26 described in the first embodiment are referred to as first inductors 18 and 19 and are replaced with the series circuit 24. A series circuit 28 including a second inductor 27, a resistor 22, and a second capacitor 23, one end of which is connected to the connection point of the first inductors 18 and 19 and the other end of which is grounded. The low frequency band cut-off circuit 29 formed by the circuit 26 and the series circuit 28 is configured and functioned as a band rejection filter that removes an arbitrary low frequency.

  The inductance values of the first inductors 18 and 19 and the second inductor 27 are set so that the loss of the bias loop 17 in the low frequency band exceeds the gain of the amplification element 2 in accordance with the frequency characteristics of the low frequency gain of the amplification element 2. , The capacitance values of the first capacitors 20 and 21, the capacitance value of the second capacitor 23, and the resistance value of the resistor 22 are calculated and set based on the characteristic calculation formula of the band rejection filter. Thereby, unnecessary resonance of the first inductors 18 and 19, the second inductor 27, the first capacitors 20 and 21, the second capacitor 23, and the resistor 22 can be avoided, and compared with the first embodiment, it has a wider bandwidth. Good characteristics can be obtained.

  The capacitors 11 of the input matching circuits 3 and 5 may be arbitrarily set, for example, as a value that suppresses a high frequency band including a desired operating frequency, as in the first embodiment. For each of the capacitors 13 and 15 of the output matching circuits 4 and 6, as in the first embodiment, for example, one of them is a value that suppresses a high frequency band including a desired operating frequency, and the other is several MHz or more. Any value may be set, such as a value for suppressing the frequency band. The present invention is not limited by the method of setting the capacitance values of these capacitors 11, 13, and 15.

  FIG. 4 is a diagram illustrating an example of drain bias loop loss characteristics of the multistage amplifier according to the second embodiment. In FIG. 4, the horizontal axis indicates the frequency, and the vertical axis indicates the drain bias loop loss. In the example shown in FIG. 4, an example in which a wide band gap semiconductor FET is used as the amplifying elements 1 and 2 is shown. Also in FIG. 4, as in the example shown in FIG. 2 in the first embodiment, the drain bias loop loss in the region indicated by the oblique line above the oscillation boundary indicated by the dotted line in FIG. This shows a region smaller than the gain, that is, an oscillation region where oscillation occurs.

  As shown in FIG. 4, when the configuration according to the present embodiment is applied, the drain bias loop loss in the low frequency band is amplified more than when the configuration according to the first embodiment is applied (see FIG. 2). It can be made sufficiently larger than the gain of the element 2, and the drain bias loop loss characteristic line is greatly below the oscillation boundary line.

  As described above, in the configuration according to the present embodiment, even when a wide band gap semiconductor FET is used, unnecessary resonance of each component forming the low frequency band cutoff circuit 29 can be avoided. Compared to the above, good characteristics can be obtained in a wide band.

  In the example shown in FIG. 3, two parallel circuits 25 and 26 are formed by the first inductors 18 and 19 and the first capacitors 20 and 21 connected in parallel to the two first inductors 18 and 19, respectively. Although the example to form was demonstrated, the number of parallel circuits is not restricted to this, One or three or more may be sufficient according to the frequency characteristic of the low frequency gain of the amplification element 2. FIG.

  In the example illustrated in FIG. 3, the example in which the number of the low-frequency band cutoff circuits 29 that function as a band rejection filter is one is described. However, the number of the low-frequency band cutoff circuits 29 is not limited to this, and two or more. It is also possible to make the removal frequency of each band rejection filter constituted by the plurality of low frequency band cutoff circuits 29 the same, or to set different removal frequencies. Is possible.

  As described above, according to the multistage amplifier of the second embodiment, when a bias loop is formed via an output matching circuit that applies a bias voltage to the output terminals of a plurality of amplifying elements, this output matching circuit A parallel circuit including a first inductor connected in series to the bias loop and a first capacitor connected in parallel to the inductor, a second circuit including a second inductor, a resistor, and a second capacitor, one end of which is A series circuit connected to one end of one inductor and grounded at the other end, and a low frequency band cut-off circuit formed by the parallel circuit and the series circuit functions as a band rejection filter, which is lower than the operating frequency of the amplifying element In the frequency band, the first inductor and the second inductor are arranged so that the loss of the bias loop is larger than the gain of the amplifying element. Since the inductance value of the inductor, the capacitance value of the first capacitor and the second capacitor, and the resistance value of the resistor are calculated and set based on the characteristic calculation formula of the band rejection filter, a low frequency band cutoff circuit is formed. As compared with the first embodiment, it is possible to avoid unnecessary resonance of each component to be obtained, to obtain a good characteristic in a wide band, and to more effectively suppress a gain in a low frequency band as a whole multistage amplifier. Oscillation can be further suppressed.

  Note that the configuration according to the above-described embodiment can effectively suppress the low frequency band gain of the entire multistage amplifier and suppress the occurrence of oscillation, so that the low frequency band gain is high. It is suitable for use in a multistage amplifier to which a wide band gap semiconductor FET is applied. An FET formed of a wide band gap semiconductor has a high voltage resistance and a high allowable current density, so that the amplifying element can be miniaturized. Furthermore, the wide band gap semiconductor has a characteristic of high power efficiency. In other words, by configuring the amplifying element of the multistage amplifier according to the embodiment with a wide bandgap semiconductor FET, it is possible to further mount the circuit at a higher density and to reduce the size and efficiency of the multistage amplifier.

  Although all the amplifying elements of the multistage amplifier are preferably configured by wide band gap semiconductor FETs, any one of the amplifying elements constituting the multistage amplifier may be configured by wide band gap semiconductor FETs. Further, although gallium nitride has been described as an example of the material of the wide band gap semiconductor FET, silicon carbide or diamond may be used, and the effects described in the embodiment can be obtained.

  In addition, each capacitor, each inductor, resistor, and the like in the above-described embodiment may be configured using chip parts or the like, or may be formed using a pattern on the substrate. If each capacitor is formed using a pattern on the substrate, the circuit scale becomes large, and if the inductor is composed of chip parts or the like, the allowable current amount is small. May not meet quantity. Therefore, it is preferable that each capacitor is constituted by a chip part and each inductor has a configuration in which an inductive line is formed using a pattern on the substrate.

  In addition, each inductor can be configured using various wiring materials such as a wire, a ribbon wire, or a Teflon (registered trademark) wire.

  If the capacitor connected in series to the drain bias loop (eg, the DC component blocking capacitor 8 in the example shown in FIG. 1 of the first embodiment) is configured by a chip component or the like, the electrode of this capacitor needs to be grounded. In addition, since a bias voltage is not directly applied, it is possible to configure the chip component with a low breakdown voltage and a small size.

  In addition, when an inductor connected in series with the drain bias loop (inductors 18 and 19 in the example shown in FIG. 1 of the first embodiment) is formed using a pattern on a substrate and resonated at about several hundred MHz. For example, when a ceramic substrate having a relative dielectric constant εr = 9.8 is used, it can be formed by an inductive line having a length of about 20 mm. As for the line width, if a ceramic substrate having a thickness of 1 mm is used, an impedance exceeding 70Ω can be obtained with a line width of 0.4 mm. For this reason, as the amplifying element, for example, a wide bandgap semiconductor FET such as GaN that has a high drain voltage and is operated by, for example, class F operation to reduce the drain current for high efficiency, is used. When a multistage amplifier is constructed, it is possible to form a thin inductive line as described above.

  Note that the configuration shown in the above embodiment is an example of the configuration of the present invention, and can be combined with another known technique, and a part thereof is omitted without departing from the gist of the present invention. Needless to say, it is possible to change the configuration.

1,2 Amplifier (FET)
3 Input matching circuit (for amplifying element 1)
4 Output matching circuit (for amplifying element 1)
5 Input matching circuit (for amplifying element 2)
6 Output matching circuit (for amplifying element 2)
7, 8, 9 DC component blocking capacitor 10, 12 Inductor 11, 13, 15 Capacitor 14 Low frequency band blocking circuit 16 Drain power supply 17 Bias loop
18, 19 Inductor (first inductor)
20, 21 First capacitor 22 Resistor 23 Second capacitor 24, 28 Series circuit 25, 26 Parallel circuit 27 Second inductor

Claims (4)

A multi-stage amplifier in which a plurality of stages of amplifying elements are connected in multi-stages, an output matching circuit for applying a bias voltage to the output terminal of the amplifying element is provided, and a bias loop is formed via the output matching circuit of each stage. ,
The output matching circuit includes:
A parallel circuit including an inductor connected in series to the bias loop and a first capacitor connected in parallel to the inductor;
A series circuit including a resistor and a second capacitor, one end connected to one end of the parallel circuit and the other end grounded;
With
A resonance circuit is formed by the parallel circuit, and an inductance value of the inductor, a capacitance value of the first capacitor and the second capacitor, and a resistance value of the resistor are in a frequency band lower than an operating frequency of the amplification element, The multistage amplifier, wherein a loss of the bias loop is set to be larger than a gain of the amplifying element. A multi-stage amplifier in which a plurality of stages of amplifying elements are connected in multi-stages, an output matching circuit for applying a bias voltage to the output terminal of the amplifying element is provided, and a bias loop is formed via the output matching circuit of each stage. ,
The output matching circuit includes:
A parallel circuit including an inductor connected in series to the bias loop and a first capacitor connected in parallel to the inductor;
A series circuit including a second inductor, a resistor, and a second capacitor, one end connected to one end of the parallel circuit and the other end grounded;
With
A band rejection filter is formed by the parallel circuit and the series circuit, and an inductance value of the first inductor and the second inductor, a capacitance value of the first capacitor and the second capacitor, and a resistance value of the resistor are: The multistage amplifier, wherein a loss of the bias loop is set to be larger than a gain of the amplifying element in a frequency band lower than an operating frequency of the amplifying element.   3. The multistage amplifier according to claim 1, wherein at least one of the amplification elements in a plurality of stages is a wide band gap semiconductor FET.   4. The multistage amplifier according to claim 3, wherein the wide band gap semiconductor FET is formed of a gallium nitride-based material, silicon carbide, or diamond.

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