JP2013160913A5 - Signal transmission path - Google Patents

Signal transmission path Download PDF

Info

Publication number
JP2013160913A5
JP2013160913A5 JP2012022346A JP2012022346A JP2013160913A5 JP 2013160913 A5 JP2013160913 A5 JP 2013160913A5 JP 2012022346 A JP2012022346 A JP 2012022346A JP 2012022346 A JP2012022346 A JP 2012022346A JP 2013160913 A5 JP2013160913 A5 JP 2013160913A5
Authority
JP
Japan
Prior art keywords
conductor layer
dielectric substrate
signal transmission
mounting member
transmission path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012022346A
Other languages
Japanese (ja)
Other versions
JP2013160913A (en
JP5967518B2 (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2012022346A priority Critical patent/JP5967518B2/en
Priority claimed from JP2012022346A external-priority patent/JP5967518B2/en
Publication of JP2013160913A publication Critical patent/JP2013160913A/en
Publication of JP2013160913A5 publication Critical patent/JP2013160913A5/en
Application granted granted Critical
Publication of JP5967518B2 publication Critical patent/JP5967518B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Description

本発明は、信号伝送路に関し、例えば、信号伝送路における不要スプリアスを抑制する信号伝送路に関する。 The present invention relates to a signal transmission line , for example, a signal transmission line that suppresses unnecessary spurious in the signal transmission line .

本発明は、第1搭載部材と、空間を挟んで前記第1搭載部材と離れて配置された第2搭載部材と、前記第1搭載部材と前記第2搭載部材との間を前記空間上で橋渡しして配置された誘電体基と、前記誘電体基体の上面に形成された信号線路と、前記誘電体基体の下面に形成され、基準電位を有する第1導電層と、前記第1導電層と電気的に接続され、前記誘電体基体の側面に形成された第2導電体層と、前記第1導電体層と電気的に接続されるパッドと、を具備することを特徴とする信号伝送路である。本発明によれば、信号伝送路における不要スプリアスを抑制することができる。 The present invention provides a first mounting member, a second mounting member that is spaced apart from the first mounting member across a space, and the space between the first mounting member and the second mounting member on the space. a dielectric base body arranged bridging, the signal line formed on the upper surface of the dielectric substrate, formed on the lower surface of the dielectric substrate, a first conductor layer having a reference potential, said first A second conductor layer electrically connected to the conductor layer and formed on a side surface of the dielectric substrate ; and a pad electrically connected to the first conductor layer. This is a signal transmission path. According to the present invention, unnecessary spurious in the signal transmission path can be suppressed.

Claims (5)

第1搭載部材と、
空間を挟んで前記第1搭載部材と離れて配置された第2搭載部材と、
前記第1搭載部材と前記第2搭載部材との間を前記空間上で橋渡しして配置された誘電体基と、
前記誘電体基体の上面に形成された信号線路と、
前記誘電体基体の下面に形成され、基準電位を有する第1導電層と、
前記第1導電層と電気的に接続され、前記誘電体基体の側面に形成された第2導電体層と、
前記第1導電体層と電気的に接続されるパッドと、
を具備することを特徴とする信号伝送路。
A first mounting member;
A second mounting member disposed away from the first mounting member across a space;
A dielectric base body arranged to bridge over the space between said first mounting member and the second mounting member,
A signal line formed on the upper surface of the dielectric substrate;
Wherein formed on the lower surface of the dielectric substrate, a first conductor layer having a reference potential;
Said first conductor layer and is electrically connected to a second conductor layer formed on the side surface of the dielectric substrate,
A pad electrically connected to the first conductor layer;
A signal transmission path comprising:
前記信号線路と前記第2導電体層は、前記誘電体基体の上面において平行して配置されてなり、前記誘電体基体の上面における前記信号線路と前記第2導電体層との間の距離は、前記信号線路の幅より大きいことを特徴とする請求項1記載の信号伝送路。   The signal line and the second conductor layer are arranged in parallel on the upper surface of the dielectric substrate, and the distance between the signal line and the second conductor layer on the upper surface of the dielectric substrate is 2. The signal transmission line according to claim 1, wherein the signal transmission line is larger than a width of the signal line. 前記誘電体基体の幅は、前記誘電体基体内における伝送信号波長の1/6以下であることを特徴とする請求項1または2記載の信号伝送路。   3. The signal transmission path according to claim 1, wherein the width of the dielectric substrate is 1/6 or less of a transmission signal wavelength in the dielectric substrate. 前記誘電体基体を上下に貫通し、前記パッドと前記第1導電体層とを電気的に接続するビア配線を具備することを特徴とする請求項1から3のいずれか一項記載の信号伝送路。 Said dielectric substrate and a vertically penetrating, signal transmission according to any one claim of claims 1 to 3, characterized by including the via wiring to electrically connect the pad and the first conductor layer Road. 前記パッドの一辺は、前記第2導電体層と接することを特徴とする請求項1から3のいずれか一項記載の信号伝送路。 One side of the pad, the signal transmission path according to one of claims 1 to 3, characterized in that contact with the second conductor layer.
JP2012022346A 2012-02-03 2012-02-03 Signal transmission path Active JP5967518B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012022346A JP5967518B2 (en) 2012-02-03 2012-02-03 Signal transmission path

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012022346A JP5967518B2 (en) 2012-02-03 2012-02-03 Signal transmission path

Publications (3)

Publication Number Publication Date
JP2013160913A JP2013160913A (en) 2013-08-19
JP2013160913A5 true JP2013160913A5 (en) 2015-03-05
JP5967518B2 JP5967518B2 (en) 2016-08-10

Family

ID=49173200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012022346A Active JP5967518B2 (en) 2012-02-03 2012-02-03 Signal transmission path

Country Status (1)

Country Link
JP (1) JP5967518B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5981466B2 (en) * 2014-01-10 2016-08-31 古河電気工業株式会社 Planar transmission line waveguide converter

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02113702A (en) * 1988-10-24 1990-04-25 Mitsubishi Electric Corp Microstrip line
JPH10200311A (en) * 1997-01-14 1998-07-31 Nec Corp Coplanar waveguide line with back ground conductor
JP2004064459A (en) * 2002-07-30 2004-02-26 Sumitomo Metal Electronics Devices Inc Transmission line substrate for high frequency and method for manufacturing same
JP2008147757A (en) * 2006-12-06 2008-06-26 Sumitomo Metal Electronics Devices Inc High-frequency signal transmission substrate
JP2011129592A (en) * 2009-12-15 2011-06-30 Sumitomo Electric Ind Ltd Optical semiconductor device

Similar Documents

Publication Publication Date Title
TW201613053A (en) Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication
JP2013225610A5 (en)
ATE497223T1 (en) INSERTS WITH DOUBLE INTERFACE
JP2014082455A5 (en) Flexible substrate, substrate connection structure, and optical module
JP2013211537A5 (en)
JP2013186030A5 (en)
AR086303A1 (en) WINDSHIELD WITH AN ELECTRICAL CONNECTION ELEMENT
HK1129950A1 (en) Surface mountable lightemitting element
JP2016039365A5 (en)
JP2013042117A5 (en)
WO2015015319A3 (en) Architecture of spare wiring structures for improved engineering change orders
JP2016092414A5 (en)
JP2012256741A5 (en)
WO2011112409A3 (en) Wiring substrate with customization layers
JP2009278072A5 (en)
JP2014150102A5 (en)
WO2014053350A3 (en) Pressure sensor comprising a cover layer
JP2014165238A5 (en)
JP2014150150A5 (en) Semiconductor package and electronic equipment
JP2013073882A5 (en)
GB2532869A (en) Semiconductor die and package jigsaw submount
JP2013219348A5 (en)
JP2009044154A5 (en)
JP2013160913A5 (en) Signal transmission path
JP2014107398A5 (en)