JP2013156817A - Verification method, verification program and verification device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily discriminate between a pseudo error and a true error.SOLUTION: A verification device 1 includes a formation unit 1a for forming evaluation lines 7a-7d to identify whether it is a violation of a verification object on the basis of the shapes of mask patterns 2b-2e including a place in violation of a layout design rule, and a determination unit 1b that determines the presence or absence of interference of the evaluation lines 7a-7d formed by the formation unit 1a, and outputs the determination results.

Description

  The present invention relates to a verification method, a verification program, and a verification apparatus.

  When manufacturing a semiconductor integrated circuit, it is known to use a mask pattern subjected to optical proximity correction (OPC) or super resolution technology (RET).

  The mask pattern that has undergone these processes has a shape different from the pattern shape of the finished product designed by the designer, and has been subjected to OPC process to confirm the validity of the OPC process and transfer to the mask or wafer. The pattern is verified using a design rule check (DRC) or the like for the subsequent mask pattern.

JP 2009-14790 A

  In some cases, the designer dares to perform a design that violates the design rule check for convenience of design. In this case, when the design rule check is executed, in addition to an error with a design problem that is not intended by the designer (true error), an error with respect to the design that is violated by the design rule check but executed by the designer, or an OPC process In the subsequent mask pattern, an error that has been regarded as no problem in the past is detected as a pseudo error.

There is a problem that the number of work man-hours increases when processing for discriminating between true errors and pseudo errors is performed by checking all error occurrence locations by visual inspection of the designer.
In one aspect, the present invention aims to easily distinguish between pseudo errors and true errors.

  In order to achieve the above object, a disclosed verification method is provided. This verification method is a method for verifying a mask pattern for substrate exposure that is formed based on design data of a semiconductor device. Whether the computer violates a verification target based on the shape of a mask pattern including a portion that violates a layout design rule. A section for identifying whether or not there is formed, the presence or absence of interference in the formed section is determined, and a determination result is output.

  In one aspect, pseudo errors and true errors can be easily distinguished.

It is a figure which shows the verification apparatus of 1st Embodiment. It is a figure which shows the hardware constitutions of the verification apparatus of 2nd Embodiment. It is a block diagram which shows the function of the verification apparatus of 2nd Embodiment. It is a figure explaining the process of a space | interval type | system | group error process part. It is a figure which shows the setting method of the evaluation point with respect to an interval type | system | group error. It is a figure explaining the production | generation of the evaluation line at the time of a space | interval type | system | group error. It is a figure explaining the determination method of a true error and a pseudo error. It is a figure explaining the process of a line | wire width type | system | group error process part. It is a figure which shows the example which generated the reference point in the edge | side of the mask pattern in which the error generate | occur | produced. It is a figure which shows the setting method of the evaluation point with respect to a line width type | system | group error. It is a figure explaining the determination method of a true error and a pseudo error. It is a flowchart which shows the process of a verification apparatus. It is a figure explaining a modification.

Hereinafter, a verification apparatus according to an embodiment will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a diagram illustrating a verification apparatus according to the first embodiment.

A verification apparatus (computer) 1 according to the first embodiment is an apparatus for verifying a mask pattern for substrate exposure formed based on design data of a semiconductor device.
The verification device 1 includes a formation unit 1a, a determination unit 1b, and a storage unit 1c. The forming unit 1a and the determining unit 1b can be realized by functions provided in a central processing unit (CPU) included in the verification device 1. The storage unit 1c can be realized by a data storage area provided in a RAM (Random Access Memory), a hard disk drive (HDD), or the like included in the verification device 1.

  The forming unit 1a receives, from a storage unit (not shown), information related to the error locations 3a and 3b determined to violate the layout design rule by the design rule check of the mask pattern 2. The error location 3a is a location that is determined not to satisfy the design rule criteria because the distance between the mask patterns 2b and 2c is too close, and the error location 3b is too close to the distance between the mask patterns 2d and 2e. This is where it was determined that the design rule criteria were not met. The error locations 3a and 3b indicate spaces and not mask patterns.

  The forming unit 1a forms the evaluation lines 7a and 7b for the mask patterns 2b and 2c including the error portion 3a that violates the layout design rule, and forms the evaluation lines 7c and 7d for the mask patterns 2d and 2e including the error portion 3b. . The evaluation lines 7a to 7d are partition lines for identifying whether the error is a verification target error (true error or pseudo error). These evaluation lines 7a to 7d are formed based on combinations of corner portions of the mask patterns 2b to 2e. The combination of corners is specified according to the violation type of the layout design rule (the distance between the two mask patterns is too close (interval violation), the width of the mask pattern is too small (line width violation), etc.). In the present embodiment, a case where the violation type of the layout design rule is an interval violation will be described.

  The forming unit 1a sets verification areas 4a and 4b including a mask pattern including error locations 3a and 3b. The set verification areas 4a and 4b are areas for specifying a mask pattern as a determination target of a true error and a pseudo error. As a method for setting the verification regions 4a and 4b, for example, the forming unit 1a forms a square centered on the middle point of the error locations 3a and 3b. Then, the forming unit 1a sets the inside of the formed square as the verification regions 4a and 4b.

  And the formation part 1a sets the reference point 5 in the corner | angular part of the mask patterns 2a-2e including at least one part in the set verification area | region 4a, 4b. Here, the side 2a1 of the mask pattern 2a straddles the verification regions 4a and 4b. In this case, the forming unit 1a sets the reference point 5 at the intersection between the verification region 4a and the side 2a1 and at the intersection between the verification region 4b and the side 2a1, respectively. The sides 2d1 and 2d2 of the mask pattern 2d straddle the verification region 4b. In this case, the forming unit 1a sets the reference point 5 at the intersection of the verification region 4b and the sides 2d1 and 2d2.

  Next, the forming unit 1 a sets an evaluation point 6 in a space near the set reference point 5. The method for setting the evaluation score 6 will be described in detail in the second embodiment. Alternatively, the evaluation point 6 may be set directly without setting the reference point 5.

  Next, the forming unit 1a forms a section that defines a region by connecting the created evaluation points 6 for each combination of corners. Thereby, an evaluation line 7b including the mask pattern 2b is formed in the verification region 4a at a position away from the mask pattern 2b by a predetermined distance. An evaluation line 7a surrounding the mask pattern 2c is formed at a position away from the mask pattern 2c by a predetermined distance. An evaluation line 7c including a portion in the verification region 4b of the mask pattern 2e is formed in the verification region 4b at a position separated from the portion in the verification region 4b of the mask pattern 2e by a predetermined distance. An evaluation line 7d surrounding the mask pattern 2d and the portion in the verification region 4b of the side 2d2 of the mask pattern 2d is formed at a position a predetermined distance away from the portion in the verification region 4b of the side 2d1 of the mask pattern 2d. The

  The determination unit 1b determines whether or not the evaluation lines 7a to 7d formed by the formation unit 1a have interference. In the present embodiment, the evaluation lines 7a and 7b do not interfere with other regions. On the other hand, the evaluation lines 7c and 7d interfere with each other.

  The determination unit 1b does not store the identification information of the mask patterns 2b and 2c located in the vicinity of the evaluation lines 7a and 7b determined not to interfere with each other, and does not store the identification information of the evaluation lines 7c and 7d determined to interfere with each other. The identification information d1 of the mask patterns 2d and 2e located in the vicinity is stored in the storage unit 1c. The determination unit 1b may display the positional relationship between the mask patterns 2d and 2e on a monitor (not shown).

  According to the verification apparatus 1 of the present embodiment, the presence or absence of interference of the evaluation lines 7a to 7d is determined, and when it interferes, it is determined as a true error, and when it does not interfere, it is determined as a pseudo error. . Only the identification information d1 of the mask patterns 2d and 2e related to the true error is stored in the storage unit 1c. As a result, the pseudo error is excluded from the output result, and the designer can efficiently check the error.

  In the present embodiment, the processing method in the case of an interval violation has been described. However, the method of forming an evaluation line and discriminating a pseudo error from a true error based on the presence or absence of interference can also be applied in the case of a line width violation.

Hereinafter, in the second embodiment, the disclosed verification apparatus will be described more specifically.
<Second Embodiment>
FIG. 2 is a diagram illustrating a hardware configuration of the verification apparatus according to the second embodiment.

The entire verification apparatus 10 is controlled by the CPU 101. The CPU 101 is connected to the RAM 102 and a plurality of peripheral devices via the bus 108.
The RAM 102 is used as a main storage device of the verification device 10. The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data used for processing by the CPU 101.

  A hard disk drive 103, graphic processing device 104, input interface 105, drive device 106, and communication interface 107 are connected to the bus 108.

  The hard disk drive 103 magnetically writes data to and reads data from a built-in disk. The hard disk drive 103 is used as a secondary storage device of the verification device 10. The hard disk drive 103 stores an OS program, application programs, and various data. As the secondary storage device, a semiconductor storage device such as a flash memory can be used.

  A monitor 104 a is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 104a in accordance with a command from the CPU 101. Examples of the monitor 104a include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 105 a and a mouse 105 b are connected to the input interface 105. The input interface 105 transmits signals sent from the keyboard 105a and the mouse 105b to the CPU 101. Note that the mouse 105b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The drive device 106 reads data recorded on a portable recording medium such as an optical disc on which data is recorded so as to be readable by reflection of light or a USB (Universal Serial Bus) memory. For example, when the drive device 106 is an optical drive device, data recorded on the optical disc 200 is read using a laser beam or the like. Examples of the optical disc 200 include Blu-ray (registered trademark), DVD (Digital Versatile Disc), DVD-RAM, CD-ROM (Compact Disc Read Only Memory), CD-R (Recordable) / RW (ReWritable), and the like. .

  The communication interface 107 is connected to the network 50. The communication interface 107 transmits / receives data to / from other computers or communication devices via the network 50.

With the hardware configuration as described above, the processing functions of the present embodiment can be realized.
The following functions are provided in the verification apparatus 10 having a hardware configuration as shown in FIG.

FIG. 3 is a block diagram illustrating functions of the verification apparatus according to the second embodiment.
The verification apparatus 10 includes a design target data storage unit 11, an OPC processing unit 12, a DRC verification unit 13, an error verification unit 14, an evaluation point library storage unit 15, a process log storage unit 16, and an error information storage unit. 17.

The design target data storage unit 11 stores design data related to the semiconductor device to be designed.
In the design data, the OPC processing unit 12 uses a correction table that defines a correction amount in accordance with the width of the circuit pattern and the distance to the adjacent circuit pattern. Create a mask pattern.

  The DRC verification unit 13 performs DRC verification on the created mask pattern, and classifies and outputs the location where the error has occurred into an interval error, a line width error, and other errors. Specifically, the DRC verification unit 13 classifies, in the mask pattern, a part that is an error as a result of being determined that the interval between the two mask patterns is too close in the DRC verification, as an interval system error. In addition, the DRC verification unit 13 classifies a portion of the mask pattern that is an error as a result of being determined that the width of the mask pattern is too small in the DRC verification as a line width error. Other errors include errors indicating that the mask pattern itself has disappeared for some reason.

The error verifying unit 14 verifies whether the error portion of the mask pattern classified into the interval error and the line width error is a true error or a pseudo error.
The error verification unit 14 includes an interval system error processing unit 141 and a line width system error processing unit 142.

FIG. 4 is a diagram for explaining processing of the interval error processing unit.
FIG. 4A shows mask patterns 21, 22, 23, 24, and 25 classified as interval-related errors by the DRC verification unit 13. In addition, figures E1 and E2 that identify error portions of the interval errors that occur between the mask patterns 22 and 23 and between the mask patterns 24 and 25 are indicated by dotted lines. The figures E1 and E2 are not mask patterns. The shape of the figure is arbitrary.

  As shown in FIG. 4B, the interval error processing unit 141 sets verification areas A1 and A2 based on error locations E1 and E2. Specifically, the interval error processing unit 141 sets the area of the pitch (one side value) from the midpoint of the figures E1 and E2 to the verification areas A1 and A2. The size of the verification areas A1 and A2 can be arbitrarily set by the user. For example, a value including the line width and interval of the mask pattern, such as a minimum pitch of design rule × 2, is desirable.

  Thereafter, as shown in FIG. 4C, the interval error processing unit 141 creates an evaluation line at the corner portions (corner portions) of the mask patterns 22 to 25 existing inside the generated verification regions A1 and A2. A reference point p1 is set. In FIG. 4C, the reference point p1 is shown as a black point. The reference point p1 is basically placed at the corner portion of the mask pattern 22 in the verification areas A1 and A2, but if the length of the side arbitrarily specified by the user is satisfied, the reference point p1 is also set on the straight side. It is possible to put. For example, the side 211 of the mask pattern 21 straddles the verification area A1. In this case, since the corner portion of the mask pattern 21 does not exist in the verification region A1, the interval error processing unit 141 sets the reference point p1 at the intersection of the verification region A1 and the side 211. The sides 241 and 242 of the mask pattern 24 straddle the verification area A2. In this case, the interval system error processing unit 141 sets the reference point p1 at the intersection of the verification area A2 and the sides 241 and 242 respectively.

  The interval system error processing unit 141 acquires and sets an evaluation point corresponding to the shape in which the reference point p1 is set from the evaluation point library storage unit 15 with reference to each set reference point p1. To do.

FIG. 5 is a diagram illustrating a method for setting evaluation points for an interval error.
The evaluation point library 151 is a library corresponding to an interval system error. The evaluation point creation position coordinate generated based on each reference point p1 is set as an evaluation point p2, and the position coordinate is set by a design rule or the like and is made into a library. Is. The position coordinates can be arbitrarily set by the user, for example. For example, when the coordinates of the reference point p1 are (X, Y), the coordinates of the evaluation point p2 can be determined by (X + basic value + correction value, Y + basic value + correction value). The basic value is determined by the user according to design rules and the like. It is also possible to have a plurality of evaluation points p2 with respect to the reference point p1. Note that the number of evaluation points to be set can be arbitrarily determined by the user.

  In the evaluation score library 151, six types of setting patterns of evaluation points p2 are registered: a lower left OUT corner, a lower right OUT corner, an upper right IN corner, an upper left IN corner, a left simple line, and a right simple line. .

FIG. 5A shows an example in which the reference point p1 is set at the lower left OUT corner portion of the mask pattern 26a and the lower right OUT corner portion of the mask pattern 26b.
The interval system error processing unit 141 refers to the evaluation point library 151. Then, the interval error processing unit 141 draws an arc centering on the reference point p1 set at the lower left OUT corner portion and the lower right OUT corner portion outside the mask pattern, and sets the evaluation point p2 on the drawn arc. Set. For example, if the coordinates of the reference point p1 set at the lower left OUT corner portion of the mask pattern 26a are (0, 0), the coordinates of the evaluation point p2 corresponding to the reference point p1 are (0, -1) and (- 0.7, -0.7) and (-1, 0). When the coordinates of the reference point p1 set at the lower right OUT corner portion of the mask pattern 26b are (0, 0), the coordinates of the evaluation point p2 corresponding to the reference point p1 are (0, -1), respectively. Let (0.7, -0.7), (1,0).

FIG. 5B shows an example in which the reference point p1 is set at the upper right IN corner portion of the mask pattern 27a and the upper left IN corner portion of the mask pattern 27b.
The interval system error processing unit 141 refers to the evaluation point library 151. Then, the interval error processing unit 141 draws a perpendicular line from the point moved by the correction value along the inner sides 271 and 272 from the reference point p1 set at the upper right IN corner part of the mask pattern 27a, and the perpendicular line intersects. An evaluation point p2 is set for the point. For example, if the coordinates of the reference point p1 are (0, 0), the coordinates of the evaluation point p2 corresponding to the reference point p1 are (−2.7, −2.7). Further, the interval error processing unit 141 lowers the perpendicular from the point moved by the correction value along the inner sides 273 and 274 from the reference point p1 set at the upper left IN corner portion of the mask pattern 27b, and the perpendicular intersects. An evaluation point p2 is set for the point. For example, if the coordinates of the reference point p1 are (0, 0), the coordinates of the evaluation point p2 corresponding to the reference point p1 are (2.7, -2.7).

FIG. 5C shows an example in which the reference point p1 is set on the side 281 of the mask pattern 28a and the side 282 of the mask pattern 28b.
The interval system error processing unit 141 refers to the evaluation point library 151. Then, the interval error processing unit 141 sets an evaluation point p2 by dropping a perpendicular line to the left from the reference point p1 set on the side 281 of the mask pattern 28a by a predetermined distance. For example, if the coordinate of the reference point p1 is (0, 0), the coordinate of the evaluation point p2 corresponding to the reference point p1 is (−2, 0). The interval error processing unit 141 sets an evaluation point p2 by dropping a perpendicular line to the right from the reference point p1 set on the side 282 of the mask pattern 28b by a predetermined distance. For example, if the coordinates of the reference point p1 are (0, 0), the coordinates of the evaluation point p2 corresponding to the reference point p1 are (2, 0).

Next, the interval system error processing unit 141 connects the set evaluation points p2 with a line to generate an evaluation line.
FIG. 6 is a diagram for explaining generation of an evaluation line at the time of an interval error.

In the verification area A3 of the mask pattern 29 shown in FIG. 6, a plurality of reference points p1 set by the interval error processing unit 141 according to the evaluation point library 151 are set. The reference point p1 of the coordinates (X ₁ , Y ₁ ) is an example of the reference point set at the lower right OUT corner portion, and the reference point p1 of the coordinates (X ₂ , Y ₂ ) is set at the lower left OUT corner portion. An example of a reference point, a reference point p1 of coordinates (X ₃ , Y ₃ ) is an example of a reference point set at the upper right IN corner, and a reference point p1 of coordinates (X ₄ , Y ₄ ) It is an example of the reference point set to the simple line.

  In the verification area A3 of the mask pattern 29, a plurality of evaluation points p2a, p2b, p2c, and p2d set by the interval error processing unit 141 according to the evaluation point library 151 are set. The interval system error processing unit 141 generates the evaluation line B1 by connecting the evaluation points p2a, p2b, p2c, and p2d.

  Next, the interval system error processing unit 141 determines whether the interval system error detected by the DRC verification unit 13 based on the presence or absence of the interference of the evaluation line B1 is a true error or a pseudo error. Specifically, the interval system error processing unit 141 determines as a check-required error when it interferes with the evaluation line, and determines as a pseudo error when it does not interfere with it as a check-unnecessary error.

FIG. 7 is a diagram illustrating a method for determining a true error and a pseudo error.
In FIG. 7, the same parts as those of the mask pattern shown in FIG.
The generated evaluation lines B2 and B3 exist in the verification area A1. The interval system error processing unit 141 determines the presence or absence of interference between the evaluation line B2 and the evaluation line B3. Since the evaluation line B2 and the evaluation line B3 do not interfere with each other, the distance error processing unit 141 determines that the distance error generated between the mask patterns 22 and 23 is a pseudo error.

  In addition, the generated evaluation lines B4 and B5 exist in the verification area A2. The interval system error processing unit 141 determines the presence or absence of interference between the evaluation line B4 and the evaluation line B5. Since the evaluation line B4 and the evaluation line B5 interfere with each other, the gap error processing unit 141 is involved in the formation of the evaluation lines B4 and B5 (the source of the formation of the evaluation lines B4 and B5) between the mask patterns 24 and 25. It is determined that the interval error that occurred in step 1 is a true error.

  The interval error processing unit 141 displays error information of the mask patterns 24 and 25 determined to be true errors on the monitor 104a. This error information includes the coordinates of the interference portion and the shape information of the mask patterns 24 and 25. Further, the interval error processing unit 141 stores the error information of the mask patterns 24 and 25 in the error information storage unit 17.

On the other hand, the interval error processing unit 141 stores the error information of the mask patterns 22 and 23 determined to be pseudo errors in the processing log storage unit 16.
Next, processing of the line width error processing unit 142 will be described.

FIG. 8 is a diagram for explaining the processing of the line width system error processing unit.
FIG. 8A shows mask patterns 32 classified as line width errors by the DRC verification unit 13 and mask patterns 31 and 33 located at both ends of the mask pattern 32. In FIG. 8A, a graphic E3 for identifying an error portion of a line width system error occurring in the mask pattern 32 is indicated by a dotted line. The shape of the figure is arbitrary.

  The line width system error processing unit 142 searches the set point of the reference point p3. First, as shown in FIG. 8B, the line width error processing unit 142 detects corner portions 32a, 32b, 32c, and 32d that intersect the side of the mask pattern 32 where an error has occurred from the error location. To do. Further, the line width error processing unit 142 measures the distance h1 between the upper and lower corner portions 32a and 32c. Thereafter, the line width system error processing unit 142 sets the reference point p3 for the detected corners 32a, 32b, 32c, and 32d as shown in FIG. 8C.

  In addition, about the setting location of the reference point p3, it is fundamental to place in a corner part. However, if the distance between the upper and lower corners intersecting the side of the mask pattern in which the error has occurred is measured and the measured distance exceeds the preset distance, a reference point is generated on the side of the mask pattern in which the error has occurred. It is also possible.

FIG. 9 is a diagram illustrating an example in which a reference point is generated on the side of the mask pattern in which an error has occurred.
FIG. 9 shows, with dotted lines, a figure E4 that identifies an error portion of a line width error that has occurred in the mask pattern 42 among the mask patterns 41, 42, and 43. The line width error processing unit 142 measures the distance h2 between the upper and lower corners intersecting the side of the mask pattern 42 where the error has occurred. As a result, the measurement distance exceeds the preset distance. A reference point p3 is set at the midpoint between 421 and 422.

It is also possible to generate a plurality of reference points p3 on one side. The user can arbitrarily set the distance and the number for generating the reference point p3.
The line width system error processing unit 142 acquires, from the evaluation point library 152 stored in the evaluation point library storage unit 15, an evaluation point corresponding to the shape for which the reference point p 3 is set with reference to each set reference point p 3. Set.

FIG. 10 is a diagram showing a method for setting evaluation points for line width errors.
The evaluation point library 152 is a library corresponding to a line width system error. The evaluation line generation position coordinate generated based on each reference point p3 is set as the evaluation point p4, and the position coordinate is set by a design rule or the like to be a library. It is a thing. The position coordinates can be arbitrarily set by the user, for example.

  In the evaluation score library 152, six types of setting patterns of the evaluation points p4 of the upper left IN corner portion, the lower left IN corner portion, the upper right IN corner portion, the lower right IN corner portion, the left simple line, and the right simple line are registered. .

  In the mask patterns 31, 32, and 33 shown in FIG. 10A, the corner portion 32a corresponds to the upper left IN corner portion, the corner portion 32b corresponds to the upper right IN corner portion, and the corner portion 32c corresponds to the lower left IN corner portion. The corner portion 32d corresponds to the lower right IN corner portion.

  The line width system error processing unit 142 refers to the evaluation point library 152. Then, the line width system error processing unit 142 sets arcs around the respective reference points p3 set in the upper left IN corner portion, the lower left IN corner portion, the upper right IN corner portion, and the lower right IN corner portion in the mask pattern. The evaluation point p4 is set on the drawn arc. A dotted line connecting the reference point p3 and the evaluation point p4 indicates to which reference point p3 the set evaluation point p4 corresponds. For example, if the coordinates of the reference point p3 set in the corner portion 32a are (0, 0), the coordinates of the evaluation point p4 corresponding to the reference point p3 are (0, 1) and (0.7, 0.7), respectively. ), (1,0). If the coordinates of the reference point p3 set at the corner portion 32b are (0, 0), the coordinates of the evaluation point p4 corresponding to the reference point p3 are (0, 1), (−0.7, 0. 7) and (-1, 0). If the coordinates of the reference point p3 set at the corner portion 32c are (0, 0), the coordinates of the evaluation point p4 corresponding to the reference point p3 are (0, -1) and (0.7, -0), respectively. .7), (1,0). If the coordinates of the reference point p3 set in the corner portion 32d are (0, 0), the coordinates of the evaluation point p4 corresponding to the reference point p3 are (0, -1), (-0.7, -0. 7) and (-1, 0).

  In the mask patterns 41, 42, and 43 shown in FIG. 10B, the corner portion 42a corresponds to the upper left IN corner portion, the corner portion 42b corresponds to the upper right IN corner portion, and the corner portion 42c corresponds to the lower left IN corner portion. The corner portion 42d corresponds to the lower right IN corner portion. Also, the side 421 corresponds to the left simple line. The side 422 corresponds to the right simple line. The method of setting the evaluation point p4 corresponding to the reference point p3 set for each of the corner portions 42a, 42b, 42c, and 42d is that of the evaluation point p4 corresponding to the reference point p3 set for each of the corner portions 32a, 32b, 32c, and 32d. This is the same as the setting method.

  The line width system error processing unit 142 refers to the evaluation point library 152. Then, the line width error processing unit 142 sets an evaluation point p4 by dropping a perpendicular line from the reference point p3 set on the side 421 of the mask pattern 42 to the right side (inside the mask pattern 42) by a predetermined distance. For example, if the coordinate of the reference point p3 is (0, 0), the coordinate of the evaluation point p4 corresponding to this reference point p3 is (2, 0). Further, the line width system error processing unit 142 sets the evaluation point p4 by dropping a perpendicular line to the left side from the reference point p3 set on the side 422 of the mask pattern 42 by a predetermined distance. For example, if the coordinate of the reference point p3 is (0, 0), the coordinate of the evaluation point p4 corresponding to the reference point p3 is (−2, 0).

Next, the line width error processing unit 142 connects the set evaluation points p4 with lines to generate an evaluation line.
FIG. 11 is a diagram for explaining a method for determining a true error and a pseudo error.

In FIG. 11, in order to identify each reference point p3 and each evaluation point p4, the reference point p3 and the evaluation point p4 are further denoted by reference numerals.
First, a method for determining the line width error of the mask pattern 32 shown in FIG.

  The line width system error processing unit 142 connects the evaluation points p4a, p4b, and p4c generated based on the reference point p3a and the evaluation points p4d, p4e, and p4f generated based on the reference point p3b to generate the evaluation line C1. Further, the line width system error processing unit 142 generates the evaluation line C2 by connecting the evaluation points p4g, p4h, and p4i generated based on the reference point p3c and the evaluation points p4j, p4k, and p4L generated based on the reference point p3d. To do.

  Next, the line width system error processing unit 142 determines whether the line width system error detected by the DRC verification unit 13 in the presence or absence of interference between the evaluation lines C1 and C2 is a true error or a pseudo error. Specifically, the line width error processing unit 142 determines that the error is a confirmation-required error if it interferes with the evaluation line, and determines that it is a pseudo error if it does not interfere, resulting in a confirmation unnecessary error. Since the evaluation line C1 and the evaluation line C2 do not interfere with each other, the line width error processing unit 142 determines that the line width error generated in the mask pattern 32 is a pseudo error.

Next, a method for determining the line width error of the mask pattern 42 shown in FIG.
The line width error processing unit 142 includes evaluation points p4m, p4n, and p4o generated based on the reference point p3e, an evaluation point p4p generated based on the reference point p3f, and evaluation points p4q, p4r generated based on the reference point p3g, An evaluation line C3 is generated by connecting p4s. The line width error processing unit 142 also includes evaluation points p4t, p4u, and p4v generated based on the reference point p3h, an evaluation point p4w generated based on the reference point p3i, and an evaluation point p4x generated based on the reference point p3j, An evaluation line C4 is generated by connecting p4y and p4z.

  Next, the line width system error processing unit 142 determines whether the line width system error detected by the DRC verification unit 13 in the presence or absence of the interference of the evaluation lines C3 and C4 is a true error or a pseudo error. Since the evaluation line C3 and the evaluation line C4 interfere with each other, the line width error processing unit 142 determines that the line width error generated in the mask pattern 42 is a true error.

  The line width error processing unit 142 displays the error information of the mask pattern 42 determined to be a true error on the monitor 104a. This error information includes the shape information of the mask pattern 42. Further, the line width error processing unit 142 stores the error information of the mask pattern 42 in the error information storage unit 17.

On the other hand, the line width error processing unit 142 stores the error information of the mask pattern 32 determined to be a pseudo error in the processing log storage unit 16.
Next, the process of the verification apparatus 10 is demonstrated using a flowchart.

FIG. 12 is a flowchart showing the processing of the verification apparatus.
[Step S1] The error verification unit 14 determines whether or not there is an interval error in the error type of the verification error. If there is an interval error (Yes in step S1), the process proceeds to step S2. When there is no interval system error (No in step S1), the process proceeds to step S9.

[Step S <b> 2] The interval system error processing unit 141 sets a verification region at an error location of the interval system error. Thereafter, the process proceeds to step S3.
[Step S3] The interval system error processing unit 141 sets a reference point based on the verification region set in Step S2. Thereafter, the process proceeds to step S4.

[Step S4] The interval error processing unit 141 sets an evaluation score using the reference point set in Step S3 and the evaluation point library. Then, the process proceeds to step S5.
[Step S5] The interval error processing unit 141 generates an evaluation line by connecting the evaluation points set in Step S4 with a line. Then, the process proceeds to step S6.

  [Step S6] The interval error processing unit 141 determines whether or not an interference evaluation line exists. When an interference evaluation line exists (Yes in step S6), the process proceeds to step S7. If there is no interference evaluation line (No in step S6), the process proceeds to step S8.

  [Step S7] The interval error processing unit 141 stores in the error information storage unit 17 the error information of the mask pattern related to the formation of the interference evaluation line. Thereafter, the process proceeds to operation S9.

  [Step S8] The interval error processing unit 141 stores, in the processing log storage unit 16, the error information of the mask pattern related to the formation of the evaluation line that does not interfere. Thereafter, the process proceeds to operation S9.

  [Step S <b> 9] The error verification unit 14 determines whether or not a line width error exists in the error type of the verification error. If a line width error exists (Yes in step S9), the process proceeds to step S10. If there is no line width error (No in step S9), the processing in FIG.

[Step S10] The line width system error processing unit 142 detects a corner portion that intersects the side where the error has occurred. Then, the process proceeds to step S11.
[Step S11] The line width system error processing unit 142 measures the distance to the upper and lower corners. Thereafter, the process proceeds to operation S12.

  [Step S12] The line width system error processing unit 142 sets a reference point at a corner portion that intersects the error location. Also, a reference point is set at the midpoint according to the distance to the upper and lower corners. Thereafter, the process proceeds to operation S13.

  [Step S13] The line width error processing unit 142 sets an evaluation point using the reference point set in step S12 and the evaluation point library. Thereafter, the process proceeds to operation S14.

[Step S14] The line width error processing unit 142 generates an evaluation line by connecting the evaluation points set in step S13 with a line. Thereafter, the process proceeds to operation S15.
[Step S15] The line width system error processing unit 142 determines whether or not an interference evaluation line exists. If there is an interference evaluation line (Yes in step S15), the process proceeds to step S16. If there is no interference evaluation line (No in step S15), the process proceeds to step S17.

  [Step S16] The line width error processing unit 142 stores in the error information storage unit 17 the error information of the mask pattern related to the formation of the interference evaluation line. Thereafter, the process of FIG.

  [Step S <b> 17] The line width error processing unit 142 stores, in the processing log storage unit 16, mask pattern error information related to formation of an evaluation line that does not interfere. Thereafter, the process of FIG.

  As described above, according to the verification apparatus 10, it is possible to exclude pseudo errors by generating an evaluation line and determining whether the error is a pseudo error or a true error according to the interference result of the evaluation line. For this reason, the designer only needs to confirm the true error, and the error confirmation work can be performed efficiently.

<Modification>
FIG. 13 is a diagram illustrating a modification.
FIG. 13 shows a mask pattern 51 relating to an error location. The mask pattern 51 has a step (hereinafter referred to as a minute step) 511 smaller than a predetermined value. Hereinafter, a reference point setting method in this case will be described.

  When the mask pattern 51 is classified as an interval system error by the DRC verification unit 13, the interval system error processing unit 141 sets the reference point p1 at the OUT corner portion 511a. When the mask pattern 51 is classified as a line width error by the DRC verification unit 13, the line width error processing unit 142 sets the reference point p3 at the IN corner portion 511b.

  Alternatively, regardless of the type of error, a reference point p5 that can be used for both the interval error and the line width error may be set at the midpoint between the OUT corner portion 511a and the IN corner portion 511b.

  Note that the processing performed by the verification device 10 may be distributed by a plurality of devices. For example, one device performs DRC verification to detect a spacing error and a line width error, and the other device determines a pseudo error and a true error using the detected error information. It may be.

  The verification method, the verification program, and the verification apparatus of the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit is an arbitrary function having the same function. It can be replaced with the configuration of Moreover, other arbitrary structures and processes may be added to the present invention.

Further, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions of the verification devices 1 and 10 is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic storage device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic storage device include a hard disk drive, a flexible disk (FD), and a magnetic tape. Examples of the optical disk include a DVD, a DVD-RAM, and a CD-ROM / RW. Examples of the magneto-optical recording medium include an MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time a program is transferred from a server computer connected via a network, the computer can sequentially execute processing according to the received program.

  Further, at least a part of the above processing functions can be realized by an electronic circuit such as a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device).

Regarding the above first to second embodiments, the following additional notes are further disclosed.
(Additional remark 1) In the verification method of the mask pattern for substrate exposure formed based on the design data of a semiconductor device,
Computer
Form a section that identifies whether or not the verification object is violated based on the shape of the mask pattern including the part that violates the layout design rule,
Judge the presence or absence of interference of the formed section, and output the judgment result,
A verification method characterized by that.

(Supplementary note 2) The verification method according to supplementary note 1, wherein the section is formed so as to include corner portions of a predetermined combination of the mask patterns.
(Additional remark 3) The said predetermined combination is specified according to the violation classification of the said layout design rule, The verification method of Additional remark 2 characterized by the above-mentioned.

(Appendix 4) Create a point at a predetermined position near the corner,
The verification method according to appendix 2, wherein the sections are formed by connecting the created points.

(Supplementary Note 5) When the violation type is a violation related to an interval between a plurality of mask patterns,
Set a verification region that identifies a mask pattern to be verified based on a location that violates the layout design rule,
The verification method according to claim 4, wherein the point is set in a space near a corner of the mask pattern of the set verification area.

  (Supplementary note 6) When the side of the mask pattern that violates the layout design rule straddles the verification region, the point is set in a space near the intersection of the verification region and the side. 5. The verification method according to 5.

(Supplementary Note 7) When the violation type is a violation related to the line width of one mask pattern,
5. The verification method according to claim 4, wherein the point is set inside a mask pattern near a corner of the mask pattern including a portion that violates the layout design rule.

(Additional remark 8) The verification method in any one of additional remark 4 thru | or 7 with which the creation position of the said point changes according to the shape of a corner | angular part.
(Supplementary note 9) The verification device according to any one of supplementary notes 4 to 8, wherein the point is set by referring to a storage unit that stores a position of the point to be set according to the shape of the corner.

  (Additional remark 10) The verification apparatus in any one of additional remark 1 thru | or 9 which outputs the location which has interference of the formed division when outputting the said determination result, and does not output the location without interference.

(Additional remark 11) In the verification program of the mask pattern for board | substrate exposure formed based on the design data of a semiconductor device,
On the computer,
Form a section that identifies whether or not the verification object is violated based on the shape of the mask pattern including the part that violates the layout design rule,
Judge the presence or absence of interference of the formed section, and output the judgment result,
A verification program characterized by causing processing to be executed.

(Additional remark 12) In the verification apparatus of the mask pattern for board | substrate exposure formed based on the design data of a semiconductor device,
A forming unit for forming a section for identifying whether or not the verification target is violated based on a shape of a mask pattern including a part that violates a layout design rule;
A determination unit that determines the presence or absence of interference in the section formed by the forming unit, and outputs a determination result;
The verification apparatus characterized by having.

DESCRIPTION OF SYMBOLS 1,10 Verification apparatus 1a Formation part 1b Judgment part 1c Memory | storage part d1 Identification information 2, 2a-2e, 26a, 26b, 27a, 27b, 28a, 28b, 21-29, 31-33, 41-43, 51 Mask pattern 3a, 3b, E1 to E4 Error location 4a, 4b, A1 to A3 Verification area 5, p1, p3 Reference point 6, p2, p4 Evaluation point 7a to 7d, B1 to B5, C1 to C4 Evaluation line 11 Design target data storage Unit 12 OPC processing unit 13 DRC verification unit 14 error verification unit 141 interval system error processing unit 142 line width system error processing unit 15 evaluation point library storage unit 151, 152 evaluation point library 16 processing log storage unit 17 error information storage unit

Claims (9)

In a method for verifying a mask pattern for substrate exposure formed based on design data of a semiconductor device,
Computer
Form a section that identifies whether or not the verification object is violated based on the shape of the mask pattern including the part that violates the layout design rule,
Judge the presence or absence of interference of the formed section, and output the judgment result,
A verification method characterized by that.   The verification method according to claim 1, wherein the section is formed so as to include corner portions of a predetermined combination of the mask patterns.   The verification method according to claim 2, wherein the predetermined combination is specified according to a violation type of the layout design rule. Create a point at a predetermined position near the corner,
The verification method according to claim 2, wherein the section is formed by connecting the created points. When the violation type is a violation related to an interval between a plurality of mask patterns,
Set a verification region that identifies a mask pattern to be verified based on a location that violates the layout design rule,
5. The verification method according to claim 4, wherein the point is set in a space in the vicinity of a corner of the mask pattern in the set verification area. When the violation type is a violation related to the line width of one mask pattern,
5. The verification method according to claim 4, wherein the point is set inside a mask pattern near a corner of the mask pattern including a portion that violates the layout design rule.   The verification apparatus according to claim 1, wherein when the determination result is output, a location where there is interference in the formed partition is output, and a location where there is no interference is not output. In the verification program of the mask pattern for substrate exposure formed based on the design data of the semiconductor device,
On the computer,
Form a section that identifies whether or not the verification object is violated based on the shape of the mask pattern including the part that violates the layout design rule,
Judge the presence or absence of interference of the formed section, and output the judgment result,
A verification program characterized by causing processing to be executed. In a verification apparatus for a mask pattern for substrate exposure formed based on design data of a semiconductor device,
A forming unit for forming a section for identifying whether or not the verification target is violated based on a shape of a mask pattern including a part that violates a layout design rule;
A determination unit that determines the presence or absence of interference in the section formed by the forming unit, and outputs a determination result;
The verification apparatus characterized by having.

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