JP5359626B2 - Layout verification method and layout verification apparatus - Google Patents

Description

  The present invention relates to a layout verification method and a layout verification apparatus.

  In recent years, semiconductor devices (LSIs) have been miniaturized and highly integrated, and the distance between signal wirings arranged in the semiconductor devices has been reduced. Along with this, slight fluctuations in potential occur in the signal wiring due to interference from other signal wiring. In specific signal wirings (for example, signal wirings such as a reference voltage and a bias voltage), a slight potential fluctuation may affect the operation of the semiconductor device. In such signal wiring, stable signal wiring or power supply wiring (for example, ground wiring) is arranged around in order to reduce potential fluctuation due to interference from other signal wiring.

  In general, a signal wiring in which a slight potential fluctuation affects the operation of a semiconductor device is called a shielded wiring. A stable signal wiring or power supply wiring arranged around the shielded line is called a shield wiring. Furthermore, arranging shield wiring around a shielded wire is called shielding.

  For example, as in the layout data 50 shown in FIG. 15, the shield wiring patterns P11 and P12 are arranged with a wiring interval d10 as designed in the left-right direction with respect to the shielded wiring pattern P13.

  Then, in the layout verification of the semiconductor device, it is necessary to verify whether or not the shield is correctly performed. Conventionally, verification of whether or not shielding has been performed correctly has been performed by visual inspection or logical operation by a verification device (see Patent Document 1).

  In the visual inspection, the operator visually determines whether or not the shield wiring patterns P11 and P12 are arranged within the wiring interval d10 as designed with respect to the shielded wiring pattern P13 included in the layout data.

  In the logical operation by the verification device, the verification device sets verification regions A21 and A22 around both shield wiring patterns P11 and P12 included in the layout data 50, as indicated by broken lines in FIG. When setting the verification areas A21 and A22, first, the verification apparatus firstly sets the wiring interval d10 between the shielded wiring pattern P13 and the shielded wiring patterns P11 and P12 and half the wiring width W of the shielded wiring pattern P13 (= W / 2). ) And a distance (hereinafter referred to as an expansion distance) d11 (= d10 + W / 2). Then, the verification apparatus defines, as verification areas A21 and A22, areas that respectively surround the wiring patterns P11 and P12 from positions separated outward from the sides of the shield wiring patterns P11 and P12 by the calculated expansion distance d11. .

  Therefore, in this case, when the shield wiring patterns P11 and P12 are correctly arranged, the boundary line Lb of the verification regions A21 and A22 passes through the center of the wiring width W of the shielded wiring pattern P13.

  Then, the verification apparatus determines whether or not the shielded wiring pattern P13 is included in the verification areas A21 and A22, so that the shielded wiring patterns P11 and P12 correspond to the design values with respect to the shielded wiring pattern P13. It is determined whether or not they are arranged within the wiring interval d10.

  Specifically, when the shielded wiring pattern P13 is all included in at least one of the verification area A21 and the verification area A22, the verification apparatus correctly sets the shield wiring patterns P11 and P12 with respect to the shielded wiring pattern P13. It is determined that the shield wiring patterns P11 and P12 are correctly arranged.

  On the contrary, when the shielded wiring pattern P13 is not included in any of the verification region A21 or the verification region A22, or when the shielded wiring patterns P11 and P12 are not arranged on the left and right of the shielded wiring pattern P13 in the layout data 50, Assuming that the shield wiring patterns P11 and P12 are not correctly arranged with respect to the shielded wiring pattern P13, the shielded wiring pattern P13 that is not included in the verification areas A21 and A22 is determined as a shield error.

JP 2005-318797 A

  However, when the shield layout verification is performed by the visual inspection described above, since the worker performs the visual inspection, there is a possibility of overlooking a portion that is originally an error. If an error is overlooked, the semiconductor device operates differently from the simulation, leading to a failure of the semiconductor device. Furthermore, since visual inspection requires a lot of manpower, it has been a factor in increasing design man-hours.

On the other hand, when the shield layout verification is performed by the logical operation by the above-described verification apparatus, there is a case where an error cannot be detected correctly.
For example, a case will be described in which the layout verification of the shield is performed by the logical operation by the verification device for the layout data 30 shown in FIG.

The layout data 30 includes a shielded wiring pattern P1, shield wiring patterns P2 to P4, and other wiring patterns P5 to P7.
The verification apparatus sets verification areas A25, A26, and A27 centered on the shield wiring patterns P2 to P4 included in the layout data 30, respectively. Then, the verification device obtains the spread distance d11 in the same manner as described above, and the wiring patterns P2 to P4 from positions separated outward from the sides of the shield wiring patterns P2 to P4 by the obtained spread distance d11. Are defined as verification areas A25, A26, and A27. At this time, as shown in FIG. 17, the verification regions A25 to A27 respectively overlap with a part of the shielded wiring pattern P1.

Then, the verification device detects a portion of the shielded wiring pattern P1 that does not overlap with the verification regions A25 to A27 as a shield error.
However, since the portions of the sides E1 and E2 of the shielded wiring pattern P1 are not arranged around the shield wiring pattern, the detection device needs to be determined as a shield error originally, but cannot be detected as a shield error.

  Further, since the shield wiring pattern P2 is arranged around the side E3 of the shielded wiring pattern P1, the detection device determines that it is a shield error although it is not necessary to determine it as a shield error.

Therefore, the verification device cannot accurately determine the location of the shield error.
This is because, in the verification apparatus described with reference to FIG. 15, the shielded wiring pattern P13 is not shielded in the vertical direction of the shielded wiring pattern P13. Because there was a similar problem.

  The purpose of this verification apparatus is to accurately verify the shield of layout data.

According to one aspect of the present invention, there is provided a layout verification method of a semiconductor device, processing device, set the distance apart search area based on the design standard value with respect to the shielded wire pattern, the processing device but sets a plurality of rectangular regions to a region excluding said each wiring pattern of the set the search area, the processing device, among the set plurality of the rectangular area, the object to be shielded wiring pattern and the sheet Rudo wiring A combined area is generated by combining the rectangular areas between the patterns or between the shielded wiring pattern and the search area into one, and the processing apparatus is connected to the shielded wiring pattern or the stores information other wiring pattern in the storage area, the processing device, the shield wiring pattern and the other in contact with the storage area stored the combining region Information of the line patterns, based on the information of the reference value for the shield wiring pattern and other information of the wiring pattern, you verify whether the is the shielded wiring pattern being shielded by said shield wiring pattern.

  According to one aspect of the present invention, the verification apparatus can accurately verify the layout data shield.

It is a schematic block diagram of a verification apparatus. It is a flowchart figure of a layout verification process. It is explanatory drawing of a control card. It is explanatory drawing of a layout verification process. It is explanatory drawing of a layout verification process. It is explanatory drawing of a layout verification process. It is explanatory drawing of a layout verification process. It is explanatory drawing of a layout verification process. It is explanatory drawing of a layout verification process. (A), (b), (c) is explanatory drawing of a layout verification process. It is explanatory drawing of 1st extraction result data. It is explanatory drawing of 2nd extraction result data. It is explanatory drawing of 3rd extraction result data. It is explanatory drawing of extraction result data. It is explanatory drawing of the conventional layout verification process. It is explanatory drawing of the conventional layout verification process. It is explanatory drawing of the conventional layout verification process.

Hereinafter, embodiments will be described with reference to FIGS.
FIG. 1 is a schematic configuration diagram of a computer system for performing layout verification processing.

  As shown in FIG. 1, the computer (verification device) 11 includes a general CAD (Computer Aided Design) device, and includes a central processing unit (hereinafter referred to as CPU) 12, a memory 13, a storage device 14, and a display device 15. , An input device 16 and a drive device 17, which exchange data with each other via a bus 18.

  The CPU 12 executes a program using the memory 13 and realizes necessary processing such as layout verification. The memory 13 stores programs and data necessary for providing various processes. The memory 13 typically includes a cache memory, a system memory, and a display memory.

  The display device 15 is used for displaying a layout display, a parameter input screen, and the like, and for this, a CRT, LCD, PDP or the like is used. The input device 16 is used for inputting requests, instructions, patterns, and parameters from the user, and for this, a keyboard and a mouse device (not shown) are used.

  The storage device 14 usually includes a magnetic disk device, an optical disk device, and a magneto-optical disk device. The storage device 14 stores program data and files for verifying the layout data shield composed of steps S1 to S4 shown in FIG. The CPU 12 is stored in the storage device 14 in response to an instruction from the input device 16. The program and data are transferred to the memory 13 and executed.

  The drive device 17 drives the recording medium 19 and accesses the stored contents. The CPU 12 reads program data from the recording medium 19 via the drive device 17 and stores it in the storage device 14.

  As the recording medium 19, any computer-readable recording such as magnetic tape (MT), memory card, flexible disk, optical disk (CD-ROM, DVD-ROM,...), Magneto-optical disk (MO, MD,...), Etc. Media can be used. The above-described program data can be stored in the recording medium 19 and loaded into the memory 13 for use as necessary.

  The recording medium 19 includes a medium and a disk device that record program data uploaded or downloaded via a communication medium. Furthermore, not only a recording medium that records a program that can be directly executed by a computer, but also a recording medium that records a program that can be executed once installed on another recording medium (such as a hard disk), or an encrypted program In addition, a recording medium on which a compressed program is recorded is also included.

Next, a process in which the above-described verification apparatus 11 performs shield verification on layout data will be described with reference to FIG.
(Control card setting)
First, the CPU 12 uses the input device 16 in the control card 21 based on the layout conditions 20 stored in the storage device 14 determined by the restrictions on the process steps of the semiconductor device. It is set (step S1).

  The control card 21 is stored in the storage device 14, and includes a hierarchical structure of each condition, a net name of the shielded wiring pattern, a net name of the shielded wiring pattern, a wiring width of the shielded wiring pattern, a layer name of the shielded wiring pattern, a different node A distance that can be ignored is defined.

  The hierarchical structure of each condition refers to the hierarchical structure of each of the above conditions defined in the control card 21. The distance at which different nodes can be ignored means the wiring interval between the shielded wiring pattern and the wiring pattern of the other node, which is necessary so that the shielded wiring pattern is not affected by the wiring pattern of the other node.

FIG. 3 is a configuration diagram of an example of the control card 21.
The control card 21 includes a hierarchical structure 22 for each condition, a common condition 23, and first and second conditions 24 and 25.

  In the present embodiment, the control card 21 has a hierarchical structure of each condition “Hierarchy Condition”, a shielded wiring pattern net name “target_node”, a shielded wiring pattern net name “shield_node”, and a shield wiring pattern wiring The width is described as “shield_width”, the layer name of the shield wiring pattern as “shield_layer”, and the distance that can ignore different nodes as design reference values is described as “ignore distance”.

  In the hierarchical structure (Hierarchy Condition) 22 of each condition, the hierarchy of the described condition is higher as it is described on the left side. Conversely, the hierarchy of the described condition is lower as it is described on the right side. That is, in the control card 21, the net name (target_node) of the shielded wiring pattern, the layer name (shield_layer) of the shield wiring pattern, the net name (shield_node) of the shielded wiring pattern, the wiring width (shield_width) of the shield wiring pattern, The hierarchy is lower in the order of the distance at which the node can be ignored (ignore distance).

  In this embodiment, one condition is set for the net name (target_node) of the shielded wiring pattern and the layer name (shield_layer) of the shield wiring pattern, and two conditions are set for the net name (shield_node) of the wiring pattern to be shielded.

  In the control card 21, the net name (target_node) of the shielded wiring pattern and the layer name (shield_layer) of the shield wiring pattern are described in the upper layer than the net name (shield_node) of the wiring pattern to be shielded. That is, the net name (target_node) of the shielded wiring pattern and the layer name (shield_layer) of the shield wiring pattern are described in the upper layer as the common condition 23, and the net name (shield_node) of the wiring pattern to be shielded is the first and second conditions. 24 and 25 are described in the lower hierarchy. As a result, it is not necessary to describe the net name (target_node) of the shielded wiring pattern and the layer name (shield_layer) of the shield wiring pattern in each condition of the net name (shield_node) of the wiring pattern to be shielded. Has been simplified.

  The common condition 23 is defined for the net name (target_node) of the shielded wiring pattern and the layer name (shield_layer) of the shield wiring pattern. The net name (target_node) of the shielded wiring pattern is described as “NetA / Metal_Layer”, and the net name of the shielded wiring pattern is defined as “NetA”. The layer name (shield_layer) of the shield wiring pattern is described as “same”, and defines that the layer name of the shield wiring pattern is the same layer as the shielded wiring pattern.

  The first and second conditions 24 and 25 define the net name (shield_node) of the wiring pattern to be shielded, the wiring width (shield_width) of the shield wiring pattern, and the distance (ignore distance) at which different nodes can be ignored. That is, in the control card 21, the net width of the wiring pattern to be shielded defines the wiring width of the shield wiring pattern and the distance at which different nodes can be ignored.

  The first condition 24 is that the net name (shield_node) of the wiring pattern to be shielded, the wiring width (shield_width) Wr of the shield wiring pattern, and the distance that can ignore different nodes (ignore distance) are “GND”, “2mic”, “4mic”. Are described respectively. In other words, the first condition 24 is that when “GND” is used for the net of the shield wiring pattern, the wiring width of the shield wiring pattern is 2 microns or more, and the distance at which different nodes can be ignored is 4 microns or more. Defined.

The second condition 25 is that the net name (shield_node) of the wiring pattern to be shielded, the wiring width (shield_width) Wr of the shield wiring, and the distance that can ignore different nodes (ignore distance) are “GND_A”, “1mic”, “4mic”. ”, Respectively. In other words, the second condition 25 defines that when “GND_A” is used for the net of the shield wiring pattern, the wiring width of the shield wiring pattern is 1 micron or more and the distance at which different nodes can be ignored is 4 microns or more. doing.
(Extraction of shield state)
When the conditions necessary for verification of the shield are set in the control card 21 in step S1, the CPU 12 then changes the layout data 30 holding the net to the layout data 30 holding the net based on the layout data 30 holding the control card 21 and the net. A state (shield state) in which the shielded wiring pattern included is shielded is extracted (step S2).

Here, the layout data 30 holding a net refers to layout data in which a net is assigned to each layout pattern included in the layout data.
Specifically, first, the CPU 12 can ignore the net name (target_node) of the shielded wiring pattern defined by the common condition 23 of the control card 21 and the different nodes defined by the first and second conditions 24 and 25. Based on the distance (ignore distance), an area from the shielded wiring pattern included in the layout data 30 to a distance at which a different node can be ignored is set as a search area (search area setting step, search area setting means).

  For example, the case of layout data 30 as shown in FIG. 4 will be described. The layout data 30 includes shielded wiring pattern P1, shield wiring patterns P2 to P4, and other wiring patterns (simply referred to as other wiring patterns) P5 to P7.

  Incidentally, the shield wiring pattern P2 has the node name “GND” and the wiring width in the vertical direction in FIG. 4 is “W1”, the shield wiring pattern P3 has the node name “GND”, and the wiring width in the horizontal direction in FIG. ”And the wiring width in the vertical direction is“ W3 ”, the shield wiring pattern P4 has the node name“ GND ”, and the wiring width in the horizontal direction in FIG. 4 is“ W4 ”.

  The other wiring patterns P5 to P7 are “node C”, “node D”, and “node E”, respectively. Further, the shield wiring patterns P2 to P4 and the other wiring patterns P5 to P7 are in the same layer as the shielded wiring pattern P1.

  As shown in FIG. 4, the CPU 12 sets a search area A <b> 1 for the shielded wiring pattern P <b> 1 based on the control card 21. That is, the search area A1 centered on the shielded wiring pattern P1 is set. Then, the CPU 12 sets the shielded wiring pattern P1 as an expansion distance by using a distance (ignore distance) di1 (4 microns in the present embodiment) in which the different node defined in the control card 21 can be ignored. A region surrounding the same wiring pattern P1 from a position separated from each side of P1 by an distance (distance distance) di1 is defined as a search region A1.

  Next, as shown in FIG. 5, in the search area A1 of the layout data 30, the CPU 12 draws a lead line L1 vertically and horizontally in FIG. 5 from each vertex of the shielded wiring pattern P1.

  Similarly, the CPU 12 draws a lead line L1 in the vertical and horizontal directions in FIG. 5 from the vertices of the shield wiring patterns P2 to P4 and the other wiring patterns P5 to P7 (rectangular area setting step, rectangular area setting means). The lead lines L1 are not drawn across the shielded wiring pattern P1, the shield wiring patterns P2 to P4, and the other wiring patterns P5 to P7. Here, a plurality of areas partitioned by these lead lines L1 are referred to as rectangular areas R.

  Then, in the search area A1 of the layout data 30, the CPU 12 sets the rectangular area R in contact with the left side of the shielded wiring pattern P1 as first to third rectangular areas R1 to R3 from top to bottom. Define. Further, the CPU 12 defines the rectangular region R that is in contact with the right side of the shielded wiring pattern P1 as fourth to seventh rectangular regions R4 to R7 from the bottom to the top.

And CPU12 makes a synthetic | combination area | region based on 1st-3rd rectangular area | region R1-R3 (a synthetic | combination area | region setting process, a synthetic | combination area | region setting means).
First, as shown in FIG. 5, when there is another rectangular region R (R8) on the left side of the first rectangular region R1 with respect to the first rectangular region R1, One rectangular region R1 is combined into one to form a first combined region C1. Subsequently, it is determined whether another rectangular region R exists, the shield wiring pattern P4 exists, or is in contact with the search region A1 on the left side of the obtained first synthesis region C1.

In this case, since the shield wiring pattern P4 exists on the left side of the first composite region C1, the composite region C1 for the first rectangular region R1 is determined as shown in FIG.
Next, similarly, a second synthesis region C2 for the second rectangular region R2 is generated. In this case, there are three rectangular regions R (R9 to R11) between the second rectangular region R2 and the shield wiring pattern P4. Therefore, the second rectangular region R2 and the three rectangular regions R9 to R11 are combined into one to form the second combined region C2.

  Next, for the third rectangular region R3, only the shield wiring pattern P3 exists on the left side of the third rectangular region R3, and no other rectangular region R exists. Therefore, the third rectangular region R3 itself becomes the third composite region C3.

And CPU12 makes the 4th-7th synthetic | combination area | region C4-C7 by the same method based on 4th-7th rectangular area | region R4-R7.
Incidentally, with respect to the fourth rectangular region R4, the shield wiring patterns P2 to P4 and the other wiring patterns P5 to P7 do not exist on the left side of the fourth rectangular region R4, and there are two between the fourth rectangular region R4 and the search region A1. A rectangular area R (R12, R13) exists. For this reason, the fourth rectangular region R4 and the rectangular regions R12, R13 are combined into a fourth combined region C4.

  Further, with respect to the fifth rectangular region R5, only the other wiring pattern P6 exists on the right side of the fifth rectangular region R5, and no other rectangular region R exists. Therefore, the fifth rectangular region R5 itself becomes the fifth composite region C5.

  Further, for the sixth rectangular region R6, there are three rectangular regions R (R14 to R16) between the sixth rectangular region R6 and the other wiring pattern P6. Therefore, the sixth rectangular region R6 and the three rectangular regions R14 to R16 are combined into one to form a sixth combined region C6.

  Furthermore, for the seventh rectangular region R7, one rectangular region R (R17) exists between the seventh rectangular region R7 and the other wiring pattern P5. Therefore, the seventh rectangular region R7 and the one seventeenth rectangular region R17 are combined into one to form a seventh combined region C7.

  When the first to seventh synthesis regions C1 to C7 are obtained, the CPU 12 contacts and arranges the shielded wiring pattern P1 and the shield wiring patterns P2 to P4 from the first to seventh synthesis regions C1 to C7. The combined area to be processed is obtained together with the shield wiring patterns P2 to P4 that are in contact with each other (wiring information extracting step, wiring information extracting means).

  In this case, as is apparent from FIG. 6, there are three combined regions, the first to third combined regions C1 to C3, interposed between the shielded wiring pattern P1 and the shielded wiring patterns P2 to P4.

  For each of the first to third synthesis regions C1 to C3, the CPU 12 determines the distance between the shield wiring patterns P2 to P4 and the shielded wiring pattern P1 that are in contact with each other, and the shield wiring patterns P2 to P4 that are in contact with each other. The wiring width is stored in the first extraction result data De1.

  Incidentally, since the CPU 12 is in contact with the shield wiring pattern P4 in the first and second composite regions C1, C2, the distance “D1, D2” between the shield wiring pattern P4 and the shielded wiring pattern P1, and the shield thereof The wiring width “W4” of the wiring pattern P4 is stored in the first extraction result data De1.

  Similarly, since the CPU 12 is in contact with the shield wiring pattern P3 in the third synthesis region C3, the distance “D3” between the shield wiring pattern P3 and the shielded wiring pattern P1 and the horizontal direction of the shield wiring pattern P3. The wiring width “W2” is stored in the first extraction result data De1.

  Next, when the CPU 12 is in contact with the shielded wiring pattern P1 and the other wiring patterns P5 to P7 from the first to seventh synthesis regions C1 to C7, the CPU 12 is between the contacted other wiring patterns P5 to P7. The combined area to be placed in contact is obtained together with the other wiring patterns P5 to P7 that are in contact with each other.

  In this case, as is apparent from FIG. 6, there are three combined regions, the fifth to seventh combined regions C5 to C7, which are interposed between the shielded wiring pattern P1 and the other wiring patterns P5 to P7.

Then, for each of the fifth to seventh synthesis areas C5 to C7, the CPU 12 stores the node names of the other wiring patterns P5 to P7 in contact with the first extraction result data De1.
In this case, the CPU 12 stores the node name “node D” in the first extraction result data De1 in order to contact the other wiring pattern P6 of the node name “node D” for the fifth and sixth synthesis regions C5 and C6. . Further, the CPU 12 stores the node name “node C” in the first extraction result data De1 in order to come into contact with the other wiring pattern P5 of the node name “node C” in the seventh synthesis region C7.

  Subsequently, the CPU 12 coordinates N1 to N11 at the upper and lower ends of the side of the rectangular region R (in this case, the first to seventh rectangular regions R1 to R7) in contact with the left side or the right side of the shielded wiring pattern P1. Is stored in the first extraction result data De1.

  In this case, if the sides of the first to seventh rectangular regions R1 to R7 that are in contact with the left side or the right side of the shielded wiring pattern P1 are the first to seventh contact sides a1 to a7, the first to seventh contacts. The sides a1 to a7 can be represented by coordinates N1 to N11.

  Incidentally, the first contact side a1 is represented by coordinates N1 and N2, the second contact side a2 is represented by coordinates N3 and N4, and the third contact side a3 is represented by coordinates N4 and N5. The fourth contact side a4 is represented by coordinates N6 and N7, and the fifth contact side a5 is represented by coordinates N7 and N8. Further, the sixth contact side a6 is represented by coordinates N9 and N10, and the seventh contact side a7 is represented by coordinates N10 and N11.

  With the above processing, the CPU 12 performs the first to seventh synthesis regions C1 to C1 corresponding to the first to seventh contact sides a1 to a7 for each of the first to seventh contact sides a1 to a7 as shown in FIG. Information on shield wiring patterns P2 to P4 or other wiring patterns P5 to P7 facing each other through C7 is stored in the first extraction result data De1.

  Specifically, in the first extraction result data De1, the data Da1 indicates that the shielded wiring pattern P1 in the portion of the first contact side a1 from the coordinates N1 to the coordinates N2 is the node name “GND” and the wiring “W4” It shows that the shielded wiring pattern P4 having the width and the distance to the shielded wiring pattern P1 is “D1”.

  The data Da2 indicates that the shielded wiring pattern P1 in the portion of the second contact side a2 from the coordinates N3 to the coordinates N4 has a node name of “GND”, a wiring width of “W4”, and a distance from the shielded wiring pattern P1 of “D2”. It is shown that the shield wiring pattern P4 is shielded.

  The data Da3 indicates that the shielded wiring pattern P1 of the third contact side a3 from the coordinates N4 to the coordinate N5 has a node name of “GND”, a wiring width of “W2”, and a distance from the shielded wiring pattern P1 of “D3”. It is shown that the shield wiring pattern P3 is shielded.

The data Da4 indicates that the shielded wiring pattern P1 in the portion of the fourth contact side a4 from the coordinates N6 to the coordinates N7 is not shielded.
The data Da5 indicates that the shielded wiring pattern P1 in the portion of the fifth contact side a5 from the coordinates N7 to the coordinate N8 and the portion of the sixth contact side a6 in the coordinates N9 to the coordinate N10 is the other wiring pattern P6 of the “node D”. The shielded data Da6 indicates that the shielded wiring pattern P1 in the portion of the seventh contact side a7 from the coordinates N10 to the coordinates N11 is shielded by the other wiring pattern P5 of the “node C”.

  Next, as shown in FIG. 7, the CPU 12 obtains a rectangular area R that is in contact with the rightmost side of the lower side of the shielded wiring pattern P1 in the search area A1 of the layout data 30, and the rectangular area R Is defined as the twentieth rectangular region R20. Similarly, the CPU 12 obtains a rectangular region R that is in contact with the leftmost side of the upper side of the shielded wiring pattern P1 in the search region A1 of the layout data 30, and defines the rectangular region R as the twenty-first rectangular region R21. To do.

First, the CPU 12 creates a synthesis area based on the twentieth rectangular area R20 and the second and ninth rectangular areas R2 and R9 defined above.
First, as shown in FIG. 8, for the ninth rectangular region R9, since there is no other rectangular region R between the ninth rectangular region R9 and the shield wiring pattern P3, the ninth rectangular region R9 itself is changed to the eleventh region. Let it be a synthesis region C11.

  Next, for the second rectangular region R2, the shield wiring patterns P2 to P4 and the other wiring patterns P5 to P7 do not exist below the second rectangular region R2, and the second rectangular region R2 is between the second rectangular region R2 and the search region A1. There are two rectangular regions R (R3, R23). Therefore, the second rectangular region R2 and the two rectangular regions R3 and R23 are combined into one to form a twelfth combined region C12.

  Next, for the twentieth rectangular area R20, there are no shield wiring patterns P2 to P4 and other wiring patterns P5 to P7 below the twentieth rectangular area R20, and the twentieth rectangular area R20 and the search area A1 There is no other rectangular region R between them. Therefore, the twentieth rectangular region R20 itself becomes the thirteenth composite region C13.

  Subsequently, the CPU 12 performs the 14th to 17th synthesis areas C14 in the same manner based on the 21st rectangular area R21 and the previously defined 6th, 14th and 15th rectangular areas R6, R14, R15. Make ~ C17.

  Incidentally, for the fifteenth rectangular area R15, only the other wiring pattern P5 exists on the upper side, and no other rectangular area R exists. Therefore, the fifteenth rectangular region R15 itself becomes the fourteenth composite region C14.

  For the fourteenth rectangular region R14, two rectangular regions R (R17, R24) exist between the fourteenth rectangular region R14 and the shield wiring pattern P2. Therefore, the fourteenth rectangular region R14 and the two rectangular regions R17, R24 are combined into one to form a fifteenth combined region C15.

  Further, for the sixth rectangular region R6, the shield wiring patterns P2 to P4 and the other wiring patterns P5 to P7 do not exist above the sixth rectangular region R6, and there are 5 between the sixth rectangular region R6 and the search region A1. There are two rectangular regions R (R7, R25 to R28). Therefore, the sixth rectangular region R6 and the five rectangular regions R7, R25 to R28 are combined into one to form a sixteenth combined region C16.

  Furthermore, for the twenty-first rectangular region R21, there are no shield wiring patterns P2 to P4 and other wiring patterns P5 to P7 above the twenty-first rectangular region R21, and between the twenty-first rectangular region R21 and the search region A1, There are three rectangular regions R (R29 to R31). Therefore, the twenty-first rectangular region R21 and the three rectangular regions R29 to R31 are combined into one to form a seventeenth combined region C17.

  When the 11th to 17th combined regions C11 to C17 are obtained in this way, the CPU 12 selects the shielded wiring pattern P1 and the shielded wiring patterns P2 to P4 from the 11th to 17th combined regions C11 to C17. The combined area disposed in contact with each other is obtained together with the shield wiring patterns P2 to P4 in contact therewith.

  In this case, as is apparent from FIG. 8, there are two combined regions, eleventh and fifteenth combined regions C11 and C15, which are interposed between the shielded wiring pattern P1 and the shielded wiring patterns P2 to P4.

  Then, for each of the eleventh and fifteenth synthesis regions C11 and C15, the CPU 12 determines the distance between the shield wiring patterns P2 to P4 and the shielded wiring pattern P1 that are in contact with each other, and the shield wiring patterns P2 to P4 that are in contact with each other. The wiring width is stored in the second extraction result data De2.

  Incidentally, since the CPU 12 is in contact with the shield wiring pattern P3 in the eleventh synthetic region C11, the distance “D5” between the shield wiring pattern P3 and the shielded wiring pattern P1 and the vertical direction in FIG. 8 of the shield wiring pattern P3. The wiring width “W3” is stored in the second extraction result data De2.

  Similarly, since the CPU 12 is in contact with the shield wiring pattern P2 in the fifteenth synthetic region C15, the distance “D6” between the shield wiring pattern P2 and the shielded wiring pattern P1 and the wiring width “W1” of the shield wiring pattern P2 Is stored in the second extraction result data De2.

  Next, the CPU 12 contacts the shielded wiring pattern P1 and the other wiring patterns P5 to P7 from among the first to seventeenth synthesis regions C11 to C17, and contacts between the contacted other wiring patterns P5 to P7. The combined region to be arranged is obtained together with the other wiring patterns P5 to P7 that are in contact therewith.

In this case, as is apparent from FIG. 8, the combined region interposed between the shielded wiring pattern P1 and the other wiring patterns P5 to P7 is one of the fourteenth combined regions C14.
And with respect to this 14th synthetic | combination area | region C14, CPU12 memorize | stores the node name of the other wiring patterns P5-P7 which touches it in 2nd extraction result data De2.

  In this case, since the CPU 12 is in contact with the other wiring pattern P5 of the node name “node C” for the fourteenth synthesis region C14, the CPU 12 stores the node name of “node C” in the second extraction result data De2.

  Subsequently, the CPU 12 makes a rectangular region R (in this case, the second, sixth, ninth, fourteenth, fifteenth, twentieth, and twenty-first rectangular regions R2) in contact with the upper side or the lower side of the shielded wiring pattern P1. , R6, R9, R14, R15, R20, R21), the coordinates N1 to N3, N5, N6, N8, N9, N11, N21 to N23 of the left and right ends of the sides are stored in the second extraction result data De2.

  In this case, the second, sixth, ninth, fourteenth, fifteenth, twentieth, and twenty-first rectangular regions R2, R6, R9, R14, R15, and R20 are in contact with the upper side or the lower side of the shielded wiring pattern P1. , R21 are the 11th to 17th contact sides a11 to a17, respectively, the 11th to 17th contact sides a11 to a17 have coordinates N1 to N3, N5, N6, N8, N9, N11, N21 to It can be represented at N23.

  Incidentally, the eleventh contact side a11 is represented by coordinates N2 and N21, the twelfth contact side a12 is represented by coordinates N3 and N21, and the thirteenth contact side a13 is represented by coordinates N5 and N6. The fourteenth contact side a14 is represented by coordinates N8 and N22, and the fifteenth contact side a15 is represented by coordinates N22 and N23. Further, the sixteenth contact side a16 is represented by coordinates N9 and N23, and the seventeenth contact side a17 is represented by coordinates N1 and N11.

  With the above processing, the CPU 12 performs the 11th to 17th combined regions C11 to 11 corresponding to the 11th to 17th contact sides a11 to a17 for each of the 11th to 17th contact sides a11 to a17 as shown in FIG. Information on shield wiring patterns P2 to P4 or other wiring patterns P5 to P7 facing each other through C17 is stored in the first extraction result data De1.

  Specifically, in the second extraction result data De2, the data Da11 indicates that the shielded wiring pattern P1 in the portion of the eleventh contact side a11 from the coordinates N2 to the coordinates N21 is the node name “GND”, the wiring width “W3” This indicates that the shielded wiring pattern P3 having the distance “D5” from the shielded wiring pattern P1 is shielded.

  The data Da12 indicates that the shielded wiring pattern P1 in the portion of the twelfth contact side a12 from the coordinates N3 to the coordinate N21 and the portion of the thirteenth contact side a13 from the coordinates N5 to the coordinate N6 is not shielded.

  The data Da13 indicates that the shielded wiring pattern P1 in the portion of the fourteenth contact side a14 from the coordinates N8 to the coordinates N22 is shielded by the other wiring pattern P5 having the node name “node C”.

  The data Da14 indicates that the shielded wiring pattern P1 in the portion of the fifteenth contact side a15 from the coordinates N22 to the coordinate N23 has a node name of “GND”, a wiring width of “W1”, and a distance from the shielded wiring pattern P1 of “D6”. It is shown that the shield wiring pattern P2 is shielded.

  The data Da15 indicates that the shielded wiring pattern P1 in the portion of the sixteenth contact side a16 from the coordinates N9 to the coordinate N23 and the portion of the seventeenth contact side a17 in the coordinates N1 to the coordinate N11 is not shielded.

  Subsequently, the CPU 12 sets the reduced search areas A11 to A16 for the shielded wiring pattern P1, based on the control card 21, as shown in FIG. That is, the reduced search areas A11 to A16 are set based on the coordinates N1, N2, N5, N6, N8, and N11 of each vertex of the shielded wiring pattern P1. Then, the CPU 12 sets the shielded wiring pattern P1 as an expansion distance by using a distance (ignore distance) di1 (4 microns in the present embodiment) in which the different node defined in the control card 21 can be ignored. The sides intersected by the coordinates N1, N2, N5, N6, N8, and N11 of the vertices of P1 are respectively extended outward by the distance (ignition distance) di1. Further, the CPU 12 defines the areas surrounded by the extended side and the boundary line of the search area A1 as the reduced search areas A11 to A16, respectively.

  The shield state extraction process of the reduced search area A11 will be described with reference to FIGS. 10 (a) to 10 (c). Since the CPU 12 performs the same process as the shield state extraction process of the reduced search area A11 for the shield state extraction process of the reduced search areas A12 to A16, the description thereof will be omitted for convenience of description.

  As shown in FIG. 10A, the CPU 12 in the reduced search area A11 has a quadrangular area centered on the vertex (coordinate N1) of the shielded wiring pattern P1 and the radius di1 (expansion distance). Is set as the shield area SA. Then, the CPU 12 sets a rectangular area R (in this case, a rectangular area R31) that is completely out of the shield area SA in the reduced search area A11 as a rectangular area R that is not subject to processing.

  Next, as shown in FIG. 10B, the CPU 12 has a rectangular area in contact with the vertex (coordinate N1) of the shielded wiring pattern P1 among the rectangular areas R in the set quadrant shield area SA. R (in this case, the 32nd rectangular region R32) is obtained.

  Next, the CPU 12 comes into contact with the vertex 32 of the thirty-second rectangular region R32 that is diagonally opposed to the vertex (coordinate N1) of the shielded wiring pattern P1 and is the thirty-second rectangular region R32. A rectangular area R (in this case, a 33rd rectangular area R33) located diagonally to the area R32 is obtained.

  Further, the CPU 12 contacts the vertex b2 that is diagonally opposite to the vertex b1 of the thirty-second rectangular region R32 and is positioned diagonally with respect to the thirty-third rectangular region R33. The rectangular area R to be performed (in this case, the 34th rectangular area R34) is obtained.

  That is, the CPU 12 is a rectangular region R that is partly included in the shield region SA, and is a rectangular region R that is arranged at an angle of 45 ° to the left with respect to the vertex (coordinate N1) of the shielded wiring pattern P1. (32nd to 34th rectangular regions R32 to R34) are obtained.

  Subsequently, as shown in FIG. 10C, the CPU 12 performs shield wiring in the reduced search area A11 for each of the obtained 32nd to 34th rectangular areas R32 to R34 in the vertical and horizontal directions in FIG. It is verified whether the patterns P2 to P4 or the other wiring patterns P5 to P7 exist.

  When the shield wiring patterns P2 to P4 are present in the vertical and horizontal directions of the rectangular regions R32 to R34, the CPU 12 determines the distance between the shield wiring patterns P2 to P4 and the shielded wiring pattern P1, and the shield wiring pattern P2. The wiring width of P4 is stored in the third extraction result data De3.

  On the other hand, the CPU 12 stores the node names of the other wiring patterns P5 to P7 in the third extraction result data De3 when the other wiring patterns P5 to P7 exist in the vertical and horizontal directions of the 32nd to 34th rectangular regions R32 to R34. .

  Specifically, first, the CPU 12 does not create the third extraction result data De3 because the shield wiring patterns P2 to P4 and the other wiring patterns P5 to P7 do not exist above the 32nd rectangular region R32.

  Next, the CPU 12 has a shield wiring pattern P4 on the left side of the thirty-second rectangular region R32. Therefore, the CPU 12 stores the distance “D1” between the shield wiring pattern P4 and the shielded wiring pattern P1 and the wiring width “W4” of the shield wiring pattern P4 in the third extraction result data De3.

  Subsequently, the CPU 12 has another wiring pattern P7 in the upward direction of the 33rd rectangular region R33. Therefore, the CPU 12 stores the node name “node E” of the other wiring pattern P7 in the third extraction result data De3.

  The CPU 12 does not create the third extraction result data De3 because the shield wiring patterns P2 to P4 or the other wiring patterns P5 to P7 do not exist in the left direction of the 33rd rectangular area R33.

  Next, the CPU 12 does not create the third extraction result data De3 because there are no shield wiring patterns P2 to P4 or other wiring patterns P5 to P7 above the 34th rectangular region R34.

Subsequently, the CPU 12 does not have shield wiring patterns P2 to P4 or other wiring patterns P5 to P7 in the left direction of the 34th rectangular region R34.
Thereby, by the above processing, the CPU 12 obtains the third information on the shield wiring patterns P2 to P4 and the other wiring patterns P5 to P7 corresponding to the shielded wiring pattern P1 having the vertex (coordinate N1) as shown in FIG. Stored in the extraction result data De3.

Specifically, the data Da31 indicates that the shielded wiring pattern P1 at the coordinate N1 is shielded by the other wiring pattern P7 at “node E”.
Further, the data Da32 is shielded by the shielded wiring pattern whose coordinate N1 is the shielded wiring pattern P1 having the node name “GND”, the wiring width “W4”, and the distance from the shielded wiring pattern P1 is “D1”. It is shown that.

  And CPU12 reads said 1st-3rd extraction result data De1-De3, synthesize | combines the 1st-3rd extraction result data De1-De3, and produces | generates extraction result data De.

FIG. 14 is a configuration diagram of an example of the extraction result data De described above.
The extraction result data De has a hierarchical structure (Hierarchy Condition) 31 of each condition and result, a common condition 32, and first to third results 33 to 35.

In the extraction result data De, first to third extraction result data 33 to 35 are described based on each condition and a hierarchical structure (Hierarchy Condition) of the results.
That is, in the hierarchical structure (Hierarchy Condition) 31 of each condition, the hierarchy of the described condition is higher as it is described on the left side. Conversely, the hierarchy of the described condition is lower as it is described on the right side. That is, in the extraction result data De, the net name (target_node) of the shielded wiring pattern P1, the layer name (shield_layer) of the shield wiring pattern, the net name (shield_node) of the wiring pattern to be shielded, the width (shield_width) of the shield wiring pattern, Hierarchies are lower in the order of distance (distance 1) in which different nodes can be ignored.

  Therefore, the extraction result data De is described based on each condition and the hierarchical structure of the result (Hierarchy Condition), so that the net name (1) of the shielded wiring pattern P1 of the common condition 32 is added to the first to third results 33 to 35. (target_node) and the layer names (shield_layer) of the shield wiring patterns P2 to P4 are not required to be described, which can be simplified.

  The common condition 32 describes the net name (target_node) of the shielded wiring pattern P1 and the layer names (shield_layer) of the shield wiring patterns P2 to P4. The net name (target_node) of the shielded wiring pattern P1 is described as “NetA / N1, N2, N3, N5, N6, N8, N9, N11 / 1 Metal_Layer”, and the extraction result data De is “NetA”. N1, N2, N5, N6, N8, N11 ”is the result for the shielded wiring pattern P1 of the outer shape having the apex, the layer“ 1Metal_Layer ”.

  The layer name (shield_layer) of the shield wiring patterns P2 to P4 is described as “same”, and the extraction result data De shields the shielded wiring pattern P1 with the shield wiring patterns P2 to P4 in the same layer as the shielded wiring pattern. The result is shown.

The first result 33 includes a net name (shield_node) of the wiring pattern to be shielded and detailed results 41 to 44.
The net name (shield_node) of the wiring pattern to be shielded is described as “GND”, and the first result 33 indicates that the shielded wiring pattern P1 is shielded by the shield wiring patterns P2 to P4 having the net name “GND”. ing.

  The detailed result 41 shows that the width (shield_width) of the shield wiring pattern P4 is “W4”, the distance (shield_distance) between the shielded wiring pattern P1 and the shield wiring pattern P4 is “D1: N1 to N2”, “D2: N3 to N4”. The shielded wiring pattern P1 from the coordinates “N1” to the coordinates “N2” is shielded by the shield wiring pattern P4 having the wiring width “W4” with a wiring interval “D1”, and from the coordinates “N3”. This shows that the shielded wiring pattern P1 of the coordinate “N4” is shielded by the shield wiring pattern P4 of the wiring width “W4” with a wiring interval “D2”.

  In the detailed result 42, the width (shield_width) of the shield wiring pattern P3 is described as “W2”, the distance (shield_distance) between the shielded wiring pattern P1 and the shield wiring pattern P3 is described as “D3: N4 to N5”, and the coordinates “N4”. ”Indicates that the shielded wiring pattern P1 having the coordinates“ N5 ”is shielded by the shield wiring pattern P3 having the wiring width“ W2 ”with a wiring interval“ D3 ”.

  In the detailed result 43, the wiring width (shield_width) of the shield wiring pattern P2 is described as “W1”, the distance (shield_distance) between the shielded wiring pattern P1 and the shield wiring pattern P2 is described as “D6: N22 to N23”, and the coordinates “ This shows that the shielded wiring pattern P1 having the coordinates “N23” from “N22” is shielded by the shield wiring pattern P2 having the wiring width “W1” with a wiring interval “D6”.

  In the detailed result 44, the wiring width (shield_width) of the shield wiring pattern P3 is described as “W3”, the distance (shield_distance) between the shielded wiring pattern P1 and the shield wiring pattern P3 is described as “D4: N2 to N21”, and the coordinates “ This shows that the shielded wiring pattern P1 having the coordinates “N21” from “N2” is shielded by the shield wiring pattern P3 having the wiring width “W3” with a wiring interval “D5”.

  In the second result 34, the net name (shield_node) of the wiring pattern to be shielded is described as “NodeC: N8 to N22, N10 to N11”, the coordinates “N8” to the coordinates “N22”, and the coordinates “N10” to the coordinates “N11”. The shielded wiring pattern P1 of “” is shielded by the other wiring pattern P5 of “node C”.

  In the second result 34, the net name (shield_node) of the wiring pattern to be shielded is described as “NodeD: N7 to N8, N8 to N9”, the coordinates “N7” to the coordinates “N8”, and the coordinates “N8” to the coordinates. The shielded wiring pattern P1 of “N9” is shielded by the other wiring pattern P6 of “node D”.

  Furthermore, in the second result 34, the net name (shield_node) of the wiring pattern to be shielded is described as “ignore: N1 to N11, N3 to N21, N5 to N6, N6 to N7, N9 to N23”, and the coordinates “N1”. To coordinates “N11”, coordinates “N3” to coordinates “N21”, coordinates “N5” to coordinates “N6”, coordinates “N6” to coordinates “N7”, coordinates “N9” to coordinates “N23” This indicates that no wiring pattern is arranged within a distance (distance) di1 in which a different node defined by the control card 21 can be ignored with respect to the pattern P1.

  The fourth result 35 is that the shielded wiring pattern P1 at the coordinate “N1” is shielded by the wiring pattern P7 at the “node E”, and the shielded wiring pattern P1 at the coordinate “N1” is the node “GND”, the wiring width. It shows that the shield wiring pattern P4 of “W4” is shielded with a wiring interval “D1”.

  When the shield state extraction process (step S2) is completed, the CPU 12 determines, based on the control card 21, whether or not the layout data 30 is correctly shielded from the extraction result data De (step S3, verification process, Verification means).

  If it is determined that the layout data 30 is properly shielded (YES in step S3), the CPU 12 completes the process. On the contrary, if it is determined that the shielding of the layout data 30 is not properly performed (NO in step S3), the CPU 12 uses the item of the extraction result data De determined as an error as an error list or a layout reflecting the content of the error. The data 30 is displayed on the display device 15 (step S4), and the process is completed.

  Specifically, the CPU 12 determines whether or not the wiring width (shield_width) We of the shield wiring pattern of the extraction result data De is equal to or greater than a value Wr defined in the control card 21 (2 microns in this embodiment). In other words, when the wiring width (shield_width) We of the shield wiring pattern of the extraction result data De is equal to or greater than the value Wr defined in the control card 21, the CPU 12 determines that the shield is normally shielded. Conversely, when the wiring width (shield_width) We of the shield wiring pattern of the extraction result data De is smaller than the value Wr defined in the control card 21, the CPU 12 determines that the shield is not normally shielded.

  Further, the CPU 12 determines whether or not there is a wiring pattern other than the net name (shield_node) of the wiring pattern to be shielded defined in the control card 21 in the extraction result data De. In other words, when there is a wiring pattern other than the net name (shield_node) of the wiring pattern to be shielded defined in the control card 21 in the extraction result data De, the CPU 12 determines that the wiring pattern is an error. Conversely, when there is no wiring pattern other than the net name (shield_node) of the wiring pattern to be shielded defined in the control card 21 in the extraction result data De, the CPU 12 determines that the shield is normally shielded.

As described above, according to the present embodiment, the following effects can be obtained.
(1) It is detected whether each of the combined regions C1 to C7 and C11 to C17 that are in contact with all sides of the shielded wiring pattern P1 is in contact with the shield wiring patterns P2 to P4 or the other wiring patterns P5 to P7. I made it. Therefore, in the conventional logical operation, there is a case where the side of the shielded wiring pattern P1 that is not shielded is erroneously determined to be shielded, but the shielded wiring pattern P2 that shields all the sides of the shielded wiring pattern P1. ~ P4 can be reliably detected.

As a result, the verification apparatus 11 can verify the shield of the layout data 30 with high accuracy.
(2) Further, in the rectangular area R, search is performed between the shielded wiring pattern P1 and the shielded wiring patterns P2 to P4, between the shielded wiring pattern P1 and the other wiring patterns P5 to P7, and with the shielded wiring pattern P1. A synthesized area is generated by synthesizing one rectangular area R between the area A1.

  Therefore, in the conventional logical operation, the shield wiring patterns P2 to P4 cannot be detected if the distance between the shield wiring patterns P2 to P4 and the shielded wiring pattern P1 is large, but the shield wiring patterns P2 to P4 are not detected. Even if the distance between the shielded wiring pattern P1 and the shielded wiring pattern P1 is large, the shielded wiring patterns P2 to P4 can be detected.

As a result, the verification device 11 can verify the shield of the layout data 30 with higher accuracy.
In addition, you may implement the said embodiment in the following aspects.
The format of the control card 21 and the extraction result data De in the above embodiment is not particularly limited.

14 Storage area 20 Reference value information (control card)
A1 Search area C1 to C7, C11 to C17 Composite area De Wiring pattern information (extraction result data)
P1 shielded wiring pattern P1 to P7 wiring pattern P2 to P4 shield wiring pattern R1 to R38 rectangular area R32 first search rectangular area (32nd rectangular area)
R33, R34 Second search rectangular area (33rd and 34th rectangular areas)

Claims (5)

A layout verification method of a semiconductor device,
Processor sets a distance apart search area based on the design standard value with respect to the shielded wire pattern,
Wherein the processing unit sets a plurality of rectangular regions to a region excluding said each wiring pattern of the set the search region,
The processing device, among the set plurality of the rectangular area, between the object to be shielded wiring pattern and the sheet Rudo wiring pattern, or one said rectangular area is between said the shielded wire pattern the search area synthesized to generate a synthesized region,
The processing device stores the information of the shield interconnection patterns or other wiring pattern in contact with the synthetic region in the storage area,
The processing apparatus is configured to obtain information on the shield wiring pattern and the other wiring patterns that are in contact with the combined area stored in the storage area based on information on reference values for the information on the shield wiring patterns and the other wiring patterns. Te, verify whether it is shielded by the can the shielded wire pattern the shielding wiring pattern
Layout verification method, wherein a call. The layout verification method according to claim 1,
The processing device is
In the search area, the object to be shielded wiring pattern included in the search area, the shield wiring pattern and draw a lead line from the apex of the other wiring patterns in the vertical and horizontal directions, the rectangular region is partitioned and formed by the lead line A layout verification method characterized by: The layout verification method according to claim 1 or 2,
The processing device is
In the search area, extend a side passing through the vertex of the shielded wiring pattern, and set an area surrounded by the extended side and the search area as a reduced search area,
In the reduced search area, set a quadrilateral area with a distance based on the design criteria as a half centered on the vertex of the shielded wiring pattern,
Of the rectangular areas in the set quadrant area, obtain a rectangular area that contacts the vertex of the shielded wiring pattern as a first search rectangular area,
In the quadrangular area, a rectangular area located diagonally with respect to the vertex of the shielded wiring pattern of the obtained first search rectangular area is obtained as a second search rectangular area.
In the quadrangular region, search for the shield wiring pattern or other wiring pattern in the vertical and horizontal directions from the obtained first and second search rectangular regions,
A layout verification method characterized in that information on the searched shield wiring pattern or other wiring pattern is stored in the storage area. The layout verification method according to any one of claims 1 to 3,
The wiring pattern information and the reference value information are:
A layout verification method characterized in that each item has a hierarchical structure. In a layout design of a semiconductor device, a layout verification device for verifying whether a shielded wiring pattern is shielded by a shield wiring pattern,
Search area setting means for setting a search area at a distance based on the design reference value for the shielded wiring pattern;
A rectangular area setting means for setting a plurality of rectangular areas in an area excluding the wiring patterns of the set search area;
Among the plurality of set rectangular areas, the rectangular areas between the shielded wiring pattern and the shielded wiring pattern or between the shielded wiring pattern and the search area are combined into one. A synthetic area setting means for generating an area;
Wiring information extraction means for storing information on a shield wiring pattern or other wiring pattern in contact with the combined area in a storage area;
Information on the shield wiring pattern and the other wiring patterns that are in contact with the composite area stored in the storage area is obtained based on information on a reference value for the information on the shield wiring pattern and other wiring patterns. And a verification means for verifying whether or not the wiring pattern is shielded by the shield wiring pattern.

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