JP2013153511A - Solid-state imaging apparatus, method for driving solid-state imaging apparatus, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a picked-up image from becoming laterally long by suppressing reduction in an angle of view when performing interlaced scan on pixel rows.SOLUTION: For example, two systems of pixel driving lines 17A, 17B are wired for each pixel row, and respective pixels 20 are connected to the pixel driving lines 17A, 17B in a unit of two adjacent columns, thereby enabling simultaneous scanning of two pixel rows in different pixel columns. Then, horizontal thinning readout is performed while vertical thinning readout is performed, so that a picked-up image is prevented from becoming laterally long by suppressing reduction in an angle of view while high-speed imaging is realized by reducing the number of vertical readout lines.

Description

  The present disclosure relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic apparatus.

  An imaging device that converts light into an electrical signal and outputs an image signal, such as a digital still camera, uses a solid-state imaging device as its image capturing unit (photoelectric conversion unit). In recent years, in the field of solid-state imaging devices, with the increase in the number of pixels and the increase in frame rate, a technology for realizing high-speed reading and a technology for reducing power consumption have become indispensable technologies.

  As one type of solid-state imaging device, there is a CMOS (including MOS) type image sensor (hereinafter referred to as “CMOS image sensor”) utilizing characteristics that can be manufactured by the same process as a CMOS integrated circuit. The CMOS image sensor has a configuration in which electric charges are converted into electric signals for each pixel, and electric signals read from the pixels are processed in parallel for each pixel column. By the parallel processing for each pixel column, the reading speed of the pixel signal can be improved.

Conventionally, as a CMOS image sensor that reads signals from a plurality of pixels arranged in a matrix in parallel for each pixel column, a column that performs analog-digital conversion (hereinafter referred to as “A conversion”) for each pixel column. An AD conversion type is known (for example, see Patent Document 1).

  A column AD conversion type CMOS image sensor shares a signal readout line (hereinafter referred to as “vertical signal line”) in the vertical direction of pixels arranged in a two-dimensional matrix, and an AD conversion circuit for each pixel column. And the structure which provided the read-out circuit is taken. Simultaneous signal processing equivalent to the total number of pixel columns is performed by simultaneously driving the AD conversion circuit and the readout circuit.

  The AD conversion circuit compares the analog pixel signal applied through the vertical signal line with a reference signal having a slope that changes linearly with a slope and linearly changes for each pixel column, and simultaneously starts the count operation of the counter. The counter performs a counting operation in synchronization with a clock having a fixed period.

  Thereafter, the AD converter circuit crosses the analog pixel signal and the reference signal, and stops the counting operation of the counter at the inversion timing of the output of the comparator. The final count value of the counter becomes a digital signal corresponding to the magnitude of the analog pixel signal. As described above, the column AD conversion method is a readout method characterized by high-speed imaging in order to A / D convert pixel signals for one row at a time.

JP-A-2005-278135

  In recent years, the demand for high-speed imaging has been increasing. In the column AD conversion type CMOS image sensor, the demand has been met by reducing the number of vertical readouts (number of rows / number of lines). As a method for reducing the number of vertical readouts, for example, there is a method called interlaced scanning such as vertical thinning readout for skipping a pixel row at a constant row period, or vertical cutout for reading a pixel signal in a specific region in the vertical direction. However, when the number of readouts is reduced by thinning readout, the resolution is deteriorated, and when the number of vertical readouts is reduced by interlaced scanning, there is a problem that the captured image becomes horizontally long due to the reduction of the angle of view.

  Accordingly, the present invention provides a solid-state imaging device capable of reducing resolution deterioration during vertical thinning, and preventing a captured image from becoming horizontally long by suppressing a reduction in the angle of view when scanning interlaced pixel rows. An object is to provide a driving method of an imaging apparatus and an electronic apparatus.

The solid-state imaging device according to the present invention is
A pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and pixel drive lines that transmit a drive signal for driving to read out signals from the pixels are wired for a plurality of systems for each pixel row;
A row scanning unit that simultaneously outputs the drive signals through the plurality of pixel drive lines to a plurality of pixel rows in different pixel columns.

  By simultaneously outputting pixel drive signals from a row scanning unit to a plurality of pixel rows in different pixel columns through a plurality of pixel drive lines, a plurality of pixel rows can be simultaneously scanned in different pixel columns. As a result, for a plurality of pixel rows, signals are read from some of the pixels instead of all the pixels in one pixel row. In other words, if attention is paid to one pixel row, the signals of some pixels are thinned out during signal readout. Since the number of signals in the horizontal direction can be reduced by this horizontal thinning readout, the frame rate can be improved as compared with the case where horizontal thinning readout is not performed, and the field angle is reduced when interlaced scanning is performed. Can be suppressed.

Other solid-state imaging devices according to the present invention are:
A pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and signal lines for transmitting signals read from the pixels are wired for a plurality of systems for each pixel column;
A row scanning unit that simultaneously outputs a driving signal for performing driving for reading signals from the pixels to a plurality of pixel rows.

  By simultaneously outputting pixel drive signals to a plurality of pixel rows from the row scanning unit, pixel signals are read from the plurality of pixel rows to a plurality of signal lines. At this time, when any one of a plurality of signal lines is selected for each pixel column, signals are read from some of the pixels instead of all the pixels in one pixel row. In other words, if attention is paid to one pixel row, the signals of some pixels are thinned out during signal readout. Since the number of signals in the horizontal direction can be reduced by this horizontal thinning readout, the frame rate can be improved as compared with the case where horizontal thinning readout is not performed, and the field angle is reduced when interlaced scanning is performed. Can be suppressed.

  According to the present invention, it is possible to prevent the captured image from becoming horizontally long by performing horizontal thinning readout by performing horizontal thinning readout when performing interlace scanning of pixel rows. .

1 is a system configuration diagram showing an outline of a system configuration of a CMOS image sensor to which the present invention is applied. It is a circuit diagram which shows an example of the circuit structure of a unit pixel. 1 is a system configuration diagram showing an outline of a system configuration of a CMOS image sensor according to a first embodiment of the present invention. It is a connection diagram which shows the example of a connection of the unit pixel with respect to 2 types of pixel drive lines. It is a figure which shows the color coding of RGB Bayer arrangement | sequence. It is operation | movement explanatory drawing about the example of a drive in the simultaneous scanning mode of the several pixel row in the CMOS image sensor which concerns on 1st Embodiment. It is a figure explaining the effect by the CMOS image sensor which concerns on 1st Embodiment. It is a block diagram which shows an example of a structure of the column scanning part in the case of taking the method of changing a column scanning order. It is operation | movement explanatory drawing about the drive example of the scanning mode of the single pixel row in the CMOS image sensor which concerns on 1st Embodiment. It is a system configuration | structure figure which shows the outline of the system configuration | structure of the CMOS image sensor which concerns on 2nd Embodiment of this invention. It is operation | movement explanatory drawing about the drive example of the simultaneous scanning mode of the several pixel row in the CMOS image sensor which concerns on 2nd Embodiment. It is operation | movement explanatory drawing about the drive example of the scanning mode of the single pixel row in the CMOS image sensor which concerns on 2nd Embodiment. It is a system configuration | structure figure which shows the outline of the system configuration | structure of the CMOS image sensor which concerns on 3rd Embodiment of this invention. It is a system configuration | structure figure which shows the outline of the system configuration | structure of the CMOS image sensor which concerns on 4th Embodiment of this invention. It is sectional drawing which shows a back-illuminated pixel structure. It is a block diagram which shows the structural example of the imaging device which is an example of the electronic device by this invention.

Hereinafter, modes for carrying out the invention (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The description will be given in the following order.
1. 1. Solid-state imaging device to which the present invention is applied First Embodiment (An example in which two pixel drive lines are provided for each pixel row)
3. Second Embodiment (Example in which two vertical signal lines are provided for each pixel column)
4). Third Embodiment (Example of vertical pixel addition)
5. Fourth embodiment (example of horizontal thinning readout + vertical pixel addition)
6). 6. Back-illuminated pixel structure Electronic equipment (example of imaging device)

<1. Solid-state imaging device to which the present invention is applied>
(System configuration)
FIG. 1 is a system configuration diagram showing an outline of a system configuration of a solid-state imaging device to which the present invention is applied, for example, a CMOS image sensor which is a kind of XY address type solid-state imaging device. Here, the CMOS image sensor is an image sensor created by applying or partially using a CMOS process.

  The CMOS image sensor 10 according to this application example is integrated on a pixel array unit 12 formed on a semiconductor substrate (hereinafter also referred to as “chip”) 11 and on the same chip 11 as the pixel array unit 12. And a peripheral circuit portion. In this example, for example, a row scanning unit 13, a column processing unit 14, a column scanning unit 15, and a system control unit 16 are provided as peripheral circuit units.

  In the pixel array unit 12, unit pixels (hereinafter sometimes simply referred to as “pixels”) having photoelectric conversion elements that generate photoelectric charges having a charge amount corresponding to the amount of incident light and store them in a matrix form are arranged in a matrix. Two-dimensional arrangement. A specific configuration of the unit pixel will be described later.

  The pixel array section 12 is further provided with a pixel drive line 17 for each pixel row with respect to the matrix-like pixel arrangement along the horizontal direction / row direction (pixel arrangement direction of the pixel row), and vertical for each pixel column. The signal line 18 is wired along the vertical direction / column direction (pixel arrangement direction of the pixel column). The pixel drive line 17 transmits a drive signal for driving to read a signal from the pixel. In FIG. 1, the pixel drive line 17 is shown as one wiring, but the number is not limited to one. One end of the pixel drive line 17 is connected to an output end corresponding to each row of the row scanning unit 13.

  The row scanning unit 13 includes a shift register, an address decoder, and the like, and is a pixel driving unit that drives each pixel of the pixel array unit 12 at the same time or in units of rows. Although the specific configuration of the row scanning unit 13 is not shown, the row scanning unit 13 generally has two scanning systems, a reading scanning system and a sweeping scanning system.

  The readout scanning system selectively scans the unit pixels of the pixel array unit 12 sequentially in units of rows in order to read out signals from the unit pixels. The signal read from the unit pixel is an analog signal. The sweep-out scanning system performs sweep-out scanning with respect to the readout row on which readout scanning is performed by the readout scanning system, preceding the readout scanning by a time corresponding to the shutter speed.

  By the sweep scanning by the sweep scanning system, unnecessary charges are swept out from the photoelectric conversion elements of the unit pixels in the readout row, so that the photoelectric conversion elements are reset. A so-called electronic shutter operation is performed by sweeping (reset) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion element is discarded and a new exposure is started (photocharge accumulation is started).

  The signal read by the reading operation by the reading scanning system corresponds to the amount of light incident after the immediately preceding reading operation or electronic shutter operation. The period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photocharge accumulation period (exposure period) in the unit pixel.

  A signal output from each unit pixel in the pixel row selectively scanned by the row scanning unit 13 is supplied to the column processing unit 14 through each vertical signal line 18. For each pixel column of the pixel array unit 12, the column processing unit 14 performs predetermined signal processing on a signal output from each pixel of the selected row through the vertical signal line 18, and temporarily outputs the pixel signal after the signal processing. Hold on.

  Specifically, the column processing unit 14 receives a signal of a unit pixel and removes noise from the signal by, for example, CDS (Correlated Double Sampling), signal amplification, or AD (analog-digital). ) Perform signal processing such as conversion. By the noise removal processing, fixed pattern noise unique to the pixel such as reset noise and variation in threshold value of the amplification transistor is removed. The signal processing illustrated here is only an example, and the signal processing is not limited to these.

  The column scanning unit 15 includes a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 14. By the selective scanning by the column scanning unit 15, the pixel signals processed by the column processing unit 14 are sequentially output to the horizontal bus 19 and transmitted to the outside of the chip 11 through the horizontal bus 19.

  The system control unit 16 receives a clock given from the outside of the chip 11, data for instructing an operation mode, and the like, and outputs data such as internal information of the CMOS image sensor 10. The system control unit 16 further includes a timing generator that generates various timing signals. Based on the various timing signals generated by the timing generator, the row scanning unit 13, the column processing unit 14, the column scanning unit 15, and the like. Drive control of the peripheral circuit section is performed.

(Circuit configuration of unit pixel)
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the unit pixel 20. As shown in FIG. 2, the unit pixel 20 according to this circuit example includes, for example, four transistors such as a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to a photodiode 21 that is a photoelectric conversion unit. It has composition which has.

  Here, as the four transistors 22 to 25, for example, N-channel MOS transistors are used. However, the conductivity type combinations of the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 illustrated here are merely examples, and are not limited to these combinations.

  For the unit pixel 20, as the pixel drive line 17, for example, three drive wirings of a transfer line 171, a reset line 172, and a selection line 173 are provided in common for each pixel in the same pixel row. One end of each of the transfer line 171, the reset line 172, and the selection line 173 is connected to an output end corresponding to each pixel row of the row scanning unit 13 in units of pixel rows, and is a transfer that is a drive signal for driving the pixels 20. A pulse φTRF, a reset pulse φRST, and a selection pulse φSEL are transmitted.

  The photodiode 21 has an anode electrode connected to a negative power source (for example, ground), and photoelectrically converts the received light into a photocharge (here, photoelectrons) having a charge amount corresponding to the amount of light. Accumulate. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 through the transfer transistor 22. A node 26 electrically connected to the gate electrode of the amplification transistor 24 is referred to as an FD (floating diffusion) portion.

  The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and the FD portion 26. A transfer pulse φTRF in which the high level (for example, Vdd level) is active (hereinafter referred to as “High active”) is applied to the gate electrode of the transfer transistor 22 via the transfer line 171. Thereby, the transfer transistor 22 is turned on, and the photoelectric charge photoelectrically converted by the photodiode 21 is transferred to the FD unit 26.

  The reset transistor 23 has a drain electrode connected to the pixel power source Vdd and a source electrode connected to the FD unit 26. A high active reset pulse φRST is applied to the gate electrode of the reset transistor 23 via the reset line 172. As a result, the reset transistor 23 is turned on, and the FD unit 26 is reset by discarding the charge of the FD unit 26 to the pixel power supply Vdd.

  The amplification transistor 24 has a gate electrode connected to the FD unit 26 and a drain electrode connected to the pixel power source Vdd. Then, the amplification transistor 24 outputs the potential of the FD unit 26 after being reset by the reset transistor 23 as a reset signal (reset level) Vreset. The amplification transistor 24 further outputs the potential of the FD unit 26 after the transfer of the signal charge by the transfer transistor 22 as a light accumulation signal (signal level) Vsig.

  For example, the selection transistor 25 has a drain electrode connected to the source electrode of the amplification transistor 24 and a source electrode connected to the vertical signal line 18. A high active selection pulse φSEL is applied to the gate electrode of the selection transistor 25 via a selection line 173. As a result, the selection transistor 25 is turned on, and the unit pixel 20 is selected and the signal output from the amplification transistor 24 is relayed to the vertical signal line 18.

  Note that the selection transistor 25 may have a circuit configuration connected between the pixel power supply Vdd and the drain of the amplification transistor 24.

  In addition, the unit pixel 20 is not limited to the pixel configuration including the four transistors having the above configuration. For example, a pixel configuration including three transistors that serve as both the amplification transistor 24 and the selection transistor 25 may be used, and the configuration of the pixel circuit is not limited.

<2. First Embodiment>
FIG. 3 is a system configuration diagram showing an outline of the system configuration of the CMOS image sensor 10A according to the first embodiment of the present invention. In FIG. 3, the same parts as those in FIG.

  The CMOS image sensor 10A according to the present embodiment has a configuration in which the pixel drive lines 17 are wired in a plurality of systems, for example, two systems for each pixel row. The unit pixel 20 is connected in units of two adjacent columns to the two systems of pixel drive lines 17A and 17B. Specifically, each pixel 20 in the first and second pixel columns from the left in the figure is the pixel drive line 17A, and each pixel 20 in the third and fourth pixel columns is the pixel drive line 17B. Each pixel 20 in the fifth and sixth pixel columns is connected to the pixel drive line 17A.

  The unit pixel 20 is driven through one of the two systems of pixel drive lines 17A and 17B. In FIG. 3, the two pixel drive lines 17A and 17B are shown as one wiring. However, when the unit pixel 20 has the pixel configuration shown in FIG. 2, the pixel drive lines 17A and 17B are respectively For example, it is composed of three wirings of a transfer line 171, a reset line 172 and a selection line 173.

  When connecting each pixel 20 to the pixel drive lines 17A and 17B, the pixels 20 may be directly connected, or if the chip 11 has a sufficient size, a connection configuration in which a switch is interposed may be employed. As an example, the case where the pixel drive line 17 to be connected is the transfer line 171 (171A, 171B) will be specifically described with reference to FIG.

  In the case of direct connection (A) in FIG. 4, the gate electrode of the transfer transistor 22 is directly connected to the transfer lines 171A and 171B in units of two adjacent columns as in FIGS. In the case of connection (B) with a switch interposed, the gate electrode of the transfer transistor 22 is connected to the transfer lines 171A and 171B via the switch SW for all pixel rows.

  Then, by setting the switch SW to the switching state as shown in FIG. 4B, for example, the same connection relationship as that in FIG. 4A can be obtained. That is, according to the connection example (B) in which the switch SW is interposed, it is possible to select which of the transfer lines 171A and 171B is connected to the gate electrode of the transfer transistor 22 by switching the switch SW. Therefore, the connection between the transfer lines 171A and 171B and the unit pixel 20 can be freely changed.

  While two pixel drive lines 17A and 17B are wired for each pixel row, the row scanning unit 13 has a mode for scanning a single pixel row and a mode for simultaneously scanning a plurality of pixel rows. It is the structure which can take selectively. This mode switching is performed under the control of the system control unit 16 based on designation from the outside.

  In the case of the scanning mode for a single pixel row, the row scanning unit 13 drives the driving signals (transfer pulse φTRF, reset pulse φRST and selection pulse) through the two pixel drive lines 17A and 17B for the single pixel row. Pulse φSEL) is output simultaneously. According to the row scanning by the row scanning unit 13, a signal can be read from each pixel of the selected row while selecting a readout row in order for each pixel row, as in the conventional case.

  In the case of the simultaneous scanning mode of a plurality of pixel rows, the row scanning unit 13 drives a drive signal (transfer) through two systems of pixel drive lines 17A and 17B for a plurality of image rows, in this example, two pixel rows. Pulse φTRF, reset pulse φRST and selection pulse φSEL) are output simultaneously. According to the row scanning by the row scanning unit 13, a readout row from which a pixel signal is read out can be selected for each pixel column. As a result, in this example, two rows can be read simultaneously with different pixel columns.

  For simultaneous output of drive signals to two pixel rows, the row scanning unit 13 designates two addresses of pixel rows to be read simultaneously, or designates one designated address as a thinning number (number of rows). This can be easily realized by specifying the number of simultaneous selections. In this example of addressing, it is assumed that the row scanning unit 13 is configured using an address decoder.

  However, even when the row scanning unit 13 is configured using a shift register, it is possible to simultaneously output drive signals to a plurality of pixel rows. Specifically, for example, when two pixel rows are simultaneously selected, the row scanning unit 13 is configured by using two shift registers, and two shifts are performed by a scanning time difference between two pixel rows to be simultaneously read. This can be realized by shifting the scanning start timing of the register. In any case, the row scanning unit 13 drives each pixel 20 so that the signals of the plurality of pixels 20 are not read simultaneously on one vertical signal line 18.

  The column processing unit 14 employs a column AD conversion system that AD converts an analog pixel signal into a digital signal for each pixel column. The column AD conversion type column processing unit 14 uses an AD conversion circuit 140 having a circuit configuration including at least a comparator 141 and a counter 142 as a unit circuit, and the AD conversion circuit 140 is arranged corresponding to the pixel column of the pixel array unit 12. It has been configured.

  In the case of the column AD conversion method, the CMOS image sensor 10 </ b> A includes a reference signal generation unit 30 that generates a reference signal to be given to the column processing unit 14. The reference signal generation unit 30 includes, for example, a DA (digital-analog) conversion circuit, and generates a reference signal REF having a slope waveform (so-called ramp (RAMP) waveform) that changes linearly with a certain slope. This reference signal REF is given to all the pixel columns in common with respect to one input terminal (for example, a non-inverting input terminal) of the comparator 141.

  The comparator 141 compares the analog pixel signal supplied to the other input terminal (for example, the inverting input terminal) through the vertical signal line 18 with the reference signal REF for each pixel column. At the same time, the counter 142 starts counting. The counter 142 includes, for example, an up (U) / down (D) counter, and performs a counting operation in synchronization with a clock having a fixed period.

  When the analog pixel signal and the reference signal REF intersect, the comparator 141 inverts its output. The counter 142 stops the count operation at the inversion timing of the output of the comparator 141. The final count value of the counter 142 becomes digital data (pixel data) corresponding to the magnitude of the analog pixel signal. The digital data is sequentially read out to the horizontal bus 19 through a horizontal scanning switch (not shown) which is turned on in order in synchronization with the column scanning by the column scanning by the column scanning unit 15.

(Simultaneous scanning mode for multiple pixel rows)
Next, a specific driving example of the CMOS image sensor 10A in the mode in which a plurality of pixel rows are simultaneously scanned will be described.

  Here, a case where the color coding of the color filter arranged on the pixel array unit 12 is an R (red) G (green) B (blue) Bayer array as shown in FIG. The operation will be described with reference to FIG. FIG. 6 shows a pixel arrangement of 4 vertical pixels × 4 horizontal pixels for simplification of the drawing. In FIG. 6, the pixel to be read is surrounded by a thick line.

  In this operation description, as an example, it is assumed that three pixel rows are used as a unit, two of the three rows are skipped, and vertical 1/3 decimation readout for reading signals from the remaining one row of pixels is performed. By performing vertical thinning readout, the number of vertical readouts (number of rows / number of lines) can be reduced, so that high-speed imaging can be realized as compared with the case where vertical thinning readout is not performed.

  When performing vertical 1/3 decimation readout, the row scanning unit 13 applies driving signals (transfer pulse φTRF, reset pulse φRST, and reset pulse φRST to the first and fourth pixel rows from the top through one pixel drive line 17A. The selection pulse φSEL) is output simultaneously.

  By the row scanning by the row scanning unit 13, the R pixel signal and the G pixel signal are read out from the first pixel row every two pixels, and the G pixel is read out from the fourth pixel row every two pixels. And the B pixel signal are read out. That is, in addition to vertical 1/3 thinning readout, horizontal 2/4 thinning readout is performed by simultaneous readout of two rows.

  As described above, for example, two pixel drive lines 17A and 17B are wired for each pixel row, and each pixel 20 is connected in units of two adjacent columns to the pixel drive lines 17A and 17B. Two pixel rows can be scanned simultaneously in the pixel column. As a result, in the above example, horizontal 2/4 thinning readout can be performed while performing vertical 1/3 thinning readout.

  If attention is paid to one pixel row by horizontal 2/4 thinning readout, the number of pixels read out in the horizontal direction is halved, so that the frame rate can be improved as compared with the case where horizontal thinning readout is not performed. In addition, since the number of pixels read out in the horizontal direction can be reduced, it is possible to eliminate the problem that the angle of view is reduced as in the case where horizontal thinning readout is not performed, so that the captured image can be prevented from being horizontally long. .

  In this operation example, the case where two rows are simultaneously read has been described as an example. However, the operation is not limited to two rows. In the case of simultaneous readout of three rows, the number of pixels read in the horizontal direction can be reduced to １ ／, and in the case of simultaneous readout of four rows, the number of pixels read in the horizontal direction can be reduced to ¼.

  In this operation example, the case of using the method of vertical thinning readout in which pixel rows are skipped at a constant row period is used as an example to reduce the number of vertical readouts (number of rows / number of lines). It is not limited to. For example, it is possible to use a vertical cutout method for reading out signals of pixels in a specific region in the vertical direction, or to use a vertical thinning out read method and a vertical cutout method in combination.

  Incidentally, in the case of performing vertical cutout that cuts out half of the pixel area in the vertical direction by a conventional method that does not perform horizontal thinning, and performing vertical 1/5 thinning out reading in this cutout area, as shown in FIG. In addition, there is a problem that the angle of view is reduced.

  In contrast, as shown in FIG. 7B, the angle of view is improved by performing horizontal 2/4 thinning readout while performing vertical 1/5 thinning readout without performing vertical clipping. it can. Further, when performing vertical cutout for cutting out 2/3 of the vertical pixel area and performing horizontal 2/4 thinning readout while performing vertical 1/3 thinning readout in this cutout area, as shown in FIG. In addition, the angle of view and the vertical resolution can be improved as compared with the conventional method.

  The analog pixel signal read out by the row scanning by the row scanning unit 13 is converted into digital data by the AD conversion circuit 140 and then output to the outside of the chip 11 through the horizontal bus 19 by the column scanning by the column scanning unit 15. When the column scanning is performed by the column scanning unit 15 in order from the end, pixel data is output across two rows.

  Specifically, in the example of FIG. 6, the R pixel data and the G pixel data in the first row are sequentially output, and then the G pixel data and the B pixel data in the fourth row are sequentially output. Thereafter, the data of two pixels R and G in the first row and the data of two pixels G and B in the fourth row are alternately output. These signals are supplied to a data processing unit (for example, a DSP (Digital Signal Processor) circuit) provided outside the chip 11.

  The data processing unit at the subsequent stage performs signal processing corresponding to the output over the two rows on the pixel data output over the two rows. Specifically, as an example, signal processing for each row may be performed after reading out pixel data for two rows.

  Further, in order to increase the affinity of the data processing unit for normal one-line reading and two-line simultaneous reading, the following method may be employed. That is, pixel data is temporarily stored in the image memory using an image memory such as a line memory or a frame memory, and the pixel data is rearranged in the pixel row order and output, or the column scanning order is changed to change the pixel row order. What is necessary is just to take the method of outputting pixel data.

  An example of the configuration of the column scanning unit 15 when the latter method, that is, the method of changing the column scanning order is adopted is shown in FIG. FIG. 8 shows a pixel arrangement of 4 vertical pixels × 8 horizontal pixels. In FIG. 8, pixels to be read are shown surrounded by a thick line.

  In the case of a horizontal 8-pixel arrangement, the column scanning unit 15 uses four flip-flops 151 to 154. That is, in the case of two rows simultaneous reading, the column scanning unit 15 is configured using flip-flops that are ½ the number of pixels in the horizontal direction.

  Also, switches 155 to 157 for selecting an input pulse are provided on the input side of the second and subsequent flip-flops 152 to 154. These switches 155 to 157 have the output pulses of the preceding flip-flops 151 to 153 as “0” inputs. The second stage switch 155 is the output pulse of the third stage flip-flop 153, the second stage switch 156 is the output pulse of the first stage flip-flop 151, and the third stage switch 157 is the second stage. Each of the output pulses of the flip-flop 152 is “1” input.

  In the column scanning section 15 configured as described above, the start pulse φST is input to the first flip-flop 151, and the flip-flops 152 to 154 perform a shift operation in synchronization with the horizontal clock φCK. The start pulse φST and the horizontal clock φCK are supplied from the system control unit 16.

  Here, when all the switches 155 to 157 are set to the “0” side input, shift pulses are sequentially output from the flip-flops 152 to 154, and these shift pulses are supplied to the column processing unit 14 as horizontal scanning pulses. Given this, a column scan is performed. Then, by the column scanning by the column scanning unit 15, the first row and the fourth row are alternately scanned in units of two columns. In the case of this column scanning, as described above, pixel data is output across two rows of the first row and the fourth row.

  On the other hand, when all the switches 155 to 157 are set to the “1” side input, the output pulse of the first stage flip-flop 151 is input to the third stage flip-flop 153. The output pulse of the third-stage flip-flop 153 is input to the second-stage flip-flop 152, and the output pulse of the second-stage flip-flop 152 is input to the fourth-stage flip-flop 154.

  As a result, shift pulses are output from the respective stages in the order of flip-flop 151 → flip-flop 153 → flip-flop 152 → flip-flop 154, and these scan pulses become horizontal scanning pulses to perform column scanning. Then, by the column scanning by the column scanning unit 15, first, the first row is scanned every two pixels (jumping two columns), and then the fourth row is scanned every two pixels, thereby outputting pixel data in the order of pixel rows. It will be possible.

(Single pixel row scanning mode)
As described above, in addition to the mode in which a plurality of pixel rows are simultaneously scanned, the row scanning unit 13 can selectively take a mode in which the pixel rows are sequentially scanned one by one without performing horizontal thinning readout. . A specific driving example of the CMOS image sensor 10A in the mode of scanning a single pixel row will be described.

  The row scanning unit 13 simultaneously outputs two drive signals (transfer pulse φTRF, reset pulse φRST and selection pulse φSEL) for a single pixel row, and outputs the two drive signals to the two systems of pixel drive lines 17A, This is given to each pixel 20 through 17B. The row scanning by the row scanning unit 13 can realize conventional one-row all-column readout.

  Specifically, the row scanning unit 13 first outputs two drive signals simultaneously for the first row. As a result, as shown in FIG. 9A, the signals of the pixels of RGRG... In the first row are read simultaneously through the vertical signal line 18. Next, the row scanning unit 13 outputs two drive signals to the second row at the same time, so that the signals of the pixels in the GBGB of the second row are all vertical as shown in FIG. 9B. Read out through the signal line 18.

  Thereafter, in the same manner, by performing row scanning by the row scanning unit 13 in order of the third row, the fourth row,..., Signals are read from the pixels 20 for all the columns one by one without performing horizontal thinning readout. Can do. Note that, in FIGS. 9A and 9B, the pixel to be read is surrounded by a thick line.

<3. Second Embodiment>
FIG. 10 is a system configuration diagram showing an outline of the system configuration of the CMOS image sensor 10B according to the second embodiment of the present invention. In FIG. 10, the same parts as those in FIG.

  The CMOS image sensor 10B according to the present embodiment has a configuration in which the vertical signal lines 18 are wired in a plurality of systems, for example, two systems (two lines) for each pixel column. The unit pixels 20 are alternately connected to the two vertical signal lines 18A and 18B for each pixel row. Specifically, from the top of the figure, each pixel 20 in the first pixel row is connected to the vertical signal line 18A and each pixel 20 in the second pixel row is connected to the vertical signal line 18B. Each pixel 20 is connected to the vertical signal line 18A as follows.

  The pixel drive line 17 is wired by one system for each pixel row. The unit pixel 20 is connected to the pixel drive line 17 for each pixel row. In FIG. 10, one line of the pixel drive line 17 is shown as one wiring. However, when the unit pixel 20 has the pixel configuration shown in FIG. 2, the pixel drive line 17 is, for example, the transfer line 171, It consists of three wires, a reset line 172 and a selection line 173.

  When connecting each pixel 20 to the vertical signal lines 18A and 18B, as in the case of the pixel drive lines 17A and 17 in the first embodiment, the pixels 20 may be directly connected. It is also possible to adopt a connection configuration that interposes. The connection location of the pixel 20 to the vertical signal lines 18A and 18B becomes the source electrode of the selection transistor 25 when the unit pixel 20 has the pixel configuration shown in FIG.

  When a switch is interposed between the unit pixel 20 and the vertical signal lines 18A and 18B, the source electrode of the selection transistor 25 is connected to the vertical signal lines 18A and 18B via the switch for all the pixel columns. . Thus, by interposing a switch between the unit pixel 20 and the vertical signal lines 18A and 18B, it is possible to select which of the vertical signal lines 18A and 18B the unit pixel 20 is connected to by switching the switch. Therefore, the connection between the vertical signal lines 18A and 18B and the unit pixel 20 can be freely changed.

  While two vertical signal lines 18A and 18B are wired for each pixel column, the row scanning unit 13 has a mode for scanning a single pixel row and a mode for simultaneously scanning a plurality of pixel rows. It is the structure which can take selectively. This mode switching is performed under the control of the system control unit 16 based on designation from the outside.

  In the case of the scanning mode for a single pixel row, the row scanning unit 13 executes row scanning by outputting drive signals (transfer pulse φTRF, reset pulse φRST, and selection pulse φSEL) in order for each pixel row. . According to the row scanning by the row scanning unit 13, a signal can be read from each pixel of the selected row while selecting a readout row in order for each pixel row, as in the conventional case.

  In the case of the simultaneous scanning mode of a plurality of pixel rows, the row scanning unit 13 applies driving signals (transfer pulse φTRF, reset pulse φRST, and reset pulse φRST to two pixel rows connected to different vertical signal lines 18A / 18B. The row scanning is executed by simultaneously outputting the selection pulse (φSEL). By the row scanning by the row scanning unit 13, the signal of each pixel 20 of one pixel row is read to one vertical signal line 18A, and the signal of each pixel 20 of the other pixel row is read to the other vertical signal line 18B. It is read and supplied to the column processing unit 14.

  As for the simultaneous output of drive signals for two pixel rows, as in the case of the first embodiment, the row scanning unit 13 designates two addresses of pixel rows to be simultaneously read, and the designated address is It can be easily realized by specifying a thinning number (number of lines), the number of simultaneous selections, etc. as one.

  As in the case of the first embodiment, the column processing unit 14 employs a column AD conversion system that AD converts an analog pixel signal into a digital signal for each pixel column. The column processing unit 14 according to the present embodiment includes a selection switch 143 on the front stage of the AD conversion circuit 140 having a circuit configuration including at least the comparator 141 and the counter 142, specifically, on the inverting input terminal side of the comparator 141. It has become.

  The selection switch 143 has two fixed contacts connected to the two vertical signal lines 18A and 18B, respectively, and a movable contact connected to the inverting input terminal of the comparator 141. The selection switch 143 applies an analog pixel signal transmitted through one of the vertical signal lines 18A and 18B to the inverting input terminal of the comparator 141. Selection of the vertical signal lines 18A / 18B by the selection switch 143 can be performed by control by the system control unit 16 based on designation from the outside.

  In the case of this example with two vertical signal lines 18, the selection switch 143 selects one of the vertical signal lines 18A and 18B in units of two adjacent pixel columns. Specifically, the selection switch 143 includes vertical signal lines 18A in the first and second pixel columns, and vertical signal lines 18B in the third and fourth pixel columns, in the fifth and sixth columns. In the pixel column of the eye, the vertical signal line 18A is alternately selected in units of two pixel columns, and so on.

  That is, the selection switch 143 operates to select signals of different systems in units of a plurality of pixel columns for the signals of the plurality of systems transmitted by the plurality of systems of vertical signal lines 18 (details will be described later). By simultaneously outputting drive signals for the two pixel rows by the row scanning unit 13 in the above-described simultaneous scanning mode of a plurality of pixel rows and selecting the vertical signal lines 18A and 18B by the selection switch 143, pixel signals are obtained for each pixel column. Can be selected. As a result, in this example, two rows can be read simultaneously with different pixel columns.

(Simultaneous scanning mode for multiple pixel rows)
Next, a specific driving example of the CMOS image sensor 10B in the mode of simultaneously scanning a plurality of pixel rows will be described with reference to the operation explanatory diagram of FIG.

  Also here, it is assumed that the color coding of the color filter arranged on the pixel array unit 12 is an RGB Bayer array (see FIG. 5). FIG. 11 shows a pixel arrangement of 4 vertical pixels × 4 horizontal pixels for simplification of the drawing. In FIG. 11, the pixel to be read is surrounded by a thick line.

  In this operation description, as an example, it is assumed that three pixel rows are used as a unit, two of the three rows are skipped, and vertical 1/3 decimation readout for reading signals from the remaining one row of pixels is performed. As described in the first embodiment, the number of vertical readouts (number of rows / number of lines) can be reduced by performing vertical thinning readout, so that high-speed imaging can be realized as compared with the case where vertical thinning readout is not performed.

  When performing vertical 1/3 thinning readout, the row scanning unit 13 drives the drive signals (transfer pulse φTRF, reset pulse φRST, and selection pulse through the pixel drive line 17 for the first and fourth pixel rows from the top. φSEL) is output simultaneously.

  By the row scanning by the row scanning unit 13, the signal of each pixel of repetition of RGRG... Is read from the first pixel row to the vertical signal line 18 A for one row, and GBGB. The signal of each pixel repeated is read out to the vertical signal line 18B for one row. At this time, the selection switches 143 in every second column of the first column, the second column, the fifth column, the sixth column,... Are connected to the vertical signal line 18A, the third column, the fourth column, the seventh column, the eighth column. The selection switches 143 in every second column of the first,... Are in the state of selecting the vertical signal line 18B.

  As a result, when the first and fourth rows are simultaneously scanned by the row scanning unit 13, finally, for the first pixel row, the selection switch 143 causes the R pixel signal and the G pixel signal every two pixels. Is read out. For the fourth pixel row, the selection switch 143 reads the G pixel signal and the B pixel signal every two pixels. That is, in addition to vertical 1/3 thinning readout, horizontal 2/4 thinning readout is performed by simultaneous readout of two rows.

  As described above, for example, two vertical signal lines 18A and 18B wired for each pixel column are alternately selected in units of two adjacent columns by the selection switch 143, so that two pixel rows in different pixel columns can be selected. Signals can be read from the pixels 20 simultaneously. As a result, in the above example, horizontal 2/4 thinning readout can be performed while performing vertical 1/3 thinning readout.

  If attention is paid to one pixel row by horizontal 2/4 thinning readout, the number of pixels read out in the horizontal direction is halved, so that the frame rate can be improved as compared with the case where horizontal thinning readout is not performed. In addition, since the number of pixels read out in the horizontal direction can be reduced, it is possible to eliminate the problem that the angle of view is reduced as in the case where horizontal thinning readout is not performed, so that the captured image can be prevented from being horizontally long. .

  In this operation example, the case where two rows are simultaneously read has been described as an example. However, the operation is not limited to two rows. In the case of simultaneous readout of three rows, the number of pixels read in the horizontal direction can be reduced to １ ／, and in the case of simultaneous readout of four rows, the number of pixels read in the horizontal direction can be reduced to ¼.

  In this operation example, the case of using the method of vertical thinning readout in which pixel rows are skipped at a constant row period is used as an example to reduce the number of vertical readouts (number of rows / number of lines). It is not limited to. For example, it is possible to use a vertical cutout method for reading out signals of pixels in a specific region in the vertical direction, or to use a vertical thinning out read method and a vertical cutout method in combination. About the effect at the time of taking these methods, it is the same as that of the case of 1st Embodiment (refer FIG. 7).

  As in the case of the first embodiment, the data processing unit at the subsequent stage performs signal processing corresponding to the output over two rows on the pixel data output over two rows. Specifically, as an example, signal processing for each row may be performed after reading out pixel data for two rows.

  In addition, when it is desired to increase the affinity of the data processing unit for normal one-line reading and two-line simultaneous reading, pixel data is temporarily stored in the image memory using an image memory such as a line memory or a frame memory, and the pixel data May be rearranged in the pixel row order and output. Alternatively, pixel data may be output in order of pixel rows by changing the column scanning order using the column scanning unit of the configuration example shown in FIG.

(Single pixel row scanning mode)
As described above, in addition to the mode in which a plurality of pixel rows are simultaneously scanned, the row scanning unit 13 can selectively take a mode in which the pixel rows are sequentially scanned one by one without performing horizontal thinning readout. . A specific driving example of the CMOS image sensor 10B in the mode of scanning a single pixel row will be described.

  The row scanning unit 13 outputs drive signals (transfer pulse φTRF, reset pulse φRST, and selection pulse φSEL) to a single pixel row in order from the first row, and outputs the drive signals to one system of pixel drive lines 17. To each pixel 20.

  In synchronization with the scanning by the row scanning unit 13, the system control unit 16 performs switching control of the selection switch 143 so that the selection switch 143 selects the same vertical signal line 18A / 18B in the same row.

  Specifically, the system control unit 16 switches the selection switch 143 so that the selection switch 143 selects the vertical signal line 18A as shown in FIG. 12A when scanning the odd-numbered pixel rows. Take control. Further, the system control unit 16 performs switching control of the selection switch 143 so that the selection switch 143 selects the vertical signal line 18B as shown in FIG. 12B when scanning even-numbered pixel rows. .

  As a result, during scanning of the odd-numbered pixel rows, the signal of each pixel of RGRG... Is read from the odd-numbered pixel rows to the vertical signal line 18A for one row, and the column processing unit is connected via the selection switch 143. 14. Further, when scanning even-numbered pixel rows, a signal of each pixel of GBGB... Is read to the vertical signal line 18B for one row and supplied to the column processing unit 14 via the selection switch 143.

  As described above, conventional one-row all-column readout can be realized. That is, signals can be read from the pixels 20 for all the columns in order one by one without performing horizontal thinning readout. Note that in FIGS. 12A and 12B, pixels to be read are shown surrounded by thick lines.

<4. Third Embodiment>
FIG. 13 is a system configuration diagram showing an outline of the system configuration of a CMOS image sensor 10C according to the third embodiment of the present invention. In FIG. 13, the same parts as those in FIG.

  In the CMOS image sensor 10B according to the second embodiment, for example, two systems of vertical signal lines 18A and 18B are wired for each pixel column. Then, the vertical signal lines 18A and 18B are alternately selected in units of two adjacent columns by the selection switch 143, and signals are simultaneously read from the pixels 20 of two pixel rows in different pixel columns, thereby performing vertical thinning readout. Horizontal thinning readout is performed.

  The CMOS image sensor 10C according to the present embodiment is a second embodiment in that a plurality of systems, for example, two systems of vertical signal lines 18A and 18B are wired for each pixel column, and signals are simultaneously read from the pixels 20 in two pixel rows. This is the same as the CMOS image sensor 10B according to FIG. In addition, the CMOS image sensor 10C according to the present embodiment includes a capacitor 144 and a switch 145 connected in series to the end of the vertical signal line 18A, and a capacitor 146 connected in series to the end of the vertical signal line 18B, and A switch 147 is provided.

  The output terminals of the switches 145 and 147 are commonly connected to the inverting input terminal of the comparator 141. That is, the ends of the vertical signal lines 18A and 18B are AC-coupled via the switches 145 and 147 by the capacitors 144 and 146, respectively. The signals of the two pixels in the vertical direction that are read simultaneously through the vertical signal lines 18A and 18B are accumulated in the capacitors 144 and 146, so that the signals are added between the two pixels.

  In this example, each pixel in the odd row is connected to the vertical signal line 18A, and each pixel in the even row is connected to the vertical signal line 18B. Therefore, when both the switches 145 and 147 are in the on (closed) state, two-pixel addition (vertical two-pixel addition) is performed between two rows adjacent in the vertical direction by row scanning by the row scanning unit 13. The vertical two-pixel addition in this case is preferably performed when the color filter is a monochrome filter.

  Here, a case where vertical pixel addition is performed between an odd-numbered row and an even-numbered row has been described as an example. However, by changing the connection relationship of each pixel row with respect to the vertical signal lines 18A and 18B, Vertical addition between rows is also possible. This vertical addition is useful when the color filter has the Bayer arrangement (see FIG. 5) described above.

  Incidentally, the conventional one-row all-column readout can be realized by alternately turning on / off the switches 145 and 147 in synchronization with the row scanning by the row scanning unit 13. That is, signals can be read from the pixels 20 for all the columns in order one by one without performing horizontal thinning readout. The on / off driving of the switches 145 and 147 in synchronization with the row scanning is executed under the control of the system control unit 16.

  As described above, according to the CMOS image sensor 10C according to the third embodiment, the vertical signal lines 18 are wired in a plurality of lines for each pixel column, and the signals of the pixels in the plurality of rows are sent to the vertical signal lines 18 in the plurality of lines. By simultaneously reading, vertical addition can be performed between a plurality of pixel rows. Since the signal level can be increased by this vertical addition, the sensitivity can be improved.

  Incidentally, such signal addition between pixels in the vertical direction can be performed by, for example, the AD conversion circuit 140. However, when signal addition is performed by the AD conversion circuit 140, AD conversion processing needs to be performed twice, which increases AD conversion time and causes a decrease in frame rate. On the other hand, if signal addition is performed by analog addition using capacitors 144 and 146, the same AD conversion time as that at the time of non-addition may be used, and thus there is an advantage that the sensitivity can be improved without reducing the frame rate.

<5. Fourth Embodiment>
FIG. 14 is a system configuration diagram showing an outline of the system configuration of a CMOS image sensor 10D according to the fourth embodiment of the present invention. In FIG. 14, the same parts as those in FIGS. 10 and 13 are denoted by the same reference numerals. ing.

  The CMOS image sensor 10D according to the present embodiment is configured to have both the function of the CMOS image sensor 10B according to the second embodiment and the function of the CMOS image sensor 10C according to the third embodiment. As described above, the CMOS image sensor 10B according to the second embodiment has a function of performing horizontal thinning readout while performing vertical thinning readout. The CMOS image sensor 10C according to the third embodiment has a function of improving sensitivity by vertical addition.

  That is, the functions of the CMOS image sensors 10C and 10D according to the second and third embodiments are independent functions. The CMOS image sensor 10D according to this embodiment is a combination of these independent functions. That is, the CMOS image sensor 10D according to the present embodiment has a configuration in which signals are simultaneously read from each pixel of, for example, two pixel rows in different pixel columns to perform horizontal thinning readout, and vertical addition is performed between, for example, two pixel rows. It has become.

  Specifically, in the CMOS image sensor 10D according to the present embodiment, for example, four systems (four lines) of vertical signal lines 18A, 18B, 18C, and 18D are wired for each pixel column. A capacitor 144 and a switch 145 are connected in series to the end of the vertical signal line 18A. A capacitor 146 and a switch 147 are connected in series to the end of the vertical signal line 18B. The output terminals of the switches 145 and 147 are connected in common.

  A capacitor 148 and a switch 149 are connected in series to the end of the vertical signal line 18C. A capacitor 150 and a switch 151 are connected in series to the end of the vertical signal line 18D. The output terminals of the switches 149 and 151 are connected in common. A selection switch 143 is provided on the inverting input terminal side of the comparator 141.

  Two fixed contacts of the selection switch 143 are connected to a common connection node of the switches 145 and 147 and a common connection node of the switches 149 and 151, respectively. Here, as is apparent from the description of the operations in the second and third embodiments, the selection switch 143 selects signals of different systems in units of a plurality of pixel columns from among a plurality of systems of signals obtained by addition processing using capacitors. To output.

  According to the CMOS image sensor 10D according to the fourth embodiment having the above-described configuration, a signal is simultaneously read out from each pixel of a plurality of pixel rows in different pixel columns and horizontal thinning readout is performed to improve the angle of view. Sensitivity can be improved by performing vertical addition between pixel rows.

  Since the CMOS image sensors 10 </ b> A to 10 </ b> D according to the first to fourth embodiments described above have a plurality of lines of wiring for each pixel row or for each pixel column, the wiring of the pixel array unit 13 increases. As a result, since the amount of light incident on the unit pixel 20 is reduced, there is a concern that sensitivity may be lowered. However, this concern can be solved by using a back-illuminated pixel structure that captures incident light from the side opposite to the wiring layer, rather than a front-illuminated pixel structure that captures incident light from the wiring layer side.

<6. Back-illuminated pixel structure>
FIG. 15 is a cross-sectional view illustrating an example of a back-illuminated pixel structure. Here, a cross-sectional structure for two pixels is shown.

  In FIG. 15, a photodiode 42 and a pixel transistor 43 are formed in the silicon portion 41. That is, the silicon part 41 is an element forming part. Here, the photodiode 42 corresponds to the photodiode 21 of FIG. The pixel transistor 43 corresponds to the transistors 22 to 25 in FIG.

  A color filter 45 is formed on one surface side of the silicon portion 41 via an interlayer film 44. Thereby, light incident from one surface side of the silicon portion 41 is guided to the light receiving surface of the photodiode 42 via the color filter 45. On the other hand, on the other surface side of the silicon portion 41, a wiring layer 47 is formed in which a gate electrode and a metal wiring of the pixel transistor 43 are multilayered in the interlayer insulating film 46. A support substrate 49 is attached to the surface of the wiring layer 47 opposite to the silicon portion 41 with an adhesive 48.

  In the above pixel structure, the wiring layer 47 side of the silicon part 41 where the photodiode 42 and the pixel transistor 43 are formed is referred to as a front surface side, and the side opposite to the wiring layer 47 of the silicon part 41 is referred to as a back surface side. Under such a definition, the present pixel structure is a back-illuminated pixel structure because incident light is taken in from the back surface side of the silicon portion 41.

  According to this back-illuminated pixel structure, incident light is taken in from the side opposite to the wiring layer 47, so that the aperture ratio can be 100%. In addition, since the wiring layer 47 does not exist on the side where the incident light is captured, the incident light can be condensed on the light receiving surface of the photodiode 42 without using an on-chip lens. Moreover, even if a configuration having a plurality of lines of wiring for each pixel row or for each pixel column as in the CMOS image sensors 10A to 10D according to the first to fourth embodiments, the size of the unit pixel does not have to be reduced. Therefore, there is no concern about sensitivity reduction.

<7. Electronic equipment>
The solid-state imaging device according to the present invention can be mounted and used in all electronic devices that use a solid-state imaging device for an image capturing unit (photoelectric conversion unit). Examples of the electronic device include an imaging device (camera system) such as a digital still camera and a video camera, a portable terminal device having an imaging function such as a mobile phone, and a copying machine using a solid-state imaging device for an image reading unit. Note that a camera module mounted on an electronic device may be an imaging device.

(Imaging device)
FIG. 16 is a block diagram illustrating an example of a configuration of, for example, an imaging apparatus which is one of electronic apparatuses according to the present invention. As shown in FIG. 16, an imaging apparatus 100 according to the present invention includes an optical system including a lens group 101 and the like, an imaging element 102, a DSP circuit 103 that is a camera signal processing unit, a frame memory 104, a display apparatus 105, and a recording apparatus 106. The operation system 107 and the power supply system 108 are included. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.

  The lens group 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 102. The imaging element 102 converts the amount of incident light imaged on the imaging surface by the lens group 101 into an electrical signal in units of pixels and outputs the electrical signal. As the imaging device 102, a solid-state imaging device such as a CMOS image sensor according to the first to fourth embodiments can be used.

  The display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 102. The recording device 106 records a moving image or a still image captured by the image sensor 102 on a recording medium such as a video tape or a DVD (Digital Versatile Disc).

  The operation system 107 issues operation commands for various functions of the imaging apparatus under operation by the user. The power supply system 108 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.

  Such an imaging apparatus 100 is applied to a camera module for a mobile device such as a video camera, a digital still camera, or a mobile phone. In this imaging apparatus 100, by using the CMOS image sensor according to the first to fourth embodiments described above as the imaging element 102, the CMOS image sensor particularly suppresses the reduction of the angle of view, and the captured image becomes horizontally long. Therefore, a good captured image can be provided.

  DESCRIPTION OF SYMBOLS 10,10A, 10B, 10C, 10D ... CMOS image sensor, 11 ... Semiconductor substrate (chip), 12 ... Pixel array part, 13 ... Row scanning part, 14 ... Column processing part, 15 ... Column scanning part, 16 ... System control 17, 17 A, 17 B: Pixel drive line, 18, 18 A, 18 B, 18 C, 18 D ... Vertical signal line, 20 ... Unit pixel, 21 ... Photodiode, 22 ... Transfer transistor, 23 ... Reset transistor, 24 ... Amplification transistor 25 ... Select transistor

If attention is paid to one pixel row by horizontal 2/4 thinning readout, the number of pixels read out in the horizontal direction is halved, so that the frame rate can be improved as compared with the case where horizontal thinning readout is not performed. In addition, since the number of pixels read out in the horizontal direction can be reduced, it is possible to eliminate a problem that the angle of view is reduced as in the case where horizontal thinning readout is not performed. .

If attention is paid to one pixel row by horizontal 2/4 thinning readout, the number of pixels read out in the horizontal direction is halved, so that the frame rate can be improved as compared with the case where horizontal thinning readout is not performed. In addition, since the number of pixels read out in the horizontal direction can be reduced, it is possible to eliminate a problem that the angle of view is reduced as in the case where horizontal thinning readout is not performed. .

The CMOS image sensor 10D according to the present embodiment is configured to have both the function of the CMOS image sensor 10B according to the second embodiment and the function of the CMOS image sensor 10C according to the third embodiment . As described above, the CMOS image sensor 10B according to the second embodiment has a function of performing horizontal thinning readout while performing vertical thinning readout. The CMOS image sensor 10C according to the third embodiment has a function of improving sensitivity by vertical addition.

That is, the functions of the CMOS image sensors 10C and 10D according to the second and third embodiments are independent functions. The CMOS image sensor 10D according to this embodiment is a combination of these independent functions. That is, the CMOS image sensor 10D according to the present embodiment has a configuration in which a signal is simultaneously read from each pixel of, for example, two pixel rows in different pixel columns to perform horizontal thinning readout, and vertical addition is performed between, for example, two pixel rows. It has become.

According to the CMOS image sensor 10D of the fourth embodiment of the above configuration, to improve the angle of view by performing the horizontal thinning read simultaneously read the signals from each pixel of the plurality of pixel rows in different pixel columns, a plurality of Sensitivity can be improved by performing vertical addition between pixel rows.

Claims (5)

A pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and pixel drive lines that transmit a drive signal for driving to read out signals from the pixels are wired for a plurality of systems for each pixel row;
A row scanning unit capable of simultaneously outputting the drive signals through the plurality of pixel drive lines to a plurality of pixel rows in different pixel columns, and capable of selectively taking a mode of scanning a single pixel row;
A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the row scanning unit performs interlaced scanning that skips a specific pixel row of the pixel array unit.   2. The solid-state imaging device according to claim 1, wherein the row scanning unit simultaneously outputs the drive signals to the pixel rows of the pixel array unit through the plurality of pixel drive lines. In driving a solid-state imaging device in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix and pixel drive lines that transmit a drive signal for driving to read signals from the pixels are wired in a plurality of systems for each pixel row. ,
Driving of a solid-state imaging device that simultaneously outputs the drive signal through a plurality of pixel drive lines to a plurality of pixel rows in different pixel columns from a row scanning unit capable of selectively taking a mode for scanning a single pixel row Method. A pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and pixel drive lines that transmit a drive signal for driving to read out signals from the pixels are wired for a plurality of systems for each pixel row;
A row scanning unit capable of simultaneously outputting the drive signals through the plurality of pixel drive lines to a plurality of pixel rows in different pixel columns, and capable of selectively taking a mode of scanning a single pixel row;
An electronic apparatus having a solid-state imaging device.

Images