JP2013153064A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which facilitates microfabrication without incurring significant increase in the number of steps.SOLUTION: The manufacturing method comprises steps of: forming a semiconductor film 104 on a semiconductor substrate 101, whose lower layer portion 104a has p-type conductivity and whose upper layer portion 104d has n-type conductivity, where the total amount of impurities constituting a donor is greater than the total amount of impurities constituting an acceptor; removing the upper portion of the semiconductor film 104 to ensure that the total amount of impurities constituting the donor included in the semiconductor film 104 is smaller than the total amount of impurities constituting the acceptor in a region Rc; spreading the impurities constituting the donor and impurities constituting the acceptor within the semiconductor film 104 after the upper portion of the semiconductor film 104 is removed; and selectively removing the semiconductor film 104 in the region Rc to form a p-type electrode and also selectively removing the semiconductor film 104 in a region Rp different than the region Rc to form an n-type electrode.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  With respect to nonvolatile semiconductor memory devices, miniaturization of memory cells has been actively promoted for the purpose of expanding storage applications and reducing manufacturing costs through high integration. In addition, the replacement of hard disk drives is also progressing due to the reduction in power consumption accompanying the miniaturization of memory cells. In particular, in the NAND flash memory, rapid miniaturization is progressing in which the bit density increases approximately twice every year.

  With such miniaturization of memory cells, there are problems that the threshold value is lowered and the breakdown voltage of the tunnel insulating film is lowered. As a countermeasure, it is conceivable to change the material of the floating gate electrode of the memory cell from a conventional n-type semiconductor to a p-type semiconductor. Thereby, even if the memory cell is miniaturized, it becomes easy to ensure the threshold value of the memory cell and the breakdown voltage of the tunnel insulating film. On the other hand, for the peripheral circuit transistors, the gate electrode is preferably formed of an n-type semiconductor in order to utilize conventional design assets. However, if the floating gate electrode of the memory cell and the gate electrode of the peripheral circuit are formed separately, the number of processes increases and the manufacturing cost increases.

"P-Type Floating Gate for Retention and P / E Window Improvement of Flash Memory Devices" Chen Shen, Student Member, IEEE, Jing Pu, Ming-Fu Li, Senior Member, IEEE, and Byung Jin Cho, Senior Member, IEEE; IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 8, AUGUST 2007 p1910-1917

  An object of the present invention is to provide a method of manufacturing a semiconductor device that can be easily miniaturized without significantly increasing the number of steps.

  In the method of manufacturing a semiconductor device according to the embodiment, the conductivity type of the lower layer portion is p-type and the conductivity type of the upper layer portion is n-type on the semiconductor substrate, and the total amount of impurities serving as donors is an acceptor. Forming a semiconductor film larger than the total amount, and removing the upper portion of the semiconductor film in a part of the region, thereby accepting a total amount of impurities serving as donors included in the semiconductor film in the part of the region; The step of reducing the total amount of impurities to become, the step of diffusing the impurity to be the donor and the impurity to be the acceptor in the semiconductor film after removing the upper portion of the semiconductor film, and the partial region A p-type electrode is formed by selectively removing the semiconductor film, and an n-type electrode is formed by selectively removing the semiconductor film in another region different from the partial region. Provided that the step.

6 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment; FIG. 6 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment; FIG. 6 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment; FIG. 6 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment; FIG. 11 is a process sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment; FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the first embodiment will be described.
1 to 4 are process cross-sectional views illustrating the method for manufacturing the nonvolatile semiconductor memory device according to this embodiment. FIG. 1A to FIG. 4A are cross-sectional views perpendicular to the AA direction of the cell region. ) Shows a cross section perpendicular to the GC direction of the cell region, and (c) shows a cross section of the peripheral circuit region.

The present embodiment is a method for manufacturing a nonvolatile semiconductor memory device, more specifically, a method for manufacturing a planar NAND flash memory.
In this embodiment, a silicon film having a p-type lower layer and an n-type upper layer is formed, the upper n-type layer is removed in the cell region, and the lower p-type portion is left. In the peripheral circuit region, The entire silicon film is left. Thereafter, heat treatment is performed to diffuse impurities in the silicon film, thereby forming a p-type floating gate electrode in the cell region and an n-type gate electrode in the peripheral circuit region. Further, in order to suppress the diffusion of impurities before the heat treatment, a dividing layer made of nitrogen-doped silicon and a non-doped silicon layer are inserted between the lower layer portion and the upper layer portion.

First, as shown in FIGS. 1A to 1C, a silicon substrate 101 is prepared. In the silicon substrate 101, the cell region R _C which memory cells are _formed, and the peripheral circuit region R _P in which the peripheral circuit is formed is set. In the peripheral circuit region _Rp , a high voltage region R _H where a high voltage circuit is formed and a low voltage region _RL where a low voltage circuit is formed are set.

Impurities are ion-implanted into the silicon substrate 101 to form a well (not shown) and a channel region (not shown) in the upper layer portion of the silicon substrate 101. Next, the upper surface of the silicon substrate 101 is selectively recessed by a lithography technique and a reactive ion etching (RIE) technique. Thereby, the upper surface of the silicon substrate 101 is retreated, for example, by 30 nm in the high voltage region _RH .

Next, a thermal oxidation process is performed to form a silicon thermal oxide film 102 having a thickness of, for example, 35 nm over the entire upper surface of the silicon substrate 101. The silicon thermal oxide film 102 is a film that becomes a gate insulating film of a high voltage circuit in the high voltage region _RH after the device is completed. Next, a portion of the silicon thermal oxide film 102 formed in a region other than the high voltage region _RH is removed and a portion formed in the high voltage region _{RH is} left by the lithography technique and the wet etching technique. .

Next, by performing thermal oxidation treatment or high-temperature oxygen radical oxidation treatment, a silicon thermal oxide film having a thickness of, for example, 6.0 nm is formed on the upper surface of the silicon substrate 101 in the cell region _RC and the low voltage region _RL . To do. Next, the interface between the silicon thermal oxide film and the silicon substrate 101 is nitrided by performing a heat treatment in nitric oxide (NO). Further, the upper surface of the silicon thermal oxide film is nitrided by performing a plasma nitriding process. Thereby, the silicon oxynitride film 103 having a film thickness of, for example, 6.5 nm is formed. The silicon oxynitride film 103 is a film that becomes a tunnel insulating film of a memory cell in the cell region _RC and a gate insulating film of a low voltage circuit in the low voltage region _RL after the device is completed.

Next, by depositing silicon doped with boron (B) at a concentration of 3 × 10 ¹⁹ atoms / cm ³ by, eg, CVD (Chemical Vapor Deposition), the conductivity type is p-type. A p-type silicon layer 104a having a thickness of, for example, 50 nm is formed. Subsequently, by exposing the p-type silicon layer 104a to an ammonia (NH ₃ ) atmosphere, nitrogen (N) is doped into the upper layer portion of the p-type silicon layer 104a at a concentration of 1 × 10 ²¹ atoms / cm ³ , for example. A nitrogen-doped silicon layer 104b having a thickness of, for example, 1 nm is formed. Next, non-doped silicon is deposited to form a non-doped silicon layer 104c having a thickness of, for example, 10 nm. Next, by depositing silicon doped with, for example, phosphorus (P) at a concentration of 5 × 10 ²⁰ atoms / cm ³ , the n-type silicon layer 104d having an n-type conductivity and a thickness of, for example, 30 nm is deposited. Form.

As described above, the p-type silicon layer 104a, the nitrogen-doped silicon layer 104b, the non-doped silicon layer 104c, and the n-type silicon layer 104d are continuously formed by CVD, so that the conductivity type of the lower layer portion is p-type. A silicon film 104 having an n-type conductivity at the upper layer and a film thickness of, for example, 90 nm is formed. Silicon film 104, after completion of the device, it becomes a floating gate electrode of the memory cell in the cell region R _C, a film to be a lower layer portion of the gate electrode of the peripheral circuit in the peripheral circuit region R _P. In addition, the total amount of impurities such as phosphorus doped into the n-type silicon layer 104d is larger than the total amount of impurities such as boron doped into the p-type silicon layer 104a.

Next, silicon nitride is deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) to form a silicon nitride film 105 having a thickness of, for example, 15 nm. Next, a hard mask (not shown) is formed by a lithography technique and an RIE technique, and etching such as RIE is performed using the hard mask to thereby form a silicon nitride film 105, a silicon film 104, a silicon oxynitride film 103, or The silicon thermal oxide film 102 and the upper layer portion of the silicon substrate 101 are selectively removed. Thereby, the trench 106a is formed. At this time, in the cell region _RC , a plurality of trenches 106a are formed in parallel to each other. The direction in which the trench 106a extends in the cell region _RC is referred to as “AA direction”.

Next, silicon oxide is deposited by a CVD method using TEOS (Tetraethoxysilane: Si (OC ₂ H ₅ ) ₄ ) and ozone (O ₃ ) as raw materials, and the silicon nitride film 105 is stoppered against the silicon oxide. By applying CMP (Chemical Mechanical Polishing) as described above and planarizing the upper surface, the silicon oxide member 106 is embedded in the trench 106a to form STI (Shallow Trench Isolation). At this time, in the cell region _RC , a portion between the STIs in the silicon substrate 101 becomes an active area (AA).

Next, as shown in FIGS. 2A to _2C , the silicon nitride film 105 (see FIG. 1) is removed from the cell region _RC by lithography and RIE, and the upper portion of the silicon oxide member 106 is removed. The upper surface of the silicon oxide member 106 is retreated, for example, by 80 nm. Next, the upper portion of the silicon film 104, for example, the n-type silicon layer 104d (see FIG. 1) and the non-doped silicon layer 104c (see FIG. 1) are removed from the cell region _RC by gas etching using a halogen gas. This gas etching is performed, for example, by exposing the substrate to chlorine gas having a temperature of 100 to 300 ° C., for example, 200 ° C. At this time, since the etching rate of p-type silicon is 1/10 or less of the etching rate of n-type or non-doped silicon, p-type silicon layer 104a can remain. Note that the nitrogen-doped silicon layer 104b may be removed or may remain.

Thus, by removing the upper portion of the silicon film 104 in the cell region R _C, in the cell region R _C, the total amount of impurities (phosphorus) which serves as a donor contained in the silicon film 104, an impurity serving as an acceptor (boron ) Less than the total amount. At this stage, the upper surface of the silicon oxide member 106 is at a height between the lower surface and the upper surface of the p-type silicon layer 104a. On the other hand, in the peripheral circuit region R _p, the entire silicon film 104 is left. Next, by the RIE technique, the silicon nitride film 105 (see FIG. 1) is removed in the peripheral circuit region _Rp , and the upper surface of the silicon oxide member 106 is retracted by 10 nm over the entire surface of the substrate.

Next, an RTA (Rapid Thermal Anneal) process at a temperature of, for example, 1000 ° C. is performed. As a result, phosphorus contained in the n-type silicon layer 104d is diffused to the p-type silicon layer 104a, and boron contained in the p-type silicon layer 104a is diffused to the n-type silicon layer 104d. Then, it is diffused throughout the silicon film 104. At this time, in the peripheral circuit region R _p, because the total amount of phosphorus is greater than the total amount of boron in the silicon film 104, conductivity types of the silicon film 104 is n-type as a whole. On the other hand, in the cell region _RC , since the n-type silicon layer 104d has already been removed and the total amount of phosphorus in the silicon film 104 is smaller than the total amount of boron, the conductivity type of the silicon film 104 is changed to a p-type as a whole. Become. Thus, in each cell region R _C and the peripheral circuit region R _p, silicon film 104 having a single conductivity type is formed. Prior to this RTA treatment, the process temperature is kept at 600 ° C. or lower to suppress the interdiffusion of impurities.

Next, as shown in FIGS. 3A to 3C, a silicon oxide film 107 is formed on the entire surface of the substrate. The silicon oxide film 107 is a film that becomes an IPD (Inter Poly Dielectric) film in the completed device. Next, a phosphorus-doped polycrystalline silicon film 108 having a thickness of, for example, 10 nm is formed on the entire surface of the substrate. Then, by lithography and RIE techniques, in some region where a part of the region where the selection gate electrode is formed in the cell region R _C, and the gate electrode in the peripheral circuit region R _p is formed, The phosphorus-doped polycrystalline silicon film 108 and the silicon oxide film 107 are partially removed to form a through hole 107a. Next, a phosphorus-doped polycrystalline silicon film 109 having a thickness of, for example, 20 nm is formed on the entire surface of the substrate. At this time, a region in which the selection gate electrode is formed in the cell region R _C, and, in the region where the gate electrode in the peripheral circuit region R _p is formed, phosphorus-doped polysilicon film 109 is a through hole 107a And is connected to the silicon film 104. Next, a tungsten layer and a tungsten nitride layer are stacked by sputtering to form a W / WN film 110 having a thickness of, for example, 50 nm.

  Next, as shown in FIGS. 4A to 4C, a silicon nitride film (not shown) is formed on the entire surface of the substrate and selectively removed by a lithography technique and an RIE technique. (Not shown). In forming the hard mask, a double patterning technique or a quadruple patterning technique may be applied. Next, by performing etching such as RIE using this hard mask, W / WN film 110, phosphorus-doped polycrystalline silicon film 109, phosphorus-doped polycrystalline silicon film 108, silicon oxide film 107, silicon film 104, silicon oxynitride The film 103 and the silicon thermal oxide film 102 are selectively removed.

Thereby, in the cell region _RC , the phosphorus-doped polycrystalline silicon film 108, the phosphorus-doped polycrystalline silicon film 109, and the W / WN film 110 are stacked in this order, and the control gate electrode CG extending in the GC direction orthogonal to the AA direction. Is formed, and the silicon film 104 is divided into a matrix to form a p-type floating gate electrode FG. Further, a portion where the silicon film 104 and the phosphorus-doped polycrystalline silicon film 109 are connected to each other serves as a selection gate electrode SG. On the other hand, in the peripheral circuit region R _p , an n-type silicon film 104, a phosphorus-doped polycrystalline silicon film 108, a phosphorus-doped polycrystalline silicon film 109, and a W / WN film 110 are stacked in this order, and the MOSFET constituting the peripheral circuit is formed. A gate electrode G is formed. In this way, the floating gate electrode FG is formed as a p-type electrode having at least a portion of conductivity type p-type, and the gate electrode G is formed as an n-type electrode having at least a portion of conductivity type n-type. . As a result, the silicon oxynitride film 103 becomes the tunnel insulating film of the memory cell and the gate insulating film of the MOSFET of the low voltage circuit. On the other hand, the silicon thermal oxide film 102 becomes a gate insulating film of a MOSFET of a high voltage circuit.

  Next, sidewall spacers (not shown), diffusion layers (not shown), PMD (Pre-Metal Dielectric) (not shown), contact plugs (not shown), multilayer wiring (not shown), etc. Form. Thereby, the semiconductor device according to the present embodiment is manufactured.

Next, the effect of this embodiment will be described.
In the present embodiment, the lower layer portion made of p-type silicon layer 104a, an upper portion is made of n-type silicon layer 104d, the total amount of phosphorus to form a silicon film 104 larger than the total amount of boron in the cell region R _C The n-type silicon layer 104d is removed, and then an RTA process is performed to make the impurities uniform, thereby forming a p-type silicon film 104 serving as a floating gate electrode in the cell region _RC and the peripheral circuit region R _p. Then, an n-type silicon film 104 to be the lower part of the gate electrode can be formed. As a result, the floating gate electrode of the p-type memory cell and the lower part of the gate electrode of the peripheral circuit of the n-type conductivity can be made separately by a common process.

  Thus, by setting the conductivity type of the floating gate electrode of the memory cell to p-type, the threshold value of the memory cell transistor can be increased. In addition, the breakdown voltage of the tunnel insulating film can be improved. As a result, the tunnel insulating film can be thinned and the operating voltage can be reduced. Further, when a positive potential is applied to the control gate electrode, no depletion layer is formed in the portion of the floating gate electrode on the tunnel insulating film side, so that charges can be taken in and out of the floating gate electrode with a low coupling ratio. For this reason, a floating gate electrode can be made thin and processing becomes easy. These effects facilitate the miniaturization of the memory cell. On the other hand, when the conductivity type of the gate electrode of the peripheral circuit transistor is n-type, the conventional design assets can be utilized. In addition, by sharing the steps, the number of steps can be reduced and the manufacturing cost of the semiconductor device can be reduced.

Further, by forming a common step the gate electrode of the floating gate electrode and the peripheral circuit region R _p of the cell region R _C, even if the gate insulating film of the tunnel insulating film and the low voltage region R _L of the cell region R _C, The common silicon oxynitride film 103 can be formed by patterning. As described above, the silicon oxynitride film 103 is formed by a complicated thermal process in order to ensure reliability. For this reason, if the tunnel insulating film in the cell region _RC and the gate insulating film in the low voltage region _RL are formed by separate processes, the above-described complicated thermal process is repeated, and the number of processes increases. In addition, the insulating film formed first may be deteriorated by a thermal process for forming an insulating film formed later. In contrast, according to the present embodiment, since the tunnel insulating film in the cell region _RC and the gate insulating film in the low voltage region _RL are formed in the same process, the number of processes can be reduced and the thermal process can be performed. It is possible to avoid the deterioration of the insulating film.

Further, in the present embodiment, since the non-doped silicon layer 104c is formed in the silicon film 104, the process up to the step of removing the n-type silicon layer 104d from the cell region _RC after forming the n-type silicon layer 104d. In the meantime, it is possible to suppress the diffusion of impurities between the p-type silicon layer 104a and the n-type silicon layer 104d. Thus, by removing the n-type silicon layer 104d from the cell region R _C, in the cell region R _C, the total amount of phosphorus in the silicon film 104 can be reliably smaller than the amount of boron. As a result, in the cell region _RC , the conductivity type of the silicon film 104 can be surely made p-type.

Furthermore, in the present embodiment, since the nitrogen-doped silicon layer 104b is provided in the silicon film 104, the nitrogen-doped silicon layer 104b becomes a dividing layer, and impurity diffusion can be more effectively suppressed. This also ensures that the conductivity type of the silicon film 104 is p-type in the cell region _RC .

  In the present embodiment, an example in which the p-type silicon layer 104a, the nitrogen-doped silicon layer 104b, the non-doped silicon layer 104c, and the n-type silicon layer 104d are formed in this order is shown. However, the nitrogen-doped silicon layer 104b and the non-doped silicon layer are illustrated. The formation order of 104c may be reversed. That is, after forming the non-doped silicon layer 104c on the p-type silicon layer 104a, the nitrogen-doped silicon layer 104b may be formed, and then the n-type silicon layer 104d may be formed.

Furthermore, according to the present embodiment, since the n-type silicon layer 104d and the non-doped silicon layer 104c are removed only in the cell region _RC , the floating gate electrode is formed relatively thin and the gate electrode is relatively It can be formed thick. Thereby, in the cell region _RC , the control power of the control gate electrode with respect to the active area can be increased. On the other hand, in the peripheral circuit region R _p, formation of the through-hole 107a for connecting a phosphorus-doped polysilicon film 109 on the silicon film 104 is facilitated.

  In the present embodiment, the nitrogen-doped silicon layer 104b is formed by exposing the p-type silicon layer 104a to an ammonia atmosphere, but the method for forming the nitrogen-doped silicon layer 104b is not limited to this. For example, the nitrogen-doped silicon layer 104b may be formed by in-situ doping using nitric oxide (NO).

In the present embodiment, an example is shown in which the nitrogen-doped silicon layer 104b is formed as a dividing line that suppresses the diffusion of impurities, but the dividing line is not limited to this. For example, as described in the second and third embodiments described later, the dividing layer may be an oxygen-doped silicon layer or a carbon-doped silicon layer. Oxygen doped silicon layer, for example, in-situ Doping with nitrous oxide _(N 2 O), nitrous oxide _(N 2 O) or diluted oxygen during the deposition of the silicon layer _{(O 2)} to It can be formed by exposure or interruption of film formation of the silicon layer and exposure to the atmosphere. The carbon-doped silicon layer can be formed by in-situ doping using, for example, ethylene (C ₂ H ₄ ).

Further, the thickness of the dividing layer is preferably set to (1/2) atomic layer or more. Thereby, diffusion of impurities can be reliably suppressed. For example, in order to cover 50% or more lattice points of the <100> plane of silicon having a low surface density, the surface density of nitrogen (N), oxygen (O), or carbon (C) is set to 3.4 × 10. ^It may be ¹⁴ atoms / cm ² or more.

On the other hand, the thickness of the dividing line is preferably 2 nm or less. Thus, it is possible to ensure vertical conduction without destroying or removing the dividing line intentionally. As a result, a process of destroying or removing the dividing line without damaging the thin p-type silicon layer 104a is not required, and the manufacturing is facilitated. In order to make the thickness of the split layer 2 nm or less, the surface density of nitrogen (N), oxygen (O), or carbon (C) may be 1.1 × 10 ¹⁶ atoms / cm ² or less.

From the above, it is preferable that the thickness of the dividing layer is (1/2) atomic layer or more and 2 nm or less. A more preferable thickness of the dividing layer is, for example, 1 nm. When the thickness of the split layer is 1 nm, the nitrogen dose is, for example, 5.3 × 10 ¹⁵ atoms / cm ² , the oxygen dose is, for example, 4.7 × 10 ¹⁵ atoms / cm ² , and the carbon dose is The amount is, for example, 4.8 × 10 ¹⁵ atoms / cm ² .

  Note that two or more elements of nitrogen (N), oxygen (O), and carbon (C) may be introduced into the dividing line. Further, diffusion of impurities may be prevented only by the non-doped silicon layer 104c without forming a dividing line.

  Furthermore, in the present embodiment, when the silicon film 104 is formed, an example in which the p-type silicon layer 104a to the n-type silicon layer 104d are continuously formed by the CVD method is shown. The formation method is not limited to this. For example, after the p-type silicon layer 104a, the nitrogen-doped silicon layer 104b, and the non-doped silicon layer 104c are formed by CVD, phosphorus is implanted into the upper portion of the non-doped silicon layer 104c by ion implantation or plasma doping. The upper portion of the non-doped silicon layer 104c may be changed to the n-type silicon layer 104d.

Furthermore, in the present embodiment, the example in which the n-type silicon layer 104d in the cell region _RC is removed by gas etching using a halogen gas is shown, but the etchant of the n-type silicon layer 104d is not limited to this. Not. For example, as described in the second and third embodiments described later, wet etching using an alkaline solution is replaced with gas etching using a halogen gas, or in combination with gas etching using a halogen gas. , You may go.

  Furthermore, in the present embodiment, an example in which the gate electrode is a W polymetal electrode has been shown, but the electrode structure of the gate electrode is not limited to this, and the gate electrode is a silicide including silicide such as cobalt silicide or nickel silicide. It is also possible to use an electrode. Furthermore, the acceptor introduced into the p-type silicon layer 104a is not limited to boron, and the donor introduced into the n-type silicon layer 104d is not limited to phosphorus. Further, the semiconductor is not limited to silicon.

Next, a second embodiment will be described.
5 to 12 are process cross-sectional views illustrating the method for manufacturing the nonvolatile semiconductor memory device according to this embodiment. FIG. 5A shows a cross section perpendicular to the AA direction of the cell region, and FIG. ) Shows a cross section perpendicular to the GC direction of the cell region, and (c) shows a cross section of the peripheral circuit region.

  This embodiment is also a method for manufacturing a planar NAND flash memory. In the present embodiment, a p-type floating gate electrode and an n-type gate electrode are separately formed by a common process by the same method as in the first embodiment. Further, in order to suppress impurity diffusion before the heat treatment, a dividing line made of oxygen-doped silicon is inserted. In addition to these, in this embodiment, a zirconia film is formed as a charge trap film on the floating gate electrode. Further, by removing the IPD film in the peripheral circuit region, a gate electrode is formed without forming a through hole in the IPD film.

First, as shown in FIGS. 5A to 5C, a silicon substrate 201 is prepared. In the silicon substrate 201, the cell region _RC and the peripheral circuit region _RP are set in the same manner as the silicon substrate 101 in the first embodiment described above. In the peripheral circuit region _Rp , a high voltage region _RH and a low voltage region _RL are set.
Next, by implanting impurities into the silicon substrate 201, a well (not shown) and a channel region (not shown) are formed. Next, the upper surface of the silicon substrate 201 is retreated, for example, by 30 nm in the high voltage region _RH by lithography technology and RIE technology.

Next, by performing a thermal oxidation process, a silicon thermal oxide film 202 having a thickness of, for example, 30 nm is formed on the entire upper surface of the silicon substrate 201. The silicon thermal oxide film 202 is a film that becomes a gate insulating film of a high voltage circuit in the high voltage region _RH after the device is completed. Next, a portion of the silicon thermal oxide film 202 formed in a region other than the high voltage region _RH is removed and a portion formed in the high voltage region _{RH is} left by the lithography technique and the wet etching technique. .

Next, by performing thermal oxidation treatment or high-temperature oxygen radical oxidation treatment, a silicon thermal oxide film having a thickness of, for example, 5.0 nm is formed on the upper surface of the silicon substrate 201 in the cell region _RC and the low voltage region _RL . To do. Next, the interface between the silicon thermal oxide film and the silicon substrate 201 is nitrided by performing a heat treatment in nitric oxide (NO). Further, the upper surface of the silicon thermal oxide film is nitrided by performing a plasma nitriding process. Thereby, a silicon oxynitride film 203 having a thickness of, for example, 5.5 nm is formed. The silicon oxynitride film 203 is a film that becomes a tunnel insulating film of a memory cell in the cell region _RC and a gate insulating film of a low voltage circuit in the low voltage region _RL after the memory device is completed.

Next, by depositing silicon doped with boron (B) at a concentration of 3 × 10 ¹⁹ atoms / cm ³ by, eg, CVD, the conductivity type is p-type and the film thickness is, for example, 7 nm. A shaped silicon layer 204a is formed. Subsequently, by exposing the p-type silicon layer 204a to an oxygen atmosphere containing 5% nitrogen, oxygen (O) is doped into the upper layer portion of the p-type silicon layer 204a at a concentration of, for example, 5 × 10 ²¹ atoms / cm ^3. To do. Thereby, an oxygen-doped silicon layer 204b having a thickness of, for example, 1 nm is formed. Next, for example, by depositing silicon doped with phosphorus (P) at a concentration of 5 × 10 ²⁰ atoms / cm ³ , the n-type silicon layer 204c having a conductivity type of n-type and a film thickness of, for example, 28 nm is used. Form.

As described above, the p-type silicon layer 204a, the oxygen-doped silicon layer 204b, and the n-type silicon layer 204c are continuously formed by the CVD method, so that the conductivity type of the lower layer portion is the p-type and the conductivity type of the upper layer portion. Is a n-type silicon film 204 having a film thickness of 35 nm, for example. Silicon film 204, after completion of the device, it becomes a floating gate electrode of the memory cell in the cell region R _C, a film to be a lower layer portion of the gate electrode of the peripheral circuit in the peripheral circuit region R _P. Further, the total amount of impurities, for example, phosphorus, which is doped into the n-type silicon layer 204c, is larger than the total amount of impurities, for example, boron, which are to be accepted into the p-type silicon layer 204a.

Next, as shown in FIGS. 6A to 6C, the upper part of the silicon film 204 is etched back in the cell region _RC by 30 nm using a halogen gas by the lithography technique and the RIE technique. Next, the n-type silicon layer 204c is completely removed from the cell region _RC by wet etching using an alkaline solution, for example, TMAH (Tetramethyl ammonium hydroxide). At this time, since the etching rate of p-type silicon is lower than the etching rate of n-type or non-doped silicon, the p-type silicon layer 204a can remain. As a result, in the cell region _RC , the total amount of phosphorus contained in the silicon film 204 is smaller than the total amount of boron. Note that the oxygen-doped silicon layer 204b may be removed or may remain, but the removed example is shown in the drawing. On the other hand, in the peripheral circuit region R _p, the entire silicon film 204 has remained, the total amount of phosphorus contained in the silicon film 204 is greater than the total amount of boron.

Next, a zirconia film 205 having a thickness of, for example, 10 nm is formed on the entire surface of the substrate by an ALD (Atomic Layer Deposition) method. Next, a silicon film 206 having a film thickness of, for example, 15 nm is formed on the entire surface of the substrate by ALD. The silicon film 206 is a film that serves as a CMP stopper in a later step. The zirconia film 205 is a film that becomes a charge trap film in a completed memory device.
Next, as shown in FIG. 7 (a) ~ (c) , by the lithography technique and RIE technique, in the peripheral circuit region _{R P,} to remove the silicon film 206 and zirconia film 205.

Next, as shown in FIGS. 8A to 8C, a hard mask (not shown) is formed by lithography technique and RIE technique. In forming the hard mask, a double patterning technique or a quadruple patterning technique may be applied. Next, by performing etching such as RIE using this hard mask, the silicon film 206, the zirconia film 205, the silicon film 204, the silicon oxynitride film 203, the silicon thermal oxide film 202, and the upper layer portion of the silicon substrate 201 Is selectively removed. Thereby, the trench 207a is formed. At this time, in the cell region _RC , a plurality of trenches 207a are formed so as to extend along the AA direction.

Next, silicon oxide is deposited by a CVD method using TEOS and ozone (O ₃ ) as raw materials, and the silicon oxide is subjected to CMP to flatten the upper surface, thereby silicon oxide is formed inside the trench 207a. The member 207 is embedded. Thereby, STI is formed. In the cell region _RC , a portion between the STIs in the silicon substrate 201 becomes an active area (AA).

Next, as shown in FIGS. 9A to 9C, the silicon film 206 is removed in the cell region _{RC and} the upper portion of the silicon oxide member 207 is removed by the lithography technique and the RIE technique. The upper surface of the member 207 is retreated, for example, 15 nm. At this stage, the height of the upper surface of the silicon oxide member 207 is substantially the same as the height of the upper surface of the zirconia film 205.

Next, by performing an RTA process at a temperature of, for example, 1000 ° C., impurities in the silicon film 204 are diffused throughout the silicon film 204. Thus, as in the first embodiment described above, the conductivity type of the silicon film 204 becomes p-type in the cell region R _C, the conductivity type of the silicon film 204 is n-type in the peripheral circuit region R _p. Prior to this RTA treatment, the process temperature is kept at 600 ° C. or lower to suppress the interdiffusion of impurities.

Next, as shown in FIGS. 10A to 10C, a silicon oxide film 208 having a thickness of, for example, 5 nm is formed on the entire surface of the substrate. Next, an alumina film 209 having a thickness of, for example, 10 nm is formed on the entire surface of the substrate. The silicon oxide film 208 and the alumina film 209 constitute an IPD film. Next, a tantalum nitride film (TaN film) 210 having a thickness of, for example, 10 nm is formed. Then, by lithography and RIE techniques, in the peripheral circuit region _{R P,} to remove the tantalum nitride film 210, an alumina layer 209 and the silicon oxide film 208. As a result, the upper surface of the silicon film 204 is exposed.

  Next, as shown in FIGS. 11A to 11C, a tungsten layer and a tungsten nitride layer are stacked on the entire surface of the substrate by sputtering, and a W / WN film 211 having a thickness of, for example, 50 nm is formed. Next, a silicon nitride film 212 having a thickness of, for example, 100 nm is formed on the entire surface of the substrate.

  Next, as shown in FIGS. 12A to 12C, the silicon nitride film 212, the W / WN film 211, the tantalum nitride film 210, the alumina film 209, the silicon oxide film 208, and the zirconia are formed by lithography and RIE techniques. The film 205, silicon film 204, silicon oxynitride film 203, and silicon thermal oxide film 202 are selectively removed. At this time, a double patterning technique or a quadruple patterning technique may be applied.

Thereby, in the cell region _RC , the tantalum nitride film 210 and the W / WN film 211 are laminated, and the control gate electrode CG extending in the GC direction is formed. Further, the zirconia film 205 is divided into a matrix to form the charge trap film CT. Further, the silicon film 204 is divided into a matrix to form the floating gate electrode FG. On the other hand, in the peripheral circuit region _{R p,} the gate electrode G of the silicon film 204 and W / WN film 211 are stacked is formed. Further, according to the above flow, the silicon oxynitride film 203 becomes the tunnel insulating film of the memory cell and the gate insulating film of the MOSFET of the low voltage circuit. On the other hand, the silicon thermal oxide film 202 becomes a gate insulating film of the MOSFET of the high voltage circuit.

  Next, sidewall spacers (not shown), diffusion layers (not shown), PMD (Pre-Metal Dielectric) (not shown), contact plugs (not shown), multilayer wiring (not shown), etc. Form. Thereby, the semiconductor device according to the present embodiment is manufactured.

Next, the effect of this embodiment will be described.
In this embodiment, a zirconia film 205 is formed as a charge trap film on a p-type floating gate electrode. As a result, charges that could not be captured by the floating gate electrode are captured by the zirconia film, and the captured charges are difficult to move. As a result, data retention characteristics in the memory cell are improved.

In the present embodiment, in the peripheral circuit region _{R P,} IPD film on the silicon film 204, i.e., after removal of the alumina film 209 and the silicon oxide film 208, by forming the W / WN film 211, The W / WN film 211 is in direct contact with the silicon film 204. Thus, the gate electrode can be formed by connecting the W / WN film 211 to the silicon film 204 without forming a through hole in the IPD film. As a result, when trying to form a through hole in the IPD film, a through hole is also formed in the lower thin silicon film 204, and the gate electrode is not destroyed. Therefore, formation of the gate electrode in the peripheral circuit region R _P is easy.

  The effects of the present embodiment other than those described above are the same as those of the first embodiment described above. For example, in the present embodiment, similarly to the first embodiment, a floating gate electrode having a p-type conductivity and a gate electrode having an n-type conductivity can be separately formed by a common process. Thereby, the manufacturing cost of the nonvolatile semiconductor memory device can be reduced. In addition, by forming the oxygen-doped silicon layer 204b as a dividing layer, it is possible to suppress the diffusion of impurities before the RTA treatment.

In this embodiment, an example in which the zirconia film 205 is formed as the charge trap film is shown, but the charge trap film is not limited to the zirconia film, and examples thereof include a hafnia film, an alumina film, and a silicon nitride film. A film containing abundant electron traps may also be used. Further, in this embodiment, an example in which the IPD film is a laminated film of the silicon oxide film 208 and the alumina film 109 is shown, but the film configuration of the IPD film is not limited to this, and instead of the silicon oxide film 208, A silicon oxynitride film (SiON film) or an ONO film (Oxide-Nitride-Oxide film: oxide-nitride-oxide film) may be used. Instead of the alumina film 209, a hafnia film, a hafnium silicate film, a zirconia film A zirconium silicate film, a lanthanum oxide film (La ₂ O ₃ film) or a praseodymium oxide film (Pr ₂ O ₃ film) may be used, or these films may be used in combination.

Next, a third embodiment will be described.
13 to 18 are process cross-sectional views illustrating the method for manufacturing the nonvolatile semiconductor memory device according to this embodiment. FIG. 13A is a cross-sectional view of the cell region perpendicular to the AA direction, and FIG. ) Shows a cross section perpendicular to the GC direction of the cell region, and (c) shows a cross section of the peripheral circuit region.

  This embodiment is also a method for manufacturing a planar NAND flash memory. In the present embodiment, the layer structure of the floating gate electrode in the cell region is a two-layer structure of a p-type silicon film and a tantalum nitride film. Further, by a method similar to that of the first embodiment described above, a floating gate electrode having a lower layer part and an n-type gate electrode having a lower layer part are separately formed by a common process. Further, in order to suppress impurity diffusion before the heat treatment, a dividing line made of carbon-doped silicon is inserted. Further, similarly to the second embodiment described above, the gate electrode is formed without forming the through hole in the IPD film by removing the IPD film in the peripheral circuit region.

First, as shown in FIGS. 13A to 13C, a silicon substrate 301 is prepared. In the silicon substrate 301, the cell region _RC and the peripheral circuit region _RP are set in the same manner as the silicon substrate 101 in the first embodiment described above. In the peripheral circuit region _Rp , a high voltage region _RH and a low voltage region _RL are set.
Next, by implanting impurities into the silicon substrate 301, a well (not shown) and a channel region (not shown) are formed. Next, the upper surface of the silicon substrate 301 is retreated, for example, by 30 nm in the high voltage region _RH by the lithography technique and the RIE technique.

Next, by performing a thermal oxidation process, a silicon thermal oxide film 302 having a film thickness of, for example, 30 nm is formed on the entire upper surface of the silicon substrate 301. Next, a portion of the silicon thermal oxide film 302 formed in a region other than the high voltage region _RH is removed and a portion formed in the high voltage region _{RH is} left by a lithography technique and a wet etching technique. .

Next, by performing thermal oxidation treatment or high-temperature oxygen radical oxidation treatment, a silicon thermal oxide film having a thickness of, for example, 6.0 nm is formed on the upper surface of the silicon substrate 301 in the cell region _RC and the low voltage region _RL . To do. Next, the interface between the silicon thermal oxide film and the silicon substrate 301 is nitrided by performing a heat treatment in nitric oxide (NO). Further, the upper surface of the silicon thermal oxide film is nitrided by performing a plasma nitriding process. Thereby, a silicon oxynitride film 303 having a film thickness of, for example, 6.5 nm is formed.

Next, silicon doped with boron (B) at a concentration of 3 × 10 ¹⁹ atoms / cm ³ is deposited by, eg, CVD. As a result, a p-type silicon layer 304a having a p-type conductivity and a film thickness of, for example, 7 nm is formed. Subsequently, the p-type silicon layer 304a is exposed to an atmosphere containing ethylene (C ₂ H ₄ ) and silane (SiH ₄ ), so that carbon (C) is, for example, 7 × 10 ^{20 in} the upper layer portion of the p-type silicon layer 304a. Doping is performed at a concentration of atoms / cm ³ . As a result, a carbon-doped silicon layer 304b having a thickness of, for example, 1 nm is formed. Next, by depositing silicon doped with, for example, phosphorus (P) at a concentration of 5 × 10 ²⁰ atoms / cm ³ , an n-type silicon layer 304c having a conductivity type of n-type and a thickness of, for example, 28 nm. Form.

As described above, the p-type silicon layer 304a, the carbon-doped silicon layer 304b, and the n-type silicon layer 304c are continuously formed by the CVD method, so that the conductivity type of the lower layer portion is p-type and the conductivity type of the upper layer portion. Is a n-type silicon film 304 having a film thickness of 35 nm, for example. Silicon film 304, after completion of the storage device, it becomes the lower layer portion of the floating gate electrode in the cell region R _C, a film to be a lower layer portion of the gate electrode in the peripheral circuit region R _P. In addition, the total amount of impurities such as phosphorus doped into the n-type silicon layer 304c, such as phosphorus, is greater than the total amount of impurities such as boron doped into the p-type silicon layer 304a.

Next, as shown in FIGS. 14A to 14C, a hard mask (not shown) is formed by lithography and RIE techniques. In forming the hard mask, a double patterning technique or a quadruple patterning technique may be applied. Next, by performing etching such as RIE using this hard mask, the silicon film 304, the silicon oxynitride film 303, the silicon thermal oxide film 302, and the upper layer portion of the silicon substrate 301 are selectively removed. Thereby, the trench 305a is formed. At this time, in the cell region _RC , a plurality of trenches 305a are formed so as to extend along the AA direction.

Next, silicon oxide is deposited by a CVD method using TEOS and ozone (O ₃ ) as raw materials. As a result, a TEOS / O ₃ film 305 is formed on the inner surface of the trench 305a. Next, a silicon oxide film is formed by SOG (Spin on Glass) method. Thereby, the SOG member 306 is embedded in the trench 305a. Next, CMP is performed using the silicon film 304 as a stopper to planarize the upper surface. As a result, an STI composed of the TEOS / O ₃ film 305 and the SOG member 306 is formed inside the trench 305a.

Next, as shown in FIGS. 15A to 15C, the upper portion of the silicon film 304 is etched back in the cell region _RC using 30 nm and halogen gas by the lithography technique and the RIE technique. Next, the n-type silicon layer 304c is completely removed from the cell region _RC by wet etching using an alkaline solution, for example, choline (Trimethy-2-hidoroxyethyl ammonium hydroxide). To do. Thereby, in the cell region _RC , the total amount of phosphorus contained in the silicon film 304 is smaller than the total amount of boron. At this time, the carbon-doped silicon layer 304b may be removed or may remain. On the other hand, in the peripheral circuit region R _p, the entire silicon film 304 remaining.

Next, an RTA process at a temperature of, for example, 1000 ° C. is performed to diffuse the impurities in the silicon film 304 throughout the silicon film 304. Thus, in the cell region R _C, the conductivity type of the silicon film 304 becomes p-type, in the peripheral circuit region R _p, conductivity type of the silicon film 304 is n-type.

Next, as shown in FIGS. 16A to 16C, a tantalum nitride film (TaN film) 307 having a film thickness of 15 nm is formed on the entire surface of the substrate by ALD. The tantalum nitride film 307 is a film that becomes an upper layer portion of the floating gate electrode in the completed device. Next, the tantalum nitride film 307 is etched back by 15 nm by etching using chlorine trifluoride (ClF ₃ ) gas. Thereby, the tantalum nitride film 307 remains only in the gap after the n-type silicon layer 304c in the cell region _RC is removed. Next, an alumina film 308 having a thickness of, for example, 10 nm is formed on the entire surface of the substrate. The alumina film 308 is a film that becomes an IPD film in the completed storage device. Next, a tantalum nitride film (TaN film) 309 having a thickness of, for example, 10 nm is formed on the entire surface of the substrate by ALD. The tantalum nitride film 309 is a film that becomes a lower layer portion of the control gate electrode in the cell region _RC in the completed memory device. Then, by lithography and RIE techniques, in the peripheral circuit region _{R P,} to remove the tantalum nitride film 309 and the alumina film 308. As a result, the upper surface of the silicon film 304 is exposed.

  Next, as shown in FIGS. 17A to 17C, a tungsten layer and a tungsten nitride layer are stacked by sputtering to form a W / WN film 310 having a thickness of, for example, 50 nm. Next, a silicon nitride film 311 having a film thickness of, for example, 100 nm is formed on the entire surface of the substrate.

  Next, as shown in FIGS. 18A to 18C, the silicon nitride film 311 is patterned by a lithography technique and an RIE technique to form a hard mask. At this time, a double patterning technique or a quadruple patterning technique may be applied. Next, etching such as RIE is performed using this hard mask as a mask, and W / WN film 310, tantalum nitride film 309, alumina film 308, tantalum nitride film 307, silicon film 304, silicon oxynitride film 303, and silicon thermal oxidation The film 302 is selectively removed.

Thereby, in the cell region _RC , the tantalum nitride film 309 and the W / WN film 310 are stacked, and the control gate electrode CG extending in the GC direction is formed. Further, the tantalum nitride film 307 and the silicon film 304 are divided into a matrix shape, and the floating gate electrode FG is formed. On the other hand, in the peripheral circuit region _{R p,} the gate electrode G of the silicon film 304 and W / WN film 310 are stacked is formed. In this way, the floating gate electrode FG is formed as a p-type electrode having at least a part of p-type conductivity, and the gate electrode G is formed as an n-type electrode having at least a part of n-type conductivity. Is done. Further, according to the above flow, the tunnel insulating film of the memory cell and the gate insulating film of the MOSFET of the low voltage circuit are formed from the silicon oxynitride film 303. On the other hand, a MOSFET gate insulating film of a high voltage circuit is formed from the silicon thermal oxide film 302.

  Next, sidewall spacers (not shown), diffusion layers (not shown), PMD (Pre-Metal Dielectric) (not shown), contact plugs (not shown), multilayer wiring (not shown), etc. Form. Thereby, the semiconductor device according to the present embodiment is manufactured.

Next, the effect of this embodiment will be described.
In this embodiment, the layer structure of the floating gate electrode is a two-layer structure in which a p-type silicon film 304 and a tantalum nitride film 307 are stacked. Since the tantalum nitride film 307, which is an upper layer of the floating gate electrode, has a high barrier height, it is possible to suppress the accumulated charge from leaking to the control gate electrode. Further, by forming the silicon film 304 under the floating gate electrode, the film quality of the silicon oxynitride film 303 which is a tunnel insulating film is hardly deteriorated. As a result, the data retention characteristics of the memory cell are improved and the reliability is improved.

The effects of the present embodiment other than those described above are the same as those of the second embodiment described above. For example, in this embodiment as well, as in the second embodiment, a p-type silicon film constituting the lower layer of the floating gate electrode and an n-type silicon film constituting the lower layer of the gate electrode are used in a common process. Can be made separately. Thereby, the manufacturing cost of the semiconductor device can be reduced. Further, by forming the carbon-doped silicon layer 304b as a dividing layer, it is possible to suppress the diffusion of impurities in the silicon film 304 before the RTA treatment. Further, in the peripheral circuit region _{R P,} IPD film on the silicon film 304, i.e., after removal of the alumina film 308, by forming the W / WN film 310, directly W / WN film 310 on the silicon film 304 It is in contact. Thus, the gate electrode can be formed by connecting the W / WN film 310 to the silicon film 304 without forming a through hole in the IPD film. Therefore, it is easy to form the gate electrode.

In the present embodiment, the example in which the IPD film is configured by the alumina film 308 is shown, but the IPD film is not limited to the alumina film, and the hafnia film, the hafnium silicate film, the zirconia film, the zirconium silicate film, and the lanthanum oxide A film (La ₂ O ₃ film) or a praseodymium oxide film (Pr ₂ O ₃ film) may be used, or these films may be combined.

  According to the embodiment described above, it is possible to realize a method for manufacturing a semiconductor device that can be easily miniaturized without significantly increasing the number of steps.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

101: silicon substrate, 102: silicon thermal oxide film, 103: silicon oxynitride film, 104: silicon film, 104a: p-type silicon layer, 104b: nitrogen-doped silicon layer, 104c: non-doped silicon layer, 104d: n-type silicon layer , 105: silicon nitride film, 106: silicon oxide member, 106a: trench, 107: silicon oxide film, 108: phosphorus-doped polycrystalline silicon film, 109: phosphorus-doped polycrystalline silicon film, 110: W / WN film, 201: silicon substrate 202: silicon thermal oxide film, 203: silicon oxynitride film, 204: silicon film, 204a: p-type silicon layer, 204b: oxygen-doped silicon layer, 204c: n-type silicon layer, 205: zirconia film, 206: silicon film 207: Silicon oxide member, 207a: Trench, 20 : Silicon oxide film, 209: alumina film, 210: tantalum nitride film, 211: W / WN film, 212: silicon nitride film, 301: silicon substrate, 302: silicon thermal oxide film, 303: silicon oxynitride film, 304: Silicon film, 304a: p-type silicon layer, 304b: carbon-doped silicon layer, 304c: n-type silicon layer, 305: TEOS / O ₃ film, 305a: trench, 306: SOG member, 307: tantalum nitride film, 308: alumina Film: 309: tantalum nitride film, 310: W / WN film, 311: silicon nitride film, CG: control gate electrode, CT: charge trap film, FG: floating gate electrode, G: gate electrode, SG: selection gate electrode, R _C : Cell area, R _P : Peripheral circuit area, R _H : High voltage area, R _L : Low voltage area

Claims (5)

A method of manufacturing a semiconductor device in which a cell region and a peripheral circuit region are set,
Forming a p-type semiconductor layer on a semiconductor substrate;
One or more elements selected from the group consisting of nitrogen, oxygen, and carbon on the p-type semiconductor layer are in the range of 3.4 × 10 ¹⁴ atoms / cm ^{2 to} 1.1 × 10 ¹⁶ atoms / cm ^2. Forming a dividing fault introduced in
Forming a non-doped semiconductor layer on the dividing layer;
Forming an n-type semiconductor layer on the non-doped semiconductor layer, wherein the total amount of impurities serving as donors is greater than the total amount of impurities serving as acceptors included in the p-type semiconductor layer;
Removing the n-type semiconductor layer from the cell region by performing at least one of gas etching using a halogen gas and wet etching using an alkaline solution;
After removing the n-type semiconductor layer, the impurity serving as the donor is diffused into the p-type semiconductor layer, and the impurity serving as the acceptor is diffused into the n-type semiconductor layer, thereby allowing the cell region and the peripheral circuit to be diffused. Forming a semiconductor film having a single conductivity type in each of the regions;
A p-type floating gate electrode is formed by selectively removing the semiconductor film in the cell region, and an n-type gate electrode is formed by selectively removing the semiconductor film in the peripheral circuit region. Process,
A method for manufacturing a semiconductor device comprising: Forming a semiconductor film on a semiconductor substrate, the conductivity type of the lower layer portion being p-type, the conductivity type of the upper layer portion being n-type, and the total amount of impurities serving as donors being greater than the total amount of impurities serving as acceptors; ,
Removing the upper part of the semiconductor film in a part of the region, thereby reducing the total amount of impurities serving as donors included in the semiconductor film in the part of the region less than the total amount of impurities serving as acceptors;
After removing the upper portion of the semiconductor film, the step of diffusing the impurity serving as the donor and the impurity serving as the acceptor in the semiconductor film;
A p-type electrode is formed by selectively removing the semiconductor film in the partial region, and an n-type is formed by selectively removing the semiconductor film in another region different from the partial region. Forming an electrode;
A method for manufacturing a semiconductor device comprising: The step of forming the semiconductor film includes
forming a p-type semiconductor layer;
Forming a split layer on the p-type semiconductor layer into which one or more elements selected from the group consisting of nitrogen, oxygen and carbon are introduced;
Forming an n-type semiconductor layer on the dividing layer, wherein the total amount of impurities serving as donors is greater than the total amount of impurities serving as acceptors included in the p-type semiconductor layer;
The method for manufacturing a semiconductor device according to claim 2, comprising:   The method for manufacturing a semiconductor device according to claim 2, wherein the step of removing the upper portion of the semiconductor film includes a step of performing gas etching using a halogen gas.   The method for manufacturing a semiconductor device according to claim 2, wherein the step of removing the upper portion of the semiconductor film includes a step of performing wet etching using an alkaline solution.

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