JP2013153053A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device without complicating a manufacturing process of the semiconductor device.SOLUTION: The semiconductor device, which includes a transistor having a vertical gate structure, includes a field plate electrode 30 provided under a gate electrode 20, a field plate electrode 32 provided under a gate electrode 22, and an outermost peripheral diffusion layer 54 which is adjacent to the gate electrode 22 and is provided on the side opposite to a base diffusion layer 50 when viewed from the gate electrode 22. The outermost peripheral diffusion layer 54 is not connected to a source electrode 40.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device including a transistor having a vertical gate structure and a method for manufacturing the semiconductor device.

A power MOSFET (Metal Oxide Field Effect Effect Transistor) having a vertical gate structure includes a gate electrode embedded in a trench dug in a substrate. As a technique related to such a transistor having a vertical gate structure, one disclosed in Patent Document 1 can be cited.
The technique described in Patent Document 1 is such that a gate pad portion formed continuously with a gate electrode is formed in a concave portion provided simultaneously with a concave groove for forming the gate electrode.

As a technique related to a transistor having a vertical gate structure, there is a RESURF structure in which a field plate electrode is formed under a gate electrode provided in a trench. In the RESURF structure, the insulating film provided below the trench where the field plate electrode is formed is thicker than the insulating film provided above the trench where the gate electrode is formed.
In Patent Document 2, a RESURF structure is realized by forming a gate electrode and a trench-based source electrode located under the gate electrode in a trench for embedding the gate electrode.

Japanese Patent Laid-Open No. 2002-37388 JP-T-2002-528916

  In the RESURF structure described above, the oxide film provided on the upper part of the trench where the gate electrode is formed functions as a gate oxide film. For this reason, the gate oxide film provided in the upper part of the trench is formed so as to be thinner than the field plate oxide film provided in the lower part of the trench. However, in a transistor having a vertical gate structure, when a source-drain voltage is applied, a higher electric field is generated in an oxide film formed in a trench located at the outermost periphery than other oxide films. In this case, the gate oxide film provided in the trench located on the outermost periphery may be destroyed.

In Patent Document 2, the thickness of the oxide film formed in the trench is constant only in the trench located at the outermost periphery. That is, the thickness of the gate oxide film in the trench located at the outermost periphery is increased to suppress the breakdown of the gate oxide film.
However, in this case, the film thickness of the gate oxide film in the outermost trench is different from the film thickness of the gate oxide film provided in the other trench. For this reason, the gate oxide film in the trench located at the outermost periphery and the gate oxide film provided in another trench need to be formed by different processes. Accordingly, the manufacturing process of the semiconductor device becomes complicated.
Other problems and novel features will become apparent from the description of the present invention and the accompanying drawings.

According to the present invention, a first conductivity type semiconductor substrate;
A plurality of first gate electrodes embedded in one surface of the semiconductor substrate and arranged in a first direction;
A second gate electrode embedded on the one surface side of the semiconductor substrate and positioned outside the plurality of first gate electrodes in the first direction;
A first gate insulating film covering a side surface of the first gate electrode;
A second gate insulating film covering a side surface of the second gate electrode;
A plurality of first field plate electrodes provided under the first gate electrode and connected to the first gate electrode;
A second field plate electrode provided under the second gate electrode and connected to the second gate electrode;
A first field plate insulating film covering a side surface and a lower surface of the first field plate electrode and having a thickness larger than that of the first gate insulating film;
A second field plate insulating film that covers a side surface and a lower surface of the second field plate electrode and has a thickness larger than that of the second gate insulating film;
A source electrode provided on the one surface of the semiconductor substrate;
A drain electrode provided on the other surface opposite to the one surface of the semiconductor substrate;
A second conductivity type different from the first conductivity type provided between each of the plurality of first gate electrodes and between the second gate electrode and the first gate electrode adjacent to the second gate electrode. A base diffusion layer of
A source diffusion layer of the first conductivity type provided on the base diffusion layer and connected to the source electrode;
An outermost peripheral diffusion layer of the second conductivity type provided adjacent to the second gate electrode and on the opposite side of the base diffusion layer as viewed from the second gate electrode;
With
A semiconductor device in which the outermost peripheral diffusion layer is not connected to the source electrode is provided.

According to the present invention, the step of forming a plurality of grooves arranged in the first direction in the first conductivity type semiconductor substrate;
Forming a field plate insulating film on a lower portion of the side surface of the groove and a bottom surface of the groove, and forming a gate insulating film having a thickness smaller than that of the field plate insulating film on an upper portion of the side surface of the groove; ,
Forming a gate electrode in the trench, and a field plate electrode located under the gate electrode and connected to the gate electrode;
A base diffusion layer is formed between the gate electrodes by introducing an impurity of a second conductivity type different from the first conductivity type into the semiconductor substrate, and the gate electrode located on the outermost side in the first direction And forming an outermost peripheral diffusion layer that is adjacent to and located outside the plurality of gate electrodes in the first direction;
Introducing a first conductivity type impurity into the semiconductor substrate to form a source diffusion layer on the base diffusion layer;
Forming a source electrode connected to the source diffusion layer and not connected to the outermost peripheral diffusion layer on the semiconductor substrate;
A method for manufacturing a semiconductor device is provided.

  According to the present invention, it is possible to improve the reliability of a semiconductor device without complicating the manufacturing process of the semiconductor device.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing the semiconductor device shown in FIG. 1. FIG. 2 is a plan view showing the semiconductor device shown in FIG. 1. FIG. 10 is a plan view illustrating a modification of the semiconductor device illustrated in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. It is a top view which shows the semiconductor device shown in FIG. It is sectional drawing which shows the semiconductor device which concerns on 3rd Embodiment. FIG. 13 is a plan view showing the semiconductor device shown in FIG. 12. It is a top view which shows the semiconductor device which concerns on 4th Embodiment. FIG. 2 is a circuit diagram showing an electronic device including the semiconductor device shown in FIG. 1. It is a figure which shows the structure of the vehicle which has an electronic apparatus shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 is a cross-sectional view showing a semiconductor device 200 according to the first embodiment. FIG. 2 is a plan view showing the semiconductor device 200 shown in FIG. FIG. 1 shows a part of the AA ′ cross section in FIG.
The semiconductor device 200 according to this embodiment includes a semiconductor substrate 10, a plurality of gate electrodes 20, a gate electrode 22, a gate insulating film 120, a gate insulating film 122, a plurality of field plate electrodes 30, and a field plate electrode. 32, a field plate insulating film 130, a field plate insulating film 132, a source electrode 40, a drain electrode 42, a base diffusion layer 50, a source diffusion layer 52, and an outermost peripheral diffusion layer 54.

  The semiconductor substrate 10 has, for example, an N-type conductivity type. The plurality of gate electrodes 20 are embedded on one surface side of the semiconductor substrate 10. The plurality of gate electrodes 20 are arranged in the first direction. The gate electrode 22 is embedded on one surface side of the semiconductor substrate 10. The gate electrode 22 is located outside the plurality of gate electrodes 22 in the first direction. The gate insulating film 120 covers the side surface of the gate electrode 20. The gate insulating film 122 covers the side surface of the gate electrode 22.

  The plurality of field plate electrodes 30 are provided under the gate electrode 20. The plurality of gate electrodes 20 are connected to the gate electrode 20. The field plate electrode 32 is provided under the gate electrode 22. The field plate electrode 32 is connected to the gate electrode 22. The field plate insulating film 130 covers the side surface and the lower surface of the field plate electrode 30. The field plate insulating film 130 is thicker than the gate insulating film 120. The field plate insulating film 132 covers the side surface and the lower surface of the field plate electrode 32. The field plate insulating film 132 is thicker than the gate insulating film 122.

The source electrode 40 is provided on one surface of the semiconductor substrate 10. The drain electrode 42 is provided on the other surface opposite to the one surface of the semiconductor substrate 10. The base diffusion layer 50 is provided between each of the plurality of gate electrodes 22 and between the gate electrode 20 and the gate electrode 22 adjacent to the gate electrode 22. Base diffusion layer 50 has a P-type conductivity. The source diffusion layer 52 is provided on the base diffusion layer 50 and is connected to the source electrode 40. The source diffusion layer 52 has N type conductivity. The outermost peripheral diffusion layer 54 is provided adjacent to the gate electrode 22 and on the side opposite to the base diffusion layer 50 when viewed from the gate electrode 22. The outermost peripheral diffusion layer 54 has a P-type conductivity type. Further, the outermost peripheral diffusion layer 54 is not connected to the source electrode 40.
Note that the conductivity type of each component included in the semiconductor device 200 may be opposite to that shown in the present embodiment.
Hereinafter, the configuration of the semiconductor device 200 according to the present embodiment will be described in detail.

As shown in FIG. 1, the semiconductor device 200 according to this embodiment includes a plurality of cells 60 and an outermost peripheral cell 62. Hereinafter, in this specification, a region including the cell 60 and the outermost peripheral cell 62 is also referred to as a transistor formation region.
In the semiconductor device 200 according to this embodiment, the semiconductor substrate 10 is, for example, a silicon substrate. The semiconductor substrate 10 has, for example, an N-type conductivity type. The semiconductor substrate 10 constitutes a semiconductor chip together with other components provided on the semiconductor substrate 10.
As shown in FIG. 1, the semiconductor substrate 10 includes an N-type region 12 and an N-type region 14 provided on the N-type region 12. For example, the N-type region 14 has a higher impurity concentration than the N-type region 12.
An insulating film 140 is provided on the semiconductor substrate 10, the gate electrode 20, and the gate electrode 22. The insulating film 140 is made of, for example, a silicon oxide film.

As shown in FIGS. 1 and 2, a plurality of gate electrodes 20 are provided on one surface side of the semiconductor substrate 10. The plurality of gate electrodes 20 are arranged in the first direction. In the present embodiment, the plurality of gate electrodes 20 are arranged, for example, in the Y direction in FIG. 1 and 2 are diagrams schematically showing the configuration of the semiconductor device 200. FIG. For this reason, the number of gate electrodes 20 is not limited to that shown in FIG.
The gate electrode 20 is embedded in a trench 70 formed in the semiconductor substrate 10. The gate electrode 20 is provided so as to extend in the X direction in FIG. 2, for example.
The gate electrode 20 is made of, for example, polysilicon.

As shown in FIGS. 1 and 2, a gate electrode 22 is provided on one surface side of the semiconductor substrate 10. The gate electrode 22 is provided outside the plurality of gate electrodes 20 in the first direction. That is, the gate electrode 22 is provided on the outer side of the gate electrode 20 that is located on the outermost side in the first direction among the plurality of gate electrodes 20.
In the present embodiment, the gate electrode 22 is provided on both outer sides of the plurality of gate electrodes 20 in, for example, the Y direction in FIG. In the present embodiment, the gate electrode 22 is provided, for example, above the plurality of gate electrodes 20 in FIG. 2 and below in FIG.
The gate electrode 22 is embedded in a trench 72 formed in the semiconductor substrate 10. The gate electrode 22 is provided so as to extend in a second direction perpendicular to the first direction in the plane of the semiconductor substrate 10. In the present embodiment, the gate electrode 22 is provided, for example, so as to extend in the X direction in FIG. The gate electrode 22 has the same shape as the gate electrode 20, for example.
The gate electrode 22 is made of, for example, polysilicon.
The planar shapes of the gate electrode 20 and the gate electrode 22 are configured such that, for example, the length in the X direction in FIG. 2 is larger than the length in the Y direction.

As shown in FIG. 2, the plurality of gate electrodes 20 and the gate electrodes 22 are connected to each other, for example, at both ends in the X direction in FIG.
The plurality of gate electrodes 20 and gate electrodes 22 are both arranged in the Y direction in FIG. In this case, the distance between the two adjacent gate electrodes 20 and the distance between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22 are, for example, constant.

FIG. 3 is a plan view showing the semiconductor device 200 shown in FIG. 1, and shows a structure in an upper layer than FIG.
As shown in FIG. 3, the semiconductor device 200 includes a gate wiring 24. The gate wiring 24 is provided in an upper layer than the layer in which the gate electrode 20 and the gate electrode 22 are provided. The gate electrode 20 and the gate electrode 22 are connected to an external power source through the gate wiring 24.
As shown in FIG. 3, the gate wiring 24 is provided in the same layer as the source electrode 40 described later, for example. The gate wiring 24 is provided so as to surround the source electrode 40, for example.

As shown in FIG. 2, the semiconductor device 200 includes a gate wiring 28 provided around the gate electrode 20 and the gate electrode 22. The groove for embedding the gate wiring 28 is provided, for example, continuously with the groove 80 (see FIG. 5). That is, the trench for embedding the gate wiring 28 is provided continuously with, for example, the trench 70 and the trench 72.
Similarly to the gate electrode 20 and the gate electrode 22, the gate wiring 28 is embedded in, for example, a trench provided in the semiconductor substrate 10. Further, the gate wiring 28 is continuously provided on, for example, the four sides of the gate electrode 20 and the gate electrode 22 and surrounds the gate electrode 20 and the gate electrode 22.
As shown in FIG. 2, the semiconductor device 200 includes a gate contact 26 provided on the gate wiring 28. The gate contact 26 is formed in the insulating film 140.
The gate wiring 28 is connected to the gate wiring 24 through a gate contact 26 provided on the gate wiring 28. The gate electrode 20 and the gate electrode 22 are connected to the gate wiring 28 in the extending direction of the gate electrode 20 and the gate electrode 22, for example. For this reason, the gate electrode 20 and the gate electrode 22 are connected to the gate wiring 24. Note that the gate wiring 28 is located outside the transistor formation region and does not constitute the cell 60 or the outermost peripheral cell 62. Further, in the Y direction in FIG. 2, the interval between the two adjacent gate electrodes 20 is smaller than, for example, the interval between the gate electrode 22 and the gate wiring 28 adjacent to the gate electrode 22.

  FIG. 4 is a plan view showing a modification of the semiconductor device 200 shown in FIG. 1, and corresponds to FIG. As shown in FIG. 4, in the semiconductor device 200, the gate wiring 28 may not be formed so as to surround the gate electrode 20 and the gate electrode 22. In this modification, the gate wiring 28 is provided only on both ends in the extending direction of the gate electrode 20 and the gate electrode 22, for example. In this case, the gate wiring 28 is provided so as to extend in a direction perpendicular to the extending direction of the gate electrode 20 and the gate electrode 22, for example. The configuration shown in FIG. 4 is different from the configuration shown in FIG. 2 in that the gate wiring 28 and the later-described diffusion layer 56 are not formed outside the outermost peripheral cell 62 in the Y direction in FIG. However, the cross-sectional view outside the outermost peripheral cell 62 in the Y direction in FIG. 4 is substantially the same as the cross-sectional view shown in FIG.

As shown in FIG. 1, the gate insulating film 120 covers the side surface of the gate electrode 20. The gate insulating film 120 is formed on the upper portion of the side surface of the trench 70 formed in the semiconductor substrate 10. The gate insulating film 120 is made of, for example, a silicon oxide film.
As shown in FIG. 1, the gate insulating film 122 covers the side surface of the gate electrode 22. The gate insulating film 122 is formed on the upper portion of the side surface of the trench 72 formed in the semiconductor substrate 10. The gate insulating film 122 is made of, for example, a silicon oxide film.
For example, the gate insulating film 120 and the gate insulating film 122 have the same thickness. The film thicknesses of the gate insulating film 120 and the gate insulating film 122 are, for example, not less than 1 nm and not more than 100 nm. The film thickness of the gate insulating film 120 and the gate insulating film 122 is not less than 0.01 times and not more than 0.8 times the film thickness of the field plate insulating film 130 and the field plate insulating film 132 described later.
Note that the display of the gate insulating film 120 and the gate insulating film 122 is omitted in FIG.

As shown in FIG. 1, the plurality of field plate electrodes 30 are provided below the respective gate electrodes 20. The plurality of field plate electrodes 30 are connected to the respective gate electrodes 20.
The field plate electrode 30 is formed integrally with the gate electrode 20, for example. The field plate electrode 30 is provided in a shape extending in the Y direction in FIG. 2 (not shown), for example, like the gate electrode 20. In the present embodiment, the field plate electrode 30 is made of the same material as that of the gate electrode 20, and is made of, for example, polysilicon. The field plate electrode 30 may be made of a material different from that of the gate electrode 20.

In addition, as shown in FIG. 1, the field plate electrode 32 is provided under the gate electrode 22. The field plate electrode 32 is connected to the gate electrode 22.
The field plate electrode 32 is formed integrally with the gate electrode 22, for example. Further, the field plate electrode 32 is provided in a shape extending in the Y direction in FIG. 2 (not shown), for example, like the gate electrode 22. In the present embodiment, the field plate electrode 32 is made of the same material as the gate electrode 22 and is made of, for example, polysilicon. The field plate electrode 32 may be made of a material different from that of the gate electrode 22.
The shape of the field plate electrode 30 and the field plate electrode 32 is, for example, the same.
The field plate electrode is also provided under the gate wiring 28, for example. The field plate electrode provided under the gate wiring 28 is formed integrally with the gate wiring 28, for example.

As shown in FIG. 1, the field plate insulating film 130 covers the side surface and the lower surface of the field plate electrode 30. The field plate insulating film 130 is thicker than the gate insulating film 120. The field plate insulating film 130 is made of, for example, a silicon oxide film.
Further, as shown in FIG. 1, the field plate insulating film 132 covers the side surface and the lower surface of the field plate electrode 32. The field plate insulating film 132 is thicker than the gate insulating film 122. The field plate insulating film 132 is made of, for example, a silicon oxide film.
For example, the field plate insulating film 130 and the field plate insulating film 132 have the same film thickness. The film thickness of the field plate insulating film 130 and the field plate insulating film 132 is, for example, not less than 10 nm and not more than 1000 nm.
As will be described later, the gate insulating film 122 and the field plate insulating film 132 are provided in the same process as the gate insulating film 120 and the field plate insulating film 130, respectively. The gate electrode 22 and the field plate electrode 32 are provided in the same process as the gate electrode 20 and the field plate electrode 30. Further, the gate wiring 28 and the field plate electrode provided under the gate wiring 28 are also provided by the same process as the gate electrode 20 and the fold plate electrode 30.

As shown in FIG. 1, the source electrode 40 is provided on one surface of the semiconductor substrate 10 with an insulating film 140 interposed therebetween. A plurality of source contacts 44 are provided in the insulating film 140. The source electrode 40 is connected to each source diffusion layer 52 described later via a plurality of source contacts 44.
The source contact 44 is provided so as to penetrate the source diffusion layer 52. For this reason, the source electrode 40 is also connected to the base diffusion layer 50 via the source contact 44.
Note that the source diffusion layer 52 is not provided on the base diffusion layer 50 provided between the gate electrode 20 adjacent to the gate electrode 22 and the gate electrode 22. For this reason, the source contact 44 provided on the base diffusion layer 50 connects only the base diffusion layer 50 and the source electrode 40.
As shown in FIG. 1, a drain electrode 42 is provided on the other surface of the semiconductor substrate 10. The drain electrode 42 is connected to the N-type region 12.

As shown in FIGS. 1 and 2, a base diffusion layer 50 is provided between each of the plurality of gate electrodes 20 and between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22. The base diffusion layer 50 has, for example, a P-type conductivity type.
The base diffusion layer 50 provided between each of the plurality of gate electrodes 20 is adjacent to the gate electrode 20 with the gate insulating film 120 interposed therebetween. The base diffusion layer 50 provided between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22 is adjacent to the gate electrode 20 via the gate insulating film 120 and via the gate insulating film 122. Adjacent to the gate electrode 22.
The plurality of base diffusion layers 50 are separated from each other by the gate electrode 20. The depth of the base diffusion layer 50 is shallower than the depth at which the gate electrode 20 and the gate electrode 22 are embedded in the semiconductor substrate 10, for example.

As shown in FIG. 1, a source diffusion layer 52 is provided on the base diffusion layer 50. The source diffusion layer 52 is connected to the source electrode 40 via the source contact 44. The source diffusion layer 52 has, for example, an N type conductivity type.
For example, the source diffusion layer 52 is not provided on the base diffusion layer 50 provided between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22. A source diffusion layer 52 may be provided on the base diffusion layer 50 provided between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22.

  In the present embodiment, a cell is formed by the gate electrode 20, the source electrode 40, the drain electrode 42, the N-type region 12, the N-type region 14, and the base diffusion layer 50 and the source diffusion layer 52 provided between the adjacent trenches 70. 60 is configured. That is, the semiconductor device 200 according to the present embodiment includes a plurality of cells 60 that are transistors having a vertical gate structure. The plurality of cells 60 constitute a power MOSFET. For this reason, the semiconductor device 200 is used for an electronic device used in, for example, a vehicle.

The base diffusion layer 50 and the source diffusion layer 52 provided on the base diffusion layer 50 together with the two gate electrodes 20 provided on both sides thereof form a cell 60. For example, when a voltage is applied to the gate electrode 20, a channel is formed in a region near the gate insulating film 120 in the base diffusion layer 50.
Further, a portion of the N-type region 14 located between the adjacent trenches 70 functions as a drift region. When a voltage is applied between the source electrode 40 and the drain electrode 42, a depletion layer extending from the PN junction formed by the N-type region 14 and the P-type base diffusion layer 50 to the N-type region 14 causes the PN junction to Such high voltage is blocked. For this reason, it becomes possible to improve the breakdown voltage in the PN junction.

The semiconductor device 200 in this embodiment includes a field plate electrode 30 provided under the gate electrode 20. In this case, since the electrolytic concentration at the lower end of the gate electrode 20 is suppressed, the potential gradient becomes uniform along the trench 70 in which the gate electrode 20 and the field plate electrode 30 are embedded. Thereby, the N-type region 14 is easily depleted in a region located between adjacent trenches 70. Therefore, when a voltage is applied between the source electrode 40 and the drain electrode 42, the width of the depletion layer extending from the PN junction between the N-type region 14 and the base diffusion layer 50 to the N-type region 14 is increased. Can be made. Therefore, the breakdown voltage of the PN junction can be improved.
Furthermore, in this case, even if the impurity concentration of the N-type region 14 is increased, the width of the depletion layer extending from the PN junction to the N-type region 14 can be sufficiently maintained. That is, a high breakdown voltage can be maintained in the PN junction. Therefore, the impurity concentration of the N-type region 14 with high concentration, it is possible to reduce the on-resistance R _on of the cell 60.

  In the present embodiment, the gate electrode 20 adjacent to the gate electrode 22, the gate electrode 22, the source electrode 40, the drain electrode 42, the N-type region 12, the N-type region 14, and the trench 70 and the trench 72 are provided. The outermost peripheral cell 62 is formed by the base diffusion layer 50. Thus, in the present embodiment, the outermost peripheral cell 62 does not have the source diffusion layer 52. The outermost peripheral cell 62 may have a source diffusion layer 52. In this case, the outermost peripheral cell 62 can function as a transistor.

In a semiconductor device constituting a power MOSFET, minority carriers may accumulate in a specific well such as a large area well. In such a case, when the accumulated carriers commutate, the parasitic bipolar transistor is turned on in this specific well, and a large current may flow. In this case, destruction of the cell or the like is caused, and the reliability of the semiconductor device is lowered.
The outermost peripheral cell 62 in this embodiment does not have the source diffusion layer 52. Therefore, minority carriers accumulated in the well can be extracted to the source electrode 40 by the source contact 44 connected to the base diffusion layer 50 of the outermost peripheral cell 62. Thereby, accumulation of minority carriers in a specific well can be suppressed, and a large current can be prevented from flowing.

Also in outermost peripheral cells 62, similarly to cell 60, it is possible to improve and reduce the on-resistance R _on of the breakdown voltage.

As shown in FIGS. 1, 2, and 4, the semiconductor device 200 includes an outermost peripheral diffusion layer 54 that is adjacent to the gate electrode 22 and provided on the opposite side of the base diffusion layer 50 from the gate electrode 22. . The outermost peripheral diffusion layer 54 has, for example, a P-type conductivity type. Further, the outermost peripheral diffusion layer 54 is not connected to the source electrode 40. The outermost peripheral diffusion layer 54 is provided so as to be in contact with the gate insulating film 122, for example.
In the present embodiment, the outermost peripheral diffusion layer 54 is electrically floating, for example. For this reason, the potential of the outermost peripheral diffusion layer 54 is not less than the potential of the source electrode 40 and not more than the potential of the drain electrode 42. In this specification, being electrically floating means not being connected to any external power source.
The outermost peripheral diffusion layer 54 is provided by the same process as that of the base diffusion layer 50, for example. Therefore, the outermost peripheral diffusion layer 54 has the same depth as the base diffusion layer 50, for example. The outermost peripheral diffusion layer 54 has the same impurity concentration as that of the base diffusion layer 50, for example. Further, the outermost peripheral diffusion layer 54 has substantially the same impurity concentration profile as that of, for example, the base diffusion layer 50 in the depth direction inside the semiconductor substrate 10 from the surface of the semiconductor substrate 10 on one side.
The gate wiring 28 is provided on the side opposite to the gate electrode 22 when viewed from the outermost peripheral diffusion layer 54 in the first direction. Between the outermost peripheral diffusion layer 54 and the gate wiring 28, the N-type region 14 that reaches one surface of the semiconductor substrate 10 is located.

  In the region outside the outermost peripheral cell 62, that is, on the side opposite to the side where the base diffusion layer 50 is provided when viewed from the gate electrode 22, the cell structure like the cell 60 and the outermost peripheral cell 62 is not formed. In this case, the effect of depletion by forming the field plate insulating film 130 and the field plate insulating film 132 cannot be obtained outside the outermost peripheral cell 62. For this reason, a high electric field is generated in a portion of the gate insulating film 122 located outside the outermost peripheral cell 62. As a result, the thin gate insulating film 122 may be destroyed.

  In the semiconductor device 200 according to this embodiment, the P-type outermost peripheral diffusion layer 54 is provided so as to be adjacent to the gate electrode 22 and on the opposite side of the base diffusion layer 50 as viewed from the gate electrode 22. . For this reason, when a voltage is applied between the source electrode 40 and the drain electrode 42, the gate insulating film 122 is formed by the depletion layer extending from the PN junction formed by the P-type outermost peripheral diffusion layer 54 and the N-type region 14. It is possible to reduce the electric field generated in For this reason, the gate insulating film 122 can be prevented from being destroyed.

Further, the potential of the outermost peripheral diffusion layer 54 is not less than the potential of the source electrode 40 and not more than the potential of the drain electrode 42. In this case, the portion of the gate insulating film 122 that is in contact with the outermost peripheral diffusion layer 54 has the same potential as that of the outermost peripheral diffusion layer 54. For this reason, the potential gradient generated in the portion of the gate insulating film 122 in contact with the outermost peripheral diffusion layer 54 can be smoothed. Thus, a high electric field can be prevented from being generated in the gate insulating film 122. Therefore, the gate insulating film 122 can be prevented from being destroyed.
Furthermore, the potential of the outermost peripheral diffusion layer 54 is higher than the potential of the base diffusion layer 50 connected to the source electrode 40. For this reason, the PN junction formed by the outermost peripheral diffusion layer 54 and the N-type region 14 is prevented from reaching the avalanche voltage before the PN junction formed by the base diffusion layer 50 and the N-type region 14. Is done. Accordingly, it is possible to suppress a decrease in breakdown voltage and a decrease in safe operation area SOA (Safe Operation Area) due to the formation of the outermost peripheral diffusion layer 54.

As shown in FIGS. 1 and 2, the semiconductor device 200 may include a diffusion layer 56 provided on both sides of the gate wiring 28 so as to be adjacent to the gate wiring 28, for example. For example, the diffusion layer 56 is provided so as to be in contact with an insulating film covering the gate wiring 28. The diffusion layer 56 has, for example, a P-type conductivity type. Further, the diffusion layer 56 is electrically floating, for example.
The diffusion layer 56 can be formed by the same process as that of the base diffusion layer 50 and the outermost peripheral diffusion layer 54, for example.
In such a case, the depletion layer extending from the PN junction formed by the P type diffusion layer 56 and the N type region 14 can alleviate the electric field generated in the insulating film covering the gate wiring 28. Further, since the diffusion layer 56 is electrically floating, the potential gradient generated in the insulating film covering the gate wiring 28 can be made gentle. Therefore, the insulating film covering the gate wiring 28 can be prevented from being destroyed.

  In the present embodiment, the outermost peripheral diffusion layer 54 is not connected to, for example, the end portion of the semiconductor chip. That is, it is formed so as not to reach the scribe line when cutting the semiconductor chip before the step of dividing the wafer into semiconductor chips. Thereby, it is possible to prevent the drain electrode 42 and the outermost peripheral diffusion layer 54 from being short-circuited due to damage in the cross-section of the semiconductor chip that occurs when the semiconductor chip is cut.

  Table 1 shows the breakdown rate of the gate insulating film 122 when an avalanche breakdown occurs in the PN junction formed by the base diffusion layer 50 and the N-type region 14 in the semiconductor device according to this embodiment and the comparative example. Yes. The semiconductor device according to the comparative example has the same configuration as that of the semiconductor device 200 according to this embodiment except that the outermost peripheral diffusion layer 54 is not provided. In Table 1, the breakdown rate in the semiconductor device 200 according to this embodiment is 1.

As shown in Table 1, the semiconductor device according to the comparative example showed a 20 times higher breakdown rate than the semiconductor device 200 according to the present embodiment. For this reason, it can be seen that by providing the outermost peripheral diffusion layer 54, the breakdown in the gate insulating film 122 in the outermost peripheral trench is suppressed.
Note that, in order to confirm the difference in the destruction rate from the comparative example, the experiment is performed in an environment where the thickness of the gate insulating film 122 is intentionally reduced and a high voltage higher than the actual use state is applied. Needless to say, in the semiconductor device 200 designed for actual use, there is no breakdown of the gate insulating film at the time of avalanche breakdown.

FIG. 15 is a circuit diagram showing an electronic device 300 including the semiconductor device 200 shown in FIG.
As described above, the electronic device 300 is used in, for example, a vehicle. In this case, as shown in FIG. 15, electronic device 300, power supply 302, and load 304 are mounted on the vehicle. The power supply 302 is, for example, a battery mounted on the vehicle. The load 304 is, for example, an electronic component mounted on the vehicle, such as a headlamp. The electronic device 300 controls power supplied from the power source 302 to the load 304.

  The electronic device 300 is obtained by mounting semiconductor devices 200 and 306 on a circuit board (for example, a printed wiring board). The semiconductor device 200 according to the present embodiment is used, for example, as an IPD (Intelligent Power Device). In this case, the semiconductor device 200 includes a power MOSFET 308 and a control circuit (logic circuit) 310 formed on the same semiconductor substrate. The semiconductor device 306 is a microcomputer and is connected to the semiconductor device 200 via wiring on a circuit board. The semiconductor device 306 controls the semiconductor device 200. Specifically, the semiconductor device 306 inputs a control signal to the control circuit 310. Then, the control circuit 310 inputs a signal to the gate electrode of the power MOSFET 308 in accordance with the control signal input from the semiconductor device 306. That is, the control circuit 310 controls the power MOSFET 308. By controlling the power MOSFET 308, power from the power supply 302 is appropriately supplied to the load 304.

  FIG. 16 is a diagram showing a configuration of a vehicle having the electronic device 300 shown in FIG. This vehicle may be an automobile as shown in FIG. 16A, for example, or may be a motorcycle as shown in FIG. Each vehicle has a battery as a power source 302, an electronic device 300, and a headlamp 312 as a load 304.

Next, a method for manufacturing the semiconductor device 200 according to the present embodiment will be described. 5 to 9 are cross-sectional views showing a method for manufacturing the semiconductor device 200 shown in FIG.
First, as shown in FIG. 5A, a plurality of grooves 80 arranged in the first direction are formed in the N-type semiconductor substrate 10. The plurality of grooves 80 are a trench 70 and a trench 72 for embedding the gate electrode 20 and the gate electrode 22. Simultaneously with the step of forming the trench 80, for example, a trench for embedding the gate wiring 28 may be formed (not shown). In this case, the groove for embedding the gate wiring 28 is provided continuously with the groove 80, for example. Next, an insulating film 134 is formed in the trench 80 and on the semiconductor substrate 10. The insulating film 134 is, for example, a silicon oxide film.
Next, as shown in FIG. 5B, a portion of the insulating film 134 provided on the upper portion of the side surface of the groove 80 and a portion provided on the semiconductor substrate 10 are removed. The removal step is performed, for example, by etching back the insulating film 134 by dry etching.
As a result, the field plate insulating film 130 and the field plate insulating film 132 are formed on the lower portion of the side surface of the groove 80 and on the bottom surface of the groove 80.

Next, as illustrated in FIG. 6A, the insulating film 124 is formed on the upper portion of the side surface of the groove 80 and on the semiconductor substrate 10. As a result, the gate insulating film 120 and the gate insulating film 122 are formed on the upper portion of the side surface of the trench 80. The insulating film 124 is, for example, a silicon oxide film. Note that the insulating film 124 is formed in one step. For this reason, the insulating film 124 has a constant film thickness in all the trenches 80, for example.
Next, as shown in FIG. 6B, a conductive film 29 is formed in the trench 80 and on the semiconductor substrate 10. The conductive film 29 is also formed in a trench for embedding the gate wiring 28 (not shown), for example.

Next, as shown in FIG. 7A, a portion of the conductive film 29 located outside the groove 80 is removed. Thereby, the gate electrode 20 and the gate electrode 22 are formed. Further, a field plate electrode 30 located under the gate electrode 20 and connected to the gate electrode 20 and a field plate electrode 32 located under the gate electrode 22 and connected to the gate electrode 22 are formed. At this time, the conductive film 29 formed in the trench for embedding the gate wiring 28 remains without being removed. Therefore, the gate wiring 28 is formed in the trench (not shown).
Next, as shown in FIG. 7B, a portion of the insulating film 124 located on the semiconductor substrate 10 is removed.

Next, as shown in FIG. 8A, a P-type impurity is introduced into the semiconductor substrate 10. Thus, the base diffusion layer 50 is formed between the gate electrodes, and the outermost peripheral diffusion layer is adjacent to the gate electrode located on the outermost side in the first direction and located outside the plurality of gate electrodes in the first direction. 54 is formed. That is, the base diffusion layer 50 is formed between the gate electrodes 20 and between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22. Further, an outermost peripheral diffusion layer 54 that is adjacent to the gate electrode 22 and located on the opposite side of the base diffusion layer 50 from the gate electrode 22 is formed.
The base diffusion layer 50 and the outermost peripheral diffusion layer 54 are formed as follows, for example. First, a resist film is formed on the semiconductor substrate 10. Next, the resist film is exposed and developed to form a resist mask. Next, the base diffusion layer 50 and the outermost peripheral diffusion layer 54 are formed by ion implantation using the resist mask as a mask. Thus, the base diffusion layer 50 and the outermost peripheral diffusion layer 54 can be formed by the same ion implantation.

Next, as shown in FIG. 8B, N-type impurities are introduced into the semiconductor substrate 10 to form the source diffusion layer 52 on the base diffusion layer 50. In the present embodiment, the source diffusion layer 52 is not provided on the base diffusion layer 50 provided, for example, between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22.
The source diffusion layer 52 is formed as follows, for example. First, a resist film is formed on the semiconductor substrate 10. Next, the resist film is exposed and developed to form a resist mask. Next, the source diffusion layer 52 is formed by ion implantation using the resist mask as a mask.
Note that heat treatment for thermally diffusing the base diffusion layer 50, the outermost peripheral diffusion layer 54, and the source diffusion layer 52 may be performed.

Next, as illustrated in FIG. 9, an insulating film 140 is formed on the semiconductor substrate 10, the gate electrode 20, and the gate electrode 22. Next, a plurality of source contacts 44 are formed in the insulating film 140. The source contact 44 is formed on each base diffusion layer 50.
Next, the source electrode 40 connected to the source diffusion layer 52 and the base diffusion layer 50 through the source contact 44 is formed on the insulating film 140. The source electrode 40 is not connected to the outermost peripheral diffusion layer 54. Further, the drain electrode 42 is formed on the other surface of the semiconductor substrate 10.
Thereby, the semiconductor device 200 shown in FIG. 1 is obtained.

Next, the effect of this embodiment will be described.
According to the present embodiment, the semiconductor device 200 includes the outermost peripheral diffusion layer 54 provided adjacent to the gate electrode 22 and on the opposite side of the base diffusion layer 50 as viewed from the gate electrode 22. Further, the outermost peripheral diffusion layer 54 is not connected to the source electrode 40.
Therefore, the electric field generated in the gate insulating film 122 can be reduced by the depletion layer extending from the PN junction formed by the outermost peripheral diffusion layer 54 and the N-type region 14. In addition, the potential gradient generated in the portion of the gate insulating film 122 in contact with the outermost peripheral diffusion layer 54 can be smoothed. Therefore, the gate insulating film provided in the trench located at the outermost periphery can be prevented from being destroyed.

In addition, according to the present embodiment, the semiconductor device 200 includes the outermost peripheral diffusion layer 54. In other words, the gate insulating film 122 can be prevented from being broken without increasing the thickness of the gate insulating film 122. Therefore, the gate insulating film 122 in the trench 72 located at the outermost periphery and the gate insulating film 120 provided in the trench 70 can be formed by the same process.
Therefore, the reliability of the semiconductor device can be improved without complicating the manufacture of the semiconductor device.

  FIG. 10 is a cross-sectional view showing the semiconductor device 202 according to the second embodiment, and corresponds to FIG. 1 in the first embodiment. FIG. 11 is a plan view showing the semiconductor device 202 shown in FIG. 10, and corresponds to FIG. 2 according to the first embodiment.

As shown in FIG. 10, in the semiconductor device 202 according to the present embodiment, the base diffusion layer 50 provided between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22 is connected to the source electrode 40. Absent. In the present embodiment, the source contact 44 is not formed on the base diffusion layer 50 provided between the gate electrode 20 adjacent to the gate electrode 22. The base diffusion layer 50 provided between the gate electrode 20 adjacent to the gate electrode 22 and the gate electrode 22 is, for example, electrically floating.
As shown in FIGS. 10 and 11, the distance between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22 is narrower than the distance between the two adjacent gate electrodes 20.

  As shown in FIG. 10, the source diffusion layer 52 is not provided on the base diffusion layer 50 provided between the two adjacent gate electrodes 20 located on the outermost side in the first direction. For this reason, the cell 60 located on the outermost side among the plurality of cells 60 has the same configuration as the outermost peripheral cell 62 in the first embodiment.

  The semiconductor device 202 according to the present embodiment has the same configuration as the semiconductor device 200 according to the first embodiment except for the above points.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

Further, according to the present embodiment, the base diffusion layer 50 provided between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22 is not connected to the source electrode 40. Therefore, the source contact 44 is not provided on the base diffusion layer 50 provided between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22. Accordingly, the distance between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22 can be made smaller than the distance between the two adjacent gate electrodes 20.
Thereby, in the outermost peripheral cell 62, depletion of the N-type region 14 is likely to occur in the PN junction formed by the base diffusion layer 50 and the N-type region 14. Therefore, the breakdown voltage in the outermost peripheral cell 62 can be improved.

  In this case, the breakdown voltage of the outermost peripheral cell 62 can be made higher than that of the cell 60. Thereby, the breakdown breakdown voltage of the cell 60 formed inside becomes a breakdown voltage determination point of the semiconductor device 202. Therefore, the design can be facilitated even when the VDS rating is changed by changing the impurity concentration of the semiconductor substrate.

  FIG. 12 is a cross-sectional view showing a semiconductor device 204 according to the third embodiment, and corresponds to FIG. 1 in the first embodiment. FIG. 13 is a plan view showing the semiconductor device 204 shown in FIG. 12, and corresponds to FIG. 2 in the first embodiment.

In the semiconductor device 204 according to this embodiment, the outermost peripheral diffusion layer 54 is connected to an external terminal. As shown in FIG. 12, the outermost peripheral diffusion layer 54 is connected to the pseudo electrode 46 provided on the insulating film 140. The outermost peripheral diffusion layer 54 is connected to an external terminal via the pseudo electrode 46.
As shown in FIG. 12, a contact 48 is provided in the insulating film 140. The contact 48 is connected to the outermost peripheral diffusion layer 54 and the pseudo electrode 46. For this reason, the outermost peripheral diffusion layer 54 is connected to the pseudo electrode 46.
FIG. 12 is a diagram schematically showing the structure of the semiconductor device 204. For this reason, the positional relationship between the pseudo electrode 46 and other configurations is not limited to that shown in FIG.

As shown in FIG. 13, the pseudo electrode 46 is provided outside a region surrounded by the gate wiring 28, for example. The pseudo electrode 46 is connected to a diffusion layer 56 formed so as to surround the outer periphery of the gate wiring 28.
As shown in FIG. 13, the gate wiring 28 is provided with a slit 82. In the slit 82, a P-type impurity diffusion layer that connects the diffusion layer 56 formed so as to surround the outer periphery of the gate wiring 28 and the outermost periphery diffusion layer 54 is formed. For this reason, the diffusion layer 56 formed so as to surround the outer periphery of the gate wiring 28 and the outermost periphery diffusion layer 54 are connected to each other. As a result, the outermost peripheral diffusion layer 54 is connected to the pseudo electrode 46.

In addition, the semiconductor device 204 in the present embodiment includes a control unit (not shown) that controls the potential of the outermost peripheral diffusion layer 54 via an external terminal. In the present embodiment, the control unit controls the potential of the outermost peripheral diffusion layer 54 to be equal to or lower than the potential of the drain electrode 42 and higher than the potential of the source electrode 40.
For example, the control unit controls the potential of the outermost peripheral diffusion layer 54 in such a range that no diode operation occurs at the PN junction formed by the P-type outermost peripheral diffusion layer 54 and the N-type region 14.
Further, the control unit applies, for example, the maximum voltage that is equal to or lower than the guaranteed gate voltage at the gate electrode 22 to the outermost peripheral diffusion layer 54. The potential of the portion of the gate insulating film 122 that is in contact with the outermost peripheral diffusion layer 54 is the same as that of the outermost peripheral diffusion layer 54. For this reason, it is possible to moderate the electric field generated in the gate insulating film 122 by smoothing the potential gradient generated in the portion of the gate insulating film 122 in contact with the outermost peripheral diffusion layer 54.
Note that the guaranteed gate voltage in the gate electrode 22 is a voltage designed to be lower than the voltage at which the gate insulating film 122 is broken due to the potential difference between the gate electrode 22 and the outermost peripheral diffusion layer 54.

  In the present embodiment, the control unit controls the potential of the outermost peripheral diffusion layer 54 to 10 V when, for example, the applied voltage VDS between the drain and the source reaches 15 V. In this case, the potential of the N-type region 14 is 5 V higher than the potential of the outermost peripheral diffusion layer 54. For this reason, diode operation does not occur in the PN junction formed by the outermost peripheral diffusion layer 54 and the N-type region 14. In addition, the potential of the portion in contact with the outermost peripheral diffusion layer 54 in the gate insulating film 122 is maintained at 10 V, which is the same as that of the outermost peripheral diffusion layer 54. Therefore, the electric field generated in the gate insulating film 122 can be efficiently reduced.

  The semiconductor device 202 according to the present embodiment has the same configuration as the semiconductor device 200 according to the first embodiment except for the above points.

Also in this embodiment, the same effect as that of the first embodiment can be obtained.
Further, according to the present embodiment, the potential of the outermost peripheral diffusion layer 54 can be controlled via the external terminal. For this reason, the electric field generated in the gate insulating film 122 can be efficiently relaxed. Therefore, the reliability of the semiconductor device can be improved.

FIG. 14 is a plan view showing a semiconductor device 206 according to the fourth embodiment, and corresponds to FIG. 13 in the third embodiment.
As shown in FIG. 14, in the semiconductor device 206 according to the present embodiment, the outermost peripheral cell 62 and the cell 60 have the same configuration as that of the second embodiment. The gate electrode 22 is provided with a slit 84. The semiconductor device 206 according to the present embodiment has the same configuration as that of the third embodiment except for these points.

  In the semiconductor device 206 according to the present embodiment, the outermost peripheral cell 62 and the cell 60 have the same configuration as that of the second embodiment. That is, the base diffusion layer 50 provided between the gate electrode 20 adjacent to the gate electrode 22 and the gate electrode 22 is not connected to the source electrode 40. Further, the source contact 44 is not formed on the base diffusion layer 50 provided between the gate electrode 20 adjacent to the gate electrode 22.

  In the semiconductor device 206 according to the present embodiment, the gate electrode 22 is provided with a slit 84. The slit 84 is formed with a P-type impurity diffusion layer that connects the base diffusion layer 50 provided between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22 and the outermost peripheral diffusion layer 54. ing. For this reason, the base diffusion layer 50 and the outermost peripheral diffusion layer 54 provided between the gate electrode 22 and the gate electrode 20 adjacent to the gate electrode 22 are connected to the pseudo electrode 46.

  Also in this embodiment, the same effects as those of the second and third embodiments can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 N type area | region 14 N type area | region 20 Gate electrode 22 Gate electrode 24 Gate wiring 26 Gate contact 28 Gate wiring 29 Conductive film 30 Field plate electrode 32 Field plate electrode 40 Source electrode 42 Drain electrode 44 Source contact 46 Pseudo electrode 48 Contact 50 Base diffusion layer 52 Source diffusion layer 54 Outermost peripheral diffusion layer 56 Diffusion layer 60 Cell 62 Outermost peripheral cell 70 Trench 72 Trench 80 Groove 82 Slit 84 Slit 120 Gate insulating film 122 Gate insulating film 124 Insulating film 130 Field plate insulating film 132 Field plate insulating film 134 Insulating film 140 Insulating film 200 Semiconductor device 202 Semiconductor device 204 Semiconductor device 206 Semiconductor device 300 Electronic device 302 Power supply 304 Load 306 Semiconductor device 308 Power MOSFET
310 Control Circuit 312 Headlamp

Claims (11)

A first conductivity type semiconductor substrate;
A plurality of first gate electrodes embedded in one surface of the semiconductor substrate and arranged in a first direction;
A second gate electrode embedded on the one surface side of the semiconductor substrate and positioned outside the plurality of first gate electrodes in the first direction;
A first gate insulating film covering a side surface of the first gate electrode;
A second gate insulating film covering a side surface of the second gate electrode;
A plurality of first field plate electrodes provided under the first gate electrode and connected to the first gate electrode;
A second field plate electrode provided under the second gate electrode and connected to the second gate electrode;
A first field plate insulating film covering a side surface and a lower surface of the first field plate electrode and having a thickness larger than that of the first gate insulating film;
A second field plate insulating film that covers a side surface and a lower surface of the second field plate electrode and has a thickness larger than that of the second gate insulating film;
A source electrode provided on the one surface of the semiconductor substrate;
A drain electrode provided on the other surface opposite to the one surface of the semiconductor substrate;
A second conductivity type different from the first conductivity type provided between each of the plurality of first gate electrodes and between the second gate electrode and the first gate electrode adjacent to the second gate electrode. A base diffusion layer of
A source diffusion layer of the first conductivity type provided on the base diffusion layer and connected to the source electrode;
An outermost peripheral diffusion layer of the second conductivity type provided adjacent to the second gate electrode and on the opposite side of the base diffusion layer as viewed from the second gate electrode;
With
The outermost peripheral diffusion layer is a semiconductor device that is not connected to the source electrode. The semiconductor device according to claim 1,
The outermost peripheral diffusion layer is a semiconductor device that is electrically floating. The semiconductor device according to claim 1,
The outermost peripheral diffusion layer is a semiconductor device connected to an external terminal. The semiconductor device according to claim 3.
A control unit for controlling the potential of the outermost peripheral diffusion layer via the external terminal;
The control unit controls the potential of the outermost peripheral diffusion layer to be equal to or lower than the potential of the drain electrode and higher than the potential of the source electrode. 5. The semiconductor device according to claim 1, wherein:
The first gate insulating film and the second gate insulating film are semiconductor devices having the same film thickness. The semiconductor device according to any one of claims 1 to 5,
A semiconductor device in which the base diffusion layer provided between the second gate electrode and the first gate electrode adjacent to the second gate electrode is not connected to the source electrode. The semiconductor device according to claim 6.
A semiconductor device in which an interval between the first gate electrode adjacent to the second gate electrode and the second gate electrode is narrower than an interval between two adjacent first gate electrodes. The semiconductor device according to claim 6 or 7,
A semiconductor device in which the source diffusion layer is not provided on the base diffusion layer provided between two adjacent first gate electrodes located on the outermost side in the first direction. The semiconductor device according to claim 1,
A semiconductor chip including the semiconductor substrate;
The outermost peripheral diffusion layer is a semiconductor device that is not connected to an end of the semiconductor chip. The semiconductor device according to any one of claims 1 to 9,
A gate wiring provided on the opposite side of the second gate electrode from the outermost peripheral diffusion layer in the first direction;
An impurity region of the first conductivity type located between the outermost peripheral diffusion layer and the gate wiring;
A semiconductor device comprising: Forming a plurality of grooves arranged in a first direction in a first conductivity type semiconductor substrate;
Forming a field plate insulating film on a lower portion of the side surface of the groove and a bottom surface of the groove, and forming a gate insulating film having a thickness smaller than that of the field plate insulating film on an upper portion of the side surface of the groove; ,
Forming a gate electrode in the trench, and a field plate electrode located under the gate electrode and connected to the gate electrode;
A base diffusion layer is formed between the gate electrodes by introducing an impurity of a second conductivity type different from the first conductivity type into the semiconductor substrate, and the gate electrode located on the outermost side in the first direction And forming an outermost peripheral diffusion layer that is adjacent to and located outside the plurality of gate electrodes in the first direction;
Introducing a first conductivity type impurity into the semiconductor substrate to form a source diffusion layer on the base diffusion layer;
Forming a source electrode connected to the source diffusion layer and not connected to the outermost peripheral diffusion layer on the semiconductor substrate;
A method for manufacturing a semiconductor device comprising:

Images