JP2013152838A - Plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PDP having a higher temperature suppression effect when compared with prior art, even if the number of FPCs to be connected is decreased.SOLUTION: A front plate in which a dielectric layer and a protective layer are formed, in this order, on a front substrate on which a plurality of display electrodes, consisting of a plurality of scan electrodes and a plurality of sustain electrodes, are formed so as to cover the display electrodes, and a back plate in which an insulator layer is formed on a back substrate on which a plurality of data electrodes are formed so as to cover the data electrodes are disposed to face each other and sealed with a sealing member. In a plasma display panel thus manufactured, the plurality of sustain electrodes include a common electrode which can be short-circuited electrically. The common electrode is stretched in parallel with the data electrodes, and is larger than the width of the sealing member being formed.

Description

  The present invention relates to a plasma display panel as a display device.

  Currently, a plasma display panel (hereinafter referred to as PDP) is mainly a surface discharge type having a three-electrode structure.

  In this surface discharge type PDP structure, a front plate and a rear plate, which are transparent at least on the front side, are arranged to face each other via a discharge space. A partition wall for partitioning the discharge space into a plurality of parts is disposed on the substrate, and an electrode group is disposed on the substrate so that discharge occurs in the discharge space partitioned by the partition wall.

  A plasma display device having such a PDP (hereinafter referred to as a PDP device) receives a sustain pulse from a scan electrode and a sustain electrode formed on a front plate via a flexible wiring board (hereinafter abbreviated as “FPC”). An image is displayed by applying the light alternately to generate discharge in the discharge cell to emit light.

  By the way, in recent years, electrical products with reduced power consumption have been desired for PDP devices. Also in the PDP, there is an expectation to reduce power consumption during driving. In particular, the power consumption of the developed PDP tends to increase due to the large screen and high definition of the PDP. For this reason, there is an increasing demand for technologies that realize power saving.

  By the way, with the increase in the screen size of the PDP, the current due to the sustain discharge increases, current concentration occurs near the electrode terminal on the sustain electrode side to which the FPC is connected, and the temperature rises locally at this portion. Therefore, in order to suppress the occurrence of a temperature gradient, a plurality of short-circuit wires that electrically short-circuit the sustain electrodes and a plurality of electrode terminals grouped into a plurality of electrode terminal groups that are electrically connected to the short-circuit wires are provided. There is a configuration of the PDP provided (for example, see Patent Document 1).

Japanese Unexamined Patent Publication No. 2011-100596

  In recent years, there has been a demand for a reduction in manufacturing cost while a large screen is required. Therefore, there is a need for a PDP that can suppress temperature rise even if the number of FPC connection locations is reduced. SUMMARY OF THE INVENTION An object of the present invention is to provide a PDP that exhibits a temperature suppressing effect that is higher than that of the prior art even when the number of FPC connections is reduced.

  The present invention relates to a front plate in which a dielectric layer and a protective film are formed in this order so that a display substrate is covered with a front substrate on which a plurality of display electrodes composed of a plurality of scan electrodes and a plurality of sustain electrodes are formed. A plasma display panel in which a back plate on which a data electrode is covered on a back substrate on which a plurality of data electrodes are formed, and a back plate, which is arranged oppositely and sealed with a sealing member, A common electrode for electrically short-circuiting the plurality of sustain electrodes is provided, the common electrode is extended in parallel with the data electrode, and is larger than a width at which the sealing member is formed.

  According to the present invention, even if the number of FPCs connected to the sustain electrodes is reduced, a large temperature gradient is not generated on the front plate, and a panel with excellent design can be created.

1 is an exploded perspective view showing a PDP according to an embodiment of the present invention. Sectional drawing which shows the structure of the discharge cell part of PDP by embodiment of this invention The figure which shows the electrode arrangement | sequence structure of PDP by embodiment of this invention The block diagram which shows the whole structure of the PDP apparatus using PDP by embodiment of this invention The wave form diagram which shows the drive voltage waveform applied to each electrode of PDP by embodiment of this invention The schematic diagram which shows arrangement | positioning of the display electrode pair of the front plate of PDP by embodiment of this invention, a corresponding electrode terminal, and a heat conductive part The enlarged view which shows arrangement | positioning of the display electrode pair of the front plate of PDP by embodiment of this invention, a corresponding electrode terminal, and a heat conductive part Sectional drawing which shows the positional relationship of the display electrode pair of the front plate of PDP by embodiment of this invention, a corresponding common electrode, sealing frit, and a dielectric material The figure which showed the comparative example for comparing with embodiment of this invention

<Embodiment 1>
Hereinafter, the PDP according to the first embodiment of the present invention will be described with reference to the drawings. However, the embodiment of the present invention is not limited to the first embodiment.

  First, the overall configuration of the PDP according to Embodiment 1 of the present invention will be described with reference to the drawings.

1 and PDP Configuration FIG. 1 is an exploded perspective view of a PDP 21 according to Embodiment 1 of the present invention with a front plate and a back plate separated from each other, and FIG. It is sectional drawing which shows the discharge cell structure when it did. As shown in FIGS. 1 and 2, the PDP 21 is configured by disposing a glass front plate 1 and a back plate 2 so as to form a discharge space 3 therebetween.

  The front plate 1 has a scanning electrode 5 as a conductive first electrode and a sustain electrode 6 as a second electrode arranged on a glass front substrate 4 in parallel with each other with a discharge gap MG. A plurality of display electrodes 7 are arranged in the row direction, and a dielectric layer 8 made of a glass material is formed so as to cover the scan electrodes 5 and the sustain electrodes 6. A protective film 9 made of MgO is formed on 8.

  Scan electrode 5 and sustain electrode 6 are each made of a conductive metal having a thickness of several μm made of Ag without using a transparent electrode such as ITO, and scan electrode 5 and sustain electrode 6 are shown in FIG. Thus, at least a two-layer structure (the illustrated one is two layers), and the lower layers 5a and 6a on the front substrate 4 side are made of a material containing a black metal oxide, and the upper layers 5b and 6b are lower layers 5a. The lower layer 5a, 6a of the front substrate 4 is configured to have a lower brightness than the upper layers 5b, 6b by configuring with a white material in which the Ag content is increased so that the specific resistance is smaller than 6a. Yes. That is, the display electrode 7 including the scan electrode 5 and the sustain electrode 6 is configured such that the brightness of the display electrode 7 including the scan electrode 5 and the sustain electrode 6 is low when viewed from the display surface on the front substrate 4 side. Thus, the light shielding member is not present between the display electrodes 7.

  The back plate 2 is provided with a plurality of data electrodes 12 made of Ag covered with an insulating layer 11 made of a glass material and arranged in a stripe shape in the column direction on a glass back substrate 10, and On the insulator layer 11, a grid-like partition wall 13 made of a glass material for partitioning the discharge space 3 between the front plate 1 and the back plate 2 for each discharge cell is provided. Further, red (R), green (G), and blue (B) phosphor layers 14R, 14G, and 14B are provided on the surface of the insulator layer 11 and the side surfaces of the partition walls 13. The front plate 1 and the back plate 2 are arranged to face each other so that the scan electrode 5 and the sustain electrode 6 intersect the data electrode 12, and the scan electrode 5, the sustain electrode 6 and the data electrode 12 intersect each other. As shown in FIG. 3, a discharge cell 15 is provided. The discharge space 3 is filled with, for example, a mixed gas of neon and xenon as a discharge gas. Note that the structure of the PDP 21 is not limited to that described above, and for example, a structure having stripe-shaped partition walls may be used.

  Here, as shown in FIG. 2, the cross-shaped barrier ribs 13 forming the discharge cells 15 include a vertical barrier rib 13a formed in parallel to the data electrode 12, and a horizontal barrier rib formed so as to be orthogonal to the vertical barrier rib 13a. 13b. The phosphor layers 14R, 14G, and 14B formed by coating in the barrier ribs 13 are formed of stripes of blue phosphor layers 14B, red phosphor layers 14R, and green phosphor layers 14G along the vertical barrier ribs 13a. They are arranged in order.

  FIG. 3 is an electrode array diagram of the PDP 21 shown in FIGS. N scanning electrodes Y1, Y2, Y3... Yn (5 in FIG. 1) and n sustaining electrodes X1, X2, X3... Xn (6 in FIG. 1) are arranged in a row. M data electrodes A1... Am (12 in FIG. 1) that are long in the direction are arranged. Discharge cells 15 are formed at portions where the pair of scan electrodes Y1 and sustain electrodes X1 and one data electrode A1 intersect, and m × n discharge cells 15 are formed in the discharge space. Further, as shown in FIG. 3, the scan electrode Y1 and the sustain electrode X1 are formed on the front plate 1 in a pattern that repeats in the arrangement of the scan electrode Y1, the sustain electrode X1, the sustain electrode X2, the scan electrode Y2,. Has been. Each of these electrodes is connected to a connection terminal provided at a peripheral end portion outside the image display area of the front plate 1 and the back plate 2.

2. Configuration of PDP 21 Device Next, an overall configuration of a plasma display device using the above-described PDP 21 (hereinafter referred to as a PDP device) will be described.

  FIG. 4 is a block diagram showing the overall configuration of the PDP apparatus. This PDP apparatus includes a PDP 21, an image signal processing circuit 22, a data electrode drive circuit 23, a scan electrode drive circuit 24, a sustain electrode drive circuit 25, a timing generation circuit 26, and a power supply circuit (not shown) configured as shown in FIGS. )). The data electrode drive circuit 23 includes a plurality of data drivers that are connected to one end of the data electrode 12 of the PDP 21 and are formed of semiconductor elements for supplying a voltage to the data electrode 12. The data electrode 12 is divided into a plurality of blocks as one block by several data electrodes 12, and a plurality of data drivers are connected to the electrode lead-out portion at the lower end of the PDP 21 in units of blocks.

  In FIG. 4, the image signal processing circuit 22 converts the image signal sig into image data for each subfield. The data electrode drive circuit 23 converts the image data for each subfield into signals corresponding to the data electrodes A1 to Am, and drives the data electrodes A1 to Am. The timing generation circuit 26 generates various timing signals based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to each drive circuit block. Scan electrode drive circuit 24 supplies drive voltage waveforms to scan electrodes Y1 to Yn based on timing signals, and sustain electrode drive circuit 25 supplies drive voltage waveforms to sustain electrodes X1 to Xn based on timing signals. Note that the sustain electrode side is commonly connected in the PDP 21 or outside the PDP 21, and then the common connection wiring is connected to the sustain electrode drive circuit 25.

3. Driving of PDP Next, a driving voltage waveform for driving the PDP 21 and its operation will be described with reference to FIG. FIG. 5 is a diagram showing drive voltage waveforms applied to the respective electrodes of the PDP 21.

  In PDP 21 according to the present embodiment, one field is divided into a plurality of subfields, and each subfield has an initialization period, an address period, and a sustain period.

3-1, Initialization Period In the initialization period of the first subfield, the data electrodes A1 to Am and the sustain electrodes X1 to Xn are held at 0 (V), and are equal to or lower than the discharge start voltage with respect to the scan electrodes Y1 to Yn. A ramp voltage that gradually rises from a voltage Vi1 (V) to a voltage Vi2 (V) that exceeds the discharge start voltage is applied. Then, the first weak initializing discharge is caused in all the discharge cells, negative wall voltages are accumulated on the scan electrodes Y1 to Yn, and positive walls on the sustain electrodes X1 to Xn and the data electrodes A1 to Am. The voltage is stored. Here, the wall voltage on the electrode refers to a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode.

  Thereafter, sustain electrodes X1 to Xn are maintained at positive voltage Vh (V), and a ramp voltage that gradually decreases from voltage Vi3 (V) to voltage Vi4 (V) is applied to scan electrodes Y1 to Yn. Then, the second weak initializing discharge is caused in all the discharge cells, the wall voltage between the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn is weakened, and the wall voltage on the data electrodes A1 to Am is reduced. Is also adjusted to a value suitable for the write operation.

3-2, Addressing Period In the subsequent addressing period, the scan electrodes Y1 to Yn are temporarily held at Vr (V). Next, the negative scan pulse voltage Va (V) is applied to the scan electrode Y1 in the first row, and the data electrode Ak (k = 1 to 1) of the discharge cell to be displayed in the first row among the data electrodes A1 to Am. A positive write pulse voltage Vd (V) is applied to m). At this time, the voltage at the intersection of the data electrode Ak and the scan electrode Y1 is obtained by adding the wall voltage on the data electrode Ak and the wall voltage on the scan electrode Y1 to the externally applied voltage (Vd−Va) (V). And the discharge start voltage is exceeded. An address discharge is generated between data electrode Ak and scan electrode Y1 and between sustain electrode X1 and scan electrode Y1, and a positive wall voltage is accumulated on scan electrode Y1 of the discharge cell. And a negative wall voltage is also accumulated on the data electrode Ak.

  In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection of the data electrodes A1 to Am and the scan electrode Y1 to which the address pulse voltage Vd (V) is not applied does not exceed the discharge start voltage, the address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

3-3, Sustain Period In the subsequent sustain period, the scan electrode Y1 to Yn has a positive sustain pulse voltage Vs (V) as the first voltage, and the sustain electrodes X1 to Xn have the ground voltage as the second voltage. 0 (V) is applied respectively. In the discharge cell in which the address discharge has occurred at this time, the voltage between the scan electrode Yi (i = 1 to n) and the sustain electrode Xi is equal to the sustain pulse voltage Vs (V) and the wall voltage on the scan electrode Yi. This is a sum of the wall voltage on the sustain electrode Xi and exceeds the discharge start voltage. Then, a sustain discharge occurs between the scan electrode Yi and the sustain electrode Xi, and the phosphor layer emits light by the ultraviolet rays generated at this time. A negative wall voltage is accumulated on scan electrode Yi, and a positive wall voltage is accumulated on sustain electrode Xi. At this time, a positive wall voltage is also accumulated on the data electrode Ak.

  In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained. Subsequently, 0 (V) that is the second voltage is applied to scan electrodes Y1 to Yn, and sustain pulse voltage Vs (V) that is the first voltage is applied to sustain electrodes X1 to Xn. Then, in the discharge cell in which the sustain discharge has occurred, since the voltage between the sustain electrode Xi and the scan electrode Yi exceeds the discharge start voltage, the sustain discharge occurs again between the sustain electrode Xi and the scan electrode Yi, A negative wall voltage is accumulated on sustain electrode Xi, and a positive wall voltage is accumulated on scan electrode Yi.

3-4, the second and subsequent subfields Similarly, the address discharge is caused in the address period by alternately applying the number of sustain pulses corresponding to the luminance weight to the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn. The sustain discharge is continuously performed in the discharged cells. Thus, the maintenance operation in the maintenance period is completed. The operations in the initialization period, address period, and sustain period in the subsequent subfield are substantially the same as those in the first subfield, and thus description thereof is omitted.

4. About manufacturing method of PDP 4-1. Manufacturing method of front plate Scan electrode 5 and sustain electrode 6 are formed on front substrate 4 by photolithography. As a material for scan electrode 5 and sustain electrode 6, an electrode paste containing silver (Ag), a glass frit for binding silver, a photosensitive resin, a solvent, and the like is used. First, an electrode paste is applied on the front substrate 4 by a screen printing method or the like. Next, the solvent in the electrode paste is removed by a drying furnace. Next, the electrode paste is exposed through a photomask having a predetermined pattern.

  Next, the electrode paste is developed to form a display electrode pattern. Finally, the display electrode pattern is fired at a predetermined temperature in a firing furnace. That is, the photosensitive resin in the display electrode pattern is removed. Further, the glass frit in the electrode pattern is melted. Thereafter, the glass frit that has been melted is vitrified by cooling to room temperature. Through the above steps, scan electrode 5 and sustain electrode 6 are formed.

  Here, besides the method of screen printing the electrode paste, a sputtering method, a vapor deposition method, or the like can be used.

  Next, the dielectric layer 8 is formed. As a material for the dielectric layer 8, a dielectric paste containing a dielectric glass frit, a resin, a solvent, and the like is used. First, a dielectric paste is applied on the front substrate 4 by a die coating method or the like so as to cover the scan electrodes 5 and the sustain electrodes 6 with a predetermined thickness. Next, the solvent in the dielectric paste is removed by a drying furnace. Finally, the dielectric paste is fired at a predetermined temperature in a firing furnace. That is, the resin in the dielectric paste is removed. Further, the dielectric glass frit is melted. Thereafter, the cooled dielectric glass frit is vitrified by cooling to room temperature. Through the above steps, the dielectric layer 8 is formed. Here, besides the method of die coating the dielectric paste, a screen printing method, a spin coating method, or the like can be used. Alternatively, a film that becomes the dielectric layer 8 can be formed by a CVD (Chemical Vapor Deposition) method or the like without using the dielectric paste.

  Next, a protective film 9 is formed on the dielectric layer 8.

  Through the above steps, the front plate 1 having the scan electrode 5, the sustain electrode 6, the dielectric layer 8, and the protective film 9 on the front substrate 4 is completed.

4-2, Manufacturing Method of Back Plate 2 Data electrodes 12 are formed on the back substrate 10 by photolithography. As a material of the data electrode 12, a data electrode paste containing silver (Ag) for ensuring conductivity, a glass frit for binding silver, a photosensitive resin, a solvent, and the like is used. First, the data electrode paste is applied on the back substrate 10 with a predetermined thickness by screen printing or the like. Next, the solvent in the data electrode paste is removed by a drying furnace. Next, the data electrode paste is exposed through a photomask having a predetermined pattern. Next, the data electrode paste is developed to form a data electrode pattern. Finally, the data electrode pattern is fired at a predetermined temperature in a firing furnace. That is, the photosensitive resin in the data electrode pattern is removed. Further, the glass frit in the data electrode pattern is melted. Thereafter, the glass frit that has been melted is vitrified by cooling to room temperature. The data electrode 12 is formed by the above process. Here, besides the method of screen printing the data electrode paste, a sputtering method, a vapor deposition method, or the like can be used.

  Next, the insulator layer 11 is formed. As a material of the insulator layer 11, an insulator paste containing an insulator glass frit, a resin, a solvent, and the like is used. First, an insulating paste is applied by a screen printing method or the like so as to cover the data electrode 12 on the back substrate 10 on which the data electrode 12 is formed with a predetermined thickness. Next, the solvent in the insulator paste is removed by a drying furnace. Finally, the insulator paste is fired at a predetermined temperature in a firing furnace. That is, the resin in the insulator paste is removed. Moreover, the insulator glass frit is melted. Thereafter, by cooling to room temperature, the molten insulator glass frit is vitrified. The insulator layer 11 is formed by the above process. Here, in addition to the method of screen printing the insulator paste, a die coating method, a spin coating method, or the like can be used. In addition, a film to be the insulator layer 11 can be formed by CVD (Chemical Vapor Deposition) method or the like without using the insulator paste.

  Next, the partition wall 13 is formed by photolithography. As a material of the partition wall 13, a partition wall paste including a filler, a glass frit for binding the filler, a photosensitive resin, a solvent, and the like is used. First, the barrier rib paste is applied on the insulator layer 11 with a predetermined thickness by a die coating method or the like. Next, the solvent in the partition wall paste is removed by a drying furnace. Next, the barrier rib paste is exposed through a photomask having a predetermined pattern. Next, the barrier rib paste is developed to form a barrier rib pattern. Finally, the partition pattern is fired at a predetermined temperature in a firing furnace. That is, the photosensitive resin in the partition pattern is removed. Further, the glass frit in the partition wall pattern is melted. Thereafter, the glass frit that has been melted is vitrified by cooling to room temperature. The partition wall 13 is formed by the above process. Here, in addition to the photolithography method, a sandblast method or the like can be used.

  Next, the phosphor layer 14 is formed. As a material for the phosphor layer 14, a phosphor paste containing phosphor particles, a binder, a solvent, and the like is used. First, the phosphor paste is applied to the insulating layer 11 between the plurality of adjacent barrier ribs 13 and to the side surfaces of the barrier ribs 13 by a dispensing method or the like. Next, the solvent in the phosphor paste is removed by a drying furnace. Finally, the phosphor paste is fired at a predetermined temperature in a firing furnace. That is, the resin in the phosphor paste is removed. The phosphor layer 14 is formed by the above steps. Here, in addition to the dispensing method, a screen printing method or the like can be used.

  Through the above steps, the back plate 2 having the data electrode 12, the insulator layer 11, the partition wall 13, and the phosphor layer 14 on the back substrate 10 is completed.

4-3, Assembly Method of Front Plate 1 and Back Plate 2 First, a sealing paste is applied around the back plate 2 by a dispensing method or the like. The sealing paste may contain beads, a low-melting glass material, a binder, a solvent, and the like. The applied sealing paste forms a sealing paste layer (not shown). Next, the solvent in the sealing paste layer is removed by a drying furnace. Thereafter, the sealing paste layer is temporarily fired at a temperature of about 350 ° C. The resin component etc. in the sealing paste layer are removed by temporary baking. Next, the front plate 1 and the back plate 2 are arranged to face each other so that the display electrode 7 and the data electrode 12 are orthogonal to each other.

  Further, the peripheral portions of the front plate 1 and the back plate 2 are held in a state of being pressed by a clip or the like. In this state, the low melting point glass material is melted by firing at a predetermined temperature. Then, the low-melting-point glass material that has been melted is vitrified by cooling to room temperature. Thereby, the front plate 1 and the back plate 2 are hermetically sealed. Finally, a discharge gas containing Ne, Xe or the like is sealed in the discharge space, thereby completing the PDP 21.

5. About the region near the end on the sustain electrode side The structure around the electrode terminal 30 on the sustain electrode side in the PDP of the present invention will be described with reference to FIGS.

  Since the same drive voltage may be applied to each sustain electrode 6, each sustain electrode 6 is connected to a common electrode 28 that electrically short-circuits sustain electrode 6. In order to connect the FPC 34 to the common electrode 28, the electrode terminals 30 for sustain electrodes are grouped into a plurality of electrode terminal groups 31 and provided on the left peripheral portion outside the image display area. FPC 34 is connected to each electrode terminal group 31, and FPC 34 is connected to sustain electrode drive circuit 25. Therefore, a voltage is applied to each sustain electrode 6 from sustain electrode drive circuit 25 through common electrode 28 via FPC 34. Since each of sustain electrodes 6 is electrically short-circuited, the number of electrode terminals 30 for sustain electrodes, the number of FPCs 34, and their attachment positions are arbitrary. That is, the number of electrode terminals 30, the number of FPCs 34, and the mounting position can be changed as appropriate depending on the size of the PDP 21 and the number of sustain electrodes 6.

  The common electrode 28 is formed by extending in the short side direction of the PDP 21, that is, in parallel with the data electrode. In the present embodiment, the common electrode 28 is made of an electrode paste containing silver (Ag), a glass frit for binding silver, a photosensitive resin, a solvent, and the like, similar to the sustain electrode 6.

  Furthermore, the common electrode 28 is formed with a plurality of heat conducting portions 32 electrically connected to the common electrode 28. Although the heat conducting part 32 extends parallel to the common electrode 28, the common electrode 28 having the heat conducting part 32 also has a plurality of electrode terminal groups 31 on the same side as the heat conducting part 32, so that the heat conducting part 32 32 is divided into a plurality of pieces. And the electrode terminal 30 is not formed in the area | region in which the heat conductive part 32 is formed, and the heat conductive part 32 is not formed in the place in which the electrode terminal group 31 is formed. That is, the heat conducting portion 32 is formed between the electrode terminal group 31 and the electrode terminal group 31.

  In addition, although heat conduction part 32 in the present embodiment is made of the same material as sustain electrode 6 and common electrode 28, it may be made of a material having lower resistance and conductivity.

  Further, it is desirable to reduce the number as much as possible from the viewpoint of cost reduction. Further, from the viewpoint of design, it is necessary to reduce the non-display area portion, that is, the formation area of the common electrode 28. Therefore, the formation width of the common electrode 28 is necessarily reduced. The number of FPCs 34 is limited mainly by current capacity, heat generation due to Joule heat, and a temperature difference between the front substrates caused thereby.

  In addition, the common electrode 28 includes a plurality of heat conducting portions 32 that are electrically connected to the common electrode 28. Although the heat conduction part 32 is extended in parallel with the common electrode 28, since it has a plurality of electrode terminal groups, the heat conduction part 32 is divided into a plurality. And the electrode terminal 30 is not formed in the area | region in which the heat conductive part 32 is formed, and the heat conductive part 32 is not formed in the place in which the electrode terminal group is formed. That is, the heat conducting portion 32 is formed between the electrode terminal group and the electrode terminal group. In addition, although heat conduction part 32 in the present embodiment is made of the same material as sustain electrode 6 and common electrode 28, it may be made of a material having lower resistance and conductivity.

  In the present invention, the dielectric layer 8 and the protective film are formed in this order so that the display electrode is covered with the front substrate on which the plurality of display electrodes composed of the plurality of scan electrodes 5 and the plurality of sustain electrodes 6 are formed. The front plate and the back plate on which the insulating layer 11 is formed so that the data electrodes are covered by the back substrate on which the plurality of data electrodes are formed are opposed to each other and sealed by the sealing member 27 A display panel comprising a common electrode for electrically short-circuiting a plurality of sustain electrodes, the common electrode extending parallel to the data electrode and having a width greater than a width at which the sealing member 27 is formed. To do.

  FIG. 8 is a cross-sectional view of the left side region of the PDP 21 where the electrode terminal 30 of the sustain electrode 6 is formed, and is a cross-sectional view cut in the long side direction of the PDP 21. As shown in FIG. 8, in the region where the sealing member 27 for sealing the front plate 1 and the rear plate 2 is formed, the width (W4) of the common electrode 28 formed on the front plate is the width of the sealing member 27. It is wider than (W1). The dielectric layer 8 and a part of the insulator layer 11 are bonded to the sealing member 27 in order to ensure adhesion between the sealing member 27 and the front plate and the rear plate. Since the dielectric layer 8 and the insulator layer 11 contain a glass component, the adhesiveness with the sealing member 27 is maintained. In the present embodiment, the width of the sealing member 27 is 5.25 mm, of which the width (W3) adhered to the dielectric layer 8 is 3 mm, and the width (W2) adhered to the insulator layer 11. ) Is 3 mm. The width of the common electrode 28 is not limited as long as it is equal to or larger than the width (W1) in which the sealant is formed, but can be appropriately changed depending on the dimensions of the PDP 21 and the expansion of the display area.

  Thereby, since the area of the common electrode 28 is sufficiently secured, it is possible to prevent a current from flowing locally, and to suppress an increase in power resistance. As a result, the temperature difference in the surface of the PDP 21 due to the rapid temperature rise of the PDP 21 can be further reduced, and cracking of the PDP 21 can be prevented.

  Therefore, a PDP 21 as an example which is an example of the present invention and a PDP 21 in which the common electrode 28 is not formed in a region sealed by the sealing member 27 as a comparative example of the present embodiment are subjected to a thermal test and confidential test. It was verified from the standpoints of confirmation of retention and temperature reduction effect.

  In the PDP 21 of the embodiment, the width of the sealing member 27 is 5 mm, the width of the common electrode 28 is 5 mm or more, the formation width of the front plate dielectric layer 8 is 2.5 mm, and the formation width of the insulating layer 11 of the back plate is 2.5 mm. Is designed to partially overlap with the sealing member 27 region.

  As shown in FIG. 9, the PDP 21 in the comparative example ensures a bonding area with the glass surface at the contact portion between the common electrode 28 and the sealing member 27 in order to increase the adhesive force and airtightness of the sealing member 27. Therefore, the common electrode 28 extended in the direction in which the data electrode is formed is not formed in the entire region corresponding to the sealing member 27. Instead, a linear common electrode is formed so as to be electrically connected from the electrode terminal 30 to the sustain electrode 6. The width of the sealing member 27 is 5 mm, the formation width of the dielectric layer 8 on the front plate is 1.5 mm, and the formation width of the insulating layer 11 on the back plate is 1.5 mm. It was.

  Therefore, in the PDP 21 of this embodiment, the area of the common electrode 28 is increased by about 30% compared to the comparative example.

  In the hot / cold heat test, the region where the sealing agent was sealed was immersed in 80 ° C. hot water, and then shock was applied in the order of water and heat. Thereby, sealing reliability can be evaluated.

  In the confidentiality preservation test, the inside of the PDP 21 is depressurized, helium gas is injected into the place where the sealing member is formed, the pressure change is measured, the initial lighting test is performed, and then the PDP 21 is left for one month, two months later Thereafter, voltage change in the PDP 21 after 3 months was evaluated.

  In the temperature reduction measurement, three points immediately below or just above the FPC 34 are connected in the long side direction of the PDP 21, and the temperature is measured. A temperature difference was obtained from the measured three temperatures, and a value having a larger temperature difference was adopted.

  In the heating / cooling test and the confidentiality holding test, the same effect as that of the comparative example was obtained from the present embodiment. In the temperature reduction measurement, there was a temperature reduction effect of 5 degrees as compared with the comparative example.

  As described above, the present invention is useful for providing a plasma display panel with higher display quality.

DESCRIPTION OF SYMBOLS 1 Front plate 2 Back plate 3 Discharge space 4 Front substrate 5 Scan electrode 6 Sustain electrode 5a, 6a Lower layer 5b, 6b Upper layer 7 Display electrode 8 Dielectric layer 9 Protective film 10 Back substrate 11 Insulator layer 12 Data electrode 13 Partition 14R, 14G, 14B Phosphor layer 15 Discharge cell 21 PDP
DESCRIPTION OF SYMBOLS 22 Image signal processing circuit 23 Data electrode drive circuit 24 Scan electrode drive circuit 25 Sustain electrode drive circuit 26 Timing generation circuit 27 Sealing member 28 Common electrode 30 Electrode terminal 31 Electrode terminal group 32 Thermal conduction part 34 Flexible substrate

Claims (2)

A front plate in which a dielectric layer and a protective film are formed in this order so that the display electrode is covered by a front substrate on which a plurality of display electrodes composed of a plurality of scan electrodes and a plurality of sustain electrodes are formed; A back plate on which an insulating layer is formed so that the data electrode is covered on the back substrate on which the data electrode is formed, and is a plasma display panel that is disposed oppositely and sealed with a sealing member, The plurality of sustain electrodes include a common electrode that is electrically short-circuited, and the common electrode extends parallel to the data electrode and is larger than a width in which the sealing member is formed. . The plasma display panel according to claim 1, wherein the sealing member has a region where the sealing member is formed, and a region where the dielectric layer and the insulating layer are bonded.

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