JP2013150456A - Dc/dc converter and control circuit for the same, and power supply device, power supply adapter, and electronic equipment using the dc/dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance reliability against a short circuit of a detection resistor.SOLUTION: An external detection resistor Ris connected to a detection terminal SOURCE. A pulse modulator 102 generates a pulse signal Swhose duty ratio is adjusted so that an output voltage Vof a DC/DC converter 10 approaches a target value. The pulse modulator 102 shifts the pulse signal Sto an off level of a switching transistor M1 on the basis of a detection voltage Vgenerated at the detection terminal SOURCE. After a lapse of a determination time period from when the pulse signal Sis shifted to an on level of the switching transistor M1, a short circuit detection circuit 110 generates a short circuit detection signal S_SHRT to be asserted when a detection voltage V' is higher than a predetermined threshold voltage V. A control circuit 100 stops switching of the switching transistor M1 when the short circuit detection signal S_SHRT is asserted.

Description

  The present invention relates to a DC / DC converter.

  Various home appliances such as TVs and refrigerators operate by receiving commercial AC power from the outside. Electronic devices such as laptop computers, mobile phone terminals, and PDAs (Personal Digital Assistants) can also be operated with commercial AC power, or the built-in battery can be charged with commercial AC power. . Such home appliances and electronic devices (hereinafter collectively referred to as electronic devices) have built-in power supply devices (inverters) for converting AC / DC (AC / DC) commercial AC voltage, or the inverters are external to the electronic devices. Built in the power adapter (AC adapter).

  FIG. 1 is a block diagram showing a basic configuration of an inverter. The inverter 1r mainly includes a fuse 2, an input capacitor Ci, a filter 4, a diode rectifier circuit 6, a smoothing capacitor Cs, and a DC / DC converter 10r.

Commercial AC voltage V _AC is input to the filter 4 through a fuse 2 and the input capacitor Ci. Filter 4 removes commercial AC voltage _{V AC} noise. Diode rectifier 6, a diode bridge circuit for full-wave rectifying the commercial AC voltage V _AC. The output voltage of the diode rectifier circuit 6 is smoothed by the smoothing capacitor Cs and converted into the DC voltage _VIN .

The insulated DC / DC converter 10r receives a DC voltage _VIN at an input terminal P1, steps down the voltage, and connects the output voltage _VOUT stabilized at a target value to the output terminal P2 (not shown). ).

The DC / DC converter 10r includes a control circuit 100r, an output circuit 200, and a feedback circuit 210. The output circuit 200 includes a transformer T1, a first diode D1, a first output capacitor Co1, a switching transistor M1, and a detection resistor _RS . Since the topology of the output circuit 200 is general, the description thereof is omitted.

When the switching transistor M1 is switched, the input voltage _VIN is stepped down and an output voltage _VOUT is generated. The control circuit 100r stabilizes the output voltage _VOUT to the target value by adjusting the switching duty ratio of the switching transistor M1, and controls the coil current Ip flowing through the primary winding W1 of the transformer T1.

The detection resistor _RS is provided in series with the primary winding W1 of the transformer T1 and the switching transistor M1. A voltage drop (detection voltage) V _S proportional to the current Ip flowing through the primary winding W1 and the switching transistor M1 is generated in the detection resistor R _S. The control circuit 100r controls the current Ip flowing through the primary winding W1 based on the detection voltage V _S.

FIG. 2 is a circuit diagram showing a configuration of the DC / DC converter 10r examined by the present inventors. The feedback circuit 210 generates a feedback voltage V _FB corresponding to the output voltage _VOUT and supplies the feedback voltage V _FB to the feedback terminal (FB terminal) of the control circuit 100r. The feedback circuit 210 includes a shunt regulator 212 and a photocoupler 214. The shunt regulator 212 generates a feedback signal S11 whose level is adjusted so that an error between the output voltage _VOUT and a predetermined target value becomes zero, and supplies the feedback signal S11 to the light emitting diode of the photocoupler 214. The phototransistor (or phototransistor) of the photocoupler 214 converts the optical signal S12 from the light emitting diode into a feedback voltage _VFB corresponding to the feedback signal S11.

In addition to the primary winding W1, an auxiliary winding W3 is provided on the primary side of the transformer T1. The auxiliary winding W3, the second diode D2, and the second output capacitor Co2 form a second DC / DC converter. In response to switching of the switching transistor M1, a DC voltage _VCC is generated in the second output capacitor Co2. DC voltage _{V CC} is supplied to the control circuit 100r of the power supply terminal VCC (VCC terminal).

The control circuit 100r includes a switching transistor M1, a pulse modulator 102, a driver 104, and a current limiting circuit 120. The drain of the switching transistor M1 is connected to the drain terminal DRAIN, and the source is connected to the detection terminal (SOURCE terminal). The DRIAN terminal is connected to the primary winding W1, and the detection resistor _RS is externally attached to the SOURCE terminal.

Pulse modulator 102 receives feedback voltage V _FB and detection voltage V _S. The pulse modulator 102 generates a pulse signal S _PWM whose duty ratio is adjusted according to the feedback voltage V _FB . The pulse modulator 102 controls the timing at which the switching transistor M1 is turned off according to the detection voltage V _S proportional to the coil current Ip flowing through the switching transistor M1. As such a pulse modulator 102, for example, a modulator of an average current mode or a peak current mode is known. The driver 104 switches the switching transistor M1 according to the pulse signal _SPWM .

The current limiting circuit 120 is a protection circuit that detects an overcurrent state by comparing the detection voltage V _S with the threshold voltage V _{CUR_LIM} and stops switching of the switching transistor M1 in the overcurrent state.

JP-A-9-098571 Japanese Patent Laid-Open No. 2-211055

For example, the pulse modulator 102 in the peak current mode shifts the pulse signal S _PWM to a level (on level) corresponding to the switching transistor M1 being turned on in response to a set signal asserted every predetermined period. If the circuit is normal, when the switching transistor M1 is turned on, the coil current Ip rises with a certain slope with time. Then, when the detection voltage V _S is compared with the feedback voltage V _FB and the detection voltage V _S rises to the feedback voltage V _FB , in other words, when the coil current Ip reaches the peak current level corresponding to the feedback voltage V _FB , The pulse signal S _PWM is _shifted to a level (off level) corresponding to the switching transistor M1 being turned off. Next, when the set signal is asserted, the pulse signal S _PWM transitions to the on level again.

In the DC / DC converter 10r of FIG. 2, if the detection resistor _RS is externally attached to the control circuit 100r and both ends of the detection resistor _RS are short-circuited due to adhesion of dust or the like, the coil current Ip cannot be detected. Specifically, since the detection voltage V _S is 0V regardless of the magnitude of the coil current I _P, the pulse signal S _PWM continues to maintain the on level. At this time, circuit protection by the current limiting circuit 120 is not applied. As a result, the switching transistor M1 continues to be switched at a predetermined maximum duty ratio (for example, 75%), and a large current flows through the switching transistor M1 and the primary winding W1. Soon, the fuse 2 in FIG. 1 is blown to protect the circuit, or the reliability of the circuit may be adversely affected before the fuse 2 is blown.

In order to solve this problem, it is conceivable to incorporate the detection resistor _RS in the control circuit 100r. This is because if the detection resistor _RS is built in the control circuit 100r, a short circuit due to dust or the like is eliminated. However, when the detection voltage V _S is built in the control circuit 100r, another problem arises that the designer of the inverter 1r cannot change the power of the DC / DC converter 10r.

  The present invention has been made in view of these problems, and one of the exemplary purposes of an embodiment thereof is to provide a DC / DC converter with improved reliability against a short circuit of a detection resistor.

  One embodiment of the present invention relates to a control circuit for a DC / DC converter. The DC / DC converter includes a transformer and a switching transistor provided on a current path of a primary winding of the transformer. The control circuit is provided on the current path of the primary winding, one end of which is grounded, a detection terminal for connecting the other end of the external detection resistor, and a feedback corresponding to the output voltage of the DC / DC converter A pulse modulator that generates a pulse signal whose duty ratio is adjusted so that the output voltage of the DC / DC converter approaches a target value, and receives a voltage based on the detection voltage generated at the detection terminal. Pulse modulator that transitions signal to off level corresponding to switching transistor off, driver that switches switching transistor based on pulse signal, and judgment after pulse signal transitions to on level corresponding to switching transistor on The detected voltage after the passage of time is compared with a predetermined threshold voltage, and the detected voltage It is provided with a short-circuit detecting circuit for generating a short-circuit detection signal is asserted when high. The control circuit stops switching of the switching transistor when the short detection signal is asserted.

When the detection resistor is not short-circuited and is normal, the coil current flowing in the primary winding of the transformer increases with a certain slope with time, and therefore the detection voltage generated across the detection resistor is also proportional to the coil current. Increase over time. For the detection voltage V _S , the elapsed time after the switching transistor is turned on is written as T _ON , the input voltage of the DC / DC converter is written as V _IN , the inductance of the primary winding is L1, and the resistance value of the detection resistor is written as R _S. Is given by equation (1).
V _S = V _IN / L1 × T _ON × R _S (1)
That is, when the detection resistance is normal, the detection voltage after the determination time has elapsed after the pulse signal has transitioned to the on level should have a non-zero level. On the other hand, even if the coil current increases in the state where the detection resistor is short-circuited, the detection voltage does not increase. , Lower than the threshold voltage.
Therefore, according to the control circuit of this aspect, it is possible to detect the presence or absence of a short circuit of the detection resistor by comparing the detection voltage after the determination time has elapsed after the switching transistor is turned on with the threshold voltage. The reliability against a short circuit of the resistor can be increased.

  The short detection circuit includes a window signal generation unit that generates a window signal that is asserted after the determination time has elapsed since the pulse signal transitioned to the on level, and a period during which the detection voltage is input to the input terminal and the window signal is asserted. A switch that is turned on, a voltage output from the output terminal of the switch, and a first comparator that compares a predetermined threshold voltage, and generates a short detection signal according to the comparison result of the first comparator May be.

  The window signal generation unit includes a second comparator that compares a triangular wave or sawtooth wave periodic signal with a threshold voltage corresponding to the determination time, and generates a window signal according to the comparison result of the second comparator. Also good.

  The pulse modulator may be a peak current mode pulse width modulator.

  The pulse modulator compares a detection voltage on which a periodic signal for slope compensation is superimposed with a feedback voltage, generates a reset signal that is asserted when the detection voltage becomes high, a reset signal, a predetermined period, An RS flip-flop that generates a pulse signal that transitions to a first level when the reset signal is asserted and transitions to a second level when the set signal is asserted. May be included.

  The pulse modulator may be an average current mode pulse width modulator.

  The pulse modulator compares the error voltage with a triangular wave or sawtooth wave periodic signal with a predetermined period and an error amplifier that generates an error voltage by amplifying and averaging the error between the detection voltage and the feedback voltage. And a pulse width modulation comparator that generates a pulse signal.

  The pulse modulator may be a pulse modulator in a fixed off-time mode.

  The pulse modulator compares the detection voltage on which the periodic signal for slope compensation is superimposed with the feedback voltage, and generates a OFF signal that is asserted when the detection voltage increases, and the OFF signal is asserted. There may be included an off-time fixed circuit that generates a pulse signal that has an off level corresponding to the switching transistor being turned off for a predetermined off time and then having an on level corresponding to the switching transistor being turned on.

The control circuit may be integrated on a single semiconductor substrate.
“Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.
By integrating the control circuit as one integrated circuit (IC), the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

  Another aspect of the present invention relates to a DC / DC converter. The DC / DC converter includes a transformer having a primary winding and a secondary winding, a switching transistor connected to the primary winding of the transformer, a first diode whose anode is connected to the secondary winding, and one end Is connected to the cathode of the first diode, a feedback circuit for generating a feedback voltage corresponding to the output voltage generated in the first output capacitor, a feedback voltage, and a switching transistor. And a control circuit according to any one of the above aspects that performs switching.

  The feedback circuit is a shunt regulator that generates a feedback signal whose level is adjusted so that an error between a voltage obtained by dividing the output voltage and a predetermined target value becomes zero, and a light emitting element on the primary side is controlled by the feedback signal. A photocoupler. A signal generated in the light receiving element on the secondary side of the photocoupler may be supplied to the control circuit as a feedback voltage.

  The transformer may further include an auxiliary winding provided on the primary side thereof. The DC / DC converter may further include a second diode having an anode connected to the auxiliary winding, and a second output capacitor having one end grounded and the other end connected to the cathode of the second diode. A DC voltage generated in the second output capacitor may be supplied to the power supply terminal of the control circuit.

  Yet another embodiment of the present invention relates to a power supply apparatus. The power supply device includes a filter that filters commercial AC voltage, a diode rectifier circuit that full-wave rectifies the output voltage of the filter, a smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage, and a DC input voltage The DC / DC converter according to any one of the above-described aspects is provided.

  Another embodiment of the present invention relates to an electronic device. The electronic device includes a load, a filter that filters commercial AC voltage, a diode rectifier circuit that full-wave rectifies the output voltage of the filter, a smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage, A DC / DC converter according to any one of the above-described aspects, which steps down a DC input voltage and supplies the voltage to a load.

  Another aspect of the present invention relates to a power adapter. The power adapter includes a filter for filtering commercial AC voltage, a diode rectifier circuit for full-wave rectification of the output voltage of the filter, a smoothing capacitor for smoothing the output voltage of the diode rectifier circuit and generating a DC input voltage, and a DC input voltage And the DC / DC converter according to any one of the above-described aspects that generate a DC output voltage.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, it is possible to improve the reliability of the detection resistor against a short circuit.

It is a block diagram which shows the basic composition of an inverter. It is a circuit diagram which shows the structure of the DC / DC converter which the present inventors examined. It is a circuit diagram which shows the structure of a DC / DC converter provided with the control circuit which concerns on embodiment. It is a circuit diagram which shows the structural example of a pulse modulator. It is a circuit diagram which shows another structural example of a pulse modulator. It is a circuit diagram which shows another structural example of a pulse modulator. It is a circuit diagram which shows the structural example of a short detection circuit. FIG. 4 is an operation waveform diagram when a detection resistor _RS is not short-circuited in the control circuit of FIG. 3. FIG. 4 is an operation waveform diagram when a detection resistor _RS is short-circuited in the control circuit of FIG. 3. FIG. 8 is an operation waveform diagram of the timer latch circuit of FIG. 7. It is a figure which shows an AC adapter provided with an inverter. 12A and 12B are diagrams illustrating an electronic device including an inverter.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 3 is a circuit diagram illustrating a configuration of the DC / DC converter 10 including the control circuit according to the embodiment.

The DC / DC converter 10 includes a control circuit 100, an output circuit 200, and a feedback circuit 210.
The configurations of the output circuit 200 and the feedback circuit 210 are the same as those in FIG.

Hereinafter, the configuration of the control circuit 100 will be described.
The control circuit 100 is a functional IC integrated on a single semiconductor substrate. As input / output terminals, a detection terminal (SOURCE terminal), a switching terminal (DRAIN terminal), a power supply terminal (VCC terminal), a feedback terminal ( FB terminal).

One end of the detection resistor _RS is connected to the SOURCE terminal. The other end of the detection resistor _RS is grounded. The VCC terminal, a DC voltage _{V CC} generated in the second output capacitor Co2 is supplied. A feedback voltage V _FB generated by the feedback circuit 210 and corresponding to the output voltage _VOUT of the DC / DC converter 10 is input to the _{FB terminal} .

  In the present embodiment, the switching transistor M1 is integrated in the control circuit 100. The switching transistor M1 is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), its drain is connected to the DRAIN terminal, and its source is connected to the SOURCE terminal. The switching transistor M1 may be externally attached to the control circuit 100.

The control circuit 100 adjusts the switching duty ratio of the switching transistor M1 of the DC / DC converter 10 based on at least the detection voltage V _S and the feedback voltage V _FB at the SOURCE terminal, thereby adjusting the DC output voltage V _OUT to the target level. To stabilize.

  The control circuit 100 mainly includes a switching transistor M1, a pulse modulator 102, a driver 104, an oscillator 106, a mask circuit 108, and a short detection circuit 110.

The resistor R11 is provided between the SOURCE terminal and a predetermined high level voltage. When the detection resistor _RS has an open failure, the SOURCE terminal is pulled up to a high level voltage by the resistor R11. The resistor R12 is provided between the FB terminal and the high level voltage.

The pulse modulator 102 generates a pulse signal S _PWM whose duty ratio is adjusted so that the output voltage _VOUT of the DC / DC converter 10 approaches a target value. The pulse modulator 102 transitions the pulse signal S _PWM to a level (off level) corresponding to the off state of the switching transistor M1 based on the detection voltage V _S generated at the SOURCE terminal.

Immediately after the switching transistor M1 is turned on, spike-like noise is superimposed on the detection voltage V _S. In order to prevent the switching transistor M1 from being erroneously turned off by this noise, a mask circuit 108 is provided. The mask circuit 108 invalidates (masks) the change in the detection voltage V _S for a predetermined mask time immediately after the switching transistor M1 is turned on.

The driver 104 switches the switching transistor M1 based on the pulse signal _SPWM .

  The oscillator 106 oscillates at a predetermined frequency and generates a clock signal to be synchronized with each block of the control circuit 100 and / or a periodic signal of a triangular wave or a sawtooth wave.

The short detection circuit 110 compares the detection voltage V _S after a predetermined determination time τ1 has elapsed with a predetermined threshold voltage V _TH after the pulse signal S _PWM transitions to the on level. Then, a short detection signal S_SHRT that is asserted (for example, at a high level) when the detection voltage V _S is higher than the threshold voltage V _TH is generated. The determination time τ1 is set to be equal to or shorter than the maximum ON time T _{ON_MAX} of the switching transistor M1. The maximum ON time T _{ON_MAX} is a time obtained by multiplying the switching period Tp of the switching transistor M1 by the maximum duty ratio (for example, 75%) of the switching transistor M1. The determination time τ1 may be, for example, 50% of the switching period Tp.

When the short detection signal S_SHRT is asserted, the control circuit 100 stops switching of the switching transistor M1. For example, when the short detection signal S_SHRT is asserted, the pulse modulator 102 fixes the pulse signal S _PWM to an off level corresponding to the off state of the switching transistor M1.

  In addition to these configurations, the control circuit 100 includes a starter circuit 112, a clamp circuit 114, a regulator 116, a UVLO circuit 118, a current limiting circuit 120, an overvoltage protection comparator 122, a filter 124, an overload protection comparator 126, a filter 128, and a burst comparator. 130 is further provided.

The starter circuit 112 generates a start current Ic when the control circuit 100 is started, and supplies it to the second output capacitor Co2 via the VCC terminal. Thus, in a state where the switching transistor M1 is not switching, it can charge the second output capacitor Co2, can start the power supply voltage V _CC. Instead of the starter circuit 112, a pull-up resistor may be provided between the second output capacitor Co2 and the input terminal P1.

UVLO (Under Voltage Lock Out) circuit 118 compares the voltage _{V CC} of the VCC terminal with a predetermined threshold _{V UVLO.} The threshold value V _UVLO has hysteresis of 13.5V and 8.5V, for example. When V _CC > V _UVLO is detected, the _undervoltage lockout is released and the operation of the control circuit 100 starts. Regulator 116, undervoltage lockout is released, and down the power supply voltage V _CC, to produce a stabilized internal reference voltage V _REG. Each block of the control circuit 100 becomes operable when the internal reference voltage V _REG is supplied.

The clamp circuit 114 is provided to clamp the output voltage of the driver 104, that is, the high level of the gate voltage V _G of the switching transistor M1 to a predetermined level or less. By providing the clamp circuit 114, the switching transistor M1 having a low gate breakdown voltage can be used.
Further, in order to switch the switching transistor M1, where it is necessary to charge and discharge the gate capacitance of the switching transistor M1, by limiting the amplitude of the gate voltage V _G by the clamp circuit 114, reducing the charging and discharging current Thus, the power consumption of the control circuit 100 can be reduced.

Current limiting circuit 120, the detected voltage _{V S} output from the mask circuit 108 'is compared with a predetermined threshold value _{V OCP, V S'> V} overcurrent protection which is asserted (high level) when the _OCP (OCP ) The signal S_OCP is generated. When the OCP signal S_OCP is asserted, the control circuit 100 stops switching of the switching transistor M1.

Overvoltage protection comparator 122, the power supply voltage _{V CC} is compared with a predetermined threshold value _{V OVP} (e.g. 27.5 _V), V _{CC> V} overvoltage protection which is asserted (high level) when the _OVP a (OVP) signal S_OVP Generate. The OVP signal S_OVP is filtered by a filter 124 having a certain time constant (for example, 100 μs). When the state in which the OVP signal S_OVP is asserted continues for 100 μs or longer, the control circuit 100 stops switching of the switching transistor M1.

In an overload state in which the load connected to the output terminal P2 is heavy, that is, the output current is large, the output voltage _VOUT decreases and the feedback voltage _VFB increases. The overload protection comparator 126 compares the feedback voltage V _FB with the threshold value V _OLP and generates an overload protection (OLP) signal S_OLP that is asserted (high level) when V _FB > V _OLP . The OLP signal S_OLP is filtered by a filter 128 having a certain time constant (eg, 64 ms). When the state in which the OVP signal S_OLP is asserted continues for 64 ms or longer, the control circuit 100 stops switching of the switching transistor M1. Thereafter, when a predetermined time (for example, 512 ms) elapses, the control circuit 100 resumes switching of the switching transistor M1.

In a light load state where the load connected to the output terminal P2 is light, that is, the output current is small, the output voltage _VOUT increases and the feedback voltage _VFB decreases. The burst comparator 130 compares the feedback voltage V _FB with the threshold value V _BURST and generates a light load detection signal S_BURST that is asserted (high level) when V _FB <V _BURST . When the light load detection signal S_BURST is asserted, the control circuit 100 stops switching of the switching transistor M1.

FIG. 4 is a circuit diagram illustrating a configuration example of the pulse modulator 102. The pulse modulator 102 in FIG. 4 is a peak current mode modulator, and includes a compensator 140, an adder 142, a PWM comparator 144, a logic circuit 146, and an RS flip-flop 148.
The compensator 140 is a filter that filters the detection voltage V _S ′. The adder 142 superimposes the slope compensation periodic signal V _RAMP on the detection voltage V _S ′. The PWM (pulse width modulation) comparator 144 compares the feedback voltage V _FB with the detection voltage V _S ′ on which the periodic signal V _RAMP is superimposed, and a reset signal that is asserted (high level) when V _S ′> V _FB. S _RST is generated.

A set signal S _SET that is asserted (high level) every predetermined period Tp is input to the set terminal of the RS flip-flop 148, and the set signal S _SET is asserted for the pulse signal S _PWM that is an output signal thereof. Each time it transitions to the on level. The set signal S _SET may be generated by the oscillator 106 in FIG. 3 or may be generated by a logic circuit 146 synchronized with the oscillator 106.

The reset signal S _RST output from the PWM comparator 144 is input to the reset terminal of the RS flip-flop 148, and the pulse signal S _PWM transits to an off level each time the reset signal S _RST is asserted.

The maximum duty setting circuit 138 generates a maximum duty signal S_MAXDUTY that is asserted (high level) after a lapse of a predetermined maximum on-time after the pulse signal S _PWM transitions to the on-level.

Logic circuit 146 of the reset signal _{S RST} and the maximum duty signal S_MAXDUTY, resets the RS flip-flop 148 based on a signal asserted earlier. For example the output of the OR gate OR1 which generates a logic sum of the reset signal _{S RST} and the maximum duty signal S_MAXDUTY, may be input to the reset terminal of the RS flip-flop 148.

The logic circuit 146 receives the short detection signal S_SHRT. For example, when the short detection signal S_SHRT is asserted, the logic circuit 146 may fix the set signal S _SET at a low level and fix the pulse signal S _PWM at a low level.

  Further, the above-described signals S_OVP1, S_OCP, S_OLP, and S_BUSRT are input to the logic circuit 146. The logic circuit 146 executes appropriate protection processing in accordance with each signal.

FIG. 5 is a circuit diagram illustrating another configuration example of the pulse modulator 102. The pulse modulator 102 of FIG. 5 is an average current mode pulse width modulator, and includes an average circuit 150, an error amplifier 152, and a PWM comparator 154.
The error amplifier 152 generates an error voltage V _ERR obtained by amplifying and averaging the error between the detection voltage V _S ′ and the feedback voltage V _FB . The averaging circuit 150 is a filter provided for phase compensation and averaging.

The PWM comparator 154 compares the error voltage V _ERR with a triangular wave or sawtooth wave periodic signal V _OSC having a predetermined period Tp, and generates a pulse signal S _PWM according to the comparison result. The pulse modulator 102 further includes a logic circuit 146 that receives signals such as the short detection signal S_SHRT, and performs processing according to the state of each signal.

FIG. 6 is a circuit diagram showing another configuration example of the pulse modulator 102. The pulse modulator 102 in FIG. 6 is a pulse modulator in a fixed off-time mode, and includes a compensator 156, an adder 158, a PWM comparator 160, and an off-time fixed circuit 162. The compensator 156 is a filter that filters the detection voltage V _S ′. The adder 158 superimposes the slope compensation periodic signal V _RAMP on the detection voltage V _S ′. The PWM comparator 160 compares the feedback voltage V _FB with the detection voltage V _S ′ on which the periodic signal V _RAMP is superimposed, and generates an off signal S _OFF that is asserted (high level) when V _S ′> V _FB. . The off-time fixing circuit 162 generates a pulse signal S _PWM that is off-level for a predetermined off-time T _{OFF after} the off-signal S _OFF is asserted and then on-level. The configuration of the off-time fixed circuit 162 is not particularly limited, and can be configured by, for example, a one-shot multivibrator or a timer circuit.

  As shown in FIGS. 4 to 6, there are various types of pulse modulators 102, and the present invention is applicable to them. In the following, the pulse modulator 102 is shown in the peak current mode shown in FIG. 4. The explanation will be continued as it is.

  FIG. 7 is a circuit diagram showing a configuration example of the short detection circuit 110. FIG. 7 shows an oscillator 106 and a maximum duty setting circuit 138 in addition to the short detection circuit 110.

The oscillator 106 includes a capacitor C11, a constant current source CS1, a discharge switch SW1, and a comparator 168. One end of the capacitor C11 is grounded. The constant current source CS1 charges the capacitor C11 with a predetermined constant current. The comparator 168 compares the voltage V _C11 of the capacitor C11 with a predetermined threshold voltage V _MAX and generates a discharge signal S21 that is asserted when V _C11 > V _MAX . The discharge switch SW1 is provided in parallel with the capacitor C11 and is turned on when the discharge signal S21 is asserted to discharge the capacitor C11.

The discharge signal S21 is a periodic signal having a period Tp, and is used as the set signal S _SET . The voltage V _{C11 of the} capacitor C11 becomes a sawtooth signal with a period Tp.

Maximum duty setting circuit 138 includes a comparator that compares sawtooth signal V _C11 with a predetermined threshold voltage V _MAXDUTY . The maximum duty signal S_MAXDUTY becomes high level when V _C11 > V _MAXDUTY . That is, after the switching transistor M1 is turned on, it is asserted after the lapse of the maximum on-time _{TON_MAX} corresponding to the threshold voltage V _MAXDUTY .

The sawtooth wave signal V _C11 is supplied to the short detection circuit 110. The short detection circuit 110 includes a window signal generation unit 170, a switch 172, a first comparator 174, a resistor R13, and a timer latch circuit 176.

Window signal generator 170 generates a window signal S_WIN the pulse signal S _PWM is asserted after the determination time τ1 elapses from the transition to on level. Window signal generation unit 170 includes a second comparator 178, an inverter 180, and an AND gate 182. Inverter 180 inverts the reset signal _{S RST,} and generates a signal _{#S RST} the switching transistor M1 is a period asserted to turn on. The AND gate 182 generates a logical product of the output signal S_WIN ′ of the second comparator 178 and the signal #S _RST and outputs the logical product as the window signal S_WIN.

Switch 172 is, for example, a transfer gate, and receives detection voltage V _S ′ at its input terminal. A window signal S_WIN is input to the control terminal of the switch 172, and the window signal S_WIN is turned on while the window signal S_WIN is asserted. The first comparator 174 compares the voltage output from the output terminal of the switch 172 with a predetermined threshold voltage _VTH . Output signal _{S CMP} of the first comparator 174 is asserted (high level) in short-circuit state of the detection resistor _{R S.}

The resistor R13 pulls up the potential Vi of the output terminal of the switch 172 to a high level voltage. Thus, when the switch 172 is off, the potential Vi of the inverting input terminal of the first comparator 174 is pulled up to a high level voltage, the output signal _{S CMP} of the first comparator 174 is negated.

The timer latch circuit 176, when a predetermined period .tau.2, assertion of the output signal _{S CMP} of the first comparator 174 is continuously detected, and asserts the short-circuit detection signal S_SHRT, latches the value. The period τ2 is set to 100 μs, for example. From another perspective, the timer latch circuit 176, a predetermined number of times, when the assertion of the output signal S _CMP of the first comparator 174 is continuously is detected, asserts a short-circuit detection signal S_SHRT, latches the value .
When the switching cycle of the switching transistor M1 is Tp = 15 μs (65 kHz) and the assertion of the short detection signal S_SHRT is detected continuously over 6 to 7 cycles, the short detection signal S_SHRT is asserted.

The timer latch circuit 176 includes a first flip-flop 184, a second flip-flop 186, an inverter 188, and a delay inverter 190.
The input terminal of the first flip-flop 184 (D), a high level voltage is input, to the clock signal, the output signal _{S CMP} of the first comparator 174 is inputted. The pulse signal S _PWM ′ that has passed through the inverter 188 and the delay inverter 190 is input to the reset terminal (inverted logic) of the first flip-flop 184. The pulse signal S _PWM ′ is a signal obtained by delaying the pulse signal S _PWM .
The output signal Q1 of the first flip-flop 184 is input to the input terminal (D) of the second flip-flop 186, and the pulse signal #S _PWM inverted by the inverter 188 is input to its clock terminal. The timer circuit 192 asserts the short detection signal S_SHRT (high level) when the output signal Q2 of the second flip-flop 186 continuously becomes high level for a predetermined period τ2.

The above is the configuration of the control circuit 100. Subsequently, the operation will be described separately depending on whether or not the detection resistor _RS is short-circuited.

FIG. 8 is an operation waveform diagram when the detection resistor _RS is not short-circuited in the control circuit 100 of FIG. When the set signal S _SET is asserted at time t0, the pulse signal S _PWM is turned on, the switching transistor M1 is turned on, and the coil current Ip starts to flow. At the same time, the detection voltage V _S ′ increases with a constant slope.
When the reset signal _SRST is asserted at time t1, the pulse signal _SPWM is turned off, the switching transistor M1 is turned off, and the coil current Ip becomes zero. When the set signal S _SET is asserted at time t2, the switching transistor M1 is turned on. The control circuit 100 repeats the operation from time t0 to t2.

In the operation state of FIG. 8, the reset signal _SRST is asserted before the determination time τ1 elapses after the switching transistor M1 is turned on. Therefore, the window signal S_WIN is not asserted, and the switch 172 remains off. As a result, the potential Vi of the inverting input terminal of the first comparator 174 remains high voltage, thus the output signal S _CMP of the first comparator 174 is not asserted.

FIG. 9 is an operation waveform diagram when the detection resistor _RS is short-circuited in the control circuit 100 of FIG.
When the set signal S _SET is asserted at time t0, the pulse signal S _PWM is turned on, the switching transistor M1 is turned on, and the coil current Ip starts to flow. Since the detection resistor _RS is short-circuited, the detection voltage V _S ′ does not rise, and therefore the reset signal S _RST is not asserted, and the switching transistor M1 continues to be turned on.
Thereafter, if the maximum duty signal S_MAXDUTY is asserted at time t4, the reset signal _{S RST} is asserted, the switching transistor M1 is turned off. When the detection resistor _RS is short-circuited in this way, the switching transistor M1 switches at the maximum duty ratio.

When the window signal S_WIN is asserted after the determination time τ1 has elapsed from time t0, the switch 172 is turned on, and the voltage Vi at the inverting input terminal of the first comparator 174 becomes equal to the detection voltage V _S ′. In this _{case, Vi <V TH (V S} '<V TH) because of an output signal _{S CMP} of the first comparator 174 is asserted.

While detection resistor _{R S} is short, the output signal _{S CMP} of the first comparator 174 is periodically asserted. When this state continues for a period τ2, switching of the switching transistor M1 is stopped, and the circuit is protected.

When the plug is removed from the outlet and the supply of the _AC voltage VAC is stopped, the control circuit 100 is initialized and the previous short detection signal S_SHRT is also erased. Thereafter, an AC voltage _{V AC} is supplied again, the control circuit 100 is activated. At this time, if the short-circuit abnormality of the detection resistor _RS is resolved, the control circuit 100 operates normally. If the short circuit abnormality continues, the short circuit detection signal S_SHRT is asserted again to protect the circuit.

  FIG. 10 is an operation waveform diagram of the timer latch circuit 176 of FIG. According to the timer latch circuit 176, it is possible to detect that a short abnormality has occurred continuously for a period τ2.

  As described above, according to the control circuit 100 according to the embodiment, it is possible to improve the reliability with respect to the short-circuit of the detection resistor. The above is the operation of the control circuit 100 and the DC / DC converter 10. Next, the use of the DC / DC converter 10 will be described.

  The DC / DC converter 10 can be suitably used for the inverter (power supply device) 1 shown in FIG. And the inverter 1 is utilized suitably for the power supply block of an AC adapter or an electronic device.

FIG. 11 is a diagram illustrating an AC adapter 800 including the inverter 1. The AC adapter 800 includes a plug 802, a housing 804, and a connector 806. Plug 802 is subjected to a commercial AC voltage _{V AC} from the wall outlet (not shown). The inverter 1 is mounted in the housing 804. The DC output voltage V _OUT generated by the inverter 1 is supplied from the connector 806 to the electronic device 810. Examples of the electronic device 810 include a notebook PC, a digital camera, a digital video camera, a mobile phone, and a mobile audio player.

12A and 12B are diagrams illustrating an electronic device 900 including the inverter 1. FIG. Although the electronic device 900 in FIGS. 12A and 12B is a display device, the type of the electronic device 900 is not particularly limited. I just need it.
Plug 902, receives a commercial AC voltage _{V AC} from the wall outlet (not shown). The inverter 1 is mounted in the housing 804. The DC output voltage V _OUT generated by the inverter 1 is supplied to loads such as a microcomputer, a DSP (Digital Signal Processor), a power supply circuit, a lighting device, an analog circuit, and a digital circuit mounted in the same housing 904. .

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

The configuration of the short detection circuit 110 is not limited to that of FIG. 7, and other configurations may be used. For example, a sample hold circuit may be used instead of the switch 172 and the resistor R13. Further, by omitting the timer latch circuit 176, it may be used an output signal _{S CMP} of the first comparator 174 as the short detection signal S_SHRT.

  In the embodiment, circuits that measure time, such as the window signal generation unit 170 and the maximum duty setting circuit 138, are configured to compare the sawtooth wave signal obtained by charging and discharging the capacitor with the threshold voltage. The present invention is not so limited. For example, these circuits may be constituted by a timer circuit that counts clock signals.

  In the embodiment, the case where the shunt regulator (error amplifier) 212 is provided on the secondary side of the transformer T1 has been described. However, this error amplifier may be provided on the primary side, and further incorporated in the control circuit 100. May be.

  As already described, the pulse modulator 102 may be in an average current mode or a fixed off-time mode instead of the peak current mode.

  The circuit described in the embodiment is configured by a positive logic (high active) system in which each signal is asserted at a high level and a negate is allocated at a low level, but may be configured by a negative logic system, You may comprise combining a positive logic system and a negative logic system.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

P1 ... input terminal, P2 ... output terminal, Co1 ... first output capacitor, Co2 ... second output capacitor, D1 ... first diode, D2 ... second diode, T1 ... transformer, W1 ... primary winding, W2 ... 2 winding, W3 ... auxiliary winding, M1 ... switching transistors, R S _... detection resistor, 1 ... inverter, 2 ... fuse, Ci ... input capacitor, 4 ... filter, 6 ... diode rectifier, Cs ... smoothing capacitor, 10 ... DC / DC converter, 100 ... control circuit, 200 ... output circuit, 210 ... feedback circuit, 212 ... shunt regulator, 214 ... photocoupler, 102 ... pulse modulator, 104 ... driver, 106 ... oscillator, 108 ... mask circuit, 110 ... Short detection circuit 112 ... Starter circuit 114 ... Clamp circuit 116 ... Regi 118 ... UVLO circuit, 120 ... current limiting circuit, 122 ... overvoltage protection comparator, 124 ... filter, 126 ... overload 102 protection comparator, 128 ... filter, 130 ... burst comparator, 138 ... maximum duty setting circuit, 140 ... compensation 142 ... adder, 144 ... PWM comparator, 146 ... logic circuit, 148 ... RS flip-flop, 150 ... average circuit, 152 ... error amplifier, 154 ... PWM comparator, 156 ... compensator, 158 ... adder, 160 ... PWM comparator 162 ... off time fixing circuit 170 ... window signal generation unit 172 ... switch 174 ... first comparator 176 ... timer latch circuit 178 ... second comparator 180 ... inverter 182 ... AND gate 184 ... First Flip-flop, 186 ... second flip-flop, 188 ... inverter, 190 ... delay inverter, 192 ... timer circuit, 800 ... AC adapter, 802 ... plug, 804 ... housing, 806 ... connector, 810, 900 ... electronic equipment, 902 ... Plug, 904 ... Case.

Claims (18)

A control circuit for a DC / DC converter having a transformer and a switching transistor provided on a current path of a primary winding of the transformer,
A detection terminal for connecting the other end of an external detection resistor provided on the current path of the primary winding and having one end grounded;
A feedback terminal for receiving a feedback voltage corresponding to the output voltage of the DC / DC converter;
A pulse modulator that generates a pulse signal whose duty ratio is adjusted so that an output voltage of the DC / DC converter approaches a target value, and the pulse signal is switched based on a detection voltage generated at the detection terminal. A pulse modulator that transitions to an off level corresponding to the transistor off;
A driver for switching the switching transistor based on the pulse signal;
The detected voltage is compared with a predetermined threshold voltage after the determination time has elapsed since the pulse signal transited to the on level corresponding to the on state of the switching transistor, and is asserted when the detected voltage is higher A short detection circuit for generating a short detection signal;
With
When the short detection signal is asserted, the control circuit stops switching of the switching transistor. The short detection circuit includes:
A window signal generation unit that generates a window signal that is asserted after a determination time has elapsed since the pulse signal transitioned to an on level;
A switch that is turned on during a period in which the detection voltage is input to the input terminal and the window signal is asserted;
A first comparator that compares a voltage output from the output terminal of the switch with a predetermined threshold voltage;
The control circuit according to claim 1, wherein the short detection signal is generated according to a comparison result of the first comparator. The window signal generation unit includes a second comparator that compares a periodic signal of a triangular wave or a sawtooth wave with a threshold voltage corresponding to the determination time,
The control circuit according to claim 2, wherein a window signal is generated according to a comparison result of the second comparator.   The window signal generation unit further includes an AND gate that generates a logical product of a signal that is asserted while the switching transistor is on and an output signal of the second comparator, and the output of the AND gate is the window signal. The control circuit according to claim 3, wherein:   The short detection circuit further includes a timer latch circuit that asserts the short detection signal when the assertion of the output signal of the first comparator is detected continuously for a predetermined time or a predetermined number of times. The control circuit according to 2.   6. The control circuit according to claim 1, wherein the pulse modulator is a peak current mode pulse width modulator. The pulse modulator is
A pulse width modulation comparator that compares the detected voltage superimposed with a periodic signal for slope compensation with the feedback voltage and generates a reset signal that is asserted when the detected voltage increases;
The reset signal and a set signal that is asserted every predetermined period are received, and when the reset signal is asserted, the first level is transitioned, and when the set signal is asserted, the second level is transitioned. An RS flip-flop that generates a pulse signal;
The control circuit according to claim 6, further comprising:   6. The control circuit according to claim 1, wherein the pulse modulator is an average current mode pulse width modulator. The pulse modulator is
An error amplifier that generates an error voltage obtained by amplifying and averaging an error between the detection voltage and the feedback voltage;
A pulse width modulation comparator that compares the error voltage with a periodic signal of a triangular wave or a sawtooth wave having a predetermined period, and generates the pulse signal according to a comparison result;
The control circuit according to claim 8, comprising:   The control circuit according to claim 1, wherein the pulse modulator is a pulse modulator in a fixed off-time mode. The pulse modulator is
A pulse width modulation comparator that compares the detection voltage superimposed with a periodic signal for slope compensation with the feedback voltage and generates an off signal that is asserted when the detection voltage becomes high;
The off time is fixed to generate the pulse signal that becomes an off level corresponding to the switching transistor being turned off for a predetermined off time after the off signal is asserted, and then becomes an on level corresponding to the turning on of the switching transistor. Circuit,
The control circuit according to claim 10, comprising:   The control circuit according to claim 1, wherein the control circuit is integrated on a single semiconductor substrate. A transformer having a primary winding and a secondary winding;
A switching transistor connected to the primary winding of the transformer;
A first diode having an anode connected to the secondary winding;
A first output capacitor having one end grounded and the other end connected to the cathode of the first diode;
A feedback circuit for generating a feedback voltage according to an output voltage generated in the first output capacitor;
The control circuit according to any one of claims 1 to 12, which receives the feedback voltage and switches the switching transistor;
A DC / DC converter comprising: The feedback circuit includes:
A shunt regulator that generates a feedback signal whose level is adjusted so that an error between a voltage obtained by dividing the output voltage and a predetermined target value becomes zero;
A photocoupler whose light-emitting element on the primary side is controlled by the feedback signal;
14. The DC / DC converter according to claim 13, wherein a signal generated in a light receiving element on the secondary side of the photocoupler is supplied to the control circuit as the feedback voltage. The transformer further has an auxiliary winding provided on the primary side thereof,
The DC / DC converter is
A second diode having an anode connected to the auxiliary winding;
A second output capacitor having one end grounded and the other end connected to the cathode of the second diode;
Further comprising
The DC / DC converter according to claim 13 or 14, wherein a DC voltage generated in the second output capacitor is supplied to a power supply terminal of the control circuit. A filter for filtering commercial AC voltage;
A diode rectifier circuit for full-wave rectification of the output voltage of the filter;
A smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage;
The DC / DC converter according to any one of claims 13 to 15, wherein the DC input voltage is stepped down and supplied to a load.
A power supply apparatus comprising: Load,
A filter for filtering commercial AC voltage;
A diode rectifier circuit for full-wave rectification of the output voltage of the filter;
A smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage;
The DC / DC converter according to any one of claims 13 to 15, wherein the DC input voltage is stepped down and supplied to the load.
An electronic device comprising: A filter for filtering commercial AC voltage;
A diode rectifier circuit for full-wave rectification of the output voltage of the filter;
A smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage;
The DC / DC converter according to any one of claims 13 to 15, wherein the DC input voltage is stepped down to generate a DC output voltage.
A power adapter comprising:

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