JP2013150229A - Source follower circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a source follower circuit which can reduce distortion of input/output characteristics without requiring a complicated control circuit or sacrificing characteristics of an input/output transistor.SOLUTION: A source follower circuit comprises: a first constant current circuit; a second constant current circuit configured to have a current dependent on a current flowing in the first constant current circuit; and an input/output transistor connected such that a current from the second constant current circuit flows between a source and a drain. In the input/output transistor, an input voltage is applied to a gate electrode, and an output voltage is output from a source region. The first constant current circuit is configured to have a current controlled dependently on the output voltage.

Description

  The present disclosure relates to a source follower circuit.

Conventionally, a source follower circuit has been used as a circuit constituting a level shifter, a buffer, or the like (see, for example, Non-Patent Document 1). As shown in FIG. 7A, the source follower circuit having a configuration in which the nonlinearity of the input / output characteristics is relaxed is applied to the current source (constant current circuit) CS and the input voltage (input signal) applied to the gate electrode. Accordingly, the input / output transistor Q _{p_out} is configured to output an output voltage (output signal) from the source region. Reference sign V _DD represents, for example, a high potential power supply voltage, and reference sign V _SS represents, for example, a low potential power supply voltage. In the following description, the input / output transistor Q _{p_out} is a p-channel field effect transistor (for example, PMOS), but this is merely an example.

Here, the input voltage is _expressed as V _in (= V _g ), the output voltage is _expressed as V _out , and the potential difference (that is, the source-gate voltage) between the source region and the gate electrode of the input / output transistor Q _{p_out} is expressed as V _sg. . In an ideal source follower circuit, if the current is constant, the relationship of output voltage V _out = V _in −V _sg is maintained.

However, for example, a problem in constructing a circuit excellent in power supply voltage fluctuation rejection ratio (PSRR) is the source-drain conductance g _sd (= di _sd / dv _sd ) in the input / output transistor Q _{p_out} . It is an influence.

In an ideal transistor, conductance g _sd = 0. Therefore, when the input / output transistor Q _{p_out} is an ideal transistor, the input / output transistor Q _{p_out} is driven to cause the drain current I _ds to flow according to the following equation (1). still,
μ: effective mobility L: channel length W: channel width V _th : threshold voltage C _ox : (relative permittivity of gate insulating layer) × (dielectric constant of vacuum) / (thickness of gate insulating layer)
β≡μ · C _ox · (W / L)
And

I _ds = (1/2) · β · (V _sg −V _th ) ² (1)

On the other hand, in an actual transistor, the value of conductance g _sd is not zero. Accordingly, as shown in an equivalent circuit model in dashed (A) in FIG. 7, the resistance _{r o (= 1 / g sd} ) is the source of the input and output transistor Q _{p_out} - are connected in parallel between the drain It becomes composition.

In the actual source follower circuit, the input / output transistor Q _{p_out} is driven so as to flow the drain current I _ds according to the following equation (2). The conductance g _sd is given by the following equation (3). still,
V _sd : Potential difference between the source region and the drain region λ: Channel length modulation coefficient.

I _ds = (1/2) · β · (V _sg −V _th ) ² · (1 + λ · V _sd )
= (1/2) · β · (V _sg −V _th ) ² +
(1/2) · β · (V _sg- V _th ) ² · λ · V _sd (2)

g _sd = (1/2) · β · (V _sg −V _th ) ² · λ (3)

Here, (1/2) · β · (V _sg −V _th ) ² , which is the first term of the equation (2), corresponds to the current I ₁ shown in FIG. (1/2) · β · (V _sg −V _th ) ² · λ · V _sd corresponds to the current I ₂ shown in FIG.

When the input / output transistor Q _{p_out} is an n-channel field effect transistor (for example, NMOS), the connection is changed as appropriate and V _sd → V _ds , V _sg → V _gs, etc. Good.

R. Jacob Baker, "CMOS Circuit Design, Layout, and Simulation" Revised Second Edition, 2008, IEEE Press, A John Wiley & Sons, Inc., Publication, Chapter 21.2.4, P.690

In actual source follower circuit shown in FIG. 7 (A), the value of V _sd is changed according to the value of the input voltage V _in, the value of the second term in the above equation (2) changes due to this . Therefore, the drain current I _ds , and hence the source-gate voltage V _sg , changes depending on the input voltage V _in , and finally causes distortion in the input / output characteristics of the source follower circuit. In order to cope with the distortion of the input / output characteristics, the channel length of the input / output transistor is set longer than usual to reduce the g _sd of the input / output transistor, or, for example, (B as shown in), methods such suppressing variation of V _sd by using a control circuit such controlling the drain-side potential of the output transistor Q _{p_out} input voltage V _in the level shifted signal is considered. However, the former has a problem that the characteristics (for example, mutual conductance g _m ) of the input / output transistor is sacrificed, and the latter has a problem that the circuit configuration becomes complicated because the number of elements increases.

  Accordingly, an object of the present disclosure is to provide a source follower circuit that does not require a complicated control circuit and that does not sacrifice the characteristics of the input / output transistor and can reduce distortion of the input / output characteristics. There is.

In order to achieve the above object, the source follower circuit of the present disclosure is:
A first constant current circuit;
A second constant current circuit configured to flow a current corresponding to a current flowing through the first constant current circuit; and
An input / output transistor connected so that a current from the second constant current circuit flows between the source and drain, an input voltage applied to the gate electrode, and an output voltage output from the source region;
With
The first constant current circuit is a source follower circuit configured to control a current value that flows in accordance with an output voltage value.

  The source follower circuit of the present disclosure includes a first constant current circuit, a second constant current circuit configured to flow a current corresponding to a current flowing through the first constant current circuit, and a second constant current circuit. An input / output transistor is connected so that a current from a current circuit flows between the source and the drain, an input voltage is applied to the gate electrode, and an output voltage is output from the source region. The first constant current circuit is configured such that the current value flowing according to the value of the output voltage is controlled. Therefore, it is not necessary to have a complicated circuit configuration, and the characteristics of the input / output transistor are not sacrificed.

FIG. 1 is a circuit diagram of a source follower circuit according to the first embodiment. FIG. 2 is a circuit diagram of a source follower circuit of a reference example. FIG. 3 is a circuit diagram of a source follower circuit according to a modification of the first embodiment. FIG. 4 is a circuit diagram of a circuit including a source follower circuit of a reference example. FIG. 5 is a circuit diagram of a circuit including the source follower circuit according to the first embodiment. FIG. 6 is a schematic circuit diagram of a D / A converter including the source follower circuit according to the first embodiment. FIG. 7A is a schematic circuit diagram of a source follower circuit. FIG. 7B is a schematic circuit diagram of a source follower circuit including a control circuit.

Hereinafter, the present disclosure will be described based on embodiments with reference to the drawings. The present disclosure is not limited to the embodiments, and various numerical values and materials in the embodiments are examples. In the following description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted. The description will be given in the following order.
1. 1. General description of the source follower circuit according to the present disclosure First Embodiment 3 Application examples

[General description of the source follower circuit according to the present disclosure]
In the source follower circuit according to the present disclosure,
The first constant current circuit is composed of a current mirror circuit,
The output voltage output from the input / output transistor can be fed back to the current control node of the current mirror circuit.

In this case, the first constant current circuit includes a first transistor connected to the current source and a second transistor connected to the second constant current circuit,
An output voltage output from the input / output transistor can be fed back to a current control node formed by connecting the current control terminal of the first transistor and the current control terminal of the second transistor.

  The type of the first transistor and the second transistor is not particularly limited, and may be a configuration including a bipolar transistor or a configuration including a field effect transistor such as a MOS. From the standpoint of circuit integration, the first transistor and the second transistor are preferably composed of field effect transistors.

  The type of the current source to which the first transistor is connected is not particularly limited, and a known current source (constant current circuit) can be used.

  In the source follower circuit according to the present disclosure including the above-described various preferable configurations including the first constant current circuit configured from the current mirror circuit, the adjustment element for adjusting the feedback amount of the output voltage May be connected between the current control node and the source region of the input / output transistor.

  As the adjustment element, for example, a known active element or passive element can be used. From the standpoint of cost reduction and the like, the adjustment element is preferably configured by a resistance element. The configuration of the resistance element is not particularly limited. For example, a pure resistance element such as a chip resistor can be used, or, for example, a MOS transistor can be operated in a deep triode region and used as a resistance element.

  In the source follower circuit according to the present disclosure including the above-described various preferable configurations in which the first constant current circuit includes the first transistor and the second transistor, the second constant current circuit includes the first constant current circuit. The current mirror circuit may include a third transistor connected to the second transistor and a fourth transistor connected to the input / output transistor.

  Similar to the first transistor and the second transistor, the types of the third transistor and the fourth transistor are not particularly limited, and may be a bipolar transistor or a field effect transistor such as a MOS transistor. There may be. From the standpoint of circuit integration, the third transistor and the fourth transistor are preferably composed of field effect transistors.

  In particular, a configuration in which the first to fourth transistors are field effect transistors is preferable because all of the transistors constituting the source follower circuit are formed of field effect transistors, so that the circuit can be integrated.

  Examples of circuit configurations and systems suitable for using the source follower circuit of the present disclosure include: 1. A circuit that does not need to have a wide band but requires a low distortion of input / output characteristics (for example, an output stage of a low-band amplifier); 2. A circuit in which the input / output voltage does not fluctuate very much but the PSRR characteristic is important (for example, a level shifter or an output buffer in a BIAS circuit). It is possible to increase the circuit that wants to keep current consumption and occupied area small.

  The various conditions shown in this specification are satisfied not only when they are strictly established but also when they are substantially satisfied. The presence of various variations in design or manufacturing is allowed.

[First Embodiment]
The first embodiment relates to a source follower circuit according to the present disclosure.

  FIG. 1 is a circuit diagram of a source follower circuit according to the first embodiment.

The source follower circuit 1 includes a first constant current circuit MC ₁ , a second constant current circuit MC ₂ configured so that a current having a value corresponding to a current flowing through the first constant current circuit MC ₁ flows, and , a second current source from the constant current circuit MC ₂ - is connected to flow between the drain, the input voltage V _in is applied to the gate electrode, output transistor to the output voltage V _out from the source region is output Q _{p_out} is provided. The first constant current circuit MC ₁ is configured such that the value of the flowing current is controlled according to the value of the output voltage V _out . In the example shown in the figure, the input / output transistor Q _{p_out} is composed of a p-channel field effect transistor such as PMOS.

The first constant current circuit MC ₁ is composed of a current mirror circuit, and the output voltage V _out output from the input / output transistor Q _{p_out} is fed back to the current control node ND ₁ of the current mirror circuit.

More specifically, the first constant current circuit MC ₁ includes a first transistor Q _{n_1} connected to the current source CS ₁ and a second transistor Q _{n_2} connected to the _second constant current circuit MC _2. wherein, the current control node ND ₁ the current control terminal of the first transistor Q _{n_1} and the current control terminal of the second transistor Q _{n_2,} which are connected, the output voltage V _out output from the input transistor Q _{p_out} feedback Is done.

The first transistor Q _{n_1} and the second transistor Q _{n_2} are field effect transistors. In the example shown in the figure, these are composed of n-channel field effect transistors such as NMOS, for example, and the gate electrode corresponds to the current control terminal. The first transistor Q _{n_1} and the second transistor Q _{n_2} are enhancement type, and the first transistor Q _{n_1} operates in a saturation region because it is diode-connected. Then, the first transistor Q _{n_1} and second transistors Q _{n_2} gate of the same value - because the source voltage is applied, a current having the same value as the current flowing through the first transistor Q _{n_1} flows through the second transistor Q _{n_2.}

An adjustment element R _f for adjusting the feedback amount of the output voltage V _out is connected between the current control node ND ₁ and the source region of the input / output transistor Q _{p_out} . The adjustment element R _f is composed of a resistance element.

The second constant current circuit MC ₂ includes a third transistor Q _{p_3} connected to the second transistor Q _{n_2} constituting the _first constant current circuit MC ₁ and a fourth transistor connected to the input / output transistor Q _{p_out.} Q _{p_4} and a current mirror circuit.

The third transistor Q _{p_3} and the fourth transistor Q _{p_4} are field effect transistors. In the example shown in the figure, these are composed of p-channel field effect transistors such as PMOS. The gate electrode of the third transistor Q _{p_3 and} the gate electrode of the fourth transistor Q _{p_4} are connected to form a current mirror circuit.

The drain region of the fourth transistor Q _{p_4} is connected to the source region of the input / output transistor Q _{p_out} . The source region of the fourth transistor Q _{P_4} high potential power supply voltage V _DD is applied, a low potential power supply voltage V _SS is applied to the drain region of the output transistor Q _{p_out.}

The third transistor Q _{p_3} and the fourth transistor Q _{p_4} are enhancement type, and the third transistor Q _{p_3} operates in a saturation region because it is diode-connected. Since the same source-gate voltage is applied to the third transistor Q _{p_3} and the fourth transistor Q _{p_4} , as a result, a current having the same value as the current flowing through the first transistor Q _{n_1} is applied to the fourth transistor Q _{p_4.} Flowing into.

Here, in order to help understanding of the present disclosure, the operation of the source follower circuit of the reference example in which the adjustment element _Rf illustrated in FIG. 1 is omitted will be described.

FIG. 2 shows a circuit diagram of the source follower circuit 1 ′ of the reference example. The input voltage is V _in (= V _g ), the output voltage is V _out , the potential difference between the source region and the gate electrode of the input / output transistor Q _{p_out} (ie, source-gate voltage) is V _sg , and the threshold voltage is V _th and drain current are represented as I _ds ′. In the source follower circuit 1 ′ shown in FIG. 2, the output voltage V _out from the input / output transistor Q _{p_out} is expressed by the following equation (4). However,
μ: effective mobility L: channel length W: channel width V _th : threshold voltage C _ox : (relative permittivity of gate insulating layer) × (dielectric constant of vacuum) / (thickness of gate insulating layer)
β≡μ · C _ox · (W / L)
_ro : 1 / g _sd
And

V _out = V _in −V _sg
= V _in − ((2 × I _ds ' / β) ^1/2 + V _th )
= V _in − ((2 × (I _ds ′ −V _sd × g _sd ) / β) ^1/2 + V _th ) (4)

Here, the second term in the above equation (4), (in other words [V _sd / r _o]) from the drain current _{I ds' [V sd × g} sd] the current flowing through the such resistance component r _o is reduced This causes distortion in the input / output characteristics.

Therefore, in the present disclosure, the current mirror circuit is controlled so as to compensate for the influence of the current represented by [V _sd × g _sd ] subtracted from the drain current I _ds ′.

In the source follower circuit 1 shown in FIG. 1, the output voltage V _out is, via the adjustment element R _f, it is fed back first to the current control node ND ₁ of the constant current circuit MC _1.

Therefore, the output when the voltage V _out increases, the amount of current flowing through the first constant current circuit MC ₁ is increased. When the output voltage V _out is lowered, the amount of current flowing through the first constant current circuit MC ₁ is reduced.

Since the second constant current circuit MC ₂ is configured such that a current having a value corresponding to the current flowing in the first constant current circuit MC ₁ flows, as a result, the drain current I flowing in the input / output transistor Q _{p_out. ds} increases the output voltage V _out increases, the output voltage V _out decreases to be lower.

Therefore, if indicated the amount of change in drain current due to the feedback of the output voltage V _out in [Delta] I, the drain current I _ds in the source follower circuit 1 shown in FIG. 1, 'the drain current I _ds of the' source follower circuit 1 shown in FIG. 2 Is represented by the following formula (5). Further, the output voltage V _out of the source follower circuit 1 shown in FIG. 1 is expressed by the following equation (6).

I _ds = I _ds ' + ΔI (5)

V _out = V _in −V _sg
= V _in − ((2 × I _ds ' / β) ^1/2 + V _th )
= V _in − ((2 × (I _ds ′ −V _sd × g _sd + ΔI) / β) ^1/2 + V _th ) (6)

The effect of reducing [V _sd × g _sd ] in the second term of equation (6) is compensated by adding ΔI. The relationship between ΔI and the adjustment element R _f is expressed by the following equation (7). However,
Ai: Miller ratio g _m : Mutual conductance of the diode-connected first transistor Q _{n_1} .

ΔI≈ (Ai−1) · V _sd / (R _f + 1 / g _m ) (7)

Therefore, basically, the resistance value of the adjustment element R _f may be set so as to satisfy g _sd ≈ (Ai−1) / (R _f + 1 / g _m ).

  As described above, according to the source follower circuit of the present disclosure, the distortion of the input / output characteristics of the source follower circuit is reduced by controlling the first constant current circuit according to the value of the output voltage. Further, the circuit configuration is not complicated, and the characteristics of the input / output transistor are not sacrificed.

  In the above-described example, the input / output transistor is described as a p-channel field effect transistor. However, an n-channel field effect transistor may be used. A circuit having this configuration is shown in FIG.

The source follower circuit 1A shown in FIG. 3 also has a first constant current circuit MC ₁ and a second constant current circuit MC configured such that a current having a value corresponding to the current flowing through the first constant current circuit MC ₁ flows. _2, and a second current from the constant current circuit MC ₂ source - input which is connected to flow between the drain, the input voltage V _in is applied to the gate electrode, the output voltage V _out from the source region is output An output transistor Q _{n_out} is provided. The first constant current circuit MC ₁ is configured such that the value of the flowing current is controlled according to the value of the output voltage V _out . The transistor Q _{n_out} is _composed of an n-channel field effect transistor such as NMOS.

The first constant current circuit MC ₁ is composed of a current mirror circuit, and the output voltage V _out output from the input / output transistor Q _{n_out} is fed back to the current control node ND ₁ of the current mirror circuit.

The first constant current circuit MC ₁ includes a first transistor Q _{p_1} connected to the current source CS ₁ and a second transistor Q _{p_2} connected to the second constant current circuit MC _2. to the current control node ND ₁ the current control terminal of _{p_1} and the current control terminal of the second transistor Q _{p_2} is formed by connecting the output voltage V _out output from the input transistor Q _{N_out} is fed back.

The first transistor Q _{p_1} and the second transistor Q _{p_2} are field effect transistors. In the example shown in the figure, these are composed of p-channel field effect transistors such as PMOS, and the gate electrode corresponds to the current control terminal. The first transistor Q _{p_1} and the second transistor Q _{p_2} are enhancement type, and the first transistor Q _{p_1} operates in a saturation region because it is diode-connected. Then, the first transistor Q _{p_1} and second transistors Q _{p_2} source of the same value - because the gate voltage is applied, a current having the same value as the current flowing through the first transistor Q _{p_1} flows through the second transistor Q _{p_2.}

An adjustment element R _f for adjusting the feedback amount of the output voltage V _out is connected between the current control node ND ₁ and the source region of the input / output transistor Q _{n_out} . The adjustment element R _f is composed of a resistance element.

The second constant current circuit MC ₂ includes a third transistor Q _{n_3} connected to the second transistor Q _{p_2} constituting the _first constant current circuit MC ₁ and a fourth transistor connected to the input / output transistor Q _{n_out. And} a current mirror circuit including Q _{n — 4} .

The third transistor Q _{n —} 3 and the fourth transistor Q _{n —} 4 are field effect transistors. In the example shown in the figure, these are composed of n-channel field effect transistors such as NMOS. The gate electrode of the third transistor Q _{n_3 and} the gate electrode of the fourth transistor Q _{n_4} are connected to form a current mirror circuit.

The drain region of the fourth transistor Q _{n_4} is connected to the source region of the input / output transistor Q _{n_out} . The low potential power supply voltage V _SS is applied to the source region of the fourth transistor Q _{n_4} , and the high potential power supply voltage V _DD is applied to the drain region of the input / output transistor Q _{n_out} .

The third transistor Q _{n —} 3 and the fourth transistor Q _{n —} 4 are enhancement type, and the third transistor Q _{n —} 3 operates in a saturation region because it is diode-connected. Since the same gate-source voltage is applied to the third transistor Q _{n_3} and the fourth transistor Q _{n_4} , as a result, a current having the same value as the current flowing through the first transistor Q _{p_1} is applied to the fourth transistor Q _{n_4.} Flowing into.

The operation of the source follower circuit 1A shown in FIG. 3 is not described because it can be appropriately read as V _sd → V _ds , V _sg → V _gs etc. in the description with reference to FIG.

  Next, an application example using the source follower circuit of the present disclosure will be described. First, in order to help understanding of the invention, a problem of an application example using the source follower circuit of the reference example shown in FIG. 2 will be described.

  FIG. 4 is a circuit diagram of a circuit including a source follower circuit of a reference example.

In this circuit, the voltage V ₁ from the previous circuit comprising the diode-connected transistors Q _p1 and Q _p2 and the current source CS is input to the gate electrode of the input / output transistor Q _{P_out} of the source follower circuit 1 ′. Applied. The output voltage V ₂ of the source follower circuit 1 ′ is applied to the gate electrode of the _subsequent input / output transistor Q _{P_out2} as the input voltage of the circuit composed of the resistor R _out and the _subsequent input / output transistor Q _{P_out2.} . Then, the output voltage V _out is output from the source region of the input / output transistor Q _{P_out2 at} the _subsequent stage.

As described above, in the source follower circuit 1 ′ included in this circuit, the input / output characteristics of the input / output transistor Q _{p_out} are dependent on V _sd . Therefore, for example, when a fluctuation similar to the fluctuation of the high-potential power supply voltage V _DD occurs in the voltage V ₁ , the fluctuation amount of the voltage V ₂ applied to the gate of the input / output transistor Q _{P_out2 in} the _subsequent stage and the voltage V ₁ It is not the same as the fluctuation amount.

As a result, a difference occurs between the fluctuation of the high-potential power supply voltage V _{DD and} the fluctuation of the voltage V ₂ , and the power supply voltage fluctuation rejection ratio (PSRR) of the output voltage V _out is deteriorated.

On the other hand, in the circuit including the source follower circuit 1 according to the first embodiment shown in FIG. 5, the dependency due to V _sd of the input / output characteristics of the input / output transistor Q _{p_out} is reduced.

Accordingly, the fluctuation of the high-potential power supply voltage V _DD is substantially equal to the fluctuation of the voltage V ₂ , and the power supply voltage fluctuation rejection ratio (PSRR) of the output voltage V _out is improved.

  Next, another application example using the source follower circuit of the present disclosure will be described.

  FIG. 6 is a schematic circuit diagram of a D / A converter including the source follower circuit according to the first embodiment.

Symbol OP ₁ is an operational amplifier, symbols Tr ₁ , Tr ₂ ..., Tr _(N) are transistors, symbols R _A , R _B and R _C are resistors, and symbols BF ₁ , BF ₂ and BF ₃ are inverting buffers.

  This D / A converter generates an output voltage by switching the current of the current source by turning on / off the switch. In this circuit, the changeover switch is used as a cascode in addition to the switch operation.

  Therefore, although the low level of the switch is normally lowered to the GND level, it is raised to a predetermined potential here. The source follower circuit 1 is used as a buffer for generating a low level of the predetermined potential.

  In such an application, it is necessary to secure a driving capability for maintaining a low level of a predetermined potential, a low PSRR characteristic for becoming a cascode gate voltage, and a compact source follower circuit itself. The source follower circuit 1 is used as a circuit that satisfies such requirements.

  The embodiment of the present disclosure has been specifically described above, but is not limited to the above-described embodiment of the present disclosure, and various modifications based on the technical idea of the present invention are possible.

In addition, the technique of this indication can also take the following structures.
(1) a first constant current circuit;
A second constant current circuit configured to flow a current corresponding to a current flowing through the first constant current circuit; and
An input / output transistor connected so that a current from the second constant current circuit flows between the source and drain, an input voltage applied to the gate electrode, and an output voltage output from the source region;
With
The first constant current circuit is a source follower circuit configured to control a current value flowing according to an output voltage value.
(2) The first constant current circuit is composed of a current mirror circuit,
The source follower circuit according to (1), wherein the output voltage output from the input / output transistor is fed back to the current control node of the current mirror circuit.
(3) The current mirror circuit includes a first transistor connected to the current source and a second transistor connected to the second constant current circuit,
The source follower circuit according to (2), wherein the output voltage output from the input / output transistor is fed back to a current control node formed by connecting the current control terminal of the first transistor and the current control terminal of the second transistor. .
(4) The source follower circuit according to (3), wherein the first transistor and the second transistor are field effect transistors.
(5) The adjustment element for adjusting the feedback amount of the output voltage is connected between the current control node and the source region of the input / output transistor, according to any one of (2) to (4) above Source follower circuit.
(6) The source follower circuit according to (5), wherein the adjustment element is a resistance element.
(7) The second constant current circuit includes a third transistor connected to the second transistor that constitutes the first constant current circuit, and a current mirror circuit including a fourth transistor connected to the input / output transistor. The source follower circuit according to any one of (3) to (6), which is configured.
(8) The source follower circuit according to (7), wherein the third transistor and the fourth transistor are field effect transistors.

1, 1 ', 1A ... Source follower circuit, CS, CS ₁ ... Current source, MC ₁ ... First constant current circuit, MC ₂ ... Second constant current circuit, _{Qn_1} , Q _{p_1} ... 1st transistor, Q _{n_2} , Q _{p_2} ... 2nd transistor, Q _{n_3} , Q _{p_3} ... 3rd transistor, Q _{n_4} , Q _{p_4} ... 4th transistor, Q _{n_out} , Q _{p_out} ... I / O transistor, V _in ... input voltage, V _out ... output voltage, OP ₁ ... operational amplifier, Tr ₁ , Tr ₂ ..., Tr _(N) ... transistor, R _A , R _B , R _C ... Resistors, BF ₁ , BF ₂ , BF _3.

Claims (8)

A first constant current circuit;
A second constant current circuit configured to flow a current corresponding to a current flowing through the first constant current circuit; and
An input / output transistor connected so that a current from the second constant current circuit flows between the source and drain, an input voltage applied to the gate electrode, and an output voltage output from the source region;
With
The first constant current circuit is a source follower circuit configured to control a current value flowing according to an output voltage value. The first constant current circuit is composed of a current mirror circuit,
The source follower circuit according to claim 1, wherein an output voltage output from the input / output transistor is fed back to a current control node of the current mirror circuit. The first constant current circuit includes a first transistor connected to the current source, and a second transistor connected to the second constant current circuit,
3. The source follower circuit according to claim 2, wherein the output voltage output from the input / output transistor is fed back to a current control node formed by connecting the current control terminal of the first transistor and the current control terminal of the second transistor.   4. The source follower circuit according to claim 3, wherein the first transistor and the second transistor are field effect transistors.   4. The source follower circuit according to claim 3, wherein an adjustment element for adjusting the feedback amount of the output voltage is connected between the current control node and the source region of the input / output transistor.   The source follower circuit according to claim 5, wherein the adjustment element includes a resistance element.   The second constant current circuit includes a current mirror circuit including a third transistor connected to the second transistor constituting the first constant current circuit and a fourth transistor connected to the input / output transistor. The source follower circuit according to claim 3.   The source follower circuit according to claim 7, wherein the third transistor and the fourth transistor are field effect transistors.

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