JP2013143610A - Solid state imaging element, method for manufacturing the same, solid state imaging device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging element preventing light from a slit formed around a pixel part with its structural necessity from entering a semiconductor substrate to prevent deterioration of image quality due to disturbance of a black level caused by the light from the slit, which is likely to occur as a chip size is reduced.SOLUTION: A solid state imaging element includes: a pixel part in which a plurality of sensors for generating signal charges by photoelectric conversion are arranged on a semiconductor substrate; an optical black part as a portion of the pixel part, in which the sensor outputs a signal to be a reference of a black level; a first light-shielding film provided on the pixel part so as to cover at least the optical black part of the pixel part; a wiring part having a wiring layer provided around the pixel part so as to be spaced from the first light-shielding film via a slit-like gap; and a second light-shielding film provided so as to cover the slit-like gap against the semiconductor substrate .

Description

  The present technology relates to a solid-state imaging device having an optical black portion that outputs a signal serving as a reference for a black level in an imaging portion in which a plurality of pixels are arranged, a method for manufacturing the solid-state imaging device, a solid-state imaging device, and an electronic apparatus.

  2. Description of the Related Art Conventionally, in a solid-state imaging device typified by a charge coupled device (CCD) type or a complementary metal oxide semiconductor (CMOS) type, an optical black portion (hereinafter referred to as “OB”) is provided as a pixel region in which a plurality of pixels are arranged. There is a technique for providing a part. The OB portion is a region that outputs a signal that serves as a reference for the black level in order to define the black level with respect to the effective pixel portion that outputs the signal charge as an effective pixel signal in the pixel portion. For this reason, the pixels arranged in the OB portion are shielded from light, and signals from the shielded pixels are used as a reference for the black level.

  The OB portion is generally provided around the effective pixel portion in the pixel portion. That is, the OB portion is provided at the end portion of the pixel portion with respect to the effective pixel portion constituting the main portion of the pixel portion. On the OB portion, as described above, a light shielding film for shielding light from the pixels arranged in the OB portion is provided. The light shielding film is provided so as to cover the peripheral portion of the pixel portion including the OB portion with respect to the pixel portion.

  On the other hand, some solid-state imaging devices are provided with a wiring portion in which a plurality of wirings are arranged around the pixel portion. For example, in a CCD solid-state imaging device, the wiring arranged in the wiring unit supplies a clock pulse as a drive voltage to the transfer electrode of the charge transfer unit that transfers the signal charge generated in each pixel of the pixel unit. Wiring (bus line). For example, the wiring is formed of a metal film or the like as a layer structure of the same layer as the electrode pad arranged in the peripheral region in the solid-state imaging device. As the wiring provided in the wiring part, a plurality of wirings according to the number of phases such as four-phase driving and eight-phase driving for driving the charge transfer part are arranged around the pixel part along the region of the pixel part. (For example, refer to Patent Document 1).

  Further, in the solid-state imaging device, there is a technique for providing an invalid area in the pixel portion. The invalid region is a dummy region provided to stabilize the resist shape when using a photolithography technique in an ion implantation process or an opening process of the pixel portion, or a wiring that sends a driving voltage from the wiring portion to the pixel portion. This is an area necessary for image output, or an area unnecessary for outputting an image. The invalid area is provided at the peripheral portion of the pixel portion. As described above, in the configuration in which the pixel portion includes the OB portion, the invalid region is provided outside the OB portion, and is shielded by a light shielding film that shields the OB portion.

  The light shielding film provided on the pixel portion for shielding the OB portion and the wiring of the wiring portion provided around the pixel portion have the same laminated structure in the laminated structure of the solid-state imaging device or substantially the same layer positions. Provided. The light shielding film and the wiring in the pixel portion are at different potentials. Specifically, the light shielding film in the pixel portion is at the ground potential, whereas the wiring in the wiring portion is applied with a driving voltage for driving the charge transfer portion.

  Thus, there is a gap for insulating between the light shielding film of the pixel portion and the wiring portion of the wiring portion, which have different potentials. The gap between the light shielding film and the wiring exists as a slit along the pixel portion region in the configuration in which the wiring is disposed along the pixel portion region as described above. In addition, a slit similar to that between the light shielding film and the wiring also exists between the plurality of wirings provided as the same layer portion in the wiring portion. The slit between the light shielding film and the wiring and the slit between the wiring are, for example, a portion where an insulating film or the like is present and a portion through which light is transmitted, and is present as an unshielded region.

JP 2002-76322 A

  In recent years, in order to meet the demand for cost reduction, reduction of the chip size of the solid-state image sensor has been demanded, and the solid-state image sensor has actually been downsized. In order to reduce the chip size, the distance between the pixel portion and the wiring portion is reduced, that is, the invalid region because the invalid region is an unnecessary region when outputting an image as described above. It is an effective way to reduce the size. In this regard, the recent improvement in photolithography technology has made it possible to reduce the area necessary for resist shape stability compared to the prior art, and the area of the wiring portion accompanying the reduction in the line width of the wiring. Since the reduction is possible, the invalid area can be reduced or eliminated.

  By reducing or eliminating the ineffective area, the positions of the slit between the light shielding film and the wiring and the slit between the wiring as described above approach the pixel portion. For this reason, the phenomenon that the light incident from these slits affects the image quality occurs.

  Specifically, when incident light with respect to the solid-state image sensor enters from the slit, electrons are generated by photoelectric conversion in a semiconductor substrate mainly made of silicon (Si) under the slit. The electrons generated by the incident light from the slit may move by diffusion in the semiconductor substrate and reach the pixel portion, particularly the OB portion close to the wiring portion side where the slit is formed.

  Disturbance of the black level such that when electrons generated by the incident light from the slit flow into the OB portion, which is a region for defining the black level reference signal, the black level reference signal is output more than the original signal amount. As a result, image quality deterioration called black sink occurs. Such image quality degradation due to the incident light from the slit has not been a problem in the past when a sufficient distance from the slit to the pixel portion was ensured. However, since the position of the slit approaches the pixel portion due to the recent chip size reduction, the electrons generated by the incident light from the slit easily reach the OB portion, and there is a great concern about the image quality deterioration due to the incident light from the slit. Become.

  The purpose of this technology is to prevent light from the slits formed around the pixel area from entering the semiconductor substrate due to the structure, and to make it easier to occur as the chip size is reduced. It is an object to provide a solid-state imaging device, a manufacturing method of the solid-state imaging device, a solid-state imaging device, and an electronic apparatus that can prevent deterioration in image quality due to black level disturbance caused by light.

  A solid-state imaging device according to an embodiment of the present technology includes a pixel unit in which a plurality of sensor units that generate signal charges by photoelectric conversion are arranged on a semiconductor substrate, a part of the pixel unit, and a reference of a black level by the sensor unit. An optical black portion that outputs a signal, a first light shielding film that is provided on the pixel portion and covers at least the optical black portion of the pixel portion, and is provided around the pixel portion, and the first light shielding portion. A wiring portion having a wiring layer provided with a slit-like space between the film and a second light-shielding film provided in a state of covering the slit-like space with respect to the semiconductor substrate; It is.

  In the solid-state imaging device according to the present technology, it is preferable that the second light shielding film includes a pixel portion region portion that covers the pixel portion, and extends from the pixel portion region portion to the outside of the pixel portion. And a peripheral portion that covers the slit-like interval together with the partial region portion.

  In the solid-state imaging device according to the present technology, preferably, the second light shielding film is provided as a lower layer with respect to the first light shielding film, and allows light to enter the sensor unit. A light shielding film having an opening.

  Moreover, in the solid-state imaging device according to the present technology, it is preferable that the wiring layer includes a plurality of wirings provided as slits between each other as the same layer portion, and the second light shielding. The film is provided in a state of covering the slit-like spacing between the plurality of wirings with respect to the semiconductor substrate.

  In the method for manufacturing a solid-state imaging device according to an embodiment of the present technology, an opening that allows light to enter the sensor unit is provided on a pixel unit in which a plurality of sensor units that generate signal charges by photoelectric conversion are arranged on a semiconductor substrate. A step of forming a lower-layer light-shielding film, and an upper-layer light-shielding film that covers, as an upper layer of the lower-layer light-shielding film, an optical black portion that outputs at least a signal serving as a reference for a black level by the sensor unit, Forming a wiring layer having a slit-like space between the upper layer light shielding film and the upper layer light shielding film around the pixel portion as the same layer portion, and the step of forming the lower light shielding film includes the lower layer light shielding The lower light-shielding film is formed so that the film covers the slit-like interval.

  A solid-state imaging device according to an embodiment of the present technology includes a solid-state imaging device and a driving unit that generates a driving signal for driving the solid-state imaging device, and the solid-state imaging device generates a signal by photoelectric conversion on a semiconductor substrate. A pixel unit that arranges a plurality of sensor units that generate electric charges, an optical black unit that is a part of the pixel unit, and that outputs a signal serving as a reference for a black level by the sensor unit, and the pixel unit are provided on the pixel unit A wiring layer provided at a periphery of the pixel portion and with a slit-like space between the first light shielding film covering at least the optical black portion of the pixel portion and the first light shielding film. And a second light shielding film provided in a state of covering the slit-like interval with respect to the semiconductor substrate.

  An electronic apparatus according to the present technology includes a solid-state imaging device, an optical system that guides incident light to a sensor unit of the solid-state imaging device, a drive circuit that generates a drive signal for driving the solid-state imaging device, and the solid-state imaging A signal processing circuit that processes an output signal of the element, and the solid-state imaging device includes a pixel unit that arranges a plurality of sensor units that generate signal charges by photoelectric conversion on a semiconductor substrate, and one of the pixel units. An optical black portion that outputs a signal serving as a black level reference by the sensor portion, a first light-shielding film that is provided on the pixel portion and covers at least the optical black portion of the pixel portion, and A wiring portion provided around the pixel portion and having a wiring layer provided with a slit-like spacing between the first light-shielding film and the slit-like spacing with respect to the semiconductor substrate; A second light shielding film provided in a state of Tsu, those comprising a.

  According to the present technology, the light from the slit formed around the pixel portion can be prevented from entering the semiconductor substrate due to the structure, and the incidence from the slit is likely to occur as the chip size is reduced. It is possible to prevent image quality deterioration due to black level disturbance caused by light.

The figure which shows the whole structure of the solid-state image sensor which concerns on one Embodiment of this technique. FIG. 3 is a cross-sectional view illustrating a configuration of a solid-state imaging element according to an embodiment of the present technology. The top view which shows a part of structure of the solid-state image sensor which concerns on one Embodiment of this technique. A-A 'sectional view in FIG. The top view which shows the solid-state image sensor of the comparative example with respect to this technique. B-B 'sectional drawing in FIG. The top view which shows the solid-state image sensor of the other comparative example with respect to this technique. Sectional drawing which shows the modification of the solid-state image sensor which concerns on one Embodiment of this technique. Sectional drawing which shows the other modification of the solid-state image sensor which concerns on one Embodiment of this technique. Explanatory drawing about the manufacturing method of the solid-state image sensor which concerns on one Embodiment of this technique. The figure which shows the structure of the solid-state imaging device which concerns on one Embodiment of this technique. The figure which shows the structure of the electronic device which concerns on one Embodiment of this technique.

  In the configuration in which the slit-like interval is formed around the pixel unit in relation to the wiring unit provided around the pixel unit, the present technology covers the slit-like interval with a light-shielding film so that the incident light from the slit Therefore, the image quality is not deteriorated due to the black level disturbance caused by the image quality. Hereinafter, embodiments of the present technology will be described.

[Configuration of solid-state image sensor]
An overall configuration of a solid-state imaging device according to an embodiment of the present technology will be described with reference to FIG. As shown in FIG. 1, a solid-state imaging device 1 according to this embodiment is a CCD solid-state imaging device (image sensor), and includes a pixel unit 2 that is a rectangular pixel region formed on a semiconductor substrate. Have. The solid-state imaging device 1 includes a plurality of sensor units 3 in the pixel unit 2.

  The pixel unit 2 has a plurality of sensor units 3 arranged on a semiconductor substrate. The plurality of sensor units 3 are arranged in a matrix in the pixel unit 2 provided on the semiconductor substrate. That is, the plurality of sensor units 3 are arranged in a two-dimensional matrix in the vertical and horizontal directions along the rectangular pixel unit 2. In the solid-state imaging device 1 of the present embodiment, in FIG. 1, the vertical direction (up and down direction) is the vertical direction, and the horizontal direction (left and right direction) is the horizontal direction.

  The sensor unit 3 is a light receiving unit that receives incident light with respect to the solid-state imaging device 1 and generates a signal charge by photoelectric conversion. In the present embodiment, the sensor unit 3 includes a photodiode as a light receiving element, and generates and accumulates signal charges by photoelectric conversion. That is, the sensor unit 3 has a light receiving surface, generates a signal charge corresponding to the light amount (intensity) of light incident on the light receiving surface, and accumulates the generated signal charge. Each sensor unit 3 constitutes each pixel 7 in the pixel unit 2. Therefore, the plurality of pixels 7 included in the solid-state imaging device 1 each have the sensor unit 3 and are arranged in a matrix in the pixel unit 2.

  The solid-state imaging device 1 includes a plurality of vertical transfer units 4 and a horizontal transfer unit 5 as charge transfer units that transfer signal charges generated by the sensor unit 3. The vertical transfer unit 4 is provided along a line in each column direction (vertical direction) in the matrix-like two-dimensional array of the plurality of sensor units 3. That is, as shown in FIG. 1, the plurality of vertical transfer units 4 are arranged on one side of each column (left side in FIG. 1) for each column aligned in the vertical direction of the plurality of sensor units 3 arranged in a matrix. The sensor units 3 are provided in parallel with each other along the vertical direction of the sensor unit 3.

  The signal charges generated by the sensor unit 3 are read out to the vertical transfer unit 4 and transferred in the vertical direction by the vertical transfer unit 4. The signal charge in the sensor unit 3 is read to the vertical transfer unit 4 via the reading unit 6. The vertical transfer unit 4 reads out each of the plurality of sensor units 3 arranged in the corresponding column, that is, the sensor units 3 of the plurality of sensor units 3 arranged adjacent to one side in the horizontal direction (right side in FIG. 1). The signal charges are read out via, and the read signal charges are sequentially transferred in the vertical direction.

  The reading unit 6 is provided between the sensor unit 3 and the vertical transfer unit 4 from which the signal charges generated by the sensor unit 3 are read on the semiconductor substrate, and the signal charges generated by the sensor unit 3 are transferred to the vertical transfer unit. 4 functions as a reading gate. The reading unit 6 varies the potential (potential) when the reading electrode included in the transfer electrode constituting the vertical transfer unit 4 receives a voltage (clock pulse) for reading, and is generated and stored in the sensor unit 3. The signal charge thus transferred is transferred to the vertical transfer unit 4.

  Further, a channel stop is provided between the sensor unit 3 and the vertical transfer unit 4 on the side (non-reading side) opposite to the side on which the reading unit 6 of the sensor unit 3 is provided. The channel stop forms a potential serving as a barrier with the vertical transfer unit 4 on the non-reading side (right side in FIG. 1) of the sensor unit 3, thereby non-reading the signal charge accumulated in the sensor unit 3. Restrict movement to

  The horizontal transfer unit 5 transfers the signal charges transferred by the plurality of vertical transfer units 4 in the horizontal direction. The horizontal transfer unit 5 is provided on one end side (lower side in FIG. 1) of the plurality of vertical transfer units 4 arranged in parallel with each other along the vertical direction of the sensor unit 3, and is a rectangular pixel unit 2 is arranged along a horizontal side on one side in the vertical direction (lower side in FIG. 1). Therefore, the signal charge read from the sensor unit 3 to the vertical transfer unit 4 is transferred in the vertical direction by the vertical transfer unit 4 toward the horizontal transfer unit 5 (lower side in FIG. 1).

  The signal charges transferred by the vertical transfer unit 4 and the horizontal transfer unit 5 are output from the output unit 8 provided on the end side of the horizontal transfer unit 5. The output unit 8 functions as a charge-voltage conversion unit that converts signal charge into voltage, and converts the signal charge transferred from the horizontal transfer unit 5 into an electric signal by an output amplifier such as a FD (Floating Diffusion) amplifier and outputs the electric signal. .

  The solid-state imaging device 1 of the present embodiment will be described in more detail with reference to FIGS. FIG. 2 is a cross-sectional view in which the plane perpendicular to the signal charge transfer direction by the vertical transfer unit 4 is the cross-sectional direction.

  As shown in FIG. 2, the solid-state imaging device 1 includes a semiconductor substrate 10. The semiconductor substrate 10 is an N-type silicon semiconductor substrate that is a first conductivity type. A semiconductor layer 12 is formed on the surface layer side of the semiconductor substrate 10. Therefore, the semiconductor substrate 10 has the semiconductor layer 12 on the substrate layer 11 which is an N-type silicon substrate portion.

  The semiconductor layer 12 is a P-type impurity region which is a second conductivity type with respect to the substrate layer 11 which is an N-type silicon semiconductor substrate. That is, the semiconductor layer 12 is a P-well region formed by ion implantation. In the semiconductor layer 12, the sensor units 3 arranged in a matrix as described above are provided.

  In a portion on the surface layer side of the semiconductor substrate 10, a vertical transfer unit 4 (see FIG. 1) is configured between the sensor units 3 adjacent in the horizontal direction. As shown in FIG. 2, the vertical transfer unit 4 (see FIG. 1) includes a vertical transfer register 13 provided in the semiconductor layer 12 of the semiconductor substrate 10 and a transfer electrode 14 provided on the semiconductor substrate 10, that is, on the semiconductor layer 12. And have. The vertical transfer unit 4 having a CCD structure is configured by the configuration including the vertical transfer register 13 and the transfer electrode 14.

  The vertical transfer registers 13 are provided in a row along the vertical direction between the sensor units 3 adjacent in the horizontal direction in the semiconductor layer 12. That is, the vertical transfer register 13 is provided for each column in the array of the plurality of sensor units 3 on the semiconductor substrate 10. The vertical transfer register 13 is formed as a transfer channel region that is an N-type impurity region, for example. The vertical transfer register 13 applies a drive voltage to the transfer electrode 14 that constitutes the vertical transfer unit 4, thereby moving the well of the potential where charges are accumulated along the transfer electrode 14, thereby causing the sensor unit 3 to move. The signal charge read from is transferred.

  The transfer electrode 14 receives the drive voltage as described above, thereby changing the potential of the portion of the vertical transfer register 13 forming the potential well. The transfer electrode 14 is provided on the vertical transfer register 13 via an insulating film or the like. The transfer electrode 14 is made of, for example, polycrystalline silicon. In the present embodiment, the vertical transfer unit 4 is driven by a four-phase drive pulse. For this reason, the vertical transfer unit 4 has four types of transfer electrodes 14 corresponding to four-phase driving. Specifically, the four types of transfer electrodes 14 are electrodes to which voltages of four-phase clock pulses φV1, φV2, φV3, and φV4 as drive voltages input from the outside are independently applied. These four types of transfer electrodes 14 are provided so as to be repeatedly arranged in a predetermined order for every two pixels 7 in the vertical direction.

  By appropriately controlling the magnitude and timing of the four-phase clock pulse applied to each transfer electrode 14 of the vertical transfer unit 4, the signal charge read from each sensor unit 3 to the vertical transfer unit 4 is Transfer is performed according to the arrangement of the electrodes of the vertical transfer unit 4. The vertical transfer unit 4 is not limited to four-phase driving, and may be eight-phase driving, for example.

  As shown in FIG. 3, in the solid-state imaging device 1, a wiring unit 15 is provided around the pixel unit 2. The wiring portion 15 is provided with a wiring layer 16 for supplying a clock pulse as a drive voltage to the transfer electrode 14 of the vertical transfer portion 4. In the configuration in which four-phase clock pulses φV1, φV2, φV3, and φV4 are applied as drive voltages to the transfer electrode 14 as in the present embodiment, the wiring layer 16 has four-phase clock pulses φV1, φV2, A clock pulse of either φV3 or φV4 is supplied. For this reason, the wiring layer 16 includes four wirings (bus lines) 17 corresponding to the clock pulses φV1, φV2, φV3, and φV4.

  As shown in FIG. 3, the wiring layer 16 surrounds the pixel unit 2 from three sides other than the side where the horizontal transfer unit 5 is provided (the lower side in FIG. 3) with respect to the rectangular pixel unit 2. These are arranged in the vertical direction and the horizontal direction along the region of the pixel unit 2. The four wirings 17 of the wiring layer 16 are arranged in a substantially concentric rectangular shape with the pixel unit 2 side on the inside so that portions along the three sides of the rectangular pixel unit 2 are parallel to each other. Arranged in state. The wiring layer 16 is made of a metal material such as tungsten (W) or aluminum (Al). In FIG. 3, the four wirings 17 are denoted by “17A”, “17B”, “17C”, and “17D” in order from the innermost side (pixel unit 2 side) to the outer side.

  As shown in FIG. 1, in the present embodiment, the horizontal transfer unit 5 is driven by a two-phase drive pulse. For this reason, the horizontal transfer unit 5 has two types of transfer electrodes corresponding to two-phase driving. Two-phase clock pulses φH1 and φH2 as drive voltages are input to the two types of transfer electrodes constituting the horizontal transfer unit 5 from the outside. By appropriately controlling the magnitude and timing of the two-phase clock pulses φH1 and φH2, the horizontal transfer unit 5 transfers the signal charges transferred in the vertical direction in the vertical transfer unit 4 in the horizontal direction. Note that the horizontal transfer unit 5 is not limited to two-phase driving, and may be, for example, three-phase driving or four-phase driving.

  Further, as shown in FIG. 2, in the portion on the surface layer side of the semiconductor substrate 10, between the sensor unit 3 and the vertical transfer register 13 from which the signal charge of the sensor unit 3 is read, the above-described readout unit (FIG. 1 and reading unit 6). Further, in the surface layer side portion of the semiconductor substrate 10, the above-described channel stop is provided on the side (non-reading side) opposite to the side where the reading unit is provided with respect to the sensor unit 3.

  On the semiconductor substrate 10, a light shielding film 20 is provided on the transfer electrode 14 via an interlayer insulating film provided so as to cover the transfer electrode 14. The light shielding film 20 is provided so as to cover the transfer electrode 14 provided on the semiconductor substrate 10 via an interlayer insulating film. The light shielding film 20 is made of a metal material such as tungsten (W) or aluminum (Al).

  As shown in FIG. 2, the light shielding film 20 has an opening 20 a at a position corresponding to the sensor unit 3. The light shielding film 20 is provided on a region excluding the region where the sensor unit 3 is provided, with the opening 20 a positioned in the region where the sensor unit 3 is provided on the semiconductor substrate 10. The light shielding film 20 is formed in a substantially gate shape so as to straddle between the sensor portions 3 adjacent in the horizontal direction in the cross-sectional view shown in FIG. The light shielding film 20 is provided along a boundary portion between adjacent sensor units 3 and is formed in a lattice shape in plan view.

An insulating film 21 is provided on the entire surface of the semiconductor substrate 10 so as to cover the light shielding film 20. The insulating film 21 is formed of, for example, an organic coating film such as an acrylic resin, a silicon oxide film (SiO ₂ film), or the like.

  Further, as shown in FIG. 2, a color filter layer 22 is provided on the insulating film 21 via a passivation film or the like. The color filter layer 22 is divided into a plurality of color filters 23 provided corresponding to each pixel 7 constituted by the sensor unit 3. In the present embodiment, each color filter 23 is a filter portion of any color of red (R), green (G), and blue (B), and transmits light of each color component.

  On the color filter layer 22, a planarizing film 24 made of, for example, an acrylic thermosetting resin is formed. A plurality of microlenses 25 are provided on the planarizing film 24. The micro lens 25 is a so-called on-chip micro lens, and is formed for each pixel 7 corresponding to the sensor unit 3 of each pixel 7. Therefore, the plurality of microlenses 25 are arranged in a matrix on a plane like the sensor unit 3.

  The microlens 25 collects incident light from the outside on the sensor unit 3 of the corresponding pixel 7. The light condensed by the microlens 25 enters the sensor unit 3 through the opening 20 a of the light shielding film 20 provided above the sensor unit 3. The microlens 25 is made of an inorganic material such as SiN (silicon nitride), for example.

  As shown in FIG. 4, in the solid-state imaging device 1, a light shielding film 30 is provided on the pixel unit 2. As shown in FIG. 4, the light shielding film 30 is provided in the layer portion of the insulating film 21 in the layer structure of the solid-state imaging device 1. Therefore, in the solid-state imaging device 1 of the present embodiment, the light shielding film 20 provided so as to cover the transfer electrode 14 is a lower light shielding film and the light shielding film 30 is an upper light shielding film as described above. The light shielding film 30 is made of a metal material such as tungsten (W) or aluminum (Al).

  As shown in FIG. 4, the light shielding film 30 is provided in the same hierarchical structure or at substantially the same layer position with respect to the wiring layer 16 provided around the pixel unit 2 in the stacked structure of the solid-state imaging device 1. . Therefore, the wiring layer 16 is provided on the layer portion of the insulating film 21 on the semiconductor substrate 10 like the light shielding film 30. In the present embodiment, the light shielding film 30 that is the upper layer light shielding film has the same layer structure as that of the wiring layer 16 and is made of the material of the wiring layer 16.

  The light shielding film 30 and the wiring layer 16 have different potentials. Specifically, while the light shielding film 30 is at the ground potential, the wiring layer 16 is applied with a clock pulse as a driving voltage for driving the charge transfer unit as described above. As shown in FIG. 4, there is a gap for insulating between the light shielding film 30 and the wiring layer 16 having different potentials as described above.

  A gap between the light shielding film 30 and the wiring layer 16 is a gap between the innermost wiring 17 </ b> A (pixel side 2) of the four wirings 17 formed in the wiring layer 16 and the light shielding film 30. . As described above, the gap between the light shielding film 30 and the wiring layer 16 is a slit (reference numeral 35) along the region of the pixel unit 2 in the configuration in which the wiring layer 16 is disposed along the region of the pixel unit 2. Reference) exists. In the following description, the slit-like interval between the light shielding film 30 and the wiring layer 16 is referred to as “light shielding film-wiring slit 35”.

The light shielding film 30 and the wiring layer 16 that form the light shielding film-wiring slit 35 are provided in the insulating film 21. For this reason, the portion of the slit 35 between the light shielding film and the wiring is a portion where an organic coating film such as an acrylic resin, a silicon oxide film (SiO ₂ film), or the like exists, and is a portion that transmits light. As described above, in the solid-state imaging device 1 of the present embodiment, the wiring portion 15 is provided around the pixel portion 2, and the light-shielding film-wiring slit 35 that is a slit-like space between the light-shielding film 30 is provided. A wiring layer 16 is provided separately.

  In addition, a slit-like interval similar to that between the light shielding film 30 and the wiring layer 16 exists between the four wirings 17 provided as the same layer portion in the wiring portion 15. Specifically, from the inside, between the wiring 17A and the wiring 17B, between the wiring 17B and the wiring 17C, and between the wiring 17C and the wiring 17D, a slit-like shape that follows the region of the pixel portion 2 is formed. There is an interval (see 36). In the following description, the slit-like interval between these adjacent wirings 17 is referred to as “inter-wiring slit 36”.

In the configuration having the four wirings 17 in the wiring layer 16 as in the present embodiment, the inter-wiring slits 36 exist at three locations. Similar to the light shielding film-inter-wiring slit 35, these inter-wiring slits 36 are portions where an organic coating film such as acrylic resin, a silicon oxide film (SiO ₂ film), or the like exists, and are portions that transmit light. .

  As shown in FIG. 3, the solid-state imaging device 1 of the present embodiment includes an optical black portion (hereinafter referred to as “OB portion”) 40 in the pixel portion 2. The OB unit 40 is a part of the pixel unit 2 and is an optical black region in which the sensor unit 3 outputs a signal serving as a black level reference. That is, as shown in FIG. 3, the pixel unit 2 includes an effective pixel unit 41 that outputs the signal charge obtained in the sensor unit 3 as an effective pixel signal, and the signal charge obtained in the sensor unit 3 at a black level. And an OB unit 40 that outputs as a reference.

  The pixels 7 arranged in the OB section 40 are shielded from light, and the signal from the shielded pixels 7 is used as a reference for the black level. In the solid-state imaging device 1 of the present embodiment, the OB portion 40 is covered with a two-layer light shielding film including a light shielding film 20 as a lower light shielding film and a light shielding film 30 as an upper light shielding film. Therefore, the light shielding film 30 that forms the light shielding film-wiring slit 35 together with the wiring 17 </ b> A of the wiring layer 16 is provided on the pixel portion 2 and is provided so as to cover at least the OB portion 40 of the pixel portion 2.

  The OB unit 40 is generally provided around the effective pixel unit 41 in the pixel unit 2. That is, the OB unit 40 is provided at an end portion of the pixel unit 2 with respect to the effective pixel unit 41 constituting the main portion of the pixel unit 2. In the present embodiment, as shown in FIG. 3, the OB unit 40 is provided in the pixel unit 2 so as to surround the effective pixel unit 41 along the rectangular pixel unit 2.

  In the pixel unit 2, an invalid area 42 is provided outside the OB unit 40. In the example illustrated in FIG. 3, the invalid area 42 extends along three sides other than the side where the horizontal transfer unit 5 is provided (the lower side in FIG. 3) with respect to the rectangular pixel unit 2, similar to the wiring layer 16. It is provided as a region. The invalid region 42 is a dummy region provided to stabilize the resist shape when using a photolithography technique in an ion implantation process, an opening process, or the like of the pixel unit 2, or driving from the wiring unit 15 to the pixel unit 2. It may be an area necessary for wiring to send voltage. As shown in FIG. 3, the invalid region 42 is provided as a region on the outer edge of the pixel unit 2.

  As described above, in the solid-state imaging device 1 of the present embodiment, of the two layers of light shielding films provided on the pixel unit 2, the upper light shielding film 30 is provided corresponding to the OB unit 40 and the invalid area 42. It functions as a first light shielding film that covers at least the OB portion 40 of the pixel portion 2. Similarly, of the two light shielding films, the lower light shielding film 20 is provided as a lower layer with respect to the light shielding film 30, and has a second opening 20 a that allows light to enter the sensor unit 3. Functions as a light shielding film.

  In the present embodiment, the upper light shielding film 30 is provided so as to cover the peripheral portion of the pixel portion 2, which is the OB portion 40 and the invalid region 42, whereas the lower light shielding film 20 includes the effective pixel portion 41. It is provided so as to cover the entire pixel portion 2. In the following description, the upper light shielding film 30 as the first light shielding film is referred to as “upper light shielding film 30”, and the lower light shielding film 20 as the second light shielding film is referred to as “lower light shielding film 20”.

  In the solid-state imaging device 1 of the present embodiment, the OB unit 40 is provided so as to surround the four sides of the effective pixel unit 41 in the pixel unit 2, but is not limited thereto, and the effective pixel unit of the pixel unit 2 is not limited thereto. It may be provided in another manner around 41. For example, the OB unit 40 may be provided on one side or both ends of the effective pixel unit 41 in the left-right direction (horizontal direction) in FIG. Further, the upper light shielding film 30 is not limited to the case where the upper light shielding film 30 is provided on the OB portion 40 and the invalid region 42, and a light incident path to the sensor unit 3 arranged in the effective pixel unit 41 in the pixel unit 2 is secured. As long as the predetermined area is shielded from light, it may be provided.

  Like the solid-state imaging device 1 of the present embodiment having the above-described configuration, there are a light-shielding film-wiring slit 35 between the pixel portion 2 and the wiring portion 15 and an inter-wiring slit 36 of the wiring portion 15. In the configuration, incident light (see arrow X1 in FIG. 4) to the solid-state image sensor enters from the light shielding film-wiring slit 35 and the wiring slit 36. When light incident from the light shielding film-interwiring slit 35 and the interwiring slit 36 is incident on the semiconductor substrate 10 below the slit, electrons are generated in the semiconductor substrate 10 by photoelectric conversion.

  When the electrons generated in the semiconductor substrate 10 move through the semiconductor substrate 10 by diffusion and flow into the OB portion 40, the black level is disturbed and the image quality deterioration called black sink occurs. Such deterioration of image quality due to incident light from the slit has not been a problem in the past when a sufficient distance from the slit to the pixel portion 2 has been secured. However, since the position of the slit approaches the pixel unit 2 due to the recent chip size reduction, electrons generated by the incident light from the slit can easily reach the OB unit 40, and there is a concern about image quality deterioration due to the incident light from the slit. Becomes larger.

  Therefore, in the solid-state imaging device 1 of the present embodiment, the lower-layer light-shielding film 20 as the second light-shielding film is provided in a state where the semiconductor substrate 10 covers the light-shielding film-wiring slit 35. As shown in FIG. 4, the lower light shielding film 20 is a layer positioned below the insulating film 21 with respect to the layer structure that forms the upper light shielding film 30 and the wiring layer 16. The lower light shielding film 20 is provided between the upper light shielding film 30 of the pixel unit 2 and the wiring layer 16 (wiring 17A) of the wiring unit 15 by extending from the pixel unit 2 to the wiring unit 15 side. The light shielding film-wiring slit 35 is provided so as to cover the lower side.

  That is, the lower light shielding film 20 is provided in a state of being overlapped with the light shielding film-wiring slit 35 formed thereabove. In other words, the lower-layer light-shielding film 20 has the light-shielding film-wiring slit 35 viewed from the upper side (upper side in FIG. 4), and the lower-side light-shielding film 20 side of the lower-layer light-shielding film 20 on the wiring portion 15 side. It is provided that there are overlapping extensions.

  Therefore, in the solid-state imaging device 1 of the present embodiment, the lower-layer light-shielding film 20 includes the pixel portion region portion 20A that covers the pixel portion 2 and the outside of the pixel portion 2 from the pixel portion region portion 20A as shown in FIG. The peripheral portion 20B is extended and covers the light shielding film-wiring slit 35 together with the pixel portion region portion 20A. Here, the outside of the pixel unit 2 is the side where the wiring unit 15 is provided with respect to the pixel unit 2 (the right side in FIG. 4), and three sides with respect to the rectangular pixel unit 2 as in the present embodiment. In the configuration in which the wiring portion 15 is provided on the side, at least these three sides are outside when the pixel portion 2 side is the inside.

  As described above, the lower light shielding film 20 has the peripheral portion 20B with respect to the pixel portion region portion 20A, so that it extends toward the wiring portion 15 and is provided so as to cover at least the light shielding film-wiring slit 35. That is, for example, when the light-shielding film-wiring slit 35 is located at a distance of several tens of micrometers from the pixel portion 2, the lower-layer light shielding film 20 is at least a light-shielding film-wiring located at a distance of several tens of micrometers from the pixel portion 2. It extends to the wiring part 15 side so as to cover the intermediate slit 35.

  In this regard, in the solid-state imaging device 1 of the present embodiment, the lower light shielding film 20 is provided so as to cover the inter-wiring slits 36 that exist between the wirings 17 adjacent to each other in the wiring portion 15. That is, the lower light shielding film 20 is provided so that the peripheral portion 20B extends over substantially the entire wiring portion 15, so that the wiring 17A is connected to the wiring 17B, the wiring 17B is connected to the wiring 17C, and the wiring 17C is connected to the wiring 17D. The inter-wiring slits 36 between the respective wirings are provided so as to cover from below.

  That is, the lower light-shielding film 20 is provided in an overlapping state with respect to the inter-wiring slits 36 existing at three locations in addition to the light-shielding film-wiring slit 35 formed thereabove. In other words, when the lower light shielding film 20 is viewed from above the light shielding film-wiring slit 35 and the three wiring slits 36 (upper side in FIG. 4), the light shielding film-wiring slit 35 and each wiring slit 36 are arranged. It is provided so that the part of the peripheral part 20B overlaps with the part of the back.

  As described above, in the solid-state imaging device 1 of the present embodiment, the wiring layer 16 of the wiring unit 15 includes four wirings 17A and 17B provided as the same layer portion with the inter-wiring slits 36 therebetween. 17C, 17D. The lower light shielding film 20 is provided in a state of covering the inter-wiring slits 36 between the four wirings 17 with respect to the semiconductor substrate 10 in addition to the light-shielding film-wiring slits 35.

  According to the solid-state imaging device 1 of the present embodiment having the above-described configuration, the light from the light shielding film-wiring slit 35 or the inter-wiring slit 36 formed around the pixel portion 2 is structurally transmitted from the semiconductor substrate 10. Can be prevented, and deterioration of image quality due to black level disturbance caused by incident light from the slit, which is likely to occur as the chip size is reduced, can be prevented. The operations and effects obtained by the solid-state imaging device 1 of the present embodiment will be described with reference to an example of a configuration conventionally employed in the solid-state imaging device (hereinafter referred to as “comparative example”). 5 to 7 show the configuration of the comparative example. In addition, in the structure of a comparative example, the same code | symbol is attached | subjected about the structure which is common in the solid-state image sensor 1 of this embodiment.

  5 and 6 show the configuration of the first comparative example. As shown in FIGS. 5 and 6, in the first comparative example, the invalid area 42 is provided wider than the solid-state imaging device 1 of the above-described embodiment. Specifically, as described above, the width of the portion along each side of the ineffective area 42 provided as the area along the three sides in the rectangular pixel portion 2 (see Y1 in FIG. 6) The configuration of the comparative example is provided so as to be about twice as large as the configuration of the solid-state imaging device 1 of the above-described embodiment.

  In the configuration of the first comparative example, the lower light shielding film 20 is provided only in the region of the pixel unit 2. That is, as shown in FIG. 6, in the configuration of the first comparative example, the lower light-shielding film is in the same range as the upper light-shielding film 30 that forms the light-shielding film-wiring slit 35 together with the wiring layer 16 of the wiring portion 15. 20 is provided.

  As shown in FIG. 6, in the configuration of the first comparative example, incident light (see arrow X <b> 1) with respect to the solid-state imaging device passes through the light shielding film-wiring slit 35 and the wiring slit 36 and passes through the insulating film 21. Then, it enters the semiconductor substrate 10 (see arrow X2). Thus, when light enters the semiconductor substrate 10 under the slit, electrons 44 are generated by photoelectric conversion in the semiconductor substrate 10 mainly made of silicon (Si).

  Thus, the electrons 44 generated in the semiconductor substrate 10 move by diffusion in the semiconductor substrate 10 (see arrow X3), and the pixel portion 2, particularly the wiring portion 15 side where the light shielding film-wiring slit 35 is formed. May reach the OB portion 40 close to. When electrons 44 flow into the OB section 40, which is an area for defining a black level reference signal, black level disturbance occurs such that the black level reference signal is output more than the original signal amount, which is called black sink. Image quality degradation will occur.

  FIG. 7 shows the configuration of the second comparative example. As shown in FIG. 7, in the second comparative example, the invalid area 42 is narrower than the configuration of the first comparative example, as in the solid-state imaging device 1 of the above-described embodiment. Further, in the configuration of the second comparative example, the lower-layer light shielding film 20 is provided only in the region of the pixel unit 2 as in the configuration of the first comparative example.

  As described above, the image quality deterioration due to the incident light from the slits around the pixel unit 2 is relatively a problem in the past because a sufficient distance from the slit to the pixel unit 2 was ensured as in the first comparative example. It was hard to become. However, as the second comparative example shown in FIG. 7, the position of the slit approaches the pixel unit 2 due to the recent chip size reduction, so that the electrons 44 generated by the incident light from the slit can easily reach the OB unit 40. There is a greater concern about image quality degradation caused by incident light from the slit.

  Therefore, as in the solid-state imaging device 1 of the present embodiment shown in FIG. 4, the lower layer provided as a lower layer of the upper light shielding film 30 and the wiring layer 16 in which the light shielding film-wiring slit 35 and the wiring slit 36 are formed. The light shielding film 20 is configured to cover the light shielding film-wiring slit 35 and the wiring slit 36 from below so that light from the light shielding film-wiring slit 35 and the wiring slit 36 enters the semiconductor substrate 10. This can be prevented. Accordingly, it is possible to prevent image quality deterioration due to black level disturbance caused by incident light from the slit, and it is possible to reduce the chip size by reducing or eliminating the invalid area 42.

  Regarding the chip size, specifically, by adopting a configuration like the solid-state imaging device 1 of the present embodiment, it is possible to reduce the size by several tens of micrometers on each side of the chip. By reducing the chip size, it is possible to increase the number of solid-state imaging elements obtained from one wafer, and the cost reduction effect can be obtained.

  In addition, as a configuration for covering the light shielding film-wiring slit 35 and the wiring slit 36 with respect to the semiconductor substrate 10, the light is allowed to enter the sensor unit 3 as in the solid-state imaging device 1 of the present embodiment. It is preferable to use the lower light shielding film 20 provided in the effective pixel portion 41 of the pixel portion 2 while having the opening portion 20a. Thereby, the structure for covering the slit 35 between light shielding films and wiring and the slit 36 between wiring can be easily provided using the existing structure.

  Specifically, for example, in the step of forming the lower light shielding film 20, the shape of the mask pattern is changed so that the lower light shielding film 20 has the pixel portion region portion 20A and the peripheral portion 20B. A configuration that covers the slit 35 and the inter-wiring slit 36 can be easily realized. As described above, by using the lower light shielding film 20, it is possible to provide a configuration for covering the semiconductor substrate 10 with respect to the light shielding film-wiring slit 35 and the wiring slit 36 without increasing the number of manufacturing steps.

(Modification 1)
A modification of the solid-state imaging device 1 of the present embodiment will be described. As described above, the lower light shielding film 20 has the peripheral portion 20B with respect to the pixel portion region portion 20A, and thus is extended to the wiring portion 15 side and provided so as to cover at least the light shielding film-wiring slit 35. Therefore, the lower light shielding film 20 may be provided so as to cover only the light shielding film-wiring slit 35 as shown in FIG. 8, for example. In other words, in the configuration shown in FIG. 8, among the light shielding film-wiring slit 35 and the wiring slit 36 that exist around the pixel portion 2, the light shielding film-wiring slit that is present on the innermost side (pixel portion 2 side). The lower light shielding film 20 is extended so that only 35 is covered.

  Also according to the configuration of this modification, the above-described operations and effects can be obtained. That is, by covering the innermost light-shielding film-wiring slit 35 among the plurality of slits existing around the pixel unit 2 with the lower-layer light-shielding film 20, the position of the slit for allowing light to enter the semiconductor substrate 10 correspondingly. , And away from the pixel portion 2. Thereby, the distance from the slit for allowing light to enter the semiconductor substrate 10 to the pixel portion 2 can be increased, and the electrons 44 generated by the incident light from the slit can be prevented from reaching the OB portion 40. As a result, it is possible to prevent the deterioration of the image quality due to the black level disturbance caused by the incident light from the slit, which is likely to occur as the chip size is reduced.

  Although illustration is omitted, in addition to the configuration shown in FIG. 8, only the light-shielding film-wiring slit 35 and the inter-wiring slit 36 between the innermost wiring 17A and wiring 17B are covered with the lower-layer light-shielding film 20. It may be. Similarly, the lower light-shielding film 20 may be configured to cover only the light-shielding film-wiring slit 35 and the inter-wiring slit 36 between the wiring 17A and the wiring 17B and between the wiring 17B and the wiring 17C. . Also with these configurations, the above-described operations and effects can be obtained, and as the number of slits covered by the lower light shielding film 20 increases, the incidence of light from the slits onto the semiconductor substrate 10 is prevented. It is preferable from the viewpoint.

(Modification 2)
Another modification of the solid-state imaging device 1 of the present embodiment will be described. As shown in FIG. 9, in this modification, the wiring layer 46 provided in the wiring portion 15 is provided as the same layer structure as the lower light shielding film 20. The wiring layer 46 has four wirings 47 (47A, 47B, 47C, 47D), similarly to the wiring layer 16 described above. However, in FIG. 9, only the two inner wirings 47A and 47B are shown. A light-shielding film-wiring slit 48 is formed between the lower-layer light-shielding film 20 and the wiring layer 46, that is, between the lower-layer light-shielding film 20 and the wiring 47A, and between the wirings 47 adjacent to each other in the wiring layer 46. A slit 49 is formed.

  In such a configuration, the upper light-shielding film 30 is used as a configuration for covering the semiconductor substrate 10 with respect to the light-shielding film-wiring slit 48 and the wiring slit 49. Specifically, it is as follows.

  As shown in FIG. 9, the upper light shielding film 30 is a layer positioned above the insulating film 21 with respect to the layer structure forming the lower light shielding film 20 and the wiring layer 46. The upper light shielding film 30 is provided between the lower light shielding film 20 of the pixel unit 2 and the wiring layer 46 (wiring 47A) of the wiring unit 15 by extending from the pixel unit 2 to the wiring unit 15 side. The light-shielding film-wiring slit 48 and the inter-wiring slit 49 are provided so as to cover the upper side.

  That is, the upper light shielding film 30 is provided in a state of overlapping with the light shielding film-wiring slits 48 and the wiring slits 49 formed below the upper light shielding film 30. In other words, when the upper light shielding film 30 is viewed from the lower side (lower side in FIG. 9) of the light shielding film-wiring slit 48 and the wiring slit 49, each of the light shielding film-wiring slit 48 and the wiring slit 49 is provided. The upper portion of the upper light shielding film 30 is provided so as to overlap the wiring portion 15 side.

  Therefore, in this modified example, as shown in FIG. 9, the upper light shielding film 30 is extended to the outside of the pixel unit 2 from the pixel unit region unit 30A covering the pixel unit 2 and the pixel unit region 30A. And a peripheral portion 30B that covers the light shielding film-wiring slit 48 together with the portion 30A. As described above, in this modified example, the upper light shielding film 30 has the peripheral portion 30B with respect to the pixel portion region portion 30A, so that it extends to the wiring portion 15 side, and the light shielding film-wiring slit 48 and the wiring slit. 49 is provided so as to cover 49. Also in this modification, the upper light shielding film 30 is provided so as to cover at least the light shielding film-wiring slit 48 as in the case of the lower light shielding film 20 described above.

  In this modification, the upper light-shielding film 30 functions as a second light-shielding film provided in a state of covering at least the light-shielding film-wiring slit 48 with respect to the semiconductor substrate 10, and the lower-layer light-shielding film 20 serves as the pixel unit 2. It functions as a first light shielding film that is provided above and covers at least the OB portion 40 of the pixel portion 2. Also according to the configuration of this modification, the above-described operations and effects can be obtained. The configuration of this modification can be applied, for example, when the lower light shielding film 20 can be formed of the same material as the wiring layer 46.

  As in this modification, the configuration for covering the slits formed around the pixel portion 2 with respect to the semiconductor substrate 10 is not limited to the configuration for covering the slits located in the upper layer from the lower side, and the light shielding film located in the lower layer A configuration in which the inter-wiring slit 48 and the inter-wiring slit 49 are covered from above by the upper light shielding film 30 may be employed. Therefore, in the second light-shielding film according to the present technology, in a state where the slit-like gap is covered with respect to the semiconductor substrate 10, the slit is provided by the light-shielding film provided as a lower layer of the layer in which the slit-like gap is formed. And a state in which the slit-like gap is covered from the upper side by a light-shielding film provided as an upper layer of a layer in which the slit-like gap is formed.

[Method for Manufacturing Solid-State Imaging Device]
A method for manufacturing the solid-state imaging device 1 according to this embodiment will be described. In the method for manufacturing the solid-state imaging device 1, first, a semiconductor layer 12 as a P-type impurity region is formed on a semiconductor substrate 10 which is an N-type silicon semiconductor substrate by ion implantation (see FIG. 2). An ion implantation technique is used for the semiconductor layer 12, and N-type impurities are ion-implanted under predetermined conditions, whereby the sensor unit 3 and the vertical transfer register 13 are formed.

Thereafter, an insulating film such as a silicon oxide film (SiO ₂ film) is formed on the surface of the semiconductor substrate 10 on which various impurity regions are formed by using, for example, a CVD (Chemical Vapor Deposition) method. On this insulating film, a transfer electrode 14 made of, for example, polycrystalline silicon is formed using a CVD method, a photolithography technique, or the like. An interlayer insulating film such as a silicon oxide film (SiO ₂ film) is formed on the transfer electrode 14.

  As described above, after the ion implantation technique, the lithography technique, and the like are utilized to form the sensor unit 3, the transfer electrode 14, and the like, a step of forming the lower light shielding film 20 is performed as shown in FIG. . That is, a step of forming a lower light shielding film 20 having an opening 20 a that allows light to enter the sensor unit 3 is performed on the pixel unit 2 in which the plurality of sensor units 3 are arranged on the semiconductor substrate 10.

The lower light shielding film 20 is formed so as to cover the transfer electrode 14 provided on the semiconductor substrate 10 via an interlayer insulating film. The lower light shielding film 20 is formed by patterning a metal material such as tungsten (W) or aluminum (Al) so that the opening 20a is formed by a CVD method or the like. After the lower light shielding film 20 is formed, an insulating film such as a silicon oxide film (SiO ₂ film) is formed.

  Subsequently, as illustrated in FIG. 10B, as the upper layer of the lower light shielding film 20, the upper light shielding film 30 that covers at least the OB portion 40 of the pixel portion 2, and the upper light shielding film 30 around the pixel portion 2. A step of forming the wiring layer 16 separating the light-shielding film-wiring slit 35 as the same layer portion is performed. In this step, the upper light shielding film 30 and the plurality of wirings 17 of the wiring layer 16 are simultaneously formed of the same material at the same time.

  The upper light shielding film 30 and the wiring layer 16 are formed by patterning a metal material such as tungsten (W) or aluminum (Al) into a predetermined shape by a CVD method or the like. Here, the upper light shielding film 30 is formed so as to cover the OB portion 40 and the ineffective region 42. As for the wiring 17 of the wiring layer 16, as shown in FIG. 3, the four wirings 17 other than the side (lower side in FIG. 3) where the horizontal transfer unit 5 is provided with respect to the rectangular pixel unit 2. Patterning is performed so as to surround the pixel portion 2 from the three sides. By forming the upper light shielding film 30 and the wiring layer 16, a light shielding film-wiring slit 35 is formed between the upper light shielding film 30 and the wiring layer 16 (wiring 17 </ b> A). Is formed with an inter-wiring slit 36 (see FIG. 10B).

After the upper light shielding film 30 and the wiring layer 16 are formed, an insulating film such as a silicon oxide film (SiO ₂ film) is buried between the upper light shielding film 30 and the wiring layer 16 or between the wirings 17 by a CVD method or the like. Formed as follows. The insulating film formed here is flattened, and the color filter layer 22, the flattening film 24, and the microlens 25 are sequentially formed on the flattened insulating film (insulating film 21), and the solid-state imaging device 1 is obtained. (See FIG. 2).

  As described above, in the step of forming the lower light-shielding film 20 in the solid-state imaging device 1 of the present embodiment including the step of forming the lower light-shielding film 20 and the step of forming the upper light-shielding film 30 and the wiring layer 16, The lower light shielding film 20 is formed so that the light shielding film 20 covers the light shielding film-wiring slit 35 and the wiring slit 36. That is, the lower light shielding film 20 is formed so as to overlap with the light shielding film-wiring slit 35 and the wiring slit 36 formed thereabove.

  Therefore, in the method for manufacturing the solid-state imaging device 1 of the present embodiment, the lower-layer light-shielding film 20 includes a pixel portion region portion 20A that covers the pixel portion 2 and the pixel portion region portion 20A, as shown in FIG. To the outside of the pixel portion 2 and is formed so as to have a pixel portion region portion 20 </ b> A and a peripheral portion 20 </ b> B that covers the light shielding film-wiring slit 35 and the interwiring slit 36.

  As described above, the lower light shielding film 20 has the peripheral portion 20B with respect to the pixel portion region portion 20A, so that it extends toward the wiring portion 15 and is formed so as to cover at least the light shielding film-wiring slit 35. Therefore, for example, in the case of a configuration in which the lower light shielding film 20 is provided so as to cover only the light shielding film-wiring slit 35 located at a distance of several tens of micrometers from the pixel portion 2 (see FIG. 8). In the step of forming the light shielding film 20, the lower light shielding film 20 is formed to extend to the wiring part 15 side so as to cover the light shielding film-wiring slit 35 located at a distance of several tens of micrometers from the pixel part 2. . In the case where the light shielding film-inter-wiring slit 35 and the inter-wiring slit 36 are covered by the lower light-shielding film 20, the lower light-shielding film 20 includes a part or all of the inter-wiring slits 36. 36 is formed so as to cover 36.

  According to the manufacturing method of the solid-state imaging device 1 as described above, in the solid-state imaging device 1, the light from the light shielding film-inter-wiring slit 35 or the inter-wiring slit 36 formed in the periphery of the pixel portion 2 in the structure is a semiconductor. It is possible to prevent the light from entering the substrate 10, and it is possible to prevent the deterioration of the image quality due to the black level disturbance caused by the incident light from the slit, which is likely to occur as the chip size is reduced. Since the lower light shielding film 20 is used as a configuration for covering the light shielding film-wiring slit 35 or the wiring slit 36, as described above, in the step of forming the lower light shielding film 20, the lower light shielding film 20 is formed. By changing the shape of the mask pattern, it is possible to easily realize a configuration that covers the light shielding film-wiring slit 35 and the wiring slit 36.

[Configuration of solid-state imaging device]
A solid-state imaging device 50 including a solid-state imaging device 51 corresponding to the solid-state imaging device of the above-described embodiment will be described with reference to FIG. The solid-state imaging device 50 according to the present embodiment constitutes an imaging device module, for example, in a digital still camera called a so-called digital camera, a digital video camera, a camera unit incorporated in a mobile phone, or the like.

  The solid-state imaging device 50 includes the solid-state imaging device 51 according to the above-described embodiment and a timing generator 52 that generates a drive signal for driving the solid-state imaging device 51 at a predetermined timing. The timing generator 52 has a function of generating various pulse signals for driving the solid-state image sensor 51 and a function of a driver for converting the generated pulse signals into drive pulses for driving the solid-state image sensor 51. Have. The solid-state imaging device 50 also includes a power supply unit such as a battery that supplies power to the timing generator 52 and the like, a storage unit that stores image data generated by imaging, a control unit that controls the entire apparatus, and the like.

  In the present embodiment, the circuits constituting the power supply unit, the storage unit, and the control unit included in the solid-state imaging device 50 are provided as a separate circuit (separate chip) from the solid-state imaging element 51. However, the circuits constituting these units may be provided on the same chip as the solid-state imaging device 51, or the functions may be divided and provided on a plurality of chips.

  The timing generator 52 inputs a four-phase drive pulse for driving the vertical transfer unit 4 included in the solid-state image sensor 51 to the solid-state image sensor 51. In other words, the timing generator 52 supplies four-phase clock pulses φV 1, φV 2, φV 3, and φV 4 as drive voltages to the four types of transfer electrodes 14 constituting the vertical transfer unit 4 independently to each transfer electrode 14.・ Apply.

  The solid-state imaging device 51 has an input unit for receiving the clock pulses φV1, φV2, φV3, and φV4 from the timing generator 52 independently. That is, the solid-state imaging device 51 includes a first drive signal input unit 53a that is a signal input terminal to which the clock pulse φV1 is input, and a second drive signal input unit 53b that is a signal input terminal to which the clock pulse φV2 is input. And a third drive signal input unit 53c that is a signal input terminal to which the clock pulse φV3 is input, and a fourth drive signal input unit 53d that is a signal input terminal to which the clock pulse φV4 is input.

  The clock pulses φV1, φV2, φV3, and φV4 input to the drive signal input units 53a, 53b, 53c, and 53d are transferred to the transfer electrodes constituting the vertical transfer unit 4 via bus lines, predetermined wirings, and the like. 14 is applied. The magnitudes and timings of the four-phase clock pulses φV1, φV2, φV3, and φV4 are appropriately controlled by the control unit included in the solid-state imaging device 51, and are read from each sensor unit 3 to the vertical transfer unit 4. The signal charges are transferred according to the arrangement of the transfer electrodes 14 of the vertical transfer unit 4.

  The timing generator 52 inputs a two-phase drive pulse for driving the horizontal transfer unit 5 included in the solid-state image sensor 51 to the solid-state image sensor 51. That is, the timing generator 52 supplies and applies two-phase clock pulses φH1 and φH2 as drive voltages to the two types of transfer electrodes constituting the horizontal transfer unit 5.

  The solid-state imaging device 51 has an input unit for receiving clock pulses φH1 and φH2 from the timing generator 52 independently. That is, the solid-state imaging device 51 includes a first drive signal input unit 54a that is a signal input terminal to which the clock pulse φH1 is input and a second drive signal input unit 54b that is a signal input terminal to which the clock pulse φH2 is input. And have.

  The clock pulses φH1 and φH2 input to the drive signal input units 54a and 54b are applied to the transfer electrodes constituting the horizontal transfer unit 5 through bus lines and predetermined wirings. The magnitude and timing of the two-phase clock pulses φH1 and φH2 are appropriately controlled by the control unit included in the solid-state imaging device 51, so that the signal charges transferred from the vertical transfer unit 4 to the horizontal transfer unit 5 are Transferred horizontally.

  In the solid-state imaging device 50 according to the present embodiment having the above-described configuration, the timing generator 52 functions as a driving unit that generates a driving signal for driving the solid-state imaging element 51. Then, according to the solid-state imaging device 50 including the solid-state imaging element 51 of the present embodiment, the light from the slit formed around the pixel unit 2 is structurally formed on the semiconductor substrate 10 in the solid-state imaging element 51 as described above. Incidence can be prevented, and deterioration of the image quality due to black level disturbance caused by incident light from the slit, which is likely to occur as the chip size is reduced, can be prevented.

[Configuration example of electronic equipment]
The solid-state imaging device according to the above-described embodiment is applied to various electronic devices such as a digital still camera called a so-called digital camera, a digital video camera, a mobile phone having an imaging function, and other devices. Below, the video camera 100 which is an example of an electronic device provided with the solid-state image sensor which concerns on embodiment mentioned above is demonstrated using FIG.

  The video camera 100 captures still images or moving images. The video camera 100 includes a solid-state image sensor 101 corresponding to the solid-state image sensor of the above-described embodiment, an optical system 102, a system controller 103, an input unit 104, and a signal processing circuit 105. The video camera 100 also includes a driver 106 for driving the mechanism of the optical system 102 and a timing generator (TG) 107 for driving the solid-state image sensor 101.

  The optical system 102 is configured as an optical lens system having, for example, one or a plurality of optical lenses 108, and guides incident light to the sensor unit 3 of the solid-state imaging device 101. The optical system 102 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 101. As a result, signal charges are accumulated in the solid-state imaging device 101 for a certain period. The optical system 102 includes a shutter device 109 for controlling the light irradiation period and the light shielding period to the solid-state image sensor 101. The optical system 102 includes a drive mechanism, a diaphragm, and the like for moving the optical lens 108 to perform focusing and zooming. The driver 106 controls driving of the mechanism in the optical system 102 in accordance with a control signal from the system controller 103.

  The timing generator 107 functions as a drive circuit that generates a drive signal (timing signal) for driving the solid-state imaging device 101. The timing generator 107 generates a drive signal (timing signal) for driving the solid-state image sensor 101 at a predetermined timing under the control of the system controller 103, and supplies it to the solid-state image sensor 101.

  The transfer operation of the signal electrode of the solid-state image sensor 101 is controlled by a drive signal supplied from the timing generator 107 to the solid-state image sensor 101. That is, the solid-state imaging device 101 is driven based on the drive signal supplied from the timing generator 107, and performs conversion of incident light into an electrical signal, signal charge transfer operation, and the like. The timing generator 107 has a function of generating various pulse signals as drive signals for driving the solid-state image sensor 101, and a driver that converts the generated pulse signals into drive pulses for driving the solid-state image sensor 101. With functions.

  The system controller 103 comprehensively controls each unit of the video camera 100 and executes various calculations for the control. The system controller 103 has a configuration in which, for example, a CPU (Central Processing Unit), a memory, an input / output interface, and the like are connected to each other by a bus line or the like. The input unit 104 includes various operation units such as operation keys and dials for receiving user operation inputs, and outputs a control signal corresponding to the operation input to the system controller 103.

  The signal processing circuit 105 has a function of performing various signal processing, and processes an output signal of the solid-state imaging device 101. The signal processing executed by the signal processing circuit 105 includes various camera signal processing such as AF (Auto Focus) processing and AE (Auto Exposure) processing for a digital signal output from the solid-state imaging device 101, for example. The signal processing circuit 105 processes the input signal to output a video signal. The video signal output from the signal processing circuit 105 is stored in a storage medium such as a memory or output to a monitor such as a liquid crystal display device.

  The video camera 100 according to the present embodiment has a solid-state imaging device 101, an optical system 102, a system controller 103, an input unit 104, a signal processing circuit 105, a driver 106, and a timing generator 107 as modules. The form of a camera module or an imaging function module is also included.

  According to the video camera 100 having the solid-state imaging device 101 of the present embodiment having the above-described configuration, the light from the slit formed around the pixel unit 2 is structurally structured in the solid-state imaging device 101 as described above. It is possible to prevent the light from entering the semiconductor substrate 10, and it is possible to prevent the deterioration of the image quality due to the black level disturbance caused by the incident light from the slit, which is likely to occur as the chip size is reduced.

  In the embodiments of the present technology described above, a CCD solid-state image sensor has been described as an example of the solid-state image sensor. However, the present technology can be applied to other types of solid-state image sensors including a CMOS solid-state image sensor. Application is also possible. In the case of a CMOS type solid-state imaging device, a light shielding film for shielding the transistor portion and the OB portion in the pixel portion is provided on a semiconductor substrate provided with a sensor portion, a transfer transistor, an amplification transistor, and the like. And this light shielding film is provided so that the slit-shaped space | interval formed in a wiring layer may be covered.

  In the case of a CMOS type solid-state imaging device, the manufacturing method uses an ion implantation technique, a photolithography technique, etc. to form a sensor part, a transfer transistor, an amplification transistor, etc., and then a transistor part or OB in a pixel part. A step of forming a light shielding film for shielding the portion is performed. In the step of forming the light shielding film, the light shielding film is formed so as to cover the slit of the wiring layer at a distance of, for example, several tens of micrometers from the pixel portion.

  As described above, the present technology has an OB portion in a pixel portion in which a plurality of sensor portions that generate signal charges by photoelectric conversion are arranged, and a slit-like interval is provided between the light shielding film that covers the OB portion and the wiring layer. The present invention can be applied to a solid-state imaging device having an existing configuration. According to the present technology, the light shielding film provided in the pixel portion is used to cover the slit-like interval with respect to the semiconductor substrate so that light from the slit-like interval does not reach the semiconductor substrate. can do.

In addition, this technique can take the following structures.
(1) A pixel unit in which a plurality of sensor units that generate signal charges by photoelectric conversion are arranged on a semiconductor substrate, and an optical that is a part of the pixel unit and outputs a signal serving as a black level reference by the sensor unit. A slit between the black portion, the first light shielding film provided on the pixel portion and covering at least the optical black portion of the pixel portion, and the first light shielding film provided around the pixel portion A solid-state imaging device comprising: a wiring portion having a wiring layer provided with a gap in the form of a gap; and a second light shielding film provided in a state of covering the slit-like gap with respect to the semiconductor substrate.
(2) The second light-shielding film includes a pixel portion region portion that covers the pixel portion, and a periphery that extends from the pixel portion region portion to the outside of the pixel portion and covers the slit-shaped interval together with the pixel portion region portion. A solid-state imaging device according to (1).
(3) The second light-shielding film is a light-shielding film that is provided as a lower layer with respect to the first light-shielding film and has an opening that allows light to enter the sensor unit. The solid-state image sensor as described in 1) or (2).
(4) The wiring layer has a plurality of wirings provided as slits between each other as the same layer portion, and the second light-shielding film has the plurality of wirings with respect to the semiconductor substrate. The solid-state imaging device according to any one of (1) to (3), which is provided in a state of covering a slit-like interval between wirings.
(5) forming a lower-layer light-shielding film having an opening that allows light to enter the sensor unit on a pixel unit on which a plurality of sensor units that generate signal charges by photoelectric conversion are arranged on a semiconductor substrate; An upper layer light-shielding film that covers at least an optical black part that outputs a signal serving as a black level reference by the sensor unit as the upper layer of the lower-layer light-shielding film, and the upper layer light-shielding film around the pixel part Forming a wiring layer with a slit-like spacing between them as the same layer portion, wherein the step of forming the lower-layer light-shielding film covers the slit-like spacing. A method for manufacturing a solid-state imaging device, wherein the lower-layer light-shielding film is formed so as to be in a wet state.
(6) a solid-state imaging device; and a drive unit that generates a drive signal for driving the solid-state imaging device, wherein the solid-state imaging device generates a plurality of signal charges by photoelectric conversion on a semiconductor substrate. A pixel unit in which a sensor unit is arranged; an optical black unit which is a part of the pixel unit and outputs a signal serving as a reference for a black level by the sensor unit; and provided on the pixel unit, and at least of the pixel unit A wiring portion having a first light shielding film that covers the optical black portion, a wiring layer that is provided around the pixel portion and that is provided with a slit-like space between the first light shielding film and the first light shielding film; And a second light-shielding film provided in a state of covering the slit-like interval with respect to the semiconductor substrate.
(7) A solid-state image sensor, an optical system that guides incident light to the sensor unit of the solid-state image sensor, a drive circuit that generates a drive signal for driving the solid-state image sensor, and an output signal of the solid-state image sensor A signal processing circuit for processing, wherein the solid-state imaging device is a pixel unit that arranges a plurality of sensor units that generate signal charges by photoelectric conversion on a semiconductor substrate, and a part of the pixel unit, An optical black portion that outputs a signal serving as a black level reference by the sensor portion, a first light-shielding film that is provided on the pixel portion and covers at least the optical black portion of the pixel portion, and around the pixel portion A wiring portion having a wiring layer provided with a slit-like space between the first light-shielding film and the semiconductor substrate so as to cover the slit-like space. That includes a second light-shielding film, and electronic equipment.

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 2 Pixel part 3 Sensor part 10 Semiconductor substrate 15 Wiring part 16 Wiring layer 17 Wiring 20 Light shielding film, lower layer light shielding film (2nd light shielding film)
20a Opening portion 20A Pixel portion region portion 20B Peripheral portion 30 Light shielding film, upper light shielding film (first light shielding film)
35 Light-shielding film-wiring slit 36 Wiring slit 40 OB part (optical black part)
DESCRIPTION OF SYMBOLS 50 Solid-state imaging device 51 Solid-state image sensor 52 Timing generator (drive part)
100 Video camera (electronic equipment)
DESCRIPTION OF SYMBOLS 101 Solid-state image sensor 102 Optical system 105 Signal processing circuit 107 Timing generator (drive circuit)

Claims (7)

A pixel unit that arranges a plurality of sensor units that generate signal charges by photoelectric conversion on a semiconductor substrate;
An optical black unit that is a part of the pixel unit and outputs a signal that is a reference of a black level by the sensor unit;
A first light-shielding film provided on the pixel portion and covering at least the optical black portion of the pixel portion;
A wiring portion provided around the pixel portion and having a wiring layer provided with a slit-like space between the first light-shielding film;
A second light-shielding film provided in a state of covering the slit-like interval with respect to the semiconductor substrate,
Solid-state image sensor. The second light-shielding film includes a pixel portion region portion that covers the pixel portion, a peripheral portion that extends from the pixel portion region portion to the outside of the pixel portion, and covers the slit-shaped interval together with the pixel portion region portion, Having
The solid-state imaging device according to claim 1. The second light-shielding film is a light-shielding film provided as a lower layer with respect to the first light-shielding film and having an opening that allows light to enter the sensor unit.
The solid-state imaging device according to claim 1. The wiring layer has a plurality of wirings provided with a slit-like space between each other as the same layer portion,
The second light-shielding film is provided in a state of covering the slit-like spacing between the plurality of wirings with respect to the semiconductor substrate;
The solid-state imaging device according to claim 1. Forming a lower-layer light-shielding film having an opening that allows light to enter the sensor unit on a pixel unit on which a plurality of sensor units that generate signal charges by photoelectric conversion are arranged on a semiconductor substrate;
As the upper layer of the lower light-shielding film, an upper-layer light-shielding film that covers at least an optical black part that outputs a signal serving as a black level reference by the sensor part, and the upper-layer light-shielding film around the pixel part. Forming a wiring layer with a slit-like space between them as the same layer portion, and
The step of forming the lower light shielding film forms the lower light shielding film so that the lower light shielding film covers the slit-shaped interval.
Manufacturing method of solid-state image sensor. A solid-state image sensor;
A drive unit that generates a drive signal for driving the solid-state imaging device,
The solid-state imaging device is
A pixel unit that arranges a plurality of sensor units that generate signal charges by photoelectric conversion on a semiconductor substrate;
An optical black unit that is a part of the pixel unit and outputs a signal that is a reference of a black level by the sensor unit;
A first light-shielding film provided on the pixel portion and covering at least the optical black portion of the pixel portion;
A wiring portion provided around the pixel portion and having a wiring layer provided with a slit-like space between the first light-shielding film;
A second light-shielding film provided in a state of covering the slit-like interval with respect to the semiconductor substrate,
Solid-state imaging device. A solid-state image sensor;
An optical system that guides incident light to the sensor section of the solid-state imaging device;
A drive circuit for generating a drive signal for driving the solid-state imaging device;
A signal processing circuit for processing an output signal of the solid-state imaging device,
The solid-state imaging device is
A pixel unit that arranges a plurality of sensor units that generate signal charges by photoelectric conversion on a semiconductor substrate;
An optical black unit that is a part of the pixel unit and outputs a signal that is a reference of a black level by the sensor unit;
A first light-shielding film provided on the pixel portion and covering at least the optical black portion of the pixel portion;
A wiring portion provided around the pixel portion and having a wiring layer provided with a slit-like space between the first light-shielding film;
A second light-shielding film provided in a state of covering the slit-like interval with respect to the semiconductor substrate,
Electronics.

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