JP2013138222A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device having a large ratio of the surface area of a light-receiving portion to the surface area of one pixel.SOLUTION: A solid-state imaging device includes a signal line 154 formed on a substrate, an island semiconductor disposed on the signal line, and a pixel selection line 156 connected to an upper portion of the island semiconductor. The island semiconductor includes: a first semiconductor layer 153 disposed under the island semiconductor and connected to the signal line; a second semiconductor layer adjacent to an upper side of the first semiconductor layer; a gate 155 connected to the second semiconductor layer via an insulating film; a charge storage portion 151 connected to the second semiconductor layer and composed of a third semiconductor layer in which the amount of charges changes when receiving light; and a fourth semiconductor layer 150 being adjacent to upper sides of the second semiconductor layer and the third semiconductor layer and connected to the pixel selection line 156. The solid-state imaging device is arranged in a honeycomb shape on the substrate.

Description

The present invention relates to a solid-state image sensor.

An amplification type solid-state imaging device, that is, a CMOS image sensor that has an amplification function for each pixel and reads out by a scanning circuit has been proposed. In a CMOS image sensor, a photoelectric conversion unit, an amplification unit, a pixel selection unit, and a reset unit are formed in one pixel, and three MOS transistors are used in addition to the photoelectric conversion unit formed of a photodiode (for example, Patent Documents). 1). That is, the conventional CMOS image sensor is composed of four elements. The CMOS sensor accumulates electric charges generated by a photoelectric conversion unit made of a photodiode, amplifies the accumulated electric charges by an amplification unit, and reads the amplified electric charges using a pixel selection unit.

FIG. 1 shows a unit pixel of a conventional CMOS image sensor. In FIG. 1, 5 is a photoelectric conversion photodiode, 101 is an amplifying transistor, 102 is a reset transistor, 103 is a selection transistor, 13 is a signal line, 11 is a pixel selection clock line, 12 is a reset clock line, and 14 is a power supply line. 114 are reset power lines. A unit pixel of a conventional CMOS image sensor has three MOS transistors, a total of four elements, in addition to a photodiode. That is, it is difficult to increase the ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel.

In a conventional CMOS image sensor using a 0.35 μm, 1 polysilicon layer, 2 metal layer CMOS process, the ratio of the light receiving portion (photodiode) to the surface area of one pixel is reported to be 17% ( Non-patent document 1). Further, when the 0.15 μm wiring-rule process is used, the ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel is reported to be 30% (Non-patent Document 2).

JP 2000-244818

H. Takahashi, M. Kinoshita, K. Morita, T. Shirai, T. Sato, T. Kimura, H. Yuzurihara, S. Inoue, “A 3.9 μm Pixel Pit m Git. Transistor / Pixel ", ISSCC Dig. Tech. Papers, pp. 108-109, 2004. M. Kasano, Y. Inaba, M. Mori, S. Kasuga, T. Murata, T. Yamaguchi, “A 2.0 μm Pixel Pitch MOS Image Sensor with Si Amorphous Amorphous Morph.” pp.348-349, 2005.

Therefore, an object is to provide an image sensor in which the ratio of the surface area of the light receiving portion to the surface area of one pixel is large.

In one aspect of the invention,
An amplifying transistor comprising a junction transistor in which a gate and a source function as a photoelectric conversion photodiode, a gate functions as a charge storage unit, and amplifies the charge in the charge storage unit;
A reset transistor composed of a MOS transistor having a source connected to the gate of the amplifying transistor and resetting the charge storage unit;
A diode having an anode connected to the drain of the amplifying transistor and a cathode connected to the drain of the reset transistor;
A pixel selection line connected to the source of the amplifying transistor;
A signal line connected to the cathode of the diode;
The solid-state image sensor comprised by this is provided.

Another aspect of the present invention provides a method for driving a solid-state imaging device.
That is, by applying a first drive voltage to the pixel selection line, applying a second drive voltage to the signal line, and applying a third drive voltage to the gate, the charge storage unit is reset. Do.
The first drive voltage is applied to the pixel selection line, the first drive voltage is applied to the gate, and the first drive voltage is applied to the signal line to receive light and The amount of charge accumulated in the charge accumulation unit is changed.
Further, by applying the second drive voltage to the pixel selection line, the first drive voltage to the gate, and the first drive voltage to the signal line, the charge accumulated in the charge accumulation unit is amplified. Then, a read current is supplied to perform reading.

In a preferred embodiment of the present invention,
A solid-state imaging device including a solid-state imaging device arranged on a substrate,
The solid-state imaging device is
A signal line formed on the substrate;
An island-shaped semiconductor disposed on the signal line;
A pixel selection line connected to the upper part of the island-shaped semiconductor,
The island-shaped semiconductor is
A first semiconductor layer disposed under the island-shaped semiconductor and connected to the signal line;
A second semiconductor layer adjacent to the upper side of the first semiconductor layer;
A gate connected to the second semiconductor layer via an insulating film;
The charge accumulating unit comprising a third semiconductor layer connected to the second semiconductor layer, the charge amount of which changes upon receiving light;
A fourth semiconductor layer that is adjacent to the upper side of the second semiconductor layer and the third semiconductor layer and is connected to the pixel selection line,
The solid-state imaging device is provided with a solid-state imaging device arranged in a honeycomb shape on a substrate.

In a preferred aspect of the present invention, the first semiconductor layer is an n + -type diffusion layer, the second semiconductor layer is a p-type impurity doped region, and the third semiconductor layer is an n-type diffusion layer. The fourth semiconductor layer is a p + -type diffusion layer.
The p + -type diffusion layer and the n-type diffusion layer function as a photoelectric conversion photodiode,
The p + -type diffusion layer, the n-type diffusion layer, and the p-type impurity added region function as an amplifying transistor,
The n + -type diffusion layer, the p-type impurity doped region, the n-type diffusion layer and the gate of the first semiconductor layer function as a reset transistor,
The p-type impurity doped region and the n + -type diffusion layer function as a diode.

In a preferred aspect of the present invention, in the solid-state imaging device, the island-shaped semiconductor has a cylindrical shape.

In a preferred aspect of the present invention, in the solid-state imaging device, the island-shaped semiconductor has a hexagonal column shape.

Further, in a preferred aspect of the present invention, in the solid-state imaging device, the solid-state imaging element is arranged in a matrix as n rows and m columns (n and m are 1 or more) on a substrate, and the island-shaped semiconductor is a cylindrical shape It is.

Further, in a preferred aspect of the present invention, in the solid-state imaging device, the solid-state imaging elements are arranged in a matrix as n rows and m columns (n and m are 1 or more) on a substrate, and the island-shaped semiconductor is a square pillar Shape.

In a preferred aspect of the present invention, the first semiconductor layer is an n + -type diffusion layer, the second semiconductor layer is a p-type impurity doped region, and the third semiconductor layer is an n-type diffusion layer. The fourth semiconductor layer is a p + -type diffusion layer.
The p + -type diffusion layer and the n-type diffusion layer function as a photoelectric conversion photodiode,
The p + -type diffusion layer, the n-type diffusion layer, and the p-type impurity added region function as an amplifying transistor,
The n + -type diffusion layer, the p-type impurity doped region, the n-type diffusion layer and the gate of the first semiconductor layer function as a reset transistor,
The p-type impurity doped region and the n + -type diffusion layer function as a diode.

In a preferred embodiment of the present invention,
A method of manufacturing a solid-state imaging device,
Forming a signal line on the substrate;
Forming an island semiconductor on the signal line;
Forming a first semiconductor layer connected to the signal line under the island-shaped semiconductor;
Forming a second semiconductor layer adjacent to the upper side of the first semiconductor layer;
Forming a gate connected to an adjacent second semiconductor layer on the first semiconductor layer via an insulating film;
Forming a third semiconductor layer connected to the second semiconductor layer;
Forming a fourth semiconductor layer adjacent to an upper side of the second semiconductor layer and the third semiconductor layer;
Forming a pixel selection line connected to the fourth semiconductor layer;
The method for manufacturing the solid-state imaging device is provided.

In a preferred embodiment of the present invention,
A method of manufacturing a solid-state imaging device,
P-type silicon is formed on the oxide film, a nitride film is deposited on the p-type silicon, a silicon oxide film is deposited,
Forming a resist, performing oxide film etching, performing nitride film etching, stripping the resist, forming an oxide film mask and a nitride film mask for forming a signal line;
etching p-type silicon to form a signal line;
Forming a resist to form an island-shaped semiconductor;
Etch oxide film, nitride film,
Strip the resist,
etching p-type silicon to form an island-shaped semiconductor;
Deposit oxide film, planarize, etch back,
Oxidize to form an oxide film,
In order to make a mask at the time of ion implantation, a process of depositing polysilicon, etching back, and leaving it in a sidewall shape;
Exfoliate the oxide film and expose the area where phosphorus is implanted,
An oxide film is formed to prevent ion channeling during ion implantation.
Implanting phosphorus, performing a thermal process, and forming a signal line and an n + -type diffusion layer;
Strip polysilicon and oxide film,
Deposit oxide, planarize, etch back, form oxide layer,
Perform gate oxidation to form a gate oxide film, deposit polysilicon, planarize, etch back,
Forming a resist for the gate,
Etching polysilicon to form a gate;
Strip the resist,
The thin oxide film on the side wall of the silicon pillar is peeled off, and in order to prevent ion channeling during ion implantation, the silicon pillar side wall and gate polysilicon are oxidized to form an oxide film.
Injecting phosphorus to form an n-type diffusion layer;
Strip the nitride film,
Deposit oxide, planarize, etch back, form oxide layer,
Oxidize to prevent ion channeling during ion implantation, form an oxide film,
Injecting boron and performing a thermal process to form a p + -type diffusion layer;
Strip the oxide film,
Deposit metal, planarize, etch back,
Forming a resist for the pixel selection line;
Etching the metal to form pixel selection lines;
The method for manufacturing the solid-state imaging device is further provided.

In a preferred aspect of the present invention, a part of the second semiconductor layer has a cylindrical shape, and the gate surrounds an outer periphery of a part of the second semiconductor layer through the insulating film.
The other part of the second semiconductor layer has a cylindrical shape, and the third semiconductor layer surrounds the outer periphery of the other part of the second semiconductor layer.

A unit pixel of a conventional CMOS image sensor has three MOS transistors, a total of four elements, in addition to a photodiode. That is, it is difficult to increase the ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel. When a 0.15 μm wiring-rule process is used, the ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel is reported to be 30%.
In the present invention,
An amplifying transistor comprising a junction transistor in which a gate and a source function as a photoelectric conversion photodiode, a gate functions as a charge storage unit, and amplifies the charge in the charge storage unit;
A reset transistor composed of a MOS transistor having a source connected to the gate of the amplifying transistor and resetting the charge storage unit;
A diode having an anode connected to the drain of the amplifying transistor and a cathode connected to the drain of the reset transistor;
A pixel selection line connected to the source of the amplifying transistor;
A signal line connected to the cathode of the diode;
It is a solid-state image sensor comprised by these.
That is, since the photoelectric conversion unit, the amplification unit, the pixel selection unit, and the reset unit are configured by a total of three elements, that is, an amplifying transistor composed of a junction transistor, a reset transistor composed of a MOS transistor, and a diode, the number of elements in one pixel Can be reduced.

In the present invention,
A signal line formed on the substrate;
An island-shaped semiconductor disposed on the signal line;
A solid-state imaging device including a pixel selection line connected to an upper portion of the island-shaped semiconductor,
The island-shaped semiconductor is
A first semiconductor layer disposed under the island-shaped semiconductor and connected to the signal line;
A second semiconductor layer adjacent to the upper side of the first semiconductor layer;
A gate connected to the second semiconductor layer via an insulating film;
The charge accumulating unit comprising a third semiconductor layer connected to the second semiconductor layer, the charge amount of which changes upon receiving light;
There is provided a solid-state imaging device including the second semiconductor layer and a fourth semiconductor layer adjacent to the upper side of the third semiconductor layer and connected to the pixel selection line.
The third semiconductor layer and the fourth semiconductor layer function as a photoelectric conversion photodiode,
The second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer function as an amplifying transistor,
The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the gate function as a reset transistor.
Accordingly, since the photoelectric conversion unit, the amplification unit, the pixel selection unit, and the reset unit are realized by the area of the photodiode, an image sensor in which the ratio of the surface area of the light receiving unit to the surface area of one pixel is made possible.

Further, in the solid-state imaging device, by arranging the solid-state imaging elements in a honeycomb shape, an image sensor in which the ratio of the surface area of the light receiving unit to the surface area of one pixel is made possible.

A unit pixel of a conventional CMOS image sensor. 2 is an equivalent circuit of the solid-state imaging device according to the present invention. The solid-state image sensor driving method according to the present invention. The solid-state image sensor driving method according to the present invention. The solid-state image sensor driving method according to the present invention. The solid-state image sensor driving method according to the present invention. The bird's-eye view of one solid-state image sensor concerning this invention. X ₁ -X ₁ 'sectional view of FIG. FIG. 8 is an equivalent circuit diagram of FIG. Y ₁ -Y ₁ 'sectional view of FIG. FIG. 9 is an equivalent circuit diagram of FIG. The top view of the solid-state image sensor which has arranged the solid-state image sensor concerning this invention in honeycomb form. Bird's eye view. FIG. 11 is a sectional view taken along line Z ₁ -Z ₁ ′ in FIG. 10. FIG. 11 is a sectional view taken along line Z ₂ -Z ₂ ′ in FIG. 10. FIG. 11 is a Z ₃ -Z ₃ ′ cross-sectional view of FIG. 10. FIG. 11 is a sectional view taken along line Z ₄ -Z ₄ ′ of FIG. 10. FIG. 11 is a sectional view taken along line Z ₅ -Z ₅ ′ in FIG. 10. X ₂ -X ₂ 'sectional view of FIG. Y ₂ -Y ₂ 'sectional view of FIG. The bird's-eye view which shows the other Example concerning this invention. The bird's-eye view which shows the other Example concerning this invention. The bird's-eye view which shows the other Example concerning this invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. TOP View showing a manufacturing example of a solid-state imaging device according to the present invention. X ₃ -X ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. Y ₃ -Y ₃ 'cross-sectional process drawing showing the manufacture example of the solid-state imaging device according to the present invention. The bird's-eye view which shows the other Example concerning this invention. FIG. 82 is a sectional view taken along the line X ₄ -X ₄ ′ in FIG. 81. FIG. 82 is an equivalent circuit diagram of FIG. FIG. 82 is a sectional view taken along line Y ₄ -Y ₄ ′ of FIG. 81. FIG. 83 is an equivalent circuit diagram of FIG. The bird's-eye view which shows the other Example concerning this invention. FIG. 84 is a sectional view taken along the line X ₅ -X ₅ ′ in FIG. 84. 85 is an equivalent circuit diagram of FIG. FIG. 84 is a sectional view taken along line Y ₅ -Y ₅ ′ in FIG. 84. FIG. 86 is an equivalent circuit diagram of FIG. The top view which has arrange | positioned the image sensor of this invention with a column-shaped island-shaped semiconductor in matrix form. The top view which expanded one pixel. The top view which has arrange | positioned the image sensor of this invention with a quadrangular prism-shaped island-shaped semiconductor in matrix form. The top view which expanded one pixel. The top view which has arrange | positioned the image sensor of this invention which has a column-shaped island-shaped semiconductor in honeycomb form. The top view which expanded one pixel. The top view which has arrange | positioned the image sensor of this invention which has a hexagonal column-shaped island-shaped semiconductor in honeycomb form. The top view which expanded one pixel.

Hereinafter, the present invention will be described based on embodiments shown in the drawings. The present invention is not limited to this.

An equivalent circuit of the solid-state imaging device according to the present invention is shown in FIG. The solid-state imaging device according to the present invention includes a photodiode 401, a charge storage unit 402, an amplifying transistor 403, a gate (reset line) 406, a reset transistor 405, a diode 409, a pixel selection line 404, and a signal line 407.
That is, the photoelectric conversion unit, the amplification unit, the pixel selection unit, and the reset unit are configured by a total of three elements, that is, an amplifying transistor composed of a junction transistor, a reset transistor composed of a MOS transistor, and a diode. The number of elements in one pixel can be reduced.

The solid-state imaging device driving method according to the present invention is shown in FIGS. 3, 4, 5A, and 5B.
First, 0V is applied to the pixel selection line 404, a signal line voltage V _H for example 1V is applied to the signal line 407, by applying a V _H + Vth to the gate (reset line) 406, a charge storage section 402 V _H And reset (FIG. 3). However, Vth is a threshold voltage of the reset transistor, for example, 0.5V.

Next, 0 V is applied to the pixel selection line 404, 0 V is applied to the gate (reset line) 406, and 0 V is applied to the signal line 407, whereby the optical signal incident on the photodiode 401 is converted into an electric charge. The signal charge is accumulated in the charge accumulation unit 402. That is, when light enters, the voltage of the charge storage unit 402 decreases (FIG. 4).

Next, by applying V _H, for example, 1 V to the pixel selection line 404, 0 V to the gate (reset line) 406, and 0 V to the signal line 407, the charge accumulated in the charge accumulation unit 402 is amplified and the read current Iread 408 flows. The current Iread 408 flows through the diode 409 and is read out. The stronger the light, the lower the voltage of the charge storage unit 402 and the current flows (FIG. 5 (a)). When light is not incident on the photodiode, the voltage of the charge storage unit 402 is V _H, for example, 1 V, and no current flows (FIG. 5B).
With the above driving method, it is possible to accumulate the charge generated by the photoelectric conversion unit made of a photodiode, amplify the accumulated charge by the amplification unit, and read the amplified charge using the pixel selection unit.

A bird's-eye view of one solid-state imaging device according to the present invention is shown in FIG. 7A is a sectional view taken along the line X ₁ -X ₁ ′ in FIG. 6, FIG. 7B is an equivalent circuit diagram of FIG. 7A, and FIG. a of Y ₁ -Y ₁ 'sectional view, and FIG. 8 (b) is an equivalent circuit diagram of FIG. 8 (a).
In the present invention,
An oxide film 161 is formed on the silicon substrate 160, and a signal line 154 is formed on the oxide film 161.
An island semiconductor is formed on the signal line, and the island semiconductor is
An n + -type diffusion layer 153 connected to the signal line under the island-shaped semiconductor;
A p-type impurity doped region 152 adjacent to the upper side of the n + -type diffusion layer;
A gate 155 connected to the p-type impurity doped region via an insulating film;
A charge accumulating portion 151 formed of an n-type diffusion layer connected to the p-type impurity doped region and having a charge amount that changes upon receiving light;
A p + -type diffusion layer 150 adjacent to the p-type impurity doped region and the n-type diffusion layer;
A pixel selection line 156 connected to the p + type diffusion layer on the island-like semiconductor is formed.
An oxide film 157 is formed as an interlayer insulating film.
The p + -type diffusion layer 150 and the n-type diffusion layer 151 function as a photoelectric conversion photodiode 164.
The p + -type diffusion layer 150, the n-type diffusion layer 151, and the p-type impurity added region 152 function as an amplifying transistor 165,
The n + -type diffusion layer 153, the p-type impurity added region 152, the n-type diffusion layer 151, and the gate 155 function as the reset transistor 163,
The p-type impurity doped region 152 and the n + -type diffusion layer 153 function as the diode 162.

FIG. 9 shows a plan view of a solid-state imaging element matrix (solid-state imaging device) in which the solid-state imaging elements are arranged in a honeycomb shape. FIG. 10 is a bird's-eye view. 11 is a sectional view taken along the line Z ₁ -Z ₁ ′ in FIG. 10, FIG. 12 is a sectional view taken along the line Z ₂ -Z ₂ ′ in FIG. 10, and FIG. 13 is a sectional view taken along the line Z ₃ -Z ₃ ′ in FIG. 14 is a sectional view taken along the line Z ₄ -Z ₄ ′ of FIG. 15 is a sectional view taken along the line Z ₅ -Z ₅ ′ of FIG.
In the example shown in FIG. 10, the solid-state imaging element matrix (solid-state imaging device) is on a silicon substrate.
a first solid-state imaging device array in which solid-state imaging devices having p + -type diffusion layers 201, 202, 203 are arranged in a vertical direction at a predetermined interval (vertical pixel pitch VP);
Solid-state image sensors having p + -type diffusion layers 204, 205, and 206 are arranged in the vertical direction at the same interval as the first solid-state image sensor array, and the vertical pixel pitch is perpendicular to the first solid-state image sensor array. A second solid-state image sensor array arranged with a ½ shift with respect to VP;
a third solid-state image sensor array in which solid-state image sensors having p + -type diffusion layers 207, 208, and 209 are arranged in the vertical direction at the same interval as the first solid-state image sensor array;
A plurality of element arrays configured in the above are arranged in the horizontal direction.

The adjacent first solid-state image sensor array, the adjacent second solid-state image sensor array, and the third solid-state image sensor array are arranged at an interval (horizontal pixel pitch HP) obtained by multiplying the vertical pixel pitch by √3 / 2. .
That is, the solid-state imaging elements are arranged in a so-called honeycomb shape.

The p + -type diffusion layers 201, 202, and 203 of the first solid-state imaging element array are connected to the pixel selection line 210.
The p + -type diffusion layers 204, 205, and 206 of the second solid-state imaging element array are connected to the pixel selection line 211.
The p + -type diffusion layers 207, 208, and 209 of the third solid-state imaging element array are connected to the pixel selection line 212.

The p-type impurity doped regions 222, 223, and 224 of the first solid-state imaging device array are connected to the gate 231 through an insulating film.
The p-type impurity doped regions 225, 226, and 227 of the second solid-state imaging element array are connected to the gate 232 through an insulating film.
The p-type impurity doped regions 228, 229, and 230 of the third solid-state imaging device array are connected to the gate 233 through an insulating film.

The p-type impurity addition regions 222, 223, and 224 of the first solid-state imaging device array are connected to charge storage portions 213, 214, and 215 that are n-type diffusion layers that change the amount of charge when receiving light.
The p-type impurity addition regions 225, 226, and 227 of the second solid-state imaging device array are connected to charge storage portions 216, 217, and 218 made of n-type diffusion layers that change the amount of charge when receiving light.
The p-type impurity addition regions 228, 229, and 230 of the third solid-state imaging device array are connected to charge storage portions 219, 220, and 221 each including an n-type diffusion layer that changes the amount of charge when receiving light.

The n + type diffusion layers 234, 237, and 240 of the solid-state imaging device having the p + type diffusion layers 201, 204, and 207 are connected to the signal line 243.
The n + type diffusion layers 235, 238, and 241 of the solid-state imaging device having the p + type diffusion layers 202, 205, and 208 are connected to the signal line 244.
The n + type diffusion layers 236, 239, and 242 of the solid-state imaging device having the p + type diffusion layers 203, 206, and 209 are connected to the signal line 245.

16 is a cross-sectional view taken along line X ₂ -X ₂ ′ in FIG. 9, and FIG. 17 is a cross-sectional view taken along line Y ₂ -Y ₂ ′ in FIG. 9.

An oxide film 251 is formed on the silicon substrate 250, and a signal line 245 is formed on the oxide film 251.
An island semiconductor is formed on the signal line, and the island semiconductor is
An n + -type diffusion layer 236 connected to the signal line below the island-shaped semiconductor;
A p-type impurity doped region 224 adjacent to the upper side of the n + -type diffusion layer;
A gate 231 connected to the p-type impurity doped region via an insulating film;
A charge storage unit 215 that is connected to the p-type impurity-added region and includes an n-type diffusion layer that changes its charge amount when receiving light;
A p + -type diffusion layer 203 adjacent to the p-type impurity doped region and the n-type diffusion layer;
A pixel selection line 210 connected to the p + -type diffusion layer on the island-shaped semiconductor is formed,
An oxide film 251 is formed on the silicon substrate 250, and a signal line 245 is formed on the oxide film 251.
An island semiconductor is formed on the signal line, and the island semiconductor is
An n + -type diffusion layer 242 connected to the signal line below the island-shaped semiconductor;
A p-type impurity doped region 230 adjacent to the upper side of the n + -type diffusion layer;
A gate 233 connected to the p-type impurity doped region via an insulating film;
A charge storage unit 221 that is connected to the p-type impurity-added region and includes an n-type diffusion layer that changes its charge amount when receiving light;
A p + -type diffusion layer 209 adjacent to the p-type impurity doped region and the n-type diffusion layer;
A pixel selection line 212 connected to the p + -type diffusion layer on the island-like semiconductor is formed.
A pixel selection line 211 is wired between the pixel selection lines 210 and 212.
A gate 232 is wired between the gates 231 and 233.
An oxide film 246 is formed as an interlayer insulating film.

In addition, an oxide film 251 is formed on the silicon substrate 250, and a signal line 245 is formed on the oxide film 251.
An island semiconductor is formed on the signal line, and the island semiconductor is
An n + -type diffusion layer 242 connected to the signal line below the island-shaped semiconductor;
A p-type impurity doped region 230 adjacent to the upper side of the n + -type diffusion layer;
A gate 233 connected to the p-type impurity doped region via an insulating film;
A charge storage unit 221 that is connected to the p-type impurity-added region and includes an n-type diffusion layer that changes its charge amount when receiving light;
A p + -type diffusion layer 209 adjacent to the p-type impurity doped region and the n-type diffusion layer;
A pixel selection line 212 connected to the p + -type diffusion layer on the island-like semiconductor is formed.
An oxide film 251 is formed on the silicon substrate 250, and a signal line 244 is formed on the oxide film 251.
An island semiconductor is formed on the signal line, and the island semiconductor is
An n + -type diffusion layer 241 connected to the signal line below the island-shaped semiconductor;
A p-type impurity doped region 229 adjacent to the upper side of the n + -type diffusion layer;
A gate 233 connected to the p-type impurity doped region via an insulating film;
A charge accumulating unit 220 formed of an n-type diffusion layer connected to the p-type impurity-added region and changing a charge amount when receiving light;
A p + -type diffusion layer 208 adjacent to the p-type impurity doped region and the n-type diffusion layer;
A pixel selection line 212 connected to the p + -type diffusion layer on the island-like semiconductor is formed.
An oxide film 251 is formed on the silicon substrate 250, and a signal line 243 is formed on the oxide film 251.
An island semiconductor is formed on the signal line, and the island semiconductor is
An n + -type diffusion layer 240 connected to the signal line below the island-shaped semiconductor;
A p-type impurity doped region 228 adjacent to the upper side of the n + -type diffusion layer;
A gate 233 connected to the p-type impurity doped region via an insulating film;
A charge accumulating unit 219 connected to the p-type impurity doped region and made of an n-type diffusion layer whose charge amount changes upon receiving light;
A p + -type diffusion layer 207 adjacent to the p-type impurity doped region and the n-type diffusion layer;
A pixel selection line 212 connected to the p + -type diffusion layer on the island-like semiconductor is formed.
An oxide film 246 is formed as an interlayer insulating film.

In the example, the island-shaped semiconductor used a solid-state imaging device having a cylindrical shape.
As shown in FIG. 18, the island-shaped semiconductor 820 may be a solid-state imaging device having a hexagonal column shape.

Further, in the embodiment, the adjacent first solid-state image pickup element array, the adjacent second solid-state image pickup element array, and the third solid-state image pickup element array in which the island-shaped semiconductor has a cylindrical shape have a vertical pixel pitch of √3. / Although the solid-state image pickup device is arranged at a doubled interval (horizontal pixel pitch HP), that is, the solid-state image pickup device has a structure arranged in a so-called honeycomb shape,
As shown in FIG. 19, island-shaped semiconductors 821, 822, 823, 824, 825, 826, 827, 828, and 829 are cylindrical, and the solid-state imaging device is arranged in n rows and m columns (n and m are 1 or more). It is good also as a solid-state image sensor matrix (solid-state imaging device) arranged with respect to a substrate.

Further, in the embodiment, the adjacent first solid-state image pickup element array, the adjacent second solid-state image pickup element array, and the third solid-state image pickup element array in which the island-shaped semiconductor has a cylindrical shape have a vertical pixel pitch of √3. / Although the solid-state image pickup device is arranged at a doubled interval (horizontal pixel pitch HP), that is, the solid-state image pickup device has a structure arranged in a so-called honeycomb shape,
As shown in FIG. 20, the island-shaped semiconductors 830, 831, 832, 833, 834, 835, 836, 837, and 838 have a quadrangular prism shape, and the solid-state imaging device has n rows and m columns (n and m are 1 or more). It is good also as a solid-state image sensor matrix (solid-state imaging device) arranged with respect to a substrate.
Thus, the shape of the solid-state imaging device may be a cylinder, a hexagonal column, or a quadrangular column. Furthermore, the shape of the solid-state imaging device may be a polygonal column having five or more sides. In addition, the arrangement of the solid-state imaging device on the substrate may be a honeycomb shape or a matrix shape depending on the column shape of the island-shaped semiconductor layer. What is important is that the solid-state imaging elements are arranged on the substrate in correspondence with the column shape of the solid-state imaging element so that the density when the solid-state imaging elements are arranged on the substrate is higher. The ratio of the surface area of the light receiving portion of the solid-state image sensor to the surface area of one pixel of the solid-state image sensor matrix (solid-state image pickup device) is obtained by arranging the solid-state image sensors on the substrate in correspondence with the column shape of the solid-state image sensor. Can be increased.

Hereinafter, an example of a manufacturing process for forming the structure of the solid-state imaging device according to the present invention will be described with reference to FIGS.

21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69 , 71, 73, 75, 77, 79 are TOP Views.
22 (a), 24 (a), 26 (a), 28 (a), 30 (a), 32 (a), 34 (a), 36 (a), 38 (a), 40 (a) , 42 (a), 44 (a), 46 (a), 48 (a), 50 (a), 52 (a), 54 (a), 56 (a), 58 (a), 60 (a) 62 (a), 64 (a), 66 (a), 68 (a), 70 (a), 72 (a), 74 (a), 76 (a), 78 (a), 80 (a) Corresponds to the X ₃ -X ₃ ′ section of TOP View.
22 (b), 24 (b), 26 (b), 28 (b), 30 (b), 32 (b), 34 (b), 36 (b), 38 (b), 40 (b) 42 (b), 44 (b), 46 (b), 48 (b), 50 (b), 52 (b), 54 (b), 56 (b), 58 (b), 60 (b) 62 (b), 64 (b), 66 (b), 68 (b), 70 (b), 72 (b), 74 (b), 76 (b), 78 (b), 80 (b) Corresponds to the Y ₃ -Y ₃ ′ section of TOP View.
First, an oxide film 251 is formed on a silicon substrate 250, p-type silicon 501 is formed on the oxide film 251, and a nitride film (SiN) 502 is deposited on the p-type silicon 501 to form a silicon oxide film 503. (FIGS. 21, 22 (a) and (b)).

A resist is formed, oxide film etching is performed, nitride film etching is performed, and the resist is peeled off to form nitride film masks 580, 581 and 582, and oxide film masks 504, 505 and 506 (FIGS. 23 and 24A). (B)).

The p-type silicon is etched to form signal lines 243, 244, 245 (FIGS. 25, 26 (a), (b)).

Resist 507, 508, 509, 510, 511, 512, 513, 514, 515 is formed (FIGS. 27, 28 (a), (b)).

Oxide films and nitride films are etched to form oxide film masks 583, 584, 585, 586, 587, 588, 589, 590, 591, nitride film masks 592, 593, 594, 595, 596, 597, 598, 599, 600. (FIGS. 29, 30 (a), (b)).

The resist is removed (FIGS. 31, 32 (a) and (b)).

The p-type silicon is etched to form island-like semiconductors 516, 517, 518, 519, 520, 521, 522, 523, and 524 (FIGS. 33, 34 (a), (b)).

An oxide film 525 is deposited, planarized, and etched back (FIGS. 35, 36 (a), (b)).

Oxidation is performed to form oxide films 526, 527, 528, 529, 530, 531, 532, 533, 534 (FIGS. 37, 38 (a), (b)).

In order to use as a mask for ion implantation, polysilicon is deposited, etched back, and left in the form of sidewalls 535, 536, 537, 538, 539, 540, 541, 542, 543. (FIGS. 39, 40 (a), (b)).

The oxide film is peeled off, and the place where phosphorus is implanted is exposed (FIGS. 41, 42 (a), (b)).

Oxide films 601, 602, 603 are formed to prevent ion channeling during ion implantation (FIGS. 43, 44 (a), (b)).

Phosphorus is ion-implanted and annealed to form signal lines 243, 244, 245 and n + -type diffusion layers 234, 235, 236, 237, 238, 239, 240, 241, 242 (FIGS. 45 and 46 (a ), (B)).

The polysilicon and the oxide film are peeled off (FIGS. 47, 48 (a) and (b)).

An oxide film is deposited, planarized, and etched back to form an oxide film layer 544 (FIGS. 49, 50 (a), (b)).

Gate oxidation is performed to form gate oxide films 545, 546, 547, 548, 549, 550, 551, 552, 553, polysilicon 554 is deposited, planarized, and etched back (FIGS. 51 and 52). a), (b)).

Resists 555, 556, and 557 for gates (reset lines) are formed (FIGS. 53, 54 (a) and (b)).

The polysilicon is etched to form gates (reset lines) 231, 232, 233 (FIGS. 55, 56 (a), (b)).

The resist is removed (FIGS. 57, 58 (a) and (b)).

The thin oxide film on the side wall of the silicon pillar is peeled off, and then the silicon pillar side wall and the polysilicon of the gate are oxidized to form oxide films 604, 605, and 606 in order to prevent ion channeling during ion implantation. (FIGS. 59, 60 (a), (b)).

Phosphorus is implanted to form n-type diffusion layers 213, 214, 215, 216, 217, 218, 219, 220, and 221 (FIGS. 61, 62 (a) and (b)).

The nitride film is peeled off (FIGS. 63, 64 (a) and (b)).

An oxide film is deposited, planarized, and etched back to form an oxide film 246 (FIGS. 65, 66 (a) and (b)).

Oxidation is performed to prevent ion channeling during ion implantation to form oxide films 559, 560, 561, 562, 563, 564, 565, 566, and 567 (FIGS. 67, 68 (a) and (b)).

Boron is implanted and annealed to form p + -type diffusion layers 201, 202, 203, 204, 205, 206, 207, 208, and 209 (FIGS. 69, 70 (a), (b)).

The oxide film is peeled off (FIGS. 71, 72 (a) and (b)).

Metal 568 is deposited, planarized, and etched back (FIGS. 73, 74 (a), (b)).

Resist 569, 570 and 571 for pixel selection lines are formed (FIGS. 75, 76 (a) and (b)).

The metal is etched to form pixel selection lines 210, 211, and 212 (FIGS. 77, 78 (a), (b)).

The resist is peeled off to form a surface protective film 572 (FIGS. 79, 80 (a), (b)).

In the example,
The charge storage portion surrounds the p-type impurity doped region,
Although a solid-state imaging device having a structure in which the gate surrounds the p-type impurity doped region via an insulating film,
As shown in FIG. 81, the gate 655 may surround a part of the p-type impurity added region 652 with an insulating film interposed therebetween.
81 is a bird's-eye view showing another embodiment according to the present invention, FIG. 82 (a) is a cross-sectional view taken along line X ₄ -X ₄ ′ of FIG. 81, and FIG. 82 (b) is FIG. 82 (a). 83A is a sectional view taken along the line Y ₄ -Y ₄ ′ of FIG. 81, and FIG. 83B is an equivalent circuit diagram of FIG. 83A.
An oxide film 661 is formed on the silicon substrate 660, and a signal line 654 is formed on the oxide film 661.
An island semiconductor is formed on the signal line, and the island semiconductor is
An n + -type diffusion layer 653 connected to the signal line below the island-shaped semiconductor;
A p-type impurity doped region 652 adjacent to the upper side of the n + -type diffusion layer;
A gate 655 connected to the p-type impurity doped region via an insulating film;
A charge storage unit 651 composed of an n-type diffusion layer connected to the p-type impurity-added region and having a charge amount that changes upon receiving light;
A p + -type diffusion layer 650 adjacent to the p-type impurity doped region and the n-type diffusion layer;
A pixel selection line 656 connected to the p + -type diffusion layer on the island-like semiconductor is formed.
An oxide film 657 is formed as an interlayer insulating film.
The p + -type diffusion layer 650 and the n-type diffusion layer 651 function as a photoelectric conversion photodiode 664,
The p + -type diffusion layer 650, the n-type diffusion layer 651, and the p-type impurity added region 652 function as an amplifying transistor 665,
The n + -type diffusion layer 653, the p-type impurity addition region 652, the n-type diffusion layer 651, and the gate 655 function as the reset transistor 663,
The p-type impurity doped region 652 and the n + -type diffusion layer 653 function as a diode 662.
As shown in FIG. 84, the charge storage portion 751 surrounds a part of the p-type impurity addition region 752,
The gate 755 may surround a part of the p-type impurity addition region 752 through the insulating film.
84 is a bird's-eye view showing another embodiment according to the present invention, FIG. 85 (a) is a cross-sectional view taken along line X ₅ -X ₅ ′ of FIG. 84, and FIG. 85 (b) is FIG. 86A is a cross-sectional view taken along the line Y ₅ -Y ₅ ′ of FIG. 84, and FIG. 86B is an equivalent circuit diagram of FIG. 86A.
An oxide film 761 is formed on the silicon substrate 760, and a signal line 754 is formed on the oxide film 761,
An island semiconductor is formed on the signal line, and the island semiconductor is
An n + -type diffusion layer 753 connected to the signal line below the island-shaped semiconductor;
A p-type impurity doped region 752 adjacent to the upper side of the n + -type diffusion layer;
A gate 755 connected to the p-type impurity doped region via an insulating film;
A charge storage unit 751 connected to the p-type impurity addition region and made of an n-type diffusion layer whose charge amount changes upon receiving light;
A p + -type diffusion layer 750 adjacent to the p-type impurity doped region and the n-type diffusion layer;
A pixel selection line 756 connected to the p + type diffusion layer on the island-like semiconductor is formed.
An oxide film 757 is formed as an interlayer insulating film.
The p + -type diffusion layer 750 and the n-type diffusion layer 751 function as a photoelectric conversion photodiode 764.
The p + -type diffusion layer 750, the n-type diffusion layer 751, and the p-type impurity added region 752 function as an amplifying transistor 765,
The n + -type diffusion layer 753, the p-type impurity addition region 752, the n-type diffusion layer 751 and the gate 755 function as the reset transistor 763.
The p-type impurity doped region 752 and the n + -type diffusion layer 753 function as the diode 762.

In the present invention,
An amplifying transistor comprising a junction transistor in which a gate and a source function as a photoelectric conversion photodiode, a gate functions as a charge storage unit, and amplifies the charge in the charge storage unit;
A reset transistor composed of a MOS transistor having a source connected to the gate of the amplifying transistor and resetting the charge storage unit;
A diode having an anode connected to the drain of the amplifying transistor and a cathode connected to the drain of the reset transistor;
A pixel selection line connected to the source of the amplifying transistor;
A signal line connected to the cathode of the diode;
It is a solid-state image sensor comprised by these.
That is, since the photoelectric conversion unit, the amplification unit, the pixel selection unit, and the reset unit are configured by a total of three elements, that is, an amplifying transistor composed of a junction transistor, a reset transistor composed of a MOS transistor, and a diode, the number of elements in one pixel Can be reduced.

In the present invention,
A signal line formed on the substrate;
An island-shaped semiconductor disposed on the signal line;
A solid-state imaging device including a pixel selection line connected to an upper portion of the island-shaped semiconductor,
The island-shaped semiconductor is
A first semiconductor layer disposed under the island-shaped semiconductor and connected to the signal line;
A second semiconductor layer adjacent to the upper side of the first semiconductor layer;
A gate connected to the second semiconductor layer via an insulating film;
The charge accumulating unit comprising a third semiconductor layer connected to the second semiconductor layer, the charge amount of which changes upon receiving light;
There is provided a solid-state imaging device including the second semiconductor layer and a fourth semiconductor layer adjacent to the upper side of the third semiconductor layer and connected to the pixel selection line.
The third semiconductor layer and the fourth semiconductor layer function as a photoelectric conversion photodiode,
The second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer function as an amplifying transistor,
The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the gate function as a reset transistor.
Accordingly, since the photoelectric conversion unit, the amplification unit, the pixel selection unit, and the reset unit are realized by the area of the photodiode, an image sensor in which the ratio of the surface area of the light receiving unit to the surface area of one pixel is made possible.

The ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel of the conventional CMOS image sensor was 30%. The ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel when the image sensors of the present invention are arranged in a matrix is estimated. FIG. 87 is a plan view in which the image sensors 901, 902, 903, 904, 905, 906, 907, 908, and 909 of the present invention having cylindrical island-shaped semiconductors are arranged in a matrix, and FIG. FIG. 5 is an enlarged plan view showing a light receiving unit 911 and a pixel selection line 910. F is a wiring rule. The surface area per pixel was 2 μm × 2 μm, and a 0.15 μm wiring rule process was used. The surface area of the light receiving part (photodiode) is 3.14 × 0.85 μm × 0.85 μm. The ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel when the image sensors of the present invention having cylindrical island-shaped semiconductors are arranged in a matrix is 56.7%.
FIG. 89 is a plan view in which image sensors 912, 913, 914, 915, 916, 917, 918, 919, and 920 of the present invention having a quadrangular prism-shaped island-like semiconductor are arranged in a matrix, and FIG. Is an enlarged plan view showing a light receiving portion 922 and a pixel selection line 921. F is a wiring rule. The surface area per pixel was 2 μm × 2 μm, and a 0.15 μm wiring rule process was used. The surface area of the light receiving part (photodiode) is 1.7 μm × 1.7 μm. The ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel when the image sensors of the present invention having a square pillar-shaped island-shaped semiconductor are arranged in a matrix is 72.25%. That is, since the unit pixel of the image sensor is realized by the area of the photodiode, an image sensor in which the ratio of the surface area of the light receiving unit to the surface area of one pixel is made possible.

Further, in the solid-state imaging device, by arranging the solid-state imaging elements on the substrate in a honeycomb shape, an image sensor in which the ratio of the surface area of the light receiving unit to the surface area of one pixel is made possible.

The ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel when the image sensor of the present invention is arranged in a honeycomb shape is estimated. FIG. 91 is a plan view in which the image sensors 923, 924, 925, 926, 927, 928, 929, 930, and 931 of the present invention having cylindrical island-shaped semiconductors are arranged in a honeycomb shape, and FIG. FIG. 6 is an enlarged plan view showing a light receiving unit 933 and a pixel selection line 932. F is a wiring rule. The radius of the photodiode was 0.85 μm and a 0.15 μm wiring rule process was used. The surface area of the light receiving part (photodiode) is 3.14 × 0.85 μm × 0.85 μm. The surface area of one pixel is 6 × (1 μm × 2 / √3 μm) / 2. The ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel when the image sensors of the present invention having cylindrical island-shaped semiconductors are arranged in a matrix is 65.5%. FIG. 93 is a plan view in which the image sensors 934, 935, 936, 937, 938, 939, 940, 941, 942 of the present invention having hexagonal columnar island-shaped semiconductors are arranged in a honeycomb shape, and FIG. Is an enlarged plan view showing a light receiving portion 944 and a pixel selection line 943. F is a wiring rule. The surface area of one pixel was set to 6 × (1 μm × 2 / √3 μm) / 2, and a 0.15 μm wiring rule process was used. The surface area of the light receiving portion (photodiode) is 6 × (0.85 μm × 2 × 0.85 / √3 μm) / 2. The surface area of one pixel is 6 × (1 μm × 2 / √3 μm) / 2. The ratio of the surface area of the light receiving portion (photodiode) to the surface area of one pixel when the image sensors of the present invention having hexagonal columnar island-shaped semiconductors are arranged in a matrix is 72.25%. That is, by arranging in a honeycomb shape, an image sensor in which the ratio of the surface area of the light receiving portion to the surface area of one pixel can be made large.

5. Photoelectric conversion photodiode 11. Pixel selection clock line 12. Reset clock line 13. Signal line 14. Power supply line 101. Amplification transistor 102. Reset transistor 103. Selection transistor 114. Reset power supply line 150. p + Type diffusion layer 151. Charge storage portion 152. P-type impurity doped region 153. n + type diffusion layer 154. Signal line 155. Gate 156. Pixel selection line 157. Oxide film 160. Silicon substrate 161. Oxide film 162. Diode 163 Reset transistor 164. Photoelectric conversion photodiode 165. Amplification transistor 201. p + type diffusion layer 202. p + type diffusion layer 203. p + type diffusion layer 204. p + type diffusion layer 205. p + type diffusion layer 206. p + type diffusion layer 207. p + type diffusion layer 208. p + type diffusion layer 209. p + type diffusion layer 210. Pixel selection line 211. Pixel selection line 212. Pixel selection line 213. Charge storage unit 214. Charge storage unit 215. Charge storage unit 216. Charge storage unit 217. Charge storage unit 218. Charge storage unit 219. Charge storage unit 220. Charge storage unit 221. Charge storage part 222. p-type impurity added region 223. p-type impurity added region 224. p-type impurity added region 225. p-type impurity added region 226. p-type impurity added region 227. p-type impurity added region 228. p-type impurity Addition region 229. p-type impurity addition region 230. p-type impurity addition region 231. Gate 232. Gate 233. Gate 234. n + type diffusion layer 235. n + type diffusion layer 236. n + type diffusion layer 237. n + N + type diffusion layer 239. n + type diffusion layer 240. n + type diffusion layer 241. n + type diffusion layer 242. n + type diffusion layer 243. signal line 244. signal line 245. signal line 246. Oxide film 250. Silicon substrate 251. Oxide film 401. Photodiode 402. Charge storage unit 403. Amplifying transistor 404. Pixel selection line 405. Reset transistor 406. Gate (reset line)
407. Signal line 408. Read current Iread
409. Diode 501. P-type silicon 502. Nitride film (SiN)
503. Silicon oxide film 504. Mask 505. Mask 506. Mask 507. Resist 508. Resist 509. Resist 510. Resist 511. Resist 512. Resist 513. Resist 514. Resist 515. Resist 516. Island-like semiconductor 517. Island-like semiconductor Semiconductor 518. Island semiconductor 519. Island semiconductor 520. Island semiconductor 521. Island semiconductor 522. Island semiconductor 523. Island semiconductor 524. Island semiconductor 525. Oxide film 526. Oxide film 527. Oxide film 528. Oxide film 529. Oxide film 530. Oxide film 531. Oxide film 532. Oxide film 533. Oxide film 534. Oxide film 535. Side wall 536. Side wall 537. Side wall 538. Side wall 539. Side wall 540. Side wall 541. Sidewall 542. Sidewall 543. Sidewall 544. Oxide layer 545. Gate oxide 546. Gate oxide 547. Gate oxide 548. Gate oxide 549. Gate oxide 550. Gate oxide 551. Gate oxide 552. Gate oxide 553. Gate Oxide film 554. Polysilicon 555. Resist 556. Resist 557. Resist 559. Oxide film 560. Oxide film 561. Oxide film 562. Oxide film 563. Oxide film 564. Oxide film 565. Oxide film 566. Oxide film 567. Oxide film 567. Oxide film 567 Film 568. metal 569. resist 570. resist 571. resist 572. surface protective film 580. nitride film mask 581. nitride film mask 582. nitride film mask 583. oxide film mask 584. oxide film mask 585. oxide film mask 586. Oxide mask 587. Oxide mask 588. Oxide mask 589. Oxide mask 590. Acid Oxide mask 592. Nitride mask 593. Nitride mask 595. Nitride mask 596. Nitride mask 597. Nitride mask 598. Nitride mask 599. Nitride mask 600. Oxide film 602. Oxide film 603. Oxide film 604. Oxide film 605. Oxide film 606. Oxide film 650. P + type diffusion layer 651. Charge storage portion 652. P type impurity added region 653. N + type Diffusion layer 654. Signal line 655. Gate 656. Pixel selection line 657. Oxide film 660. Silicon substrate 661. Oxide film 662. Diode 663. Reset transistor 664. Photoelectric conversion photodiode 665. Amplification transistor 750. p + type Diffusion layer 751. Charge storage portion 752. P-type impurity doped region 753. N + type diffusion layer 754. Signal line 755. Gate 756. Pixel selection line 757. Oxide film 760. Silicon substrate 761. Oxide film 762. Diode 763. Reset transistor 764. Photodiode for conversion 765. Amplification transistor 820. Island-like semiconductor 821. Island-like semiconductor 822. Island-like semiconductor 823. Island Semiconductor 824. Island Semiconductor 825. Island Semiconductor 826. Island Semiconductor 827. Island Semiconductor 828. Island Semiconductor 829. Island Semiconductor 830. Island Semiconductor 831. Island Semiconductor 832. Island Semiconductor 833. Island Semiconductor 834. Island Semiconductor 835. Island Semiconductor 836. Island Semiconductor 837. Island Semiconductor 838. Island Semiconductor 901. Image Sensor 902. Image Sensor 903. Image Sensor 904. Image Sensor 905. Image Sensor 906. Image sensor 907. Image sensor 908. Image sensor 909. Image sensor 910. Pixel selection line 911. Light receiving unit 912. Image sensor 913. Image sensor 914. Image sensor 915. Image sensor 916. Image sensor 917. Image sensor 918. Image sensor 919. Image sensor 920. Image sensor 921. Pixel Selection line 922. Light receiving unit 923. Image sensor 924. Image sensor 925. Image sensor 926. Image sensor 927. Image sensor 928. Image sensor 929. Image sensor 930. Image sensor 931. Image sensor 932. Pixel selection line 933. Light reception 934. Image sensor 935. Image sensor 936. Image sensor 937. Image sensor 938. Image sensor 939. Image sensor 940. Image sensor 941. Image sensor 94 . The image sensor 943. The pixel selection line 944. receiving portion

Claims (13)

A solid-state imaging device including a solid-state imaging device arranged on a substrate,
The solid-state imaging device is
A signal line formed on the substrate;
An island-shaped semiconductor disposed on the signal line;
A pixel selection line connected to the upper part of the island-shaped semiconductor,
The island-shaped semiconductor is
A first semiconductor layer disposed under the island-shaped semiconductor and connected to the signal line;
A second semiconductor layer adjacent to the upper side of the first semiconductor layer;
A gate connected to the second semiconductor layer via an insulating film;
The charge accumulating unit comprising a third semiconductor layer connected to the second semiconductor layer, the charge amount of which changes upon receiving light;
A fourth semiconductor layer that is adjacent to the upper side of the second semiconductor layer and the third semiconductor layer and is connected to the pixel selection line,
A solid-state imaging device, wherein the solid-state imaging elements are arranged in a honeycomb shape on a substrate.   The signal line is an n + -type diffusion layer, the first semiconductor layer is an n + -type diffusion layer, the second semiconductor layer is a p-type impurity doped region, and the third semiconductor layer is n The solid-state imaging device according to claim 1, wherein the solid-state imaging device is a type diffusion layer, and the fourth semiconductor layer is a p + type diffusion layer. The p + -type diffusion layer and the n-type diffusion layer function as a photoelectric conversion photodiode,
The p + -type diffusion layer, the n-type diffusion layer, and the p-type impurity added region function as an amplifying transistor,
The n + -type diffusion layer, the p-type impurity doped region, the n-type diffusion layer and the gate of the first semiconductor layer function as a reset transistor,
The solid-state imaging device according to claim 2, wherein the p-type impurity added region and the n + -type diffusion layer function as a diode.   The solid-state imaging device according to claim 1, wherein the island-shaped semiconductor has a cylindrical shape.   The solid-state imaging device according to claim 1, wherein the island-shaped semiconductor has a hexagonal column shape. A solid-state imaging device including a solid-state imaging device arranged on a substrate,
The solid-state imaging device is
A signal line formed on the substrate;
An island-shaped semiconductor disposed on the signal line;
A pixel selection line connected to the upper part of the island-shaped semiconductor,
The island-shaped semiconductor is
A first semiconductor layer disposed under the island-shaped semiconductor and connected to the signal line;
A second semiconductor layer adjacent to the upper side of the first semiconductor layer;
A gate connected to the second semiconductor layer via an insulating film;
The charge accumulating unit comprising a third semiconductor layer connected to the second semiconductor layer, the charge amount of which changes upon receiving light;
A fourth semiconductor layer adjacent to the second semiconductor layer and above the third semiconductor layer and connected to the pixel selection line;
The solid-state imaging device is arranged in a matrix as n rows and m columns (n and m are 1 or more) on the substrate,
The island-shaped semiconductor is a solid-state imaging device having a cylindrical shape. A solid-state imaging device including a solid-state imaging device arranged on a substrate,
The solid-state imaging device is
A signal line formed on the substrate;
An island-shaped semiconductor disposed on the signal line;
A pixel selection line connected to the upper part of the island-shaped semiconductor,
The island-shaped semiconductor is
A first semiconductor layer disposed under the island-shaped semiconductor and connected to the signal line;
A second semiconductor layer adjacent to the upper side of the first semiconductor layer;
A gate connected to the second semiconductor layer via an insulating film;
The charge accumulating unit comprising a third semiconductor layer connected to the second semiconductor layer, the charge amount of which changes upon receiving light;
A fourth semiconductor layer adjacent to the second semiconductor layer and above the third semiconductor layer and connected to the pixel selection line;
The solid-state imaging device is arranged in a matrix as n rows and m columns (n and m are 1 or more) on the substrate,
The island-shaped semiconductor is a solid-state imaging device having a quadrangular prism shape.   The signal line is an n + -type diffusion layer, the first semiconductor layer is an n + -type diffusion layer, the second semiconductor layer is a p-type impurity doped region, and the third semiconductor layer is n The solid-state imaging device according to claim 6, wherein the solid-state imaging device is a p-type diffusion layer, and the fourth semiconductor layer is a p + -type diffusion layer. The p + -type diffusion layer and the n-type diffusion layer function as a photoelectric conversion photodiode,
The p + -type diffusion layer, the n-type diffusion layer, and the p-type impurity added region function as an amplifying transistor,
The n + -type diffusion layer, the p-type impurity doped region, the n-type diffusion layer and the gate of the first semiconductor layer function as a reset transistor,
The solid-state imaging device according to claim 8, wherein the p-type impurity doped region and the n + -type diffusion layer function as a diode. A method of manufacturing a solid-state imaging device,
Forming a signal line on the substrate;
Forming an island semiconductor on the signal line;
Forming a first semiconductor layer connected to the signal line under the island-shaped semiconductor;
Forming a second semiconductor layer adjacent to the upper side of the first semiconductor layer;
Forming a gate connected to an adjacent second semiconductor layer on the first semiconductor layer via an insulating film;
Forming a third semiconductor layer connected to the second semiconductor layer;
Forming a fourth semiconductor layer adjacent to an upper side of the second semiconductor layer and the third semiconductor layer;
Forming a pixel selection line connected to the fourth semiconductor layer;
The manufacturing method of the solid-state image sensor as described in any one of Claim 1 to 9 characterized by the above-mentioned. A method of manufacturing a solid-state imaging device,
P-type silicon is formed on the oxide film, a nitride film is deposited on the p-type silicon, a silicon oxide film is deposited,
Forming a resist, performing oxide film etching, performing nitride film etching, stripping the resist, forming an oxide film mask and a nitride film mask for forming a signal line;
etching p-type silicon to form a signal line;
Forming a resist to form an island-shaped semiconductor;
Etch oxide film, nitride film,
Strip the resist,
etching p-type silicon to form an island-shaped semiconductor;
Deposit oxide film, planarize, etch back,
Oxidize to form an oxide film,
In order to make a mask at the time of ion implantation, a process of depositing polysilicon, etching back, and leaving it in a sidewall shape;
Exfoliate the oxide film and expose the area where phosphorus is implanted,
An oxide film is formed to prevent ion channeling during ion implantation.
Implanting phosphorus, performing a thermal process, and forming a signal line and an n + -type diffusion layer;
Strip polysilicon and oxide film,
Deposit oxide, planarize, etch back, form oxide layer,
Perform gate oxidation to form a gate oxide film, deposit polysilicon, planarize, etch back,
Forming a resist for the gate,
Etching polysilicon to form a gate;
Strip the resist,
The thin oxide film on the side wall of the silicon pillar is peeled off, and in order to prevent ion channeling during ion implantation, the silicon pillar side wall and gate polysilicon are oxidized to form an oxide film.
Injecting phosphorus to form an n-type diffusion layer;
Strip the nitride film,
Deposit oxide, planarize, etch back, form oxide layer,
Oxidize to prevent ion channeling during ion implantation, form an oxide film,
Injecting boron and performing a thermal process to form a p + -type diffusion layer;
Strip the oxide film,
Deposit metal, planarize, etch back,
Forming a resist for the pixel selection line;
Etching the metal to form pixel selection lines;
The method for manufacturing a solid-state imaging device according to claim 10, further comprising:   2. The solid-state imaging device according to claim 1, wherein a part of the second semiconductor layer has a columnar shape, and the gate surrounds an outer periphery of a part of the second semiconductor layer through the insulating film.   The solid-state imaging device according to claim 12, wherein another part of the second semiconductor layer has a cylindrical shape, and the third semiconductor layer surrounds an outer periphery of the other part of the second semiconductor layer. .

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