JP2013138196A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be produced by a self-aligned process, includes a source electrode and a drain electrode of low resistance, and achieve miniaturization while maintaining excellent electrical characteristics, and to provide a method of manufacturing the semiconductor device.SOLUTION: The method of manufacturing the semiconductor device comprises steps of: forming a gate electrode on an insulating surface; forming a gate insulating film which covers the gate electrode; and depositing a conductive film on the gate insulating film. A source electrode and a drain electrode, which do not overlap the gate electrode, are formed by performing removal processing such as chemical mechanical polishing on a part of the conductive film and exposing the gate insulating film.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  A technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, a transistor using an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) having an electron carrier concentration of less than 10 ¹⁸ / cm ³ as an active layer of the transistor is disclosed. (See Patent Document 1).

  Further, a transistor having a top gate structure in which a source region and a drain region are formed in a self-aligned manner by introducing ions into the active layer made of the oxide semiconductor as described above using a gate electrode as a mask is disclosed (patent) Reference 2).

JP 2006-165528 A JP 2007-220818 A

  However, in a top-gate transistor using an oxide semiconductor film as an active layer, when a source region and a drain region are formed by introducing ions into the oxide semiconductor film to reduce the resistance of the oxide semiconductor film, a channel region is formed. A resistance is generated between the source electrode (or the drain electrode) (also referred to as an offset region or a Loff region), and it is difficult to reduce the resistance. Then, the on-state current, which is one of the electrical characteristics of the transistor, is reduced.

  In addition, in a structure in which a gate electrode and a source electrode (or a drain electrode) without a Loff region overlap with each other, parasitic capacitance is generated, which hinders high-speed operation of the transistor. In the above structure, the electric field concentrates on the channel region and the source electrode end (or the drain electrode end), and the carriers flowing into the oxide semiconductor film are accelerated by the high electric field to obtain high energy. Some of the carriers enter the insulating film and are trapped in the film, resulting in “hot carrier deterioration” in which electrical characteristics such as a threshold value are deteriorated, and the off-state current of the transistor is increased.

  Therefore, the present invention may solve at least one of the above problems. For example, an object is to provide a transistor with low reduction in on-state current. Another object is to provide a transistor that can operate at high speed. Another object is to provide a highly reliable transistor with little deterioration. Another object is to provide a transistor with low off-state current.

  In order to achieve the above object, a transistor having a semiconductor structure including an oxide semiconductor film (semiconductor device) employs a bottom-gate transistor in one embodiment of the present invention. Hereinafter, a specific configuration of the present invention will be described.

  One embodiment of the present invention includes a gate electrode provided over an insulating surface, a gate insulating film covering the gate electrode, a source electrode sandwiching the gate electrode through the gate insulating film and not overlapping with an upper surface of the gate electrode, A semiconductor device includes a drain electrode and an oxide semiconductor film which is provided so as to overlap with the gate electrode with a gate insulating film interposed therebetween and which is in contact with at least part of the source electrode and the drain electrode.

  Another embodiment of the present invention is the above structure, in which the oxide semiconductor film is provided over the gate insulating film, the source electrode, and the drain electrode.

  Another embodiment of the present invention is the above structure, in which the oxide semiconductor film is sandwiched between the source electrode and the drain electrode.

  Another embodiment of the present invention is provided with a base insulating film, a gate electrode embedded in the base insulating film and having at least a part of the upper surface exposed from the base insulating film, and at least over the gate electrode The gate insulating film does not overlap with the gate electrode, and the source electrode and the drain electrode provided on the gate insulating film overlap with at least the gate electrode, at least a part of which is in contact with the source electrode and the drain electrode, and on the gate insulating film An oxide semiconductor film provided on the semiconductor device.

  According to another embodiment of the present invention, in the above structure, the heights of the upper surfaces of the source electrode and the drain electrode and the upper surface of the film (gate insulating film or oxide semiconductor film) sandwiched between the source electrode and the drain electrode are Is complete.

  In another embodiment of the present invention, a gate electrode is formed over an insulating surface, a gate insulating film covering the gate electrode is formed, a conductive film is formed over at least the gate insulating film, and the gate insulating film is exposed. Thus, a part of the conductive film is subjected to removal treatment, the removed conductive film is processed to form a source electrode and a drain electrode, and an oxide semiconductor film is formed over the gate insulating film, the source electrode, and the drain electrode This is a method for manufacturing a semiconductor device.

  In another embodiment of the present invention, a gate electrode is formed over an insulating surface, a gate insulating film covering the gate electrode is formed, an oxide semiconductor film is formed at least over the gate insulating film, and the gate insulating film and A conductive film is formed over the oxide semiconductor film, a portion of the conductive film is removed so that the oxide semiconductor film is exposed, and the removed conductive film is processed to form a source electrode and a drain electrode This is a method for manufacturing a semiconductor device.

  In another embodiment of the present invention, a base insulating film having a recess is formed, a first conductive film is formed over the base insulating film, and the first conductive film is exposed so that the base insulating film is exposed. Removing a portion, forming a gate electrode in a recess of the base insulating film, forming a gate insulating film on at least the gate electrode, forming a second conductive film on the gate insulating film, performing backside exposure, A resist mask is formed over the second conductive film that does not overlap with the gate electrode, and a source electrode and a drain electrode are formed over the gate insulating film that does not overlap with the gate electrode using the resist mask, and at least the gate electrode overlaps with the gate electrode This is a method for manufacturing a semiconductor device in which an oxide semiconductor film is formed over an insulating film.

  In another embodiment of the present invention, a gate electrode is formed over an insulating surface, a base insulating film is formed over the gate electrode, and a part of the base insulating film is removed so that the gate electrode is exposed. Forming a gate insulating film on at least the gate electrode; forming an oxide semiconductor film on the gate insulating film; performing backside exposure; forming a resist mask on the oxide semiconductor film overlapping with the gate electrode; An island-shaped oxide semiconductor film is formed over the gate insulating film overlapping with the gate electrode, and a conductive film is formed over the gate insulating film and the island-shaped oxide semiconductor film. In this method, a part of the conductive film is subjected to a removal process so that the film is exposed, and the removed conductive film is processed to form a source electrode and a drain electrode.

  Another embodiment of the present invention is the above manufacturing method, in which the removal treatment may be performed by chemical mechanical polishing.

  In one embodiment of the present invention, a source electrode and a drain electrode can be formed by a self-alignment process without overlapping with a gate electrode.

  In addition, since there is a region where the gate electrode and the source electrode (or the drain electrode) do not overlap (also referred to as an offset region or a Loff region), electric field concentration at the channel region end and the Loff region end can be reduced; The current can be lowered, and the generation of hot carriers (hot carrier deterioration) can be reduced by the Loff region which is a high resistance region. In addition, the Loff region (high resistance region) can be controlled and the resistance contributing to the oxide semiconductor film can be reduced. Thus, the on-state current of the transistor can be increased.

  Further, if the Loff region is too long, it becomes a resistance component and the on-current decreases, so it is important to control the length of the Loff region. In one embodiment of the present invention, the Loff region can be determined by the thickness of the gate insulating film by a self-alignment process. Since the length of the Loff region having a higher resistance than the source electrode (or drain electrode) can be optimized, an increase in resistance generated between the channel region of the oxide semiconductor film and the source electrode (or drain electrode) is suppressed. be able to. Thus, the off-state current of the transistor is small, the on-state current can be increased, and reliability can be improved.

  In addition, it is possible to provide a semiconductor device that can reduce parasitic capacitance and achieve miniaturization while maintaining good electrical characteristics, and a manufacturing method thereof.

4A and 4B are a plan view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a manufacturing process of a semiconductor device of one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a manufacturing process of a semiconductor device of one embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. 4A and 4B are a plan view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a manufacturing process of a semiconductor device of one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a manufacturing process of a semiconductor device of one embodiment of the present invention. 4A and 4B are a plan view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a manufacturing process of a semiconductor device of one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a manufacturing process of a semiconductor device of one embodiment of the present invention. 4A and 4B are a plan view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a manufacturing process of a semiconductor device of one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a manufacturing process of a semiconductor device of one embodiment of the present invention. 9A to 9D are cross-sectional views illustrating a manufacturing process of a semiconductor device of one embodiment of the present invention. 4A and 4B are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 6 is a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. 9A and 9B are a cross-sectional view and a plan view illustrating one embodiment of a semiconductor device. FIG. 10 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 11 is a block diagram illustrating one embodiment of a semiconductor device. The top view and sectional drawing of the transistor used for evaluation.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in describing the structure of the present invention with reference to drawings, the same portions are denoted by the same reference numerals in different drawings. Moreover, when referring to the same thing, a hatch pattern is made the same and it may not attach | subject a code | symbol in particular. For convenience, the insulating film may not be shown in the top view.

  In the present specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the components is “directly above” or “directly below”. For example, the expression “a gate electrode over a gate insulating film” does not exclude an element including another component between the gate insulating film and the gate electrode.

  Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

  In addition, the functions of “source” and “drain” may be switched when transistors having different polarities are employed or when the direction of current changes in circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

  Note that in this specification and the like, “electrically connected” includes a case of being connected via “something having an electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets.

  For example, “thing having some electric action” includes electrodes and wirings.

  In the following description, ordinal numbers such as first and second are given for convenience of description, and the number is not limited.

(Embodiment 1)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device which are one embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows a plan view and a cross-sectional view of the transistor 150. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along a line AB in FIG. 1A. Note that in FIG. 1A, some components of the transistor 150 (eg, the insulating film 110) are omitted to avoid complexity.

<Configuration of Semiconductor Device in this Embodiment>
FIG. 1 is a structural example of a semiconductor device manufactured by the method of this embodiment. 1 includes a gate electrode 102 provided over a substrate 100 having an insulating surface, a gate insulating film 104 covering at least the gate electrode 102, and the gate electrode 102 interposed therebetween. The source electrode 108a and the drain electrode 108b that do not overlap with the upper surface of the gate electrode 102 overlap with the gate electrode 102 with the gate insulating film 104 interposed therebetween, and are provided over the gate insulating film 104, the source electrode 108a, and the drain electrode 108b. The oxide semiconductor film 106, and the insulating film 110 provided over the oxide semiconductor film 106, the source electrode 108a, and the drain electrode 108b are provided.

  In the oxide semiconductor film 106, a region (Loff region) where the gate electrode 102 and the source electrode 108 a (or the drain electrode 108 b) do not overlap is determined by the thickness of the gate insulating film 104. Further, the Loff region of the oxide semiconductor film 106 functions as an electric field relaxation region with respect to the channel region. Therefore, generation of hot carriers can be suppressed, and variation in threshold voltage due to penetration of hot carriers into the gate insulating film can be reduced. In addition, off-state current of the transistor 150 can be reduced.

  Further, if the Loff region is too long, it becomes a resistance component and the on-current decreases, so it is important to control the length of the Loff region. In this embodiment, the length of the Loff region having higher resistance than the source electrode (or the drain electrode) can be optimized by adjusting the thickness of the gate insulating film 104; therefore, the channel region of the oxide semiconductor film And an increase in resistance between the source electrode (or the drain electrode) can be suppressed. Thus, the on-state current of the transistor 150 can be increased.

  In addition, since the gate electrode 102 and the source electrode 108a (or the drain electrode 108b) do not overlap with each other, parasitic capacitance can be reduced and the transistor 150 can be driven at high speed.

<Method for Manufacturing Semiconductor Device in this Embodiment>
A method for manufacturing the transistor 150 is described with reference to FIGS.

  First, the gate electrode 102 is formed over the substrate 100 (see FIG. 2A).

  As the substrate 100, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used. For mass production, it is preferable to use a mother glass of the eighth generation (2160 mm × 2460 mm), the ninth generation (2400 mm × 2800 mm, or 2450 mm × 3050 mm), the tenth generation (2950 mm × 3400 mm), or the like. Since the mother glass has a high processing temperature and contracts significantly when the processing time is long, when mass production is performed using the mother glass, the heat treatment in the manufacturing process is 700 ° C. or less, preferably 450 ° C. or less, more preferably Is preferably 350 ° C. or lower.

  Next, after a conductive film is formed over the substrate 100, the gate electrode 102 is formed by a photolithography process and an etching process. The gate electrode 102 is formed of a single layer, a single layer, a stacked layer of a single substance, a nitride, an oxide, or an alloy containing at least one of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta, and W. Use it. Alternatively, an oxide or oxynitride containing at least In and Zn may be used. For example, an In—Ga—Zn—O—N-based material or the like may be used.

  Alternatively, a base insulating film may be formed over the substrate 100, and the gate electrode 102 may be formed over the base insulating film.

  The base insulating film has a thickness of 50 to 600 nm by PE-CVD or sputtering, and is a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, Alternatively, a single layer selected from silicon nitride oxide films or a stacked film thereof is used. By the base insulating film, entry of impurities from the substrate 100 side can be suppressed.

  Note that in this specification, “oxynitride” such as silicon oxynitride refers to a composition having a higher oxygen content than nitrogen.

  Note that in this specification, a “nitride oxide” such as silicon nitride oxide means a composition having a nitrogen content higher than that of oxygen.

  Next, the gate insulating film 104 is formed over the substrate 100 and the gate electrode 102 (see FIG. 2B). Note that the gate insulating film 104 only needs to cover at least the gate electrode 102.

  As a material of the gate insulating film 104, silicon oxide, gallium oxide, aluminum oxide, zirconium oxide, yttrium oxide, hafnium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, or oxynitride It can be formed using silicon or the like.

  As the gate insulating film 104, an insulating film from which oxygen is released by heat treatment at a temperature of 250 ° C. to 700 ° C., preferably 300 ° C. to 450 ° C. is preferably used.

  In a transistor including an oxide semiconductor film, oxygen vacancies in the oxide semiconductor film serve as donors, which causes a shift in the threshold voltage of the transistor in the negative direction. Further, oxygen vacancies at the interface between the gate insulating film and the oxide semiconductor film trap electric charges due to operation of the transistor and the like, which causes variation in electric characteristics of the transistor. Therefore, reducing oxygen vacancies in the oxide semiconductor film and at the interface between the oxide semiconductor film and the gate insulating film stabilizes electrical characteristics and improves reliability of the transistor including the oxide semiconductor film. It leads to. Therefore, it is preferable that oxygen be released from the gate insulating film because oxygen vacancies in the oxide semiconductor film and at the interface between the oxide semiconductor film and the gate insulating film can be reduced.

“Release oxygen by heat treatment” means that the amount of released oxygen converted to oxygen atoms is 1.0 × 10 ¹⁹ atoms / in TDS (Thermal Desorption Spectroscopy) analysis. cm ³ or more, preferably 3.0 × 10 ¹⁹ atoms / cm ³ or more, more preferably 1.0 × 10 ²⁰ atoms / cm ³ or more, more preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. Say.

  Here, a method for measuring the amount of released oxygen converted into oxygen atoms in TDS analysis will be described below.

  The amount of gas released by TDS analysis is proportional to the integral value of the spectrum. For this reason, the amount of gas emission can be calculated from the ratio between the measured integral value of the spectrum and the reference value of the standard sample. The reference value of the standard sample is the ratio of the atomic density to the integral value of the spectrum in a sample having a predetermined atomic density.

For example, the amount of released oxygen molecules (N _O2 ) of the insulating film is obtained by the equation (1) from the TDS analysis result of a silicon wafer containing hydrogen of a predetermined density as a standard sample and the TDS analysis result of the insulating film. Can do. Here, it is assumed that all of the spectra detected when the mass-to-charge ratio (M / z) obtained by TDS is 32 are derived from oxygen molecules. There is CH ₃ OH in addition to M / z of 32, but it is not considered here as it is unlikely to exist. In addition, oxygen molecules containing an oxygen atom with an M / z of 17 and an oxygen atom with an M / z of 18 that are isotopes of oxygen atoms are not considered because their abundance ratio in nature is extremely small.

N _H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. _SH2 is an integral value of a spectrum obtained by TDS analysis of a standard sample. Here, the reference value of the standard sample is N _H2 / SH ₂ . S _O2 is an integral value of a spectrum obtained by TDS analysis of the insulating film. α is a coefficient that affects the spectral intensity in the TDS analysis. For details of the expression (1), refer to Japanese Patent Laid-Open No. 6-275697. Note that the oxygen release amount of the insulating film is a silicon wafer containing 1 × 10 ¹⁶ atoms / cm ² of hydrogen atoms as a standard sample using a temperature programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. Use to measure.

  In TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.

Note that N _{2 O 2} is the amount of released oxygen molecules. The amount of release when converted to oxygen atoms is twice the amount of release of oxygen molecules.

  Next, heat treatment for removing moisture, hydrogen, or the like may be performed on the substrate 100 over which the gate insulating film 104 is formed.

  Note that as the heat treatment, an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as an electric furnace or a resistance heating element can be used. For example, an RTA (Rapid Thermal Annial) apparatus such as an LRTA (Lamp Rapid Thermal Anneal) apparatus or a GRTA (Gas Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used.

  For example, as the heat treatment, a GRTA process may be performed in which an object to be processed is put in a heated inert gas atmosphere, heated for several minutes, and then the object to be processed is taken out from the inert gas atmosphere. When GRTA treatment is used, high-temperature heat treatment can be performed in a short time. In addition, application is possible even under temperature conditions exceeding the heat resistance temperature of the object to be processed. Note that the inert gas may be switched to a gas containing oxygen during the treatment. By performing heat treatment in an atmosphere containing oxygen, the defect density in the film can be reduced.

  Note that as the inert gas atmosphere, an atmosphere mainly containing nitrogen or a rare gas (such as helium, neon, or argon) and containing no moisture, hydrogen, or the like is preferably used. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less). , Preferably 0.1 ppm or less).

  When mother glass is used as the substrate 100, the heat treatment temperature is 200 ° C. or higher and 450 ° C. or lower, preferably 250 ° C. or higher and 350 ° C. or lower because the processing temperature is high and the processing time is significantly reduced. .

  Note that by heat treatment, impurities such as moisture and hydrogen in the gate insulating film 104 can be removed. Further, the density of defects in the film can be reduced by the heat treatment. When the impurity or defect density in the gate insulating film 104 is reduced, the electrical characteristics of the transistor are improved, and fluctuations in the electrical characteristics accompanying the operation of the transistor can be suppressed.

  By the way, since the heat treatment described above has an effect of removing moisture, hydrogen, and the like, the heat treatment can be referred to as dehydration treatment, dehydrogenation treatment, or the like. Further, such dehydration treatment and dehydrogenation treatment are not limited to one time, and may be performed a plurality of times.

  Next, a conductive film 107 to be a source electrode and a drain electrode (including a wiring formed using the same layer) is formed over the gate insulating film 104 (see FIG. 2C). The conductive film 107 may have a single-layer structure or a stacked structure. In this embodiment mode, a step is generated between the region 115a and the region 115b as illustrated in FIG.

  The conductive film 107 can be formed by a plasma CVD method, a sputtering method, or the like. The conductive film 107 is formed using a material that can withstand heat treatment performed later. As the conductive film 107, for example, a single layer, a nitride, an oxide, or an alloy including one or more of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta, and W, a single layer or a stacked layer Can be used. Alternatively, an oxide or oxynitride containing at least In and Zn may be used. For example, an In—Ga—Zn—O—N-based material or the like may be used.

  Next, by removing (polishing) the conductive film 107, part of the conductive film 107 is removed so that the gate insulating film 104 is exposed, so that the source electrode 108a and the drain electrode 108b are formed (FIG. 3B). A)).

  By the removal treatment, the conductive film 107 in a region overlapping with the gate electrode 102 is removed, and the source electrode 108a and the drain electrode 108b are formed in a self-aligning manner. As a removal method, it is preferable to use a chemical mechanical polishing (CMP) process.

  In this embodiment, as illustrated in FIG. 2C, the conductive film provided over the gate insulating film 104 is removed by using a step generated between the region 115a and the region 115b (specifically In this case, the source electrode 108a and the drain electrode 108b can be formed by CMP treatment.

  Note that in this embodiment, the heights of the upper surfaces of the source electrode 108a and the drain electrode 108b and the upper surface of the gate insulating film 104 are the same, but the present invention is not limited to this, and the upper surfaces of the source electrode 108a and the drain electrode 108b are insulated from the gate insulating film. The height of the upper surface of the film 104 may be slightly shifted.

  Note that although CMP treatment is used for removing the conductive film 107 in a region overlapping with the gate electrode 102 in this embodiment mode, other removal treatment may be used. Alternatively, polishing treatment such as CMP treatment, etching (dry etching, wet etching) treatment, plasma treatment, or the like may be combined. For example, after the CMP treatment, dry etching treatment or plasma treatment (reverse sputtering or the like) may be performed to improve the flatness of the treatment surface. In the case where the removal treatment is combined with an etching treatment, a plasma treatment, or the like, the order of steps is not particularly limited, and may be set as appropriate depending on the material, film thickness, and surface roughness of the conductive film 107. Alternatively, most of the conductive film 107 in the region 115b may be removed by CMP treatment, and the remaining conductive film 107 may be removed by dry etching treatment. By doing so, there is a film that can easily achieve an etching selection ratio between the conductive film 107 and the gate insulating film 104. Therefore, the gate insulating film 104 can be prevented from being thinned.

  The CMP process may be performed only once or a plurality of times. When performing the CMP process in a plurality of times, it is preferable to perform the final polishing at a low polishing rate after performing the primary polishing at a high polishing rate. By combining polishing with different polishing rates in this way, the flatness of the surface of the conductive film 107 can be further improved.

  Further, a part of the conductive film 107 is exposed so that the gate insulating film 104 is exposed by etching using a resist mask having an etching selectivity similar to that of the conductive film 107 instead of the CMP process. The source electrode 108a and the drain electrode 108b may be formed.

  In this embodiment mode, part of the conductive film 107 is removed and the conductive film 107 is processed to form the source electrode 108a and the drain electrode 108b. However, the present invention is not limited to this, and the conductive film 107 is processed first. The source electrode 108a and the drain electrode 108b may be formed by removing part of the conductive film 107 after processing.

  In this manner, by performing the removal process so that the gate insulating film 104 is exposed, the source electrode 108a and the drain electrode 108b can be formed in a self-aligning manner. Therefore, even when the channel length is reduced, the source electrode 108a and the drain electrode 108b can be formed without misalignment. Thus, a highly reliable semiconductor device can be manufactured.

  In the oxide semiconductor film 106, a region (Loff region) where the gate electrode 102 and the source electrode 108 a (or the drain electrode 108 b) do not overlap is determined by the thickness of the gate insulating film 104. Further, the Loff region of the oxide semiconductor film 106 functions as an electric field relaxation region with respect to the channel region. Therefore, generation of hot carriers can be suppressed, and variation in threshold voltage due to penetration of hot carriers into the gate insulating film can be reduced. In addition, off-state current of the transistor 150 can be reduced.

  In addition, by adjusting the thickness of the gate insulating film 104, the length of the Loff region having higher resistance than the source electrode (or the drain electrode) can be optimized; thus, the channel region and the source electrode ( In addition, an increase in resistance that occurs with the drain electrode) can be suppressed. Thus, the on-state current of the transistor 150 can be increased.

  In addition, since the gate electrode 102 and the source electrode 108a (or the drain electrode 108b) do not overlap with each other, parasitic capacitance can be reduced and the transistor 150 can be driven at high speed.

  Next, the oxide semiconductor film 106 is formed over the gate insulating film 104, the source electrode 108a, and the drain electrode 108b (see FIG. 3B).

  The oxide semiconductor film 106 is formed by a sputtering method, an MBE (Molecular Beam Epitaxy) method, a CVD method, a pulse laser deposition method, an ALD (Atomic Layer Deposition) method, or the like. Alternatively, the oxide semiconductor film 106 may be formed using a sputtering apparatus which performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target.

  When the oxide semiconductor film 106 is formed, it is preferable to reduce the concentration of hydrogen contained in the oxide semiconductor film 106 as much as possible. In order to reduce the concentration of hydrogen contained in the oxide semiconductor film 106, for example, when a film is formed using a sputtering method, hydrogen, water, a hydroxyl group, hydride, or the like is supplied as a gas supplied into the treatment chamber of the sputtering apparatus. It is preferable to use a high-purity rare gas (typically argon) from which the impurities are removed, oxygen, or a mixed gas of a rare gas and oxygen.

In addition, the concentration of hydrogen contained in the formed oxide semiconductor film 106 is reduced by introducing a gas from which hydrogen, water, and the like have been removed while removing residual moisture in the deposition chamber. be able to. In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, a turbo molecular pump provided with a cold trap may be used. A film formation chamber evacuated using a cryopump has a high exhaust capability such as a compound containing hydrogen atoms (more preferably a compound containing carbon atoms) such as water (H ₂ O). The concentration of impurities contained in the formed oxide semiconductor film 106 can be reduced.

  In the case where the oxide semiconductor film 106 is formed by a sputtering method, the relative density of the metal oxide target used for the film formation is 90% to 100%, preferably 95% to 99.9%. It is preferable. By using a metal oxide target having a high relative density, the formed oxide semiconductor film 106 can be a dense film.

  As a material for the oxide semiconductor film 106, for example, an In-M-Zn-O-based material may be used. Here, the metal element M is an element whose binding energy with oxygen is higher than that of In and Zn. Alternatively, the element has a function of suppressing release of oxygen from the In-M-Zn-O-based material. Generation of oxygen vacancies in the oxide semiconductor film is suppressed by the action of the metal element M. Therefore, variation in electrical characteristics of the transistor due to oxygen deficiency can be reduced, and a highly reliable transistor can be obtained.

  Specifically, the metal element M is Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Ga, Y, Zr, Nb, Mo, Sn, La, Ce, Pr, Nd, Sm, Eu. Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta or W, preferably Al, Ti, Ga, Y, Zr, Ce or Hf. The metal element M may be selected from one or more of the above elements. Further, Si or Ge can be used instead of the metal element M.

  Here, in an oxide semiconductor represented by an In-M-Zn-O-based material, carrier mobility and carrier density increase as the concentration of In increases. As a result, the higher the In concentration, the higher the conductivity of the oxide semiconductor.

  For example, the oxide semiconductor film may include a non-single crystal. The non-single crystal includes, for example, CAAC (C Axis Aligned Crystal), polycrystal, microcrystal, and amorphous. In non-single crystals, amorphous has the highest defect level density, and CAAC has the lowest defect level density. Note that an oxide semiconductor including CAAC is referred to as a CAAC-OS (C Axis Crystallized Oxide Semiconductor).

  For example, the oxide semiconductor film may include a CAAC-OS. The CAAC-OS includes an oxide semiconductor in which c-axis alignment is performed, for example, and the a-axis and / or b-axis are not aligned macroscopically.

  The oxide semiconductor film may include microcrystal, for example. The microcrystalline oxide semiconductor film includes, for example, an oxide semiconductor that includes microcrystal with a size greater than or equal to 1 nm and less than 10 nm. Alternatively, the microcrystalline oxide semiconductor film includes, for example, an oxide semiconductor having a crystal-amorphous mixed phase structure in which an amorphous phase includes a crystal part of 1 nm to less than 10 nm.

  For example, the oxide semiconductor film may be amorphous. An amorphous oxide semiconductor film includes, for example, an oxide semiconductor with disordered atomic arrangement and no crystal component. Alternatively, the amorphous oxide semiconductor film includes, for example, an oxide semiconductor that is completely amorphous and has no crystal part.

  Note that the oxide semiconductor film may be a mixed film of a CAAC-OS, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. For example, the mixed film includes an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region. The mixed film may have a stacked structure of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region, for example.

  Note that the oxide semiconductor film may include a single crystal, for example.

  The oxide semiconductor film preferably includes a plurality of crystal parts, and the c-axis of the crystal parts is aligned in a direction parallel to the normal vector of the formation surface or the normal vector of the surface. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. An example of such an oxide semiconductor film is a CAAC-OS film.

  The CAAC-OS film is not completely single crystal (a kind of non-single crystal) and is not completely amorphous. The CAAC-OS film includes an oxide semiconductor having a crystal-amorphous mixed phase structure where a crystal part and an amorphous part are included in an amorphous phase, for example. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. In addition, a clear grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

  The crystal part included in the CAAC-OS film is aligned so that, for example, the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and is perpendicular to the ab plane. It has a triangular or hexagonal atomic arrangement as viewed from the direction, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers as seen from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, the term “perpendicular” includes a range from 80 ° to 90 °, preferably from 85 ° to 95 °. In addition, a simple term “parallel” includes a range of −10 ° to 10 °, preferably −5 ° to 5 °.

  Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. In addition, when an impurity is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

  Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film ( Depending on the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface, they may face in different directions. Note that the c-axes of the crystal parts are aligned in a direction parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

  In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

In addition, the oxide semiconductor film is preferably highly purified so that impurities such as copper, aluminum, and chlorine are hardly contained. In the transistor manufacturing process, it is preferable to appropriately select a process in which these impurities are not mixed or attached to the surface of the oxide semiconductor film. When the impurity is attached to the surface of the oxide semiconductor film, oxalic acid or dilute hydrofluoric acid is used. It is preferable to remove impurities on the surface of the oxide semiconductor film by exposure to the above or plasma treatment (N ₂ O plasma treatment or the like). Specifically, the copper concentration of the oxide semiconductor film is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³ or less. In addition, the aluminum concentration of the oxide semiconductor film is 1 × 10 ¹⁸ atoms / cm ³ or less. The chlorine concentration of the oxide semiconductor film is 2 × 10 ¹⁸ atoms / cm ³ or less.

  The oxide semiconductor film is preferably in a supersaturated state in which oxygen is higher than that in the stoichiometric composition immediately after the formation. For example, in the case where an oxide semiconductor film is formed by a sputtering method, the film formation is preferably performed under a condition where the proportion of oxygen in the film formation gas is large, and the film formation is performed particularly in an oxygen atmosphere (oxygen gas 100%). It is preferable. When a film is formed under conditions where the proportion of oxygen in the film forming gas is large, particularly in an atmosphere containing 100% oxygen gas, for example, even when the film forming temperature is set to 300 ° C. or higher, the release of Zn from the film can be suppressed.

It is preferable that the oxide semiconductor film be highly purified by sufficiently removing impurities such as hydrogen or by being supplied with sufficient oxygen to be in a supersaturated state. Specifically, the hydrogen concentration of the oxide semiconductor film is 5 × 10 ¹⁹ atoms / cm ³ or less, desirably 5 × 10 ¹⁸ atoms / cm ³ or less, and more desirably 5 × 10 ¹⁷ atoms / cm ³ or less. Note that the hydrogen concentration in the oxide semiconductor film is measured by secondary ion mass spectrometry (SIMS). In addition, since sufficient oxygen is supplied to bring the oxygen into a supersaturated state, an insulating film containing excess oxygen (such as SiO _x ) is provided so as to surround the oxide semiconductor film.

  In addition, the hydrogen concentration of the insulating film containing excess oxygen is also important because it affects the characteristics of the transistor.

  The influence of the hydrogen concentration in the insulating film containing excess oxygen on the transistor characteristics will be described below.

  First, hydrogen was intentionally added into an insulating film containing excess oxygen, and the hydrogen concentration was evaluated by SIMS.

  A method for manufacturing the sample is described below.

  First, a glass substrate was prepared, and a silicon oxide film having a thickness of 300 nm was formed on the glass substrate by a sputtering method.

  The silicon oxide film was formed using a quartz target with a pressure of 0.4 Pa, a power of 1.5 kW (13.56 MHz), and a substrate temperature during film formation of 100 ° C.

Four types of samples were prepared. Each sample was the same except that the flow rates of oxygen gas (O ₂ ), deuterium gas (D ₂ ), and argon gas (Ar), which are film formation gases used for forming the silicon oxide film, were different.

Table 1 shows the sample name, the flow rate of each film forming gas used to form the silicon oxide film, the D (deuterium atom) concentration and the H (hydrogen atom) concentration at a depth of 30 nm in the silicon oxide film. Show. Note that the D ₂ ratio (D ₂ / (O ₂ + Ar + D ₂ )) in the deposition gas of each sample is 0% by volume for sample 1, 0.005% by volume for sample 2, and 0.50% by volume for sample 3. Sample 4 was 2.50% by volume.

From Table 1, it was found that the D concentration contained in the silicon oxide film was higher as the D ₂ ratio in the deposition gas was higher.

  Next, a transistor was manufactured using Samples 1 to 4 shown in Table 1.

  FIG. 22A is a top view of a transistor used for evaluation. A cross-sectional view corresponding to the alternate long and short dash line AB illustrated in FIG. 22A is illustrated in FIG. Note that in order to facilitate understanding, the protective insulating film 2118, the gate insulating film 2112, the insulating film 2102, and the like are omitted in FIG.

  A transistor illustrated in FIG. 22B includes a substrate 2100, an insulating film 2102 including excess oxygen provided over the substrate 2100, an oxide semiconductor film 2106 provided over the insulating film 2102, and an oxide semiconductor film 2106. A pair of electrodes 2116 provided above, a gate insulating film 2112 provided so as to cover the oxide semiconductor film 2106 and the pair of electrodes 2116, and the oxide semiconductor film 2106 are provided so as to overlap with each other. And a protective insulating film 2118 provided over the gate electrode 2104 and the gate insulating film 2112.

  Here, for the insulating film 2102, any one of the samples 1 to 4 shown in Table 1 was used. Note that the thickness of the insulating film 2102 was 300 nm.

  In addition, the substrate 2100 is glass, the oxide semiconductor film 2106 is IGZO (formed using an In: Ga: Zn = 1: 1: 1 [atomic ratio] target) with a thickness of 20 nm, and the pair of electrodes 2116 are Tungsten is 100 nm thick, the gate insulating film 2112 is a silicon oxynitride film 30 nm thick, the gate electrode 2104 is tantalum nitride 15 nm thick and tungsten is 135 nm thick from the gate insulating film 2112 side, and the protective insulating film 2118 is oxidized. Silicon nitride was 300 nm thick.

  A BT stress test was performed on the transistor having the above structure. Note that for the measurement, a transistor with a channel length (L) of 10 μm, a channel width (W) of 10 μm, and an overlap (Lov) between the gate electrode 2104 and the pair of electrodes 2116 of 1 μm (total 2 μm) was used. The method of the implemented BT stress test is shown below.

First, the drain current (I _d ) when the drain voltage (V _d ) of the transistor was 3 V and the gate voltage (V _g ) was swept from −6 V to 6 V at a substrate temperature of 25 ° C. was evaluated. The characteristics of the transistor at this time are called transistor characteristics before the BT test.

Next, _{V d} of 0.1 V, the _{V g} and -6 V, and held for 1 hour at a substrate temperature of 0.99 ° C..

Next, the application of V _d , V _g , and temperature was stopped, and when the substrate temperature was 25 ° C., V _d was 3 V, and I _d when V _g was swept from −6 V to 6 V was evaluated. The characteristics of the transistor at this time are referred to as the characteristics of the transistor after the BT stress test.

Table 2 shows the threshold voltage (V _th ) and field effect mobility (μ _FE ) before and after the BT stress test. However, the sample names shown in Table 2 correspond to the sample names shown in Table 1 and indicate the conditions of the insulating film 2102.

From Table 2, it was found that Sample 4 had a significant decrease in _μFE after the BT stress test.

Further, when the transistor characteristics were evaluated for a transistor having a smaller L, the variation in the negative direction of _Vth was larger in Sample 4 than in other samples.

As described above, in a transistor having a structure in which a silicon oxide film is in contact with an oxide semiconductor film, when the D concentration in the silicon oxide film is 7.2 × 10 ²⁰ atoms / cm ³ , characteristic abnormality occurs in the transistor. I understood.

As described above, when the hydrogen concentration of the insulating film containing excess oxygen is 7.2 × 10 ²⁰ atoms / cm ³ or more, the variation in the initial characteristics of the transistor is increased, the L length dependency is increased, and the BT is further increased. Since it deteriorates greatly in the stress test, the hydrogen concentration of the insulating film containing excess oxygen is set to less than 7.2 × 10 ²⁰ atoms / cm ³ . That is, the hydrogen concentration of the oxide semiconductor film is preferably 5 × 10 ¹⁹ atoms / cm ³ or less, and the hydrogen concentration of the insulating film containing excess oxygen is preferably less than 7.2 × 10 ²⁰ atoms / cm ³ .

Further, a blocking film (such as AlO _x ) that suppresses oxygen release from the oxide semiconductor film is preferably provided so as to surround the oxide semiconductor film and be disposed outside the insulating film containing excess oxygen.

  A state in which the oxide semiconductor film substantially accords with the stoichiometric composition by wrapping the oxide semiconductor film with an insulating film or blocking film containing excess oxygen, or a supersaturated state in which oxygen is higher than the stoichiometric composition. It can be. For example, when the stoichiometric composition of the oxide semiconductor film is In: Ga: Zn: O = 1: 1: 1: 4 [atomic ratio], the atomic ratio of oxygen contained in IGZO is greater than four. It becomes a state.

  Next, the insulating film 110 is formed over the source electrode 108a, the drain electrode 108b, and the oxide semiconductor film 106 (see FIG. 3C).

  As a material of the insulating film 110, silicon oxide, gallium oxide, aluminum oxide, zirconium oxide, yttrium oxide, hafnium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, or silicon nitride oxide Etc. can be used.

  As the insulating film 110, an insulating film from which oxygen is released by heat treatment at a temperature of 250 ° C to 700 ° C, preferably 300 ° C to 450 ° C is preferably used.

Further, an aluminum oxide film is preferably provided over the insulating film 110. In particular, an aluminum oxide film having a film density of 3.2 g / cm ³ or more, more preferably 3.6 g / cm ³ or more is preferably used. The thickness of the aluminum oxide film is 30 nm to 150 nm, preferably 50 nm to 100 nm. By setting the density of the aluminum oxide film to the above value, moisture and hydrogen can be prevented from entering and diffusing into the oxide semiconductor film. In addition, release of oxygen from the oxide semiconductor film 106 and / or the insulating film 110 can be suppressed.

  In addition, as illustrated in FIG. 4, the gate insulating film 105 of the transistor 160 may have a stacked structure of a gate insulating film 105a and a sidewall insulating film 105b.

  The gate insulating film 104 can be referred to for the formation method, material, and the like of the gate insulating film 105a and the sidewall insulating film 105b. The sidewall insulating film 105b is made of a material having an etching selectivity with respect to the gate insulating film 105a in order to function as a stopper so as not to be removed excessively in the removal process.

  With such a structure, leakage current flowing from the oxide semiconductor film to the gate electrode due to thinning of the gate insulating film due to miniaturization can be suppressed. Further, the Loff region can be lengthened, and the parasitic capacitance can be further reduced.

  As described above, in the semiconductor device including the oxide semiconductor described in this embodiment, the source electrode and the drain electrode are self-aligned by performing a removal process on the conductive film so that the gate insulating film is exposed. Can be formed. Since the Loff region of the oxide semiconductor film functions as an electric field relaxation region with the channel region, generation of hot carriers can be suppressed and variation in threshold voltage due to penetration of hot carriers into the gate insulating film is reduced. It is possible. Therefore, off-state current of the transistor can be reduced and hot carrier deterioration can be reduced.

  In addition, by adjusting the thickness of the gate insulating film 104, the length of the Loff region having higher resistance than the source electrode (or the drain electrode) can be optimized; thus, the channel region and the source electrode ( In addition, an increase in resistance that occurs with the drain electrode) can be suppressed. Thus, the on-state current of the transistor 150 can be increased.

  In addition, since the gate electrode and the source electrode (or the drain electrode) do not overlap with each other, parasitic capacitance can be reduced and the transistor can be driven at high speed. Furthermore, there is no misalignment when forming the source electrode and the drain electrode, and the channel length can be miniaturized. Thus, a highly reliable semiconductor device can be manufactured.

  Therefore, it is possible to reduce the off-state current of a semiconductor device using an oxide semiconductor, suppress a decrease in on-state current, and provide stable electrical characteristics such as reduction of parasitic capacitance. A highly reliable semiconductor device can be provided. In addition, a method for manufacturing the semiconductor device can be provided.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 2)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device which are another embodiment of the present invention will be described with reference to FIGS.

  5A and 5B are a plan view and a cross-sectional view of the transistor 250. FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along the line CD in FIG. 5A. Note that in FIG. 5A, some components of the transistor 250 (eg, the insulating film 210) are omitted in order to avoid complexity.

<Configuration of Semiconductor Device in this Embodiment>
FIG. 5 is a structural example of a semiconductor device manufactured by the method of this embodiment. 5 includes a gate electrode 202 provided over a substrate 200 having an insulating surface, a gate insulating film 204 covering at least the gate electrode 202, and an oxide semiconductor provided over the gate insulating film 204. The source electrode 208a and the drain electrode 208b which do not overlap with the top surface of the gate electrode 202 with the gate electrode 202 interposed between the film 206, the gate insulating film 204, and the oxide semiconductor film 206, the oxide semiconductor film 206, the source electrode 208a, and And an insulating film 210 provided over the drain electrode 208b.

  Further, there is no Loff region (high resistance region) as in the above embodiment, and the resistance contributing to the oxide semiconductor film can be reduced. Thus, the on-state current of the transistor 250 can be increased.

  In addition, since the gate electrode 202 and the source electrode 208a (or the drain electrode 208b) do not overlap with each other, parasitic capacitance can be reduced and the transistor 250 can be driven at high speed.

<Method for Manufacturing Semiconductor Device in this Embodiment>
A method for manufacturing the transistor 250 is described with reference to FIGS.

  First, the gate electrode 202 is formed over the substrate 200 (see FIG. 6A).

  For the formation method, material, and the like of the substrate 200 and the gate electrode 202, the substrate 100 and the gate electrode 102 in the above embodiment can be referred to.

  Alternatively, a base insulating film may be formed over the substrate 200 and the gate electrode 202 may be formed over the base insulating film. For the formation method and material of the base insulating film, the base insulating film of the above embodiment can be referred to.

  Next, a gate insulating film 204 is formed over the substrate 200 and the gate electrode 202 (see FIG. 6B). Note that the gate insulating film 204 only needs to cover at least the gate electrode 202.

  For the formation method, material, and the like of the gate insulating film 204, the gate insulating film 104 of the above embodiment can be referred to.

  Next, the oxide semiconductor film 206 is formed over the gate insulating film 204 (see FIG. 6C).

  For the formation method, material, and the like of the oxide semiconductor film 206, the oxide semiconductor film 106 of the above embodiment can be referred to.

  Next, a conductive film 207 to be a source electrode and a drain electrode (including a wiring formed using the same layer) is formed over the gate insulating film 204 and the oxide semiconductor film 206 (see FIG. 7A). ). The conductive film 207 may have a single-layer structure or a stacked structure. In this embodiment, a step is formed between the region 215a and the region 215b as illustrated in FIG.

  For the formation method, material, and the like of the conductive film 207, the conductive film 107 in the above embodiment can be referred to.

  Next, by removing (polishing) the conductive film 207, part of the conductive film 207 is removed so that the oxide semiconductor film 206 is exposed, so that the source electrode 208a and the drain electrode 208b are formed (FIG. 7). (See (B)).

  By the removal treatment, the conductive film 207 in the region overlapping with the gate electrode 202 is removed, and the source electrode 208a and the drain electrode 208b are formed in a self-aligning manner. As a removal method, it is preferable to use a chemical mechanical polishing (CMP) process.

  In this embodiment, as illustrated in FIG. 7A, the conductive film provided over the oxide semiconductor film 206 is removed by using a step generated between the region 215a and the region 215b (specifically Specifically, the source electrode 208a and the drain electrode 208b can be formed by CMP treatment.

  Note that in this embodiment, the top surfaces of the source electrode 208a and the drain electrode 208b are flush with the top surface of the oxide semiconductor film 206; however, the present invention is not limited to this, and the top surfaces of the source electrode 208a and the drain electrode 208b are oxidized. The height of the upper surface of the physical semiconductor film 206 may be slightly shifted.

  Note that in this embodiment mode, CMP treatment is used to remove the conductive film 207 in a region overlapping with the gate electrode 202; however, other removal treatments may be used. Alternatively, polishing treatment such as CMP treatment, etching (dry etching, wet etching) treatment, plasma treatment, or the like may be combined. For example, after the CMP treatment, dry etching treatment or plasma treatment (reverse sputtering or the like) may be performed to improve the flatness of the treatment surface. In the case where the removal treatment is combined with an etching treatment, a plasma treatment, or the like, the order of steps is not particularly limited, and may be set as appropriate depending on the material, film thickness, and surface roughness of the conductive film 207. Alternatively, most of the conductive film 207 in the region 215b may be removed by CMP treatment, and the remaining conductive film 207 may be removed by dry etching treatment. By doing so, there is a structure in which an etching selectivity between the conductive film 207 and the oxide semiconductor film 206 can be easily obtained. Therefore, the oxide semiconductor film 206 can be prevented from being thinned.

  The CMP process may be performed only once or a plurality of times. When performing the CMP process in a plurality of times, it is preferable to perform the final polishing at a low polishing rate after performing the primary polishing at a high polishing rate. By combining polishing with different polishing rates in this way, the flatness of the surface of the conductive film 207 can be further improved.

  Further, a part of the conductive film 207 is exposed so that the oxide semiconductor film 206 is exposed by etching using a resist mask having the same etching selectivity as the conductive film 207 instead of the CMP process. The source electrode 208a and the drain electrode 208b may be formed.

  In this embodiment mode, part of the conductive film 207 is removed and the conductive film 207 is processed to form the source electrode 208a and the drain electrode 208b. However, the present invention is not limited to this, and the conductive film 207 is processed first. Then, the source electrode 208a and the drain electrode 208b may be formed by removing part of the conductive film 207 after processing.

  In this manner, by performing the removal treatment so that the oxide semiconductor film 206 is exposed, the source electrode 208a and the drain electrode 208b can be formed in a self-aligning manner. Therefore, there is no alignment shift when forming the source electrode and the drain electrode, and the channel length can be miniaturized. Thus, a highly reliable semiconductor device can be manufactured.

  Further, there is no Loff region (high resistance region) as in the above embodiment, and the resistance contributing to the oxide semiconductor film 306 can be reduced. Thus, the on-state current of the transistor 250 can be increased.

  In addition, since the gate electrode 202 and the source electrode 208a (or the drain electrode 208b) do not overlap with each other, parasitic capacitance can be reduced and the transistor 250 can be driven at high speed.

  Next, the insulating film 210 is formed over the source electrode 208a, the drain electrode 208b, and the oxide semiconductor film 206 (see FIG. 7C).

  For the formation method, material, and the like of the insulating film 210, the insulating film 110 in the above embodiment can be referred to.

In addition, an aluminum oxide film is preferably provided over the insulating film 210. In particular, an aluminum oxide film having a film density of 3.2 g / cm ³ or more, more preferably 3.6 g / cm ³ or more is preferably used. The thickness of the aluminum oxide film is 30 nm to 150 nm, preferably 50 nm to 100 nm. By setting the density of the aluminum oxide film to the above value, moisture and hydrogen can be prevented from entering and diffusing into the oxide semiconductor film. Further, release of oxygen from the oxide semiconductor film 206 and / or the insulating film 210 can be suppressed.

  As described above, in the semiconductor device including the oxide semiconductor described in this embodiment, the conductive film is removed so that the oxide semiconductor film is exposed, so that the source electrode and the drain are self-aligned. An electrode can be formed. Further, there is no Loff region (high resistance region), and the resistance contributing to the oxide semiconductor film can be reduced. Thus, the on-state current of the transistor can be increased.

  In addition, since the gate electrode and the source electrode (or the drain electrode) do not overlap with each other, parasitic capacitance can be reduced and the transistor can be driven at high speed. Furthermore, there is no misalignment when forming the source electrode and the drain electrode, and the channel length can be miniaturized. Thus, a highly reliable semiconductor device can be manufactured.

  Therefore, a reduction in on-state current of a semiconductor device using an oxide semiconductor can be suppressed, and stable electrical characteristics such as reduction in parasitic capacitance can be provided, so that a highly reliable semiconductor device can be obtained. Can be provided. In addition, a method for manufacturing the semiconductor device can be provided.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 3)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device which are another embodiment of the present invention will be described with reference to FIGS.

  FIG. 8 shows a plan view and a cross-sectional view of the transistor 350. 8A is a plan view, and FIG. 8B is a cross-sectional view taken along the line EF in FIG. 8A. Note that in FIG. 8A, part of the components of the transistor 350 (eg, the insulating film 310) is omitted in order to avoid complexity.

<Configuration of Semiconductor Device in this Embodiment>
FIG. 8 is a structural example of a semiconductor device manufactured by the method of this embodiment. A transistor 350 illustrated in FIGS. 8A and 8B includes a base insulating film 301 provided over a substrate having an insulating surface, and a gate electrode embedded in the base insulating film 301 and having at least part of the upper surface exposed from the base insulating film 301. 303, the gate insulating film 304 covering at least the gate electrode 303, and the source electrode 308a and the drain electrode 308b provided on the gate insulating film 304 without overlapping with the gate electrode 303, and at least overlapping with the gate electrode 303. The oxide semiconductor film 306 provided over the gate insulating film 304 and the insulating film provided over the oxide semiconductor film 306, the source electrode 308a, and the drain electrode 308b. And a film 310.

  Further, since one side surface of the oxide semiconductor film 306 is in contact with the source electrode 308a and the side surface opposite to the one side surface of the oxide semiconductor film 306 is in contact with the drain electrode 308b, There is no resistance region), and the resistance contributing to the oxide semiconductor film can be reduced. Thus, the on-state current of the transistor 350 can be increased. Alternatively, a Loff region may be provided.

  In addition, since the gate electrode 303 and the source electrode 308a (or the drain electrode 308b) do not overlap with each other, parasitic capacitance can be reduced and the transistor 350 can be driven at high speed.

<Method for Manufacturing Semiconductor Device in this Embodiment>
A method for manufacturing the transistor 350 is described with reference to FIGS.

  First, the base insulating film 300 is formed over a substrate having an insulating surface, and a resist mask 320 is selectively formed over the base insulating film 300 (see FIG. 9A).

  As a material for the substrate and the base insulating film 300, a material that transmits light is used. Here, in this specification, “light” refers to light used in an exposure machine. For the substrate, the formation method, the material, and the like of the base insulating film 300, the substrate 100 and the base insulating film of the above embodiment can be referred to. The resist mask 320 may be formed by a photolithography method.

  Next, the base insulating film 300 is etched to form a base insulating film 301 having a recess. After the base insulating film 301 is formed, the resist mask 320 is removed (see FIG. 9B).

  Next, a conductive film 302 is formed over the base insulating film 301 (see FIG. 9C).

  As a material of the conductive film 302, a material that does not transmit light is used. For the formation method, material, and the like of the conductive film 302, the gate electrode 102 in the above embodiment can be referred to.

  Next, by removing (polishing) the conductive film 302, part of the conductive film 302 is removed so that the base insulating film 301 is exposed, so that the gate electrode 303 is formed (see FIG. 9D). .

  By the removal treatment, the conductive film 302 over the base insulating film 301 on which the resist mask 320 is overlapped is removed, and the gate electrode 303 is formed so as to fill the concave portion provided in the base insulating film 301. As a removal method, it is preferable to use a chemical mechanical polishing (CMP) process. In this embodiment, the conductive film 302 over the base insulating film 301 on which the resist mask 320 is overlapped is removed by CMP treatment, and the gate electrode 303 is formed.

  Note that in this embodiment mode, the CMP process is used to remove the conductive film 302 over the base insulating film 301 on which the resist mask 320 overlaps, but another removal process may be used. Alternatively, polishing treatment such as CMP treatment, etching (dry etching, wet etching) treatment, plasma treatment, or the like may be combined. For example, after the CMP treatment, dry etching treatment or plasma treatment (reverse sputtering or the like) may be performed to improve the flatness of the treatment surface. In the case where etching treatment, plasma treatment, or the like is performed in combination with removal treatment, the order of steps is not particularly limited, and may be set as appropriate depending on the material, film thickness, and surface roughness of the conductive film 302.

  The CMP process may be performed only once or a plurality of times. When performing the CMP process in a plurality of times, it is preferable to perform the final polishing at a low polishing rate after performing the primary polishing at a high polishing rate. By combining polishing with different polishing rates in this way, the flatness of the surface of the conductive film 302 can be further improved.

  Further, instead of the CMP treatment, a part of the conductive film 302 is etched on the conductive film 302 using a resist mask having the same etching selection ratio as the conductive film 302 so that the base insulating film 301 is exposed. It may be removed and the gate electrode 303 may be formed.

  Next, a gate insulating film 304 is formed over the base insulating film 301 and the gate electrode 303, and a conductive film 307 to be a source electrode and a drain electrode (including a wiring formed using the same layer) is formed over the gate insulating film 304. (See FIG. 10A). Note that the gate insulating film 304 only needs to cover at least the gate electrode 303.

  As a material of the gate insulating film 304, a material that transmits light is used. For example, silicon oxide, gallium oxide, aluminum oxide, zirconium oxide, yttrium oxide, hafnium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, or silicon nitride oxide is used. be able to.

  As the gate insulating film 304, an insulating film from which oxygen is released by heat treatment at a temperature of 250 ° C. to 700 ° C., preferably 300 ° C. to 450 ° C. is preferably used.

The conductive film 307 can be formed by a plasma CVD method, a sputtering method, or the like. Further, as the material for the conductive film 307, a material that can withstand heat treatment performed later is used. A material that transmits light is used for the conductive film 307. For example, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ , abbreviated as ITO), indium zinc oxide (In ₂₎ O ₃ —ZnO) or a metal oxide film containing silicon oxide can be used. Alternatively, a stacked structure of the metal film and the metal oxide film can be employed.

  Next, a photosensitive resin is formed over the conductive film 307. Backside exposure is performed from the substrate side, the photosensitive resin that does not overlap with the gate electrode 303 is exposed and fixed, and a resist mask 330 is formed over the conductive film 307 that does not overlap with the gate electrode 303 (see FIG. 10B).

  Note that in order to perform backside exposure, the substrate, the base insulating film, and the conductive film must be materials that transmit light, and the gate electrode must be a material that does not transmit light. If a film that does not transmit light, such as a metal film, is used as the conductive film, it is shielded from light, so that the photosensitive resin cannot be exposed.

  Next, oxygen plasma treatment (ashing) or the like may be performed on the resist mask 330 to widen a region where the resist mask 330 is not formed. In this manner, the conductive film 307 formed later can be processed, so that a region where the gate electrode 303 and the source electrode 308a (or the drain electrode 308b) do not overlap (Loff region) can be widened.

  Next, the conductive film 307 is etched using the resist mask 330, so that the source electrode 308a and the drain electrode 308b are formed (see FIG. 10C).

  In this manner, a resist mask is formed over the conductive film to be a source electrode and a drain electrode (including a wiring formed of the same layer as this) that does not overlap with the gate electrode 303 by backside exposure, and the source electrode 308a and the drain electrode are formed by an etching process. A drain electrode 308b can be formed. Accordingly, the source electrode 308a and the drain electrode 308b that do not overlap with the gate electrode 303 can be formed in a self-aligning manner. Therefore, there is no alignment shift when forming the source electrode 308a and the drain electrode 308b, and the channel length can be miniaturized. Thus, a highly reliable semiconductor device can be manufactured.

  Next, the oxide semiconductor film 306 is formed over the source electrode 308a and the drain electrode 308b, and the insulating film 310 is formed over the oxide semiconductor film 306, the source electrode 308a, and the drain electrode 308b (see FIG. 10D). .

  For the formation method, material, and the like of the oxide semiconductor film 306 and the insulating film 310, the oxide semiconductor film 106 and the insulating film 110 of the above embodiment can be referred to.

  In addition, the oxide semiconductor film 306 does not have the Loff region (high resistance region) as in Embodiment 1, so that the resistance contributing to the oxide semiconductor film 306 can be reduced. Thus, the on-state current of the transistor 350 can be increased. In the case where the Loff region is provided, the Loff region functions as an electric field relaxation region with the channel region. Therefore, generation of hot carriers can be suppressed, and variation in threshold voltage due to penetration of hot carriers into the gate insulating film can be reduced. In addition, off-state current of the transistor 350 can be reduced.

  In addition, since the gate electrode 303 and the source electrode 308a (or the drain electrode 308b) do not overlap with each other, parasitic capacitance can be reduced and the transistor 350 can be driven at high speed.

Further, an aluminum oxide film is preferably provided over the insulating film 310. In particular, an aluminum oxide film having a film density of 3.2 g / cm ³ or more, more preferably 3.6 g / cm ³ or more is preferably used. The thickness of the aluminum oxide film is 30 nm to 150 nm, preferably 50 nm to 100 nm. By setting the density of the aluminum oxide film to the above value, moisture and hydrogen can be prevented from entering and diffusing into the oxide semiconductor film. In addition, release of oxygen from the oxide semiconductor film 306 and / or the insulating film 310 can be suppressed.

  As described above, in the semiconductor device including the oxide semiconductor described in this embodiment, the conductive material that serves as a source electrode and a drain electrode (including a wiring formed using the same layer) that does not overlap with the gate electrode by backside exposure. A resist mask is formed over the film, and a source electrode and a drain electrode that do not overlap with the gate electrode can be formed in a self-aligned manner by an etching process. Further, there is no Loff region (high resistance region), and the resistance contributing to the oxide semiconductor film can be reduced. Thus, the on-state current of the transistor can be increased.

  Furthermore, there is no misalignment when forming the source electrode and the drain electrode, and the channel length can be miniaturized. Thus, a highly reliable semiconductor device can be manufactured.

  In addition, when the Loff region is provided, the Loff region functions as an electric field relaxation region with the channel region. Therefore, generation of hot carriers can be suppressed, and variation in threshold voltage due to penetration of hot carriers into the gate insulating film can be reduced. Therefore, off-state current of the transistor can be reduced and hot carrier deterioration can be reduced.

  Therefore, it is possible to reduce the off-state current of a semiconductor device using an oxide semiconductor, suppress a decrease in on-state current, and provide stable electrical characteristics such as reduction of parasitic capacitance. A highly reliable semiconductor device can be provided. In addition, a method for manufacturing the semiconductor device can be provided.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 4)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device which are another embodiment of the present invention will be described with reference to FIGS.

  11A and 11B are a plan view and a cross-sectional view of the transistor 450. FIG. FIG. 11A is a plan view, and FIG. 11B is a cross-sectional view taken along the line GH in FIG. 11A. Note that in FIG. 11A, part of the components of the transistor 450 (eg, the insulating film 410) is omitted in order to avoid complexity.

<Configuration of Semiconductor Device in this Embodiment>
FIG. 11 is a structural example of a semiconductor device manufactured by the method of this embodiment. A transistor 450 illustrated in FIG. 11 includes a base insulating film 401 provided over a substrate having an insulating surface, and a gate electrode embedded in the base insulating film 401 and at least a part of the upper surface of which is exposed from the base insulating film 401. 403, the gate insulating film 404 covering at least the gate electrode 403, and the source electrode 408a and the drain electrode 408b provided on the gate insulating film 404 without overlapping with the gate electrode 403, and at least overlapping with the gate electrode 403. , An island-shaped oxide semiconductor film 406 provided over the gate insulating film 404, at least partially in contact with the source electrode 408a and the drain electrode 408b, and the island-shaped oxide semiconductor film 406, the source electrode 408a, and the drain electrode 408b And an insulating film 410 provided thereon. In addition, the top surface of the island-shaped oxide semiconductor film 406 is flush with the top surfaces of the source electrode 408a and the drain electrode 408b.

  In addition, since one side surface of the island-shaped oxide semiconductor film 406 is in contact with the source electrode 408a and the side surface opposite to the one side surface of the island-shaped oxide semiconductor film 406 is in contact with the drain electrode 408b, Thus, there is no Loff region (high resistance region), and the resistance contributing to the oxide semiconductor film can be reduced. Thus, the on-state current of the transistor 450 can be increased.

  In addition, since the gate electrode 403 and the source electrode 408a (or the drain electrode 408b) do not overlap with each other, parasitic capacitance can be reduced and the transistor 450 can be driven at high speed.

<Method for Manufacturing Semiconductor Device in this Embodiment>
A method for manufacturing the transistor 450 is described with reference to FIGS.

  First, a base insulating film 401a is formed over a substrate having an insulating surface, and a gate electrode 403 is formed over the base insulating film 401 (see FIG. 12A).

  As a material for the substrate and the base insulating film 401a, a material that transmits light is used. The substrate 100, the base insulating film, and the gate electrode 102 in the above embodiment can be referred to for the formation method, material, and the like of the substrate, the base insulating film 401a, and the gate electrode 403. The gate electrode 403 is formed by forming a conductive film over the base insulating film 401a and performing a photolithography process and an etching process.

  Next, a base insulating film 401b is formed over the base insulating film 401a and the gate electrode 403 (see FIG. 12B).

  The base insulating film 401a can be referred to for the formation method, material, and the like of the base insulating film 401b.

  Next, by performing removal (polishing) treatment on the base insulating film 401b, part of the base insulating film 401b is removed so that the gate electrode 403 is exposed, so that the base insulating film 401 is formed (see FIG. 12C). ).

  By the removal treatment, the base insulating film 401b over the gate electrode 403 is removed, and the base insulating film 401 is formed. As a removal method, it is preferable to use a chemical mechanical polishing (CMP) process. In this embodiment, the base insulating film 401b over the gate electrode 403 is removed by CMP treatment, and the base insulating film 401 is formed.

  Note that although CMP treatment is used for removing the base insulating film 401b over the gate electrode 403 in this embodiment mode, other removal treatment may be used. Alternatively, polishing treatment such as CMP treatment, etching (dry etching, wet etching) treatment, plasma treatment, or the like may be combined. For example, after the CMP treatment, dry etching treatment or plasma treatment (reverse sputtering or the like) may be performed to improve the flatness of the treatment surface. In the case where the removal treatment is combined with an etching treatment, a plasma treatment, or the like, the order of steps is not particularly limited, and may be set as appropriate in accordance with the material, film thickness, and surface roughness of the base insulating film 401b.

  The CMP process may be performed only once or a plurality of times. When performing the CMP process in a plurality of times, it is preferable to perform the final polishing at a low polishing rate after performing the primary polishing at a high polishing rate. By combining polishing with different polishing rates in this way, the flatness of the surface of the base insulating film 401b can be further improved.

  Further, instead of the CMP treatment, etching is performed on the base insulating film 401b using a resist mask having the same etching selection ratio as the base insulating film 401b so that the gate electrode 403 is exposed so that the gate electrode 403 is exposed. The base insulating film 401 may be formed by removing the portion.

  Next, the gate insulating film 404 is formed over the base insulating film 401 and the gate electrode 403, and the oxide semiconductor film 405 is formed over the gate insulating film 404 (see FIG. 13A). Note that the gate insulating film 404 only needs to cover at least the gate electrode 403.

  As a material of the gate insulating film 404, a material that transmits light is used. For the formation method, material, and the like of the gate insulating film 404 and the oxide semiconductor film 405, the gate insulating film 304 and the oxide semiconductor film 106 of the above embodiment can be referred to.

  Next, a photosensitive resin is formed over the oxide semiconductor film 405. Backside exposure is performed from the substrate side, the photosensitive resin overlapping with the gate electrode 403 is not exposed and fixed, and a resist mask 430 is formed over the oxide semiconductor film 405 overlapping with the gate electrode 403 (FIG. 13B). reference).

  Note that in order to perform backside exposure, the substrate, the base insulating film, and the oxide semiconductor film must be formed of a material that transmits light, and the gate electrode must be formed of a material that does not transmit light. When a film that does not transmit light is used for the oxide semiconductor film, the film is shielded from light, so that the photosensitive resin cannot be exposed.

  Next, the oxide semiconductor film 405 is etched using the resist mask 430, so that an island-shaped oxide semiconductor film 406 overlapping with the gate electrode 403 is formed (see FIG. 13C).

  Next, a conductive film 407 to be a source electrode and a drain electrode (including a wiring formed using the same layer) is formed over the gate insulating film 404 and the island-shaped oxide semiconductor film 406 (see FIG. 14A). )reference). The conductive film 407 may have a single-layer structure or a stacked structure. In this embodiment, a step is generated between the region 415a and the region 415b as illustrated in FIG.

  For the formation method, material, and the like of the conductive film 407, the conductive film 107 in the above embodiment can be referred to.

  Next, by removing (polishing) the conductive film 407, part of the conductive film 407 is removed so that the island-shaped oxide semiconductor film 406 is exposed, so that the source electrode 408a and the drain electrode 408b are formed. (See FIG. 14B).

  By the removal treatment, the conductive film 407 in the region overlapping with the gate electrode 403 is removed, and the source electrode 408a and the drain electrode 408b are formed in a self-aligning manner. As a removal method, it is preferable to use a chemical mechanical polishing (CMP) process.

  In this embodiment, the conductive film provided over the island-shaped oxide semiconductor film 406 is removed using a step generated between the region 415a and the region 415b as illustrated in FIG. By performing treatment (specifically, CMP treatment), the source electrode 408a and the drain electrode 408b can be formed.

  Note that in this embodiment, the heights of the top surfaces of the source electrode 408a and the drain electrode 408b and the top surface of the island-shaped oxide semiconductor film 406 are the same; however, the present invention is not limited to this, and the source electrode 408a and the drain electrode 408b The height between the top surface and the top surface of the island-shaped oxide semiconductor film 406 may be slightly shifted.

  Note that although CMP treatment is used to remove the conductive film 407 in a region overlapping with the gate electrode 403 in this embodiment mode, other removal treatment may be used. Alternatively, polishing treatment such as CMP treatment, etching (dry etching, wet etching) treatment, plasma treatment, or the like may be combined. For example, after the CMP treatment, dry etching treatment or plasma treatment (reverse sputtering or the like) may be performed to improve the flatness of the treatment surface. In the case where the removal treatment is combined with an etching treatment, a plasma treatment, or the like, the order of steps is not particularly limited, and may be set as appropriate depending on the material, film thickness, and surface roughness of the conductive film 207. Alternatively, most of the conductive film 407 in the region 415b may be removed by CMP treatment, and the remaining conductive film 407 may be removed by dry etching treatment. By doing so, there is a structure in which an etching selectivity between the conductive film 407 and the island-shaped oxide semiconductor film 406 can be easily obtained. Therefore, the island-shaped oxide semiconductor film 406 can be prevented from being thinned.

  The CMP process may be performed only once or a plurality of times. When performing the CMP process in a plurality of times, it is preferable to perform the final polishing at a low polishing rate after performing the primary polishing at a high polishing rate. By combining polishing with different polishing rates in this way, the flatness of the surface of the conductive film 407 can be further improved.

  Further, instead of the CMP treatment, the conductive film 407 is etched so that the island-shaped oxide semiconductor film 406 is exposed over the conductive film 407 using a resist mask having the same etching selectivity as the conductive film 407. May be removed to form the source electrode 408a and the drain electrode 408b.

  In this embodiment mode, a part of the conductive film 407 is removed and the conductive film 407 is processed to form the source electrode 408a and the drain electrode 408b. However, the present invention is not limited to this, and the conductive film 407 is processed first. Then, part of the conductive film 407 may be removed after processing to form the source electrode 408a and the drain electrode 408b.

  In this manner, a resist mask is formed over the oxide semiconductor film which overlaps with the gate electrode 403 by backside exposure, an island-shaped oxide semiconductor film is formed by an etching process, and the island-shaped oxide semiconductor film is formed with respect to the conductive film 407. By performing the removal treatment so that the semiconductor film is exposed, the source electrode 408a and the drain electrode 408b can be formed in a self-aligning manner. Accordingly, the source electrode 408a and the drain electrode 408b that do not overlap with the gate electrode 403 can be formed. Therefore, there is no alignment shift when forming the source electrode 408a and the drain electrode 408b, and the channel length can be reduced. Thus, a highly reliable semiconductor device can be manufactured.

  Next, the insulating film 410 is formed over the island-shaped oxide semiconductor film 406, the source electrode 408a, and the drain electrode 408b (see FIG. 14C).

  For the formation method, material, and the like of the insulating film 410, the insulating film 110 in the above embodiment can be referred to.

  In addition, the island-shaped oxide semiconductor film 406 does not have the Loff region (high resistance region) as in the above embodiment, and the resistance contributing to the island-shaped oxide semiconductor film 406 can be reduced. Thus, the on-state current of the transistor 450 can be increased.

  In addition, since the gate electrode 403 and the source electrode 408a (or the drain electrode 408b) do not overlap with each other, parasitic capacitance can be reduced and the transistor 450 can be driven at high speed.

In addition, an aluminum oxide film is preferably provided over the insulating film 410. In particular, an aluminum oxide film having a film density of 3.2 g / cm ³ or more, more preferably 3.6 g / cm ³ or more is preferably used. The thickness of the aluminum oxide film is 30 nm to 150 nm, preferably 50 nm to 100 nm. By setting the density of the aluminum oxide film to the above value, moisture and hydrogen can be prevented from entering and diffusing into the oxide semiconductor film. In addition, release of oxygen from the island-shaped oxide semiconductor film 406 and / or the insulating film 410 can be suppressed.

  As described above, in the semiconductor device including an oxide semiconductor described in this embodiment, a resist mask is formed over the oxide semiconductor film which overlaps with the gate electrode by backside exposure, and the island-shaped oxide is formed with respect to the conductive film. By performing the removal treatment so that the physical semiconductor film is exposed, the source electrode and the drain electrode can be formed in a self-aligning manner. In addition, there is no Loff region (high resistance region), and the resistance contributing to the island-shaped oxide semiconductor film can be reduced. Thus, the on-state current of the transistor can be increased.

  Furthermore, there is no misalignment when forming the source electrode and the drain electrode, and the channel length can be miniaturized. Thus, a highly reliable semiconductor device can be manufactured.

  Therefore, a reduction in on-state current of a semiconductor device using an oxide semiconductor can be suppressed, and stable electrical characteristics such as reduction in parasitic capacitance can be provided, and a highly reliable semiconductor device is provided. be able to. In addition, a method for manufacturing the semiconductor device can be provided.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 5)
In this embodiment, an example of a semiconductor device which uses the transistor described in any of Embodiments 1 to 4 and can hold stored data even when power is not supplied and has no limit on the number of writing times. This will be described with reference to the drawings.

  FIG. 15 illustrates an example of a structure of a semiconductor device. 15A is a cross-sectional view of the semiconductor device, FIG. 15B is a plan view of the semiconductor device, and FIG. 15C is a circuit diagram of the semiconductor device. Here, FIG. 15A corresponds to a cross section taken along lines I-J and K-L in FIG.

  The semiconductor device illustrated in FIGS. 15A and 15B includes a transistor 760 using a first semiconductor material in a lower portion and a transistor 762 using a second semiconductor material in an upper portion. . The transistor structure described in any of the above embodiments can be used as the transistor 762. Here, an example in which the transistor 150 of Embodiment 1 is used will be described.

  Here, it is desirable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor including a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor can hold charge for a long time due to its characteristics.

  Note that although all the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. In addition to the transistor 150 in which an oxide semiconductor is used to hold information as in Embodiment 1, a specific structure of a semiconductor device such as a material used in the semiconductor device and a structure of the semiconductor device is described here. It is not necessary to limit to what is shown by.

  A transistor 760 in FIG. 15A includes a channel formation region 716 provided in a substrate 700 containing a semiconductor material (eg, silicon), an impurity region 720 provided so as to sandwich the channel formation region 716, and an impurity region. 720 includes an intermetallic compound region 724 in contact with 720, a gate insulating film 708 provided over the channel formation region 716, and a gate electrode 710 provided over the gate insulating film 708. Note that in the drawing, the source electrode and the drain electrode may not be explicitly provided, but for convenience, the state may be referred to as a transistor. In this case, in order to describe the connection relation of the transistors, the source and drain electrodes including the source and drain regions may be expressed. That is, in this specification, the term “source electrode” can include a source region.

  An element isolation insulating film 706 is provided over the substrate 700 so as to surround the transistor 760, and an insulating film 728 and an insulating film 730 are provided so as to cover the transistor 760. Note that in the transistor 760, a sidewall insulating film (sidewall insulating film) may be provided on a side surface of the gate electrode 710 so that the impurity region 720 includes regions having different impurity concentrations.

  The transistor 760 using a single crystal semiconductor substrate can operate at high speed. Therefore, information can be read at high speed by using the transistor as a reading transistor. Two insulating films are formed so as to cover the transistor 760. As a process before the formation of the transistor 762 and the capacitor 764, the two insulating films are subjected to CMP to form planarized insulating films 728 and 730, and the upper surface of the gate electrode 710 is exposed at the same time.

  The insulating films 728 and 730 are typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like. An inorganic insulating film can be used. The insulating films 728 and 730 can be formed by a plasma CVD method, a sputtering method, or the like.

  Alternatively, an organic material such as polyimide, acrylic resin, or benzocyclobutene resin can be used. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. In the case of using an organic material, the insulating film 728 and the insulating film 730 may be formed by a wet method such as a spin coating method or a printing method.

  Note that in this embodiment, a silicon nitride film is used as the insulating film 728 and a silicon oxide film is used as the insulating film 730.

  In the manufacturing process of the transistor 762, the gate electrode 748 and the gate insulating film 737 are formed on the surface of the insulating film 730, an opening is formed in the gate insulating film 737 over the gate electrode 710, and the transistor 762 is provided over the gate electrode 710 and the gate insulating film 737. A source electrode 742a and a drain electrode 742b are formed using a process of removing the conductive film by chemical mechanical polishing.

  Therefore, the Loff width of the transistor 762 can be reduced, so that the on-state characteristics of the transistor 762 can be improved.

  In the step of removing the conductive film overlapping with the gate electrode 748 in the step of forming the source electrode 742a and the drain electrode 742b, an etching process using a resist mask is not used, so that precise processing can be performed accurately. Thus, in a manufacturing process of a semiconductor device, a transistor having a fine structure with little variation in shape and characteristics can be manufactured with high yield.

  An oxide semiconductor film 744 is formed over the gate insulating film 737, the source electrode 742a, and the drain electrode 742b which are sufficiently planarized by a removal process (eg, a CMP process).

  A transistor 762 illustrated in FIG. 15A is a transistor in which an oxide semiconductor is used for a channel formation region. Here, as described in the above embodiment, the oxide semiconductor film 744 included in the transistor 762 is preferably highly purified by removing impurities such as moisture and hydrogen as much as possible. Moreover, it is preferable that oxygen deficiency is fully compensated. By using such an oxide semiconductor, a transistor 762 with extremely excellent off characteristics can be obtained.

  Since the transistor 762 has extremely low off-state current, stored data can be held for a long time by using the transistor 762. In other words, since it is possible to obtain a semiconductor memory device that does not require a refresh operation or has a very low frequency of the refresh operation, power consumption can be sufficiently reduced.

An interlayer insulating film 750 is provided as a single layer or a stacked layer over the transistor 762. In this embodiment, an aluminum oxide film is used as the interlayer insulating film 750. By setting the aluminum oxide film to a high density (film density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistor 762.

  In addition, a conductive film 753 is provided in a region overlapping with the source electrode 742 a of the transistor 762 with the interlayer insulating film 750 interposed therebetween. The source electrode 742 a, the interlayer insulating film 750, and the conductive film 753 provide capacitance. Element 764 is configured. That is, the source electrode 742a of the transistor 762 functions as one electrode of the capacitor 764, and the conductive film 753 functions as the other electrode of the capacitor 764. Note that in the case where a capacitor is not necessary, the capacitor 764 can be omitted. Further, the capacitor 764 may be provided over the transistor 762 separately.

  An insulating film 752 is provided over the transistor 762 and the capacitor 764. A transistor 762 and a wiring 756 for connecting another transistor are provided over the insulating film 752. Although not illustrated in FIG. 15A, the wiring 756 is electrically connected to the drain electrode 742b through an electrode formed in an opening formed in the interlayer insulating film 750, the insulating film 752, and the like.

  15A and 15B, the transistor 760 and the transistor 762 are provided so that at least part of them overlaps with each other. The source region or the drain region of the transistor 760 and the oxide semiconductor film 744 It is preferable that a part is provided so as to overlap. Further, the transistor 762 and the capacitor 764 are provided so as to overlap with at least part of the transistor 760. For example, the conductive film 753 of the capacitor 764 is provided so as to overlap with at least part of the gate electrode 710 of the transistor 760. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

  Note that the drain electrode 742b and the wiring 756 may be electrically connected to each other by directly contacting the drain electrode 742b and the wiring 756, or an electrode is provided on an insulating film between the drain electrode 742b and the wiring 756. You may go through. A plurality of electrodes may be interposed therebetween.

  Next, an example of a circuit configuration corresponding to FIGS. 15A and 15B is illustrated in FIG.

  In FIG. 15C, the first wiring (1st Line) and the source electrode of the transistor 760 are electrically connected, and the second wiring (2nd Line) and the drain electrode of the transistor 760 are electrically connected. It is connected. In addition, the third wiring (3rd Line) and one of the source electrode and the drain electrode of the transistor 762 are electrically connected, and the fourth wiring (4th Line) and the gate electrode of the transistor 762 are electrically connected. It is connected to the. One of a gate electrode of the transistor 760 and a source electrode or a drain electrode of the transistor 762 is electrically connected to the other electrode of the capacitor 764, and a fifth wiring (5th Line) and an electrode of the capacitor 764 One of these is electrically connected.

  In the semiconductor device illustrated in FIG. 15C, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the transistor 760 can be held.

  Information writing and holding will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 762 is turned on, so that the transistor 762 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode of the transistor 760 and the capacitor 764. That is, predetermined charge is supplied to the gate electrode of the transistor 760 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 762 is turned off and the transistor 762 is turned off, whereby the charge given to the gate electrode of the transistor 760 is held (held).

  Since the off-state current of the transistor 762 is extremely small, the charge of the gate electrode of the transistor 760 is held for a long time.

Next, reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, the first wiring is changed according to the amount of charge held in the gate electrode of the transistor 760 The two wirings have different potentials. In general, when the transistor 760 is an n-channel transistor, the apparent threshold V _{th_H} when a high level charge is applied to the gate electrode of the transistor 760 is a low level charge applied to the gate electrode of the transistor 760. This is because it becomes lower than the apparent threshold value V _{th_L} of the case. Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary for turning on the transistor 760. Therefore, the charge given to the gate electrode of the transistor 760 can be determined by _setting the potential of the fifth wiring to a potential V _{0 that} is intermediate between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 760 is turned “on” if the potential of the fifth wiring is V ₀ (> V _{th_H} ). In the case where the low-level charge is _supplied , the transistor 760 remains in the “off state” even when the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the held information can be read by looking at the potential of the second wiring.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 760 is turned “off” regardless of the state of the gate electrode, that is, a potential lower than V _{th_H} may be _supplied to the fifth wiring. _{Alternatively} , a potential that turns on the transistor 760 regardless of the state of the gate electrode, that is, a potential higher than V _{th_L} may be _supplied to the fifth wiring.

  In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

  In addition, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that there is no problem of deterioration of the gate insulating film. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data is written depending on the on / off state of the transistor, high-speed operation can be easily realized.

  As described above, a semiconductor device that achieves miniaturization and high integration and is provided with high electrical characteristics, and a method for manufacturing the semiconductor device can be provided.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 6)
In this embodiment, a semiconductor device which uses the transistor described in any of Embodiments 1 to 4 and can hold stored data even when power is not supplied and has no limit on the number of writing operations. A structure different from the structure shown in Embodiment Mode 5 will be described with reference to FIGS.

  FIG. 16A illustrates an example of a circuit configuration of a semiconductor device, and FIG. 16B is a conceptual diagram illustrating an example of a semiconductor device. First, the semiconductor device illustrated in FIG. 16A will be described, and then the semiconductor device illustrated in FIG. 16B will be described below.

  In the semiconductor device illustrated in FIG. 16A, the bit line BL and the source or drain electrode of the transistor 762 are electrically connected, the word line WL and the gate electrode of the transistor 762 are electrically connected, and the transistor 762 The source electrode or the drain electrode of the capacitor and the first terminal of the capacitor 764 are electrically connected.

  Next, the case where data is written to and stored in the semiconductor device (memory cell 850) illustrated in FIG.

  First, the potential of the word line WL is set to a potential at which the transistor 762 is turned on, so that the transistor 762 is turned on. Accordingly, the potential of the bit line BL is supplied to the first terminal of the capacitor 764 (writing). After that, the potential of the first terminal of the capacitor 764 is held (held) by setting the potential of the word line WL to a potential at which the transistor 762 is turned off and the transistor 762 being turned off.

  A transistor 762 including an oxide semiconductor has a feature of extremely low off-state current. Therefore, when the transistor 762 is turned off, the potential of the first terminal of the capacitor 764 (or the charge accumulated in the capacitor 764) can be held for an extremely long time.

  Next, reading of information will be described. When the transistor 762 is turned on, the bit line BL in a floating state and the capacitor 764 are brought into conduction, and charge is redistributed between the bit line BL and the capacitor 764. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL varies depending on the potential of the first terminal of the capacitor 764 (or the charge accumulated in the capacitor 764).

  For example, the potential of the first terminal of the capacitor 764 is V, the capacitor of the capacitor 764 is C, the capacitor component of the bit line BL (hereinafter also referred to as bit line capacitor) is CB, and before the charge is redistributed. When the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, when the potential of the first terminal of the capacitor 764 is two states of V1 and V0 (V1> V0) as the state of the memory cell 850, the bit line BL in the case where the potential V1 is held. It can be seen that the potential (= CB × VB0 + C × V1) / (CB + C)) is higher than the potential (= CB × VB0 + C × V0) / (CB + C)) of the bit line BL when the potential V0 is held. .

  Then, information can be read by comparing the potential of the bit line BL with a predetermined potential.

  As described above, the semiconductor device illustrated in FIG. 16A can hold charge that is accumulated in the capacitor 764 for a long time because the off-state current of the transistor 762 is extremely small. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. Further, stored data can be retained for a long time even when power is not supplied.

  Next, the semiconductor device illustrated in FIG. 16B is described.

  A semiconductor device illustrated in FIG. 16B includes a memory cell array 851a and a memory cell array 851b each including a plurality of memory cells 850 illustrated in FIG. 16A as a memory circuit in an upper portion, and a memory cell array 851 (memory cell array) in a lower portion. 851a and the memory cell array 851b) are provided with a peripheral circuit 853 necessary for operating. Note that the peripheral circuit 853 is electrically connected to the memory cell array 851.

  With the structure illustrated in FIG. 16B, the peripheral circuit 853 can be provided immediately below the memory cell array 851 (the memory cell array 851a and the memory cell array 851b), so that the semiconductor device can be downsized.

  The transistor provided in the peripheral circuit 853 is preferably formed using a semiconductor material different from that of the transistor 762 in Embodiment 5. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor is preferably used. In addition, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, various transistors (logic circuits, drive circuits, etc.) that require high-speed operation can be suitably realized by the transistors.

  Note that the semiconductor device illustrated in FIG. 16B illustrates a structure in which two memory cell arrays 851 (a memory cell array 851a and a memory cell array 851b) are stacked; however, the number of stacked memory cell arrays is not limited thereto. . A structure in which three or more memory cell arrays are stacked may be employed.

  Next, a specific structure of the memory cell 850 illustrated in FIG. 16A will be described with reference to FIGS.

  FIG. 17 shows an example of the structure of the memory cell 850. 17A is a cross-sectional view of the memory cell 850, and FIG. 17B is a plan view of the memory cell 850. Here, FIG. 17A corresponds to a cross section taken along line MN and OP in FIG.

  The transistor 762 illustrated in FIGS. 17A and 17B can have the same structure as those described in Embodiments 1 to 4.

  An interlayer insulating film 750 is provided as a single layer or a stacked layer over the transistor 762. In addition, a conductive film 753 is provided in a region overlapping with the source electrode 742 a of the transistor 762 with the interlayer insulating film 750 interposed therebetween. The source electrode 742 a, the interlayer insulating film 750, and the conductive film 753 provide capacitance. Element 764 is configured. That is, the source electrode 742a of the transistor 762 functions as one electrode of the capacitor 764, and the conductive film 753 functions as the other electrode of the capacitor 764.

  An insulating film 752 is provided over the transistor 762 and the capacitor 764. A memory cell 850 and a wiring 756 for connecting the adjacent memory cell 850 are provided over the insulating film 752. Although not illustrated, the wiring 756 is electrically connected to the drain electrode 742b of the transistor 762 through an opening formed in the interlayer insulating film 750, the insulating film 752, and the like. However, another conductive film may be provided in the opening, and the wiring 756 and the drain electrode 742b may be electrically connected through the other conductive film. Note that the wiring 756 corresponds to the bit line BL in the circuit diagram of FIG.

  In FIGS. 17A and 17B, the drain electrode 742b of the transistor 762 can also function as a source electrode of a transistor included in an adjacent memory cell. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced, and thus high integration can be achieved.

  By adopting the planar layout shown in FIG. 17A, the area occupied by the semiconductor device can be reduced, so that high integration can be achieved.

  As described above, the plurality of memory cells formed in multiple layers in the upper portion are formed using transistors including an oxide semiconductor. Since a transistor including an oxide semiconductor has a small off-state current, stored data can be held for a long time by using the transistor. That is, the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced.

  As described above, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and a transistor using an oxide semiconductor (in a broader sense, sufficiently off) By integrally including a memory circuit using a transistor having a small current, a semiconductor device having characteristics that have never been achieved can be realized. Further, the peripheral circuit and the memory circuit have a stacked structure, whereby the semiconductor device can be integrated.

  As described above, a semiconductor device that achieves miniaturization and high integration and is provided with high electrical characteristics, and a method for manufacturing the semiconductor device can be provided.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 7)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to a portable device such as a mobile phone, a smartphone, or an e-book reader will be described with reference to FIGS.

  In portable devices such as mobile phones, smartphones, and electronic books, SRAM or DRAM is used for temporary storage of image data. The reason why SRAM or DRAM is used is that the flash memory has a slow response and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following characteristics.

In an ordinary SRAM, as shown in FIG. 18A, one memory cell includes six transistors 801 to 806, which are driven by an X decoder 807 and a Y decoder 808. The transistors 803 and 805 and the transistors 804 and 806 form an inverter and can be driven at high speed. However, since one memory cell is composed of 6 transistors, there is a disadvantage that the cell area is large. When the minimum dimension of the design rule is F, the SRAM memory cell area is normally 100 to 150 F ² . For this reason, SRAM has the highest unit price per bit among various memories.

On the other hand, in the DRAM, a memory cell includes a transistor 811 and a storage capacitor 812 as shown in FIG. 18B, and is driven by an X decoder 813 and a Y decoder 814. One cell has a structure of one transistor and one capacitor, and the area is small. The memory cell area of a DRAM is usually 10F ² or less. However, the DRAM always needs refreshing and consumes power even when rewriting is not performed.

However, the memory cell area of the semiconductor device described in the above embodiment is around 10F ² and frequent refreshing is not necessary. Therefore, the memory cell area can be reduced and the power consumption can be reduced.

  FIG. 19 shows a block diagram of a portable device. 19 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, and a touch. A sensor 919, an audio circuit 917, a keyboard 918, and the like are included. The display 913 includes a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface (IF) 909. In general, the memory circuit 912 includes an SRAM or a DRAM. By adopting the semiconductor device described in the above embodiment for this portion, information can be written and read at high speed, and long-term storage can be performed. In addition, power consumption can be sufficiently reduced.

  FIG. 20 shows an example in which the semiconductor device described in any of the above embodiments is used for the memory circuit 950 of the display. A memory circuit 950 illustrated in FIG. 20 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. Further, the memory circuit reads a signal line from the image data (input image data), a memory 952 and data (stored image data) stored in the memory 953, and a display controller 956 that performs control and a display controller 956 A display 957 for displaying by the signal is connected.

  First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. The image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and displayed.

  When there is no change in the input image data A, the stored image data A is normally read from the display controller 956 from the memory 952 via the switch 955 at a cycle of about 30 to 60 Hz.

  Next, for example, when the user performs an operation of rewriting the screen (that is, when the input image data A is changed), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this time, stored image data A is periodically read from the memory 952 via the switch 955. When new image data (stored image data B) is stored in the memory 953, the stored image data B is read from the next frame of the display 957, and is stored in the display 957 via the switch 955 and the display controller 956. The stored image data B is sent and displayed. This reading is continued until new image data is stored in the memory 952 next time.

  In this manner, the memory 952 and the memory 953 display the display 957 by alternately writing image data and reading image data. Note that the memory 952 and the memory 953 are not limited to different memories, and one memory may be divided and used. By employing the semiconductor device described in any of the above embodiments for the memory 952 and the memory 953, information can be written and read at high speed, data can be stored for a long time, and power consumption can be sufficiently reduced. it can.

  FIG. 21 shows a block diagram of an electronic book. 21 includes a battery 1001, a power supply circuit 1002, a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.

  Here, the semiconductor device described in any of the above embodiments can be used for the memory circuit 1007 in FIG. The memory circuit 1007 has a function of temporarily holding the contents of a book. For example, when a user is reading an e-book, use a highlight function that distinguishes a specific part from the surroundings by changing the display color, underlining, making the text thicker, changing the typeface of the text, etc. There are some cases. When information on a location designated by the user is stored for a long time, it may be copied to the flash memory 1004. Even in such a case, by adopting the semiconductor device described in the above embodiment, writing and reading of information can be performed at high speed, long-term storage can be performed, and power consumption can be sufficiently reduced. Can do.

  As described above, the portable device described in this embodiment includes the semiconductor device according to any of the above embodiments. This realizes a portable device that can read data at high speed, can store data for a long period of time, and has low power consumption.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

100 Substrate 102 Gate electrode 104 Gate insulating film 105 Gate insulating film 105a Gate insulating film 105b Side wall insulating film 106 Oxide semiconductor film 107 Conductive film 108a Source electrode 108b Drain electrode 110 Insulating film 115a Region 115b Region 150 Transistor 160 Transistor 200 Substrate 202 Gate Electrode 204 Gate insulating film 206 Oxide semiconductor film 207 Conductive film 208a Source electrode 208b Drain electrode 210 Insulating film 215a Region 215b Region 250 Transistor 300 Base insulating film 301 Base insulating film 302 Conductive film 303 Gate electrode 304 Gate insulating film 306 Oxide semiconductor Film 307 Conductive film 308a Source electrode 308b Drain electrode 310 Insulating film 320 Resist mask 330 Resist mask 350 Transistor 401 Edge film 401a Base insulating film 401b Base insulating film 403 Gate electrode 404 Gate insulating film 405 Oxide semiconductor film 406 Island-shaped oxide semiconductor film 407 Conductive film 408a Source electrode 408b Drain electrode 410 Insulating film 415a Region 415b Region 430 Resist mask 450 Transistor 700 Substrate 706 Element isolation insulating film 708 Gate insulating film 710 Gate electrode 716 Channel formation region 720 Impurity region 724 Intermetallic compound region 728 Insulating film 730 Insulating film 737 Gate insulating film 742a Source electrode 742b Drain electrode 744 Oxide semiconductor film 748 Gate Electrode 750 Interlayer insulating film 752 Insulating film 753 Conductive film 756 Wiring 760 Transistor 762 Transistor 764 Capacitance element 801 Transistor 803 Transistor 804 Transistor 8 5 Transistor 806 Transistor 807 X decoder 808 Y decoder 811 Transistor 812 Holding capacitor 813 X decoder 814 Y decoder 850 Memory cell 851 Memory cell array 851a Memory cell array 851b Memory cell array 901 RF circuit 902 Analog baseband circuit 903 Digital baseband circuit 904 Battery 905 Power supply Circuit 906 Application processor 907 CPU
908 DSP
909 interface (IF)
910 Flash memory 911 Display controller 912 Memory circuit 913 Display 914 Display unit 915 Source driver 916 Gate driver 917 Audio circuit 918 Keyboard 919 Touch sensor 950 Memory circuit 951 Memory controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display controller 957 Display 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash memory 1005 Audio circuit 1006 Keyboard 1007 Memory circuit 1008 Touch panel 1009 Display 1010 Display controller 2100 Substrate 2102 Insulating film 2104 Gate electrode 2106 Oxide semiconductor film 2112 Gate insulating film 2116 Electrode 2118 Storage Insulating film

Claims (12)

A gate electrode provided on an insulating surface;
A gate insulating film covering the gate electrode;
A source electrode and a drain electrode sandwiching the gate electrode through the gate insulating film and not overlapping with an upper surface of the gate electrode;
A semiconductor device comprising: an oxide semiconductor film which is provided so as to overlap with the gate electrode with the gate insulating film interposed therebetween and in which at least part of the source electrode and the drain electrode are in contact with each other.   The semiconductor device according to claim 1, wherein the oxide semiconductor film is provided on the gate insulating film, the source electrode, and the drain electrode.   The semiconductor device according to claim 2, wherein the top surface of the gate insulating film and the top surfaces of the source electrode and the drain electrode are aligned.   The semiconductor device according to claim 1, wherein the oxide semiconductor film is sandwiched between the source electrode and the drain electrode.   The semiconductor device according to claim 4, wherein the height of the upper surface of the oxide semiconductor film is uniform with the upper surfaces of the source electrode and the drain electrode. A base insulating film;
A gate electrode embedded in the base insulating film and having at least a part of an upper surface exposed from the base insulating film;
A gate insulating film provided on at least the gate electrode;
A source electrode and a drain electrode provided on the gate insulating film without overlapping with the gate electrode;
A semiconductor device comprising: an oxide semiconductor film that overlaps at least the gate electrode, at least part of which is in contact with the source electrode and the drain electrode, and is provided over the gate insulating film.   The semiconductor device according to claim 6, wherein heights of the upper surface of the oxide semiconductor film and the upper surfaces of the source electrode and the drain electrode are uniform. Forming a gate electrode on the insulating surface;
Forming a gate insulating film covering the gate electrode;
Forming a conductive film on at least the gate insulating film;
A part of the conductive film is removed so that the gate insulating film is exposed,
Processing the conductive film subjected to the removal treatment to form a source electrode and a drain electrode;
A method for manufacturing a semiconductor device, in which an oxide semiconductor film is formed over the gate insulating film, the source electrode, and the drain electrode. Forming a gate electrode on the insulating surface;
Forming a gate insulating film covering the gate electrode;
Forming an oxide semiconductor film on at least the gate insulating film;
Forming a conductive film on the gate insulating film and the oxide semiconductor film;
A part of the conductive film is removed so that the oxide semiconductor film is exposed,
A method for manufacturing a semiconductor device, in which the conductive film subjected to the removal treatment is processed to form a source electrode and a drain electrode. Forming a base insulating film having a recess,
Forming a first conductive film on the base insulating film;
A part of the first conductive film is removed so that the base insulating film is exposed, and a gate electrode is formed in a recess of the base insulating film,
Forming a gate insulating film on at least the gate electrode;
Forming a second conductive film on the gate insulating film;
Back exposure is performed, and a resist mask is formed on the second conductive film that does not overlap with the gate electrode,
Using the resist mask, a source electrode and a drain electrode are formed on the gate insulating film that does not overlap with the gate electrode,
A method for manufacturing a semiconductor device, in which an oxide semiconductor film is formed over at least the gate insulating film overlapping with the gate electrode. Forming a gate electrode on the insulating surface;
Forming a base insulating film on the gate electrode;
A part of the base insulating film is removed so that the gate electrode is exposed,
Forming a gate insulating film on at least the gate electrode;
Forming an oxide semiconductor film on the gate insulating film;
Back exposure is performed, a resist mask is formed on the oxide semiconductor film overlapping the gate electrode,
Using the resist mask, an island-shaped oxide semiconductor film is formed over the gate insulating film overlapping the gate electrode,
Forming a conductive film over the gate insulating film and the island-shaped oxide semiconductor film;
A removal treatment is performed on a part of the conductive film so that the island-shaped oxide semiconductor film is exposed,
A method for manufacturing a semiconductor device, in which the conductive film subjected to the removal treatment is processed to form a source electrode and a drain electrode.   The method for manufacturing a semiconductor device according to claim 8, wherein the removal treatment is performed by chemical mechanical polishing.