JP2013134265A - Liquid crystal display device and method for driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make timing adjustment according to variation of output delay time due to characteristics of a gate driver IC unnecessary to expand tolerance of output characteristics of the gate driver IC in a liquid crystal display device.SOLUTION: A liquid crystal display device includes: a liquid crystal panel on which a plurality of gate wirings and source wirings are arranged like a matrix, and pixels and their drive transistors are arranged at their crossing parts; a source driver IC; a gate driver IC; and a timing control circuit for performing drive timing control of the source driver IC and the gate driver IC. In the liquid crystal display device, pieces of falling delay time are measured for each of a plurality of gate wiring drive signals to be output from the liquid crystal panel, and output timing of the source driver IC is controlled based on a plurality of pieces of delay time.

Description

  The present invention relates to a liquid crystal display device and a driving method thereof.

The liquid crystal display device includes a liquid crystal panel, a source line drive circuit, a gate line drive circuit, a timing control circuit, and a power supply circuit. In some small liquid crystal driving devices, these wiring driving circuits are driven by an IC formed on a single chip. However, in a liquid crystal display device that cannot use a single chip IC due to an improvement in display resolution, a plurality of source wiring driving circuits and gates are used. Each wiring drive circuit is required.
Further, when a temperature change occurs in the wiring drive circuit of the liquid crystal display device due to the use environment, the output timing varies in the source wiring drive circuit and the gate wiring drive circuit depending on the characteristics of the device used. For this reason, since the operation timing in the liquid crystal display device fluctuates due to temperature changes in the usage environment, the pixel writing timing in the liquid crystal display device cannot be kept constant. For this reason, the visibility is lowered due to a decrease in contrast or uneven stripes due to insufficient writing time or erroneous writing of display data. As a countermeasure against this, the scanning signal applied to the gate wiring is detected by the signal detection unit for the presence or absence of a delay of the turn-on signal, and the pulse width of the clock signal at the logic high interval is adjusted based on the detection result. A technique for compensating for the delay of the turn-on signal is well known (Patent Document 1).

  Here, the pixel writing timing inside the liquid crystal panel of the liquid crystal display device depends on the characteristics of the source wiring driving circuit and the gate wiring driving circuit, and the internal characteristics of both the driving circuits change depending on the temperature of the use environment, If the delay time (particularly the turn-off timing) is large, the pixel writing time is insufficient, or erroneous data writing corresponding to the gate wiring in the next stage occurs, resulting in display unevenness and deterioration of visual characteristics.

JP 2008-176265 A

As described above, in the countermeasure for the fluctuation of the output timing in the gate wiring drive circuit, in the liquid crystal display device adopting, for example, a gate driver IC of a certain manufacturer in the gate wiring drive circuit, various circumstances such as procurement and cost. Therefore, when considering changing the gate driver IC of another manufacturer that has the same performance as the driver IC instead of the manufacturer, the output delay time varies due to the difference in device characteristics, and timing adjustment is required. The replacement is not easy, and the cost is increased by changing the constant in the timing control circuit.
The present application can solve the above-described problems and expands the tolerance of the output characteristics of the gate driver IC in the liquid crystal display device.

  The liquid crystal display device according to the present invention is characterized in that a fall delay time is measured for each of a plurality of gate line drive signals output from a liquid crystal panel, and a source line drive timing is controlled based on the plurality of delay times.

  By correcting the operation timing in the present invention, the pixel writing timing in the liquid crystal display device is always constant, so that it is possible to suppress a decrease in visibility with respect to a temperature change in the usage environment. In addition, when the gate driver IC is replaced in the drive circuit, the replacement can be easily performed without requiring timing adjustment, which contributes to cost reduction.

Schematic configuration diagram of a liquid crystal display device Block diagram of timing control circuit Measurement timing chart for one horizontal scanning period Detection timing of gate output delay time Timing diagram of gate wiring drive signal waveform and source driver IC control signal

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In order to avoid redundant descriptions, the same reference numerals are given to elements having the same or corresponding functions in each drawing.

Embodiment 1 FIG.
An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a schematic configuration diagram of a liquid crystal display device 1, in which a plurality of gate lines and source lines are arranged in a matrix, and a plurality of pixels and TFTs (not shown) for driving the pixels are arranged at intersections thereof. The liquid crystal panel 2 and two source driver ICs as a source wiring driving circuit and one gate driver IC as a gate wiring driving circuit are mounted on a COF (Chip On Film). ), Horizontal and vertical synchronization signals (not shown), data signals (not shown), and reference clock signals are supplied to the control board 14.
In FIG. 1, a plurality of input / output terminals of a source driver IC 12 and a gate driver IC 13 are connected between the liquid crystal panel 2 and the control substrate 14 and drive a plurality of source lines and gate lines. The timing control circuit 15 generates the gate driver IC control signal 3 and the source driver IC control signal 4 based on the reference clock signal and the horizontal and vertical synchronization signals input from the outside, and controls the source driver IC 12 and the gate driver IC 13. To do. The control board 14 includes a timing control circuit 15, a power supply circuit 16, a level conversion circuit unit 17, and the like.

Each gate wiring drive signal applied to the gate wiring input terminal of the liquid crystal panel 2 includes three gate wirings (G ₁ , G _n , G _end ) in the first stage, the nth stage, and the final stage in the liquid crystal panel 2. It is taken out from the side opposite to the input terminal (right side in FIG. 1), inputted to the level conversion circuit unit 17, and inputted to the timing control circuit 15 through the level conversion circuit unit 17. In the present embodiment, the gate driver delay td is detected based on the level-converted gate wiring drive signals (OG ₁ , OG _n , OG _end ), and the source driver outputs to the source driver IC 12 according to the value. The IC control signal 4 is delayed by a predetermined amount. As a result, the timing of the source driver IC control signal 4 output from the source driver IC 12 can always be kept constant with respect to the gate wiring drive signal inside the liquid crystal panel 2.

FIG. 2 shows a schematic configuration diagram of the timing circuit 15. The timing circuit 15 includes a timing generation circuit 21, a first counter 22 (counter 1), and three second counters 23 (counter 2a, counter 2b, counter). 2c) and the arithmetic circuit 25.
In the present embodiment, a level conversion circuit unit 17 for converting the amplitude levels (VDDG / VEEG) of the three gate wiring drive signals into signal amplitude levels (VCC / VSS) that can be input to the control board is further required. is there. The plurality of second counters 23 measure the effective horizontal scanning period of the three gate wiring drive signals, the arithmetic circuit 25 detects the delay time td and stores the value, and based on the stored values. The arithmetic circuit 25 calculates the timing correction value 18 of the source driver IC control signal 4 and outputs it to the timing generation circuit 21.

Next, the timing correction operation of the source driver IC control signal 4 in the timing circuit 15 will be described in detail. Three gate wiring drive signals (OG ₁ , OG _n , OG _end ) input via the level conversion circuit unit 17 having three amplitude conversion circuits are respectively associated with the three second counters 23 (counters 2a, 2a, The counter 1b and the counter 2c) count one effective horizontal scanning period by the reference clock signal DCLK. Here, the effective one horizontal scanning period is a period from the horizontal scanning start timing of the _Gn stage to the fall of the _OGn signal. The counted value is compared with a count value which is a theoretical value for one horizontal scanning period input from the first counter 22 in the arithmetic circuit 25, and the difference is detected as a delay time of each gate wiring drive signal Gn.

The counter control signal 9 (counter reset and count start command) of the first counter 22 and the second counter 23 is input from the timing generation circuit 21 to each counter. Here, the first counter 22 starts and stops counting based on the counter control signal 9 and performs a counting operation for a period corresponding to a theoretical scanning period of each gate wiring.
On the other hand, the three second counters 23 start counting at the same timing as the first counter 22 and are the same as the horizontal scanning start timing, but stop counting is the gate wiring drive signals (OG ₁ , OG _n , OG _end). The count value corresponds to an effective one horizontal scanning period.

  Here, the theoretical value of one horizontal scanning period in the first counter 22 can be set according to the resolution of the liquid crystal panel 2 at the time of activation. In FIG. 2, it is assumed that the output delay of each wiring among the plurality of output wirings is different at each output stage, even if the gate wiring driving signal output is output from one gate driver IC, and arbitrarily detect three points. Although the points are provided and described, the detection points are not limited.

FIG. 3 shows the measurement timing of one horizontal scanning period in each counter, and the detailed timing will be described by taking the gate wiring Gn stage as an example. The G _n signal representing the n-th stage gate wiring scanning period in the figure is an ideal output waveform of the gate driver IC 13, and the falling period from the rising edge of the G _n signal becomes Count 1 shown in FIG. This is the count value of the first counter 22 shown. This is a theoretical value for one horizontal scanning period.

On the other hand, in FIG. 3, the second counter 23 counts a period from the rising time of the signal G _n representing the gate wiring n-th stage gate wiring scanning period to the falling time of the n-th stage gate wiring drive signal OG _n. This is a count value for an effective n-stage horizontal scan period.
In the liquid crystal display device, the output of the gate driver IC 13 has several hundred stages, and there is a possibility that the signal delay time td differs in the actual drive signal depending on the number of stages of each gate wiring. This difference is mainly due to variations in output impedance at each output stage of the gate driver IC 13 and variations in stray capacitance of the gate wiring of the liquid crystal panel 2.

FIG. 4 is an example of detection timing of the delay time of the gate wiring drive signals (OG ₁ , OG _n , OG _end ). Stage G _1, optional output stage G _n, the run specific horizontal scanning period by the gate line driving signals in the last stage G _{with ned} counted by the reference clock signal DCLK of three second counter 23 as shown in the figure, 1 Based on the theoretical value of the horizontal scanning period and the count values (Count2a, 2b, 2c) including the delay of the gate wiring driving signal, the arithmetic circuit 25 calculates the delay time (tda, tdb, tdc) for each gate wiring driving signal. , And output to the timing generation circuit 21.

In the present embodiment, a predetermined constant (which may be a negative number) is added to the above three delay time values, and the source line drive output timing correction value 18 (Tgs) is calculated and stored in the timing generation circuit 21. To do. Further, the scanning period by all the gate wirings G _{1 to} G _end of the liquid crystal panel 2 is divided into two, that is, the vertical scanning period is divided into two, and two timing correction values 18 (Tgsa, Tgsb) are used as the gate wiring G of the next frame. _This is applied to the horizontal scanning period from ₁ to the _Gend stage.
That is, in the horizontal scanning period according to _{G n} stages from the gate line _{G 1} stage, using a timing correction value 18 corresponding to the average value of the delay time tdb of the delay time of the gate lines _{G 1} tda same _{G n} (Tgsa), In the horizontal scanning period from the gate line G _{n + 1} to the G _end stage, the timing correction value 18 (Tgsb) corresponding to the average value of the delay time tdb of the gate line Gn and the delay time tdc of the same G _end is used.

FIG. 5 shows a timing chart of the gate wiring drive signal (OG _n , OG _{n + 1} ) waveform and the source driver IC 12 control signal. The arithmetic operation circuit 25 causes the source line drive output timing correction value 18 to correspond to the output timing of the control signal 4 (LD, POL, Data, etc. in FIG. 5) output to the source line drive circuit (source driver IC 12) in the next frame. As a result, with respect to the ideal gate wiring drive signal indicated by a broken line in the figure, a constant timing corresponding to the time when the effective gate wiring drive signal falls is always maintained. As a result, the pixel writing timing of the liquid crystal panel can suppress the deterioration of display quality due to the usage environment and the characteristic variation of the gate driver IC 13.

In this embodiment, the delay time td of the gate wiring drive signal is measured with three stages of G ₁ stage, G _n stage, and G _end stage. The average value of can be calculated. Further, the source wiring drive timing of the next frame is corrected based on the calculation value, but it may be in the calculation circuit as a storage location of the correction value between detection and the next frame, or may be a timing generation circuit.

On the other hand, although the liquid crystal panel is divided into two regions by performing the three gate wire drive signal delay values, the source wire drive timing correction is exemplified, but there is no reason for the two regions in particular, and the detected gate wire drive signal is Increasing and increasing the area enables further fine correction.
In the horizontal scanning period according to G _n stages from the gate line G ₁ stage in the present embodiment, the timing correction value corresponding to the average value of the delay time tdb of the delay time of the gate lines G ₁ tda same G _n In the horizontal scanning period from the gate wiring G _{n + 1} to the G _end stage, the timing correction value corresponding to the average value of the delay time tdb of the gate wiring Gn and the delay time tdc of the same G _end is used. in the horizontal scanning period according to _{G n + 1} stage from _one stage, using a timing correction value corresponding to the average value of the delay time tdb delay time tda same _{G n} of gate lines _{G 1, G end the} stage from the gate line _{G n} be used in a horizontal scanning period, the timing correction value corresponding to the average value of the delay time tdc of the delay time tdb same G _{end the} gate lines Gn by There.

  In general, an external timing control circuit is configured by a large-scale integrated circuit such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a microcomputer (microcontroller). It is possible to include a counter circuit that detects the delay of the gate wiring drive signal and an arithmetic circuit that adjusts the output timing in accordance with the delay of the gate wiring drive signal, for inputting the gate output signal from the liquid crystal display device. This can be realized by adding a level conversion circuit.

2 Liquid crystal panel 3 Gate driver IC control signal 4 Source driver IC control signal 9 Counter control signal 12 Source driver IC
13 Gate driver IC
14 control board 15 timing control circuit 17 level conversion circuit unit 18 source wiring drive output timing correction value 21 timing generation circuit 22 first counter 23 second counter 25 arithmetic circuit

Claims (3)

A liquid crystal panel in which a plurality of gate wirings and source wirings are arranged in a matrix and pixels and driving transistors are arranged at intersections thereof, a source wiring driving circuit, a gate wiring driving circuit, and the source wiring driving circuit and gate wiring In a liquid crystal display device having a timing control circuit that performs drive timing control of a drive circuit,
A liquid crystal display device, wherein a fall delay time is measured for each of a plurality of gate line drive signals output from the liquid crystal panel, and a source line drive timing is controlled based on the plurality of delay times.   Source line driving for measuring the falling delay time corresponding to each of the two gate wiring driving signals and driving the pixels arranged between the two gate wirings using the average of the two delay times The liquid crystal display device according to claim 1, wherein timing is controlled. A liquid crystal panel in which a plurality of gate wirings and source wirings are arranged in a matrix and pixels and driving transistors are arranged at intersections thereof, a source wiring driving circuit, a gate wiring driving circuit, and the source wiring driving circuit and gate wiring A driving method of a liquid crystal display device having a timing control circuit for controlling driving timing of a driving circuit,
A driving method of a liquid crystal display device, wherein a falling delay time is measured for each of a plurality of gate wiring driving signals output from the liquid crystal panel, and a source wiring driving timing is controlled based on the plurality of delay times.

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