JP2013131773A - Group-iii nitride crystal and its surface treatment method, group-iii nitride laminate and its manufacturing method, and group-iii nitride semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a surface treatment method of group-III nitride crystal, which can reduce impurities on a crystal surface by removing hard abrasive grain remaining in crystal after lapping.SOLUTION: The surface treatment method of group-III nitride crystal comprises a step of: lapping a surface of group-III nitride crystal using hard abrasive grain whose Mohs hardness is higher than 7; and a non-abrasive polishing step of polishing the surface of lapped group-III nitride crystal 1 using polishing liquid 27 which contains no abrasive grain. A platen used in the lapping step is a platen containing at least one chosen from Sn, Sn-Bi alloy, Sn-Sb alloy, Sn-Pb alloy, Cu, AlO, SiO, CeO, phenol resin, urethane resin, amide resin, and imide resin, or a platen on which a pad is attached thereon. The pH of polishing liquid 27 containing no abrasive grain is 1-6 or 8.5-14.

Description

  The present invention relates to a surface treatment method for a group III nitride crystal suitably used for a substrate of a semiconductor device.

For use as a substrate of a semiconductor device or the like, it is preferable that the surface of the grown group III nitride crystal be processed to be as flat and low as possible. For this reason, in US Pat. No. 6,399,500 (Patent Document 1), after polishing the surface of a Ga ₁ -XY Al _X In _Y N crystal using a basic polishing liquid not containing abrasive grains, Polishing with water is disclosed.

  However, since the group III nitride crystal is chemically stable, the polishing efficiency is low even when polishing is performed using a basic polishing liquid that does not contain abrasive grains as described above.

US Pat. No. 6,399,500

  Therefore, in order to efficiently surface the chemically stable group III nitride crystal, it is necessary to wrap or polish using abrasive grains. In particular, it is preferable to wrap the group III nitride crystal using hard abrasive grains having a Mohs hardness higher than that of the group III nitride crystal, for example, a Mohs hardness higher than 7.

  However, when lapping a group III nitride crystal, the hard abrasive grains cut into the crystal surface and mechanically remove the surface layer, so that the hard abrasive grains bite into the crystal surface after lapping and remain. Since group III nitride crystals are chemically stable, etching of the surface with a chemical solution does not proceed. Therefore, the hard abrasive grains remaining on the crystal surface cannot be sufficiently removed by the cleaning treatment with the chemical solution. Therefore, a problem of contamination due to abrasive grains remaining on the crystal surface occurs in a subsequent process such as forming an epitaxial layer on the crystal.

  Therefore, an object of the present invention is to provide a group III nitride crystal surface treatment method that can remove hard abrasive grains remaining on the crystal surface after lapping and reduce impurities on the crystal surface.

  Here, after lapping, the hard abrasive grains remaining on the crystal surface after lapping can be removed by polishing using soft abrasive grains having a Mohs hardness of 7 or less. However, after polishing with soft abrasive grains, the soft abrasive grains remain on the crystal surface. Further, in a group III nitride crystal including a high dislocation density region and a low dislocation density region, a large amount of the high dislocation density region and its periphery are removed, causing a problem that sagging occurs and the effective area becomes small.

  Therefore, in the present invention, when polishing with soft abrasive grains after lapping, excessive removal of the surface in the high dislocation density region and its surroundings can be suppressed to prevent sagging, and soft crystals remaining on the crystal surface can be prevented. It is another object of the present invention to provide a surface treatment method for a group III nitride crystal that can remove abrasive grains and reduce impurities on the crystal surface.

The present invention includes a step of lapping the surface of a group III nitride crystal using hard abrasive grains having a Mohs hardness higher than 7, and a polishing liquid containing no abrasive grains on the surface of the lapped group III nitride crystal. The surface plate used in the lapping step includes Sn, Sn—Bi alloy, Sn—Sb alloy, Sn—Pb alloy, and Cu metal material, Al ₂ O _3. , inorganic materials SiO _2, and CeO _2, and phenol resins, urethane resins, amide resins, and surface plate containing at least one organic material imide resin, as well as any fixed surface plate fixed thereon a pad A surface treatment method of a group III nitride crystal, wherein the polishing liquid not containing abrasive grains has a pH of 1 or more and 6 or less, or 8.5 or more and 14 or less. .

In the non-abrasive polishing step in the surface treatment method for a group III nitride crystal according to the present invention, a polishing pressure of 0.98 kPa (10 gf / cm ²⁾ using a polishing pad having a compression ratio of 1.5% or more and 20% or less. ) Polishing can be performed at 58.8 kPa (600 gf / cm ² ) or less.

  Moreover, this invention is a group III nitride crystal obtained by said surface treatment. Here, by the above surface treatment, the surface roughness Ra of the group III nitride crystal can be made 2 nm or less. Further, the thickness of the work-affected layer can be 50 nm or less. The group III nitride crystal includes a low dislocation density region and a high dislocation density region, and the height difference between the surface of the low dislocation density region and the surface of the high dislocation density region can be 3 μm or less. In the group III nitride crystal including the low dislocation density region and the high dislocation density region, the flat surface region of the low dislocation density region may have an area of 40% or more with respect to the entire surface in the low dislocation density region. it can.

  In addition, the present invention is a group III nitride laminate including the above group III nitride crystal and at least one group III nitride layer epitaxially grown on the surface of the group III nitride crystal. The present invention also relates to a method for producing a group III nitride laminate using the above group III nitride crystal, comprising a step of preparing a group III nitride crystal, and at least a surface of the group III nitride crystal. And a step of epitaxially growing one group III nitride layer. A method for producing a group III nitride laminate.

  The present invention also provides the above group III nitride crystal, at least one group III nitride layer epitaxially grown on the surface of the group III nitride crystal, the outermost layer of the group III nitride layer and the group III nitride A group III nitride semiconductor device including an electrode formed on at least one surface of the physical crystal. The present invention also relates to a method of manufacturing a group III nitride semiconductor device using the above group III nitride crystal, the step of preparing a group III nitride crystal, and at least a surface of the group III nitride crystal. A group III nitride semiconductor device comprising: epitaxially growing a group III nitride layer; and forming an electrode on at least one surface of the outermost layer of the group III nitride layer and the group III nitride crystal. It is a manufacturing method.

  According to the present invention, it is possible to provide a surface treatment method for a group III nitride crystal that can reduce impurities on the crystal surface by removing hard abrasive grains remaining on the crystal surface after lapping by abrasive-free polishing. it can. In addition, when polishing with soft abrasive grains after lapping, the hard abrasive grains remaining on the crystal surface after lapping are removed by soft abrasive polishing, and further, soft abrasive grains remaining on the crystal surface after polishing soft abrasive grains are removed. It is possible to provide a surface treatment method for a group III nitride crystal that can be removed to reduce impurities on the crystal surface.

It is a schematic sectional drawing which shows the lapping process in the surface treatment method of the group III nitride crystal concerning this invention. It is a schematic sectional drawing which shows the non-abrasive polishing process in the surface treatment method of the group III nitride crystal concerning this invention. It is a schematic sectional drawing which shows the soft abrasive grain polishing process in the surface treatment method of the group III nitride crystal concerning this invention. It is the schematic which shows the group III nitride crystal | crystallization containing a high dislocation density area | region and a low dislocation density area | region after a soft abrasive grain polishing process. Here, (a) shows a schematic plan view, and (b) shows a schematic cross-sectional view. It is a schematic sectional drawing which shows the group III nitride laminated body concerning this invention. It is a schematic sectional drawing which shows the group III nitride semiconductor device concerning this invention.

(Embodiment 1)
In one embodiment of the surface treatment method of a group III nitride crystal according to the present invention, referring to FIGS. 1 and 2, the surface of the group III nitride crystal 1 is hardened with hard abrasive grains 16 having a Mohs hardness higher than 7. And a polishing process for polishing the surface of the lapped group III nitride crystal 1 using a polishing liquid 27 that does not include abrasive grains, and a polishing liquid 27 that does not include abrasive grains. The pH is from 1 to 6, or from 8.5 to 14. The surface treatment method of the group III nitride crystal of this embodiment is a non-polishing solution using a polishing liquid that does not include abrasive grains after the lapping process using hard abrasive grains and has a pH of 1 to 6 or 8.5 to 14. The abrasive polishing process can remove hard abrasive grains remaining on the crystal surface and reduce impurities on the crystal surface.

  The surface treatment method for a group III nitride crystal according to the present embodiment includes a step of lapping the surface of the group III nitride crystal 1 using hard abrasive grains 16 having a Mohs hardness higher than 7 with reference to FIG. . By such lapping step, the surface of the group III nitride crystal can be efficiently lapped.

  The lapping process of the present embodiment refers to a process of mechanically smoothing the surface of the group III nitride crystal 1 using the hard abrasive grains 16 having a Mohs hardness higher than 7, for example, referring to FIG. While rotating the platen 15 about the shaft 15c, the hard abrasive grains 16 are supplied from the abrasive grain supply port 19 onto the surface plate 15, and the weight 14 is placed on the crystal holder 11 to which the group III nitride crystal 1 is fixed. The surface of the group III nitride crystal 1 is lapped by pressing the group III nitride crystal 1 against the surface plate 15 supplied with the hard abrasive grains 16 while rotating about the rotation axis 11c. be able to.

Here, the surface plate 15 is not particularly limited as long as lapping can be performed smoothly, but Sn (tin), Sn-Bi (tin-bismuth) alloy, Sn-Sb (tin-antimony) alloy, Sn -pb (tin - lead) alloy, Cu (copper) metal material such as, Al ₂ O ₃ (aluminum oxide), (silicon dioxide) SiO _2, an inorganic material such as CeO ₂ (cerium oxide), phenolic resins, urethane resins A platen containing an organic material such as an amide resin or an imide resin, or a platen made by combining them is preferably used. Further, a pad (not shown) can be fixed on the surface plate 15, and hard abrasive grains 16 can be sprayed thereon and lapped in the same manner as described above.

Further, the hard abrasive grains 16 are not particularly limited as long as the Mohs hardness is higher than 7, but are abrasives containing materials such as diamond, SiC, BN, Si ₃ N ₄ , Al ₂ O ₃ , Cr ₂ O ₃ , and ZrO _2. Grains are preferably used. The type and particle size of these abrasive grains are selected after considering their mechanical lapping action. In order to increase the lapping speed, abrasive grains having high hardness and large particle diameter are used. In order to reduce the surface roughness Ra and Ry to obtain a smooth surface and / or to reduce the work-affected layer, abrasive grains having a low hardness and a small particle diameter are used. In order to shorten the polishing time and obtain a smooth surface, multi-stage wrapping is performed from a large grain size to a small grain size.

  Here, the surface roughness Ra means that the reference area is extracted from the roughness curved surface in the direction of the average surface, and the absolute value of the distance (deviation) from the average surface of the extracted portion to the measurement curved surface is summed up. This is the value averaged over the reference area. The surface roughness Ry is the sum of the height from the average surface of the extracted portion to the highest peak and the depth to the lowest valley bottom from the rough curved surface in the direction of the average surface. . The surface roughness Ra and Ry can be confirmed by AFM (atomic microscope) observation. Further, the work-affected layer refers to a layer in which the crystal lattice formed in the surface side region of the crystal is disturbed by grinding or polishing of the crystal surface, and is observed by TEM (transmission electron microscope) observation and CL (cathode luminescence) observation. The presence of the layer and its thickness can be confirmed.

  In addition to lapping, grinding can be used as the step of mechanically smoothing the surface of group III nitride crystal 1. In grinding, a grindstone in which hard abrasive grains are fixed with a binder is used, and the surface of the group III nitride crystal can be removed and smoothed at a higher speed than lapping.

  In the surface treatment method of the group III nitride crystal of the present embodiment, referring to FIG. 2, the surface of the lapped group III nitride crystal 1 is polished using a polishing liquid 27 containing no abrasive grains. A grain polishing step is provided. By this non-abrasive polishing step, the hard abrasive grains remaining in the crystal can be removed and impurities on the crystal surface can be reduced.

  The abrasive-free polishing step of the present embodiment refers to a step of chemically smoothing the surface of the group III nitride crystal 1 using a polishing liquid that does not contain abrasive grains. For example, referring to FIG. While rotating the polishing pad 28 fixed on the surface plate 25 about the shaft 25c, the polishing liquid 27 containing no abrasive grains is supplied onto the polishing pad 28 from the polishing liquid supply port 29, and the group III nitride is supplied. By placing the weight 24 on the crystal holder 21 to which the crystal 1 is fixed and rotating it about the rotation axis 21c, the group III nitride crystal 1 is pressed against the polishing pad 28, thereby obtaining the group III nitride crystal 1 Impurities such as abrasive grains remaining on the surface can be efficiently removed.

Here, the surface plate 25 is not particularly limited as long as it can smoothly perform abrasive-free polishing. However, a metal material such as stainless steel and aluminum (Al), aluminum oxide (Al ₂ O ₃ ), magnesium oxide ( Preferred is a platen containing inorganic materials such as MgO), aluminum nitride (AlN), silicon carbide (SiC), organic materials such as phenol resin, urethane resin, amide resin, imide resin, etc., and a platen made by combining them. Used.

  The polishing liquid not containing abrasive grains used in the abrasive-free polishing step has a pH of 1 or more and 6 or less, or 8.5 or more and 14 or less. If the pH is less than 1 or greater than 14, the crystal surface roughness Ra and Ry increase. Further, when the pH is larger than 6.5 and smaller than 8.5, the effect of removing impurities on the crystal surface is small. For the same reason, the pH is more preferably 2 or more and 4 or less, or 10 or more and 12 or less.

Here, for adjusting the pH of the polishing liquid not containing abrasive grains, inorganic acids such as hydrochloric acid, nitric acid, sulfuric acid, phosphoric acid, formic acid, acetic acid, citric acid, malic acid, tartaric acid, succinic acid, phthalic acid, maleic acid, Organic acids such as fumaric acid, inorganic alkalis such as KOH and NaOH, organic alkalis such as NH ₄ OH and amines, inorganic salts such as sulfates, nitrates and phosphates, organic salts such as citrates and malates Is used. Among these pH adjusters, from the viewpoint of enhancing the effect of removing impurities on the crystal surface, organic acids and organic alkalis that do not contain a metal element are preferable to inorganic acids and inorganic alkalis. Among organic acids, polyvalent carboxylic acids having 2 or more carboxyl groups are preferred. Furthermore, pH can also be adjusted by adding an oxidizing agent described later.

  Moreover, it is preferable that the polishing liquid not containing abrasive grains contains an oxidizing agent. A polishing liquid that does not contain abrasive grains increases the ORP (oxidation-reduction potential) by containing an oxidizing agent, and the effect of removing impurities such as abrasive grains remaining on the crystal surface is enhanced. Here, the oxidizing agent is not particularly limited, but from the viewpoint of increasing ORP, chlorinated isocyanuric acid such as hypochlorous acid and trichloroisocyanuric acid, chlorinated isocyanurate such as sodium dichloroisocyanurate, permanganic acid Permanganates such as potassium, dichromates such as potassium dichromate, bromates such as potassium bromate, thiosulfates such as sodium thiosulfate, persulfates such as ammonium persulfate and potassium persulfate, nitric acid, persulfate Hydrogen oxide water, ozone and the like are preferably used.

Here, from the viewpoint of enhancing the effect of removing impurities such as abrasive grains remaining on the crystal surface, the polishing liquid not containing abrasive grains has the following relationship between the pH value x and the ORP value y (mV). Preferably there is. That is, in the acidic condition of 1 ≦ x ≦ 6,
−50x + 1000 <y <−50x + 1800 (1)
In alkaline conditions of 8.5 ≦ x ≦ 14,
−50x + 800 <y <−50x + 1500 (2)
It is preferable to satisfy the relationship.

  Further, a surfactant can be further added to the polishing liquid not containing abrasive grains from the viewpoint of enhancing the effect of removing impurities. The surfactant added to the polishing liquid not containing abrasive grains is not particularly limited, and anionic, cationic or nonionic surfactants can be used. From the viewpoint of high impurity removal effect, anionic or cationic A surfactant is preferably used.

Here, the group III nitride crystal is grown by various vapor phase methods such as HVPE (hydride vapor phase epitaxy) method and sublimation method, and various liquid phase methods such as solution method (including flux method). In the growth of group III nitride crystals, in order to reduce the dislocation density in the crystal, a mask layer such as SiO ₂ having an opening is formed on the base substrate, and the group III nitride crystal is facet grown thereon. (For example, refer to JP2003-165799A, JP2003-183100A, etc.).

  Referring to FIG. 4, group III nitride crystal 1 grown by facet growth has a high dislocation density region 1h in which dislocations existing in the crystal are collected, and a low dislocation density region 1k in which dislocations are reduced. Exists. Here, the group III nitride crystal including the high dislocation density region 1h and the low dislocation density region 1k has a structure in which high dislocation density regions are arranged in stripes with respect to the low dislocation density region (striped structure, FIG. 4) or a structure in which high dislocation density regions are arranged in a dot shape with respect to a low dislocation density region (dot type structure, not shown). Further, the high dislocation density region 1h and the low dislocation density region 1k in the group III nitride crystal 1 can be observed by CL observation (S-4300 manufactured by Hitachi, Ltd.).

  In the group III nitride crystal grown by the above facet growth method, the surface of the low dislocation density region 1k is a Ga atom surface, while the surface of the high dislocation density region 1h is an N atom surface. For this reason, the surface of the high dislocation density region 1h has a higher chemical polishing rate than the surface of the low dislocation density region 1k. Therefore, referring to FIG. 4, when the surface of group III nitride crystal 1 including high dislocation density region 1h and low dislocation density region 1k is subjected to chemical polishing such as abrasive-free polishing, high dislocation density region 1h. Is indented compared to the surface of the low dislocation density region 1k.

  For this reason, it is preferable to use the polishing pad 28 having a compression rate of 1.5% or more and 20% or less in the abrasive-free polishing step of the present embodiment. When the compressibility of the polishing pad 28 is less than 1.5%, the surface roughness Ra and Ry of the crystal after the abrasive-free polishing is increased. When the compressibility of the polishing pad 28 is larger than 20%, the effect of removing impurities is reduced, the dents in the surface of the high dislocation density region 1h of the group III nitride crystal are increased, and the surface of the low dislocation density region 1k is increased. The flat surface area 1 ps is reduced. From this viewpoint, the compression rate of the polishing pad used in the abrasive-free polishing step is more preferably 3% or more and 10% or more.

  From the above viewpoint, the polishing pad 28 is preferably made of polyurethane or the like and has a form such as suede, non-woven fabric, elastomer, foam (foam) or the like.

Here, in the present application, the compression rate of the polishing pad is defined as the pad thickness T ₁ after 1 minute from the initial load W ₁ being applied to the pad and the pad thickness 1 minute after the load is increased to W _2. From T ₂ , the following formula (A)
Compression rate (%) = (T ₁ −T ₂ ) / T ₂ × 100 (A)
Defined by Here, in the calculation of the compressibility, the initial load W ₁ was 100 g, and the load W ₂ was 1600 g.

The polishing pressure in the abrasive-free polishing step is preferably 0.98 kPa (10 gf / cm ² ) or more and 58.8 kPa (600 gf / cm ² ) or less. When the polishing pressure is smaller than 0.98 kPa (10 gf / cm ² ), the effect of removing impurities such as hard abrasive grains remaining on the crystal surface is reduced, and the effect of smoothing the entire crystal surface is reduced. When the polishing pressure is greater than 58.8 kPa (600 gf / cm ² ), the surface roughness Ra and Ry of the crystal increase, and the flat surface region 1 ps on the surface of the low dislocation density region 1k decreases. From this viewpoint, the polishing pressure in the abrasive-free polishing step is more preferably 4.9 kPa (50 gf / cm ² ) or more and 39.2 kPa (400 gf / cm ² ) or less.

  Further, in order to further remove the hard abrasive grains, a water washing step can be provided after the non-abrasive polishing step. The cleaning method is not particularly limited, and ultrasonic cleaning, scrub cleaning, and the like are used, but scrub cleaning is preferable from the viewpoint of enhancing the effect of removing hard abrasive grains. The scrub cleaning is preferably performed after polishing and before the crystal surface is dried. By scrub cleaning, impurities on the side surface as well as the main surface of the crystal can be effectively removed.

  Note that the surface of the group III nitride crystal 1 ground using a grindstone in which hard abrasive grains are fixed by a binder can also be polished using a polishing liquid 27 that does not contain abrasive grains. By this non-abrasive polishing step, the hard abrasive grains remaining in the crystal can be removed and impurities on the crystal surface can be reduced.

(Embodiment 2)
Another embodiment of the surface treatment method of a group III nitride crystal according to the present invention is described below with reference to FIG. 1 to FIG. 3, after the lapping step (FIG. 1) of the surface treatment method of the first embodiment. Before the polishing step (FIG. 2), the lapping surface is further provided with a soft abrasive polishing step (FIG. 3) for polishing using a polishing liquid 37 containing soft abrasive particles 36 having a Mohs hardness of 7 or less. The soft abrasive grain polishing step can remove hard abrasive grains remaining on the crystal surface. Further, the soft abrasive grains remaining on the surface of the crystal by the soft abrasive polishing process are removed by the subsequent abrasive-free polishing process.

  That is, in the surface treatment method for a group III nitride crystal of the present embodiment, the surface of the group III nitride crystal is lapped using a hard abrasive having a Mohs hardness higher than 7 (FIG. 1) and the lapping process. A soft abrasive polishing step (FIG. 3) for polishing the surface of the group III nitride crystal using a polishing liquid 37 containing soft abrasive grains 36 having a Mohs hardness of 7 or less, and the group III nitride subjected to soft abrasive polishing A non-abrasive polishing step (FIG. 2) in which the surface of the crystal is polished using a polishing liquid having no abrasive grains and having a pH of 1 or more and 6 or less or 8.5 or more and 14 or less.

  Here, the lapping process of the present embodiment is the same as the lapping process of the first embodiment. The soft abrasive polishing process of the present embodiment refers to a process of smoothing the surface of the group III nitride crystal 1 chemically and mechanically. For example, referring to FIG. While rotating the polishing pad 38 fixed on the surface 35, a polishing liquid 37 containing soft abrasive grains 36 is supplied onto the polishing pad 38 from the polishing liquid supply port 39, and a crystal holder in which the group III nitride crystal 1 is fixed A group 34 nitride crystal 1 is pressed against the polishing pad 38 while a weight 34 is placed on 31 and rotated about its rotation axis 31c, whereby the surface of the group III nitride crystal 1 is chemically and mechanically applied. Can be policed. The soft abrasive grain polishing step can remove hard abrasive grains remaining on the crystal surface.

Here, the surface plate 35 is not particularly limited as long as it can smoothly polish the soft abrasive grains, but is stainless steel, aluminum (Al), aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO), nitriding. A platen containing an inorganic material such as aluminum (AlN) or silicon carbide (SiC), an organic material such as a phenol resin, a urethane resin, an amide resin, or an imide resin, or a platen obtained by combining them is preferably used.

The soft abrasive grains used in the soft abrasive polishing step are not particularly limited as long as the Mohs hardness is 7 or less, but ZrO ₂ , SiO ₂ , CeO ₂ , MnO ₂ , Fe ₂ O ₃ , Fe ₃ O ₄ , NiO. Abrasive grains containing materials such as ZnO, CoO, Co ₃ O ₄ , GeO ₂ , Ga ₂ O ₃ , and In ₂ O ₃ are preferably used. From the standpoint of enhancing the removability of the soft abrasive grains in the subsequent abrasive-free polishing, it is preferable that the metal element of the soft abrasive grains has a large ionization tendency. Furthermore, from the viewpoint of enhancing the removability of soft abrasive grains in cleaning described later, those having a larger ionization tendency than H (hydrogen) are more preferable.

  The polishing liquid 37 containing the soft abrasive grains 36 is not particularly limited, but is the same as the polishing liquid containing no abrasive grains from the viewpoint of enhancing the effect of removing impurities such as hard abrasive grains remaining on the crystal surface. It is preferable to have a pH. That is, the pH of the polishing liquid 37 containing the soft abrasive grains 36 is preferably 1 or more and 6 or less, or 8.5 or more and 14 or less, and more preferably 2 or more and 4 or less, or 10 or more and 12 or less. Further, for adjusting the pH of the polishing liquid containing soft abrasive grains, the same inorganic acid, organic acid, inorganic alkali, organic alkali, inorganic salt, organic salt and oxidizing agent as the polishing liquid not containing abrasive grains can be used. . Moreover, in these pH adjusters, the organic acid and organic alkali which do not contain a metal element from an inorganic acid and an inorganic salt are preferable from a viewpoint of improving the effect of removing impurities on the crystal surface. Among organic acids, polyvalent carboxylic acids having 2 or more carboxyl groups are preferred.

Also, from the viewpoint of enhancing the effect of removing impurities such as hard abrasive grains remaining on the crystal surface, the polishing liquid containing soft abrasive grains is similar to the polishing liquid not containing abrasive grains in the pH value x and ORP value y. It is preferable that there is the following relationship with (mV). That is, in the acidic condition of 1 ≦ x ≦ 6,
−50x + 1000 <y <−50x + 1800 (3)
In alkaline conditions of 8.5 ≦ x ≦ 14,
−50x + 800 <y <−50x + 1500 (4)
It is preferable to satisfy the relationship.

Here, the group III nitride crystal is grown by various vapor phase methods such as HVPE (hydride vapor phase epitaxy) method and sublimation method, and various liquid phase methods such as solution method (including flux method). In the growth of group III nitride crystals, in order to reduce the dislocation density in the crystal, a mask layer such as SiO ₂ having an opening is formed on the base substrate, and the group III nitride crystal is facet grown thereon. (For example, refer to JP2003-165799A, JP2003-183100A, etc.). Referring to FIG. 4, group III nitride crystal 1 grown by such facet growth has a high dislocation density region 1h in which dislocations present in the crystal are collected and a low dislocation density region 1k in which dislocations are reduced. Exists. Here, the group III nitride crystal including the high dislocation density region 1h and the low dislocation density region 1k has a structure in which high dislocation density regions are arranged in stripes with respect to the low dislocation density region (striped structure, FIG. 4) or a structure in which high dislocation density regions are arranged in a dot shape with respect to a low dislocation density region (dot type structure, not shown). Further, the high dislocation density region 1h and the low dislocation density region 1k in the group III nitride crystal 1 can be observed by CL observation (S-4300 manufactured by Hitachi, Ltd.).

  In the group III nitride crystal grown by the above facet growth method, the surface of the low dislocation density region 1k is a Ga atom surface, while the surface of the high dislocation density region 1h is an N atom surface. For this reason, the surface of the high dislocation density region 1h has a higher chemical mechanical polishing rate than the surface of the low dislocation density region 1k. Therefore, referring to FIG. 4, when the surface of group III nitride crystal 1 including high dislocation density region 1h and low dislocation density region 1k is subjected to chemical mechanical polishing such as polishing with a polishing liquid containing soft abrasive grains. The surface of the high dislocation density region 1h is recessed compared to the surface of the low dislocation density region 1k.

For this reason, in the soft abrasive polishing process of the present embodiment, a polishing pressure of 4.9 kPa (50 gf / cm ² ) or more and 98 kPa (1000 gf / 1000) is used using a polishing pad 38 having a compression rate of 0.8% or more and 5% or less. It is preferable to perform polishing at a cm ² ) or less. From this point of view, the polishing pad 38 is preferably made of polyurethane or the like and has a form such as suede, non-woven fabric, elastomer, foam (foam) or the like.

  When the compressibility of the polishing pad 38 is less than 0.8%, the surface roughness Ra and Ry of the crystal after the soft abrasive polishing is increased. When the compressibility of the polishing pad 38 is larger than 5%, the surface dent of the high dislocation density region 1h of the group III nitride crystal becomes large, and the flat surface region 1ps on the surface of the low dislocation density region 1k becomes small. From this viewpoint, the compression rate of the polishing pad 38 is more preferably 1% or more and 3% or less.

Also, if the polishing pressure is smaller than 4.9 kPa (50 gf / cm ² ), the effect of removing impurities such as hard abrasive grains remaining on the crystal surface is reduced, and the effect of smoothing the entire crystal surface is reduced. When the polishing pressure is larger than 98.1 kPa (1000 gf / cm ² ), the surface roughness Ra, Ry of the crystal is increased, the surface dent of the high dislocation density region is increased, and the surface of the low dislocation density region 1k is increased. The flat surface area 1 ps is reduced. From this viewpoint, the polishing pressure is more preferably 9.8 kPa (100 gf / cm ² ) or more and 68.6 kPa (700 gf / cm ² ) or less.

  The abrasive-free polishing step of the present embodiment is the same as that of the first embodiment except that the surface of the group III nitride crystal subjected to soft abrasive polishing is polished instead of the surface of the lapped group III nitride crystal. This is the same as the grain polishing step. By this non-abrasive polishing step, impurities such as soft abrasive grains remaining on the crystal surface are removed.

  Further, in order to further remove the soft abrasive grains, a water washing step can be provided after the non-abrasive polishing step. The cleaning method is not particularly limited, and ultrasonic cleaning, scrub cleaning, and the like are used, but scrub cleaning is preferable from the viewpoint of enhancing the effect of removing soft abrasive grains. The scrub cleaning is preferably performed after polishing and before the crystal surface is dried. By scrub cleaning, impurities on the side surface as well as the main surface of the crystal can be effectively removed.

(Embodiment 3)
One embodiment of a group III nitride crystal according to the present invention is a group III nitride crystal 1 obtained by the surface treatment of Embodiment 1 or Embodiment 2 with reference to FIG. Since the group III nitride crystal of this embodiment is subjected to the surface treatment of Embodiment 1 or Embodiment 2, impurities such as hard abrasive grains and soft abrasive grains remaining on the crystal surface are removed. Therefore, by epitaxially growing one or more group III nitride layers on the surface of the group III nitride crystal of the present embodiment, a high-performance semiconductor device can be obtained with high yield.

  The group III nitride crystal 1 of the present embodiment has a surface roughness Ra of 2 nm or less from the viewpoint of obtaining a semiconductor device with high yield by epitaxially growing one or more group III nitride layers on the crystal surface. Preferably, 1 nm or less is more preferable. From the same viewpoint, the surface roughness Ry is preferably 20 nm or less, and more preferably 10 nm or less. Furthermore, from the same viewpoint, the thickness of the work-affected layer of the group III nitride crystal is preferably 50 nm or less, and more preferably 30 nm or less.

  The group III nitride crystal of this embodiment may be a crystal having a uniform dislocation density on the crystal surface or a crystal having a non-uniform dislocation density on the crystal surface. An example of a crystal having a non-uniform dislocation density on the crystal surface is a crystal including a low dislocation density region 1k and a high dislocation density region 1h as shown in FIG.

  In the group III nitride crystal of this embodiment, referring to FIG. 4, the height difference D between the surface of the low dislocation density region 1k and the surface of the high dislocation density region 1h is preferably 3 μm or less. By epitaxially growing one or more group III nitride layers on the surface of the group III nitride crystal 1 having a height difference D of 3 μm or less between the surface of the low dislocation density region 1k and the surface of the high dislocation density region 1h, A high-performance semiconductor device can be obtained with high yield.

In addition, with reference to FIG. 4, the group III nitride crystal of the present embodiment has an area where the flat surface region 1ps of the low dislocation density region 1k is 40% or more with respect to the entire surface 1ks in the low dislocation density region 1k. It is preferable. Here, the flat surface region 1 ps in the low dislocation density region 1k is a point P at a constant distance of 10 μm from the highest point P ₀ or the highest line L _{0 on} the surface of the low dislocation density region 1k toward the outer edge of the low dislocation density region. ₁ , point P ₂ ,..., Point P _k−1 , point P _k (where k is a positive integer), the highest point P ₀ or the highest line L _{0 on} the surface of the low dislocation density region 1 k An arbitrary point P _{k at} which an inclination angle θ formed by a straight line including the points P _k-1 and P _k is less than 0.1 ° with respect to a reference plane Q that is in contact with the surface (a curved surface close to a plane). Is defined as the surface area where the The flat surface region 1 ps continuously exists from the center of the surface of the low dislocation density region 1k toward the outer edge. Since the high dislocation density region 1h is easily removed during polishing, the outer edge portion of the low dislocation density region 1k located in the vicinity of the high dislocation density region 1h is preferentially removed as compared with the central portion of the low dislocation density region 1k. Shape sag occurs. For this reason, the tilt angle θ is increased, and a region of 0.1 ° or more is generated. Further, the ratio (percentage) of the area of the flat surface region 1ps of the low dislocation density region 1k to the area of the entire surface 1ks in the low dislocation density region 1k is defined as a flat surface region ratio (unit:%).

  Further, the group III nitride crystal in which the flat surface region 1ps of the low dislocation density region 1k has an area of 40% or more with respect to the entire surface 1ks in the low dislocation density region 1k (that is, the III having a flat surface region ratio of 40% or more) By epitaxially growing one or more group III nitride layers on the surface of the group nitride crystal), a group III nitride semiconductor device having high characteristics and high yield can be obtained. From this viewpoint, the flat surface area ratio is preferably 60% or more, and more preferably 80% or more.

(Embodiment 4)
Referring to FIG. 5, a group III nitride laminate according to the present invention includes a group III nitride crystal 1 of embodiment 3 and at least one group III group epitaxially grown on the surface of group III nitride crystal 1. A nitride layer 650. The group III nitride laminated body 500 of the present embodiment has at least one group III nitride layer 650 epitaxially grown on the surface of the group III nitride crystal of the third embodiment, and therefore, by a PL (photoluminescence) method. The intensity of emitted light (PL intensity) is high.

More specifically, referring to FIG. 5, the group III nitride laminate of this embodiment is at least epitaxially grown on one main surface of an n-type GaN crystal substrate (group III nitride crystal 1). As a group III nitride layer, an n-type GaN layer 621 having a thickness of 1 μm as an n-type semiconductor layer 620, an n-type Al _0.1 Ga _0.9 N layer 622 having a thickness of 150 nm, a light emitting layer 640, and a p-type semiconductor layer 630 are used. A p-type Al _0.2 Ga _0.8 N layer 631 having a thickness of 20 nm and a p-type GaN layer 632 having a thickness of 150 nm are sequentially disposed. Here, the light emitting layer 640 is formed by alternately laminating four barrier layers formed of GaN layers having a thickness of 10 nm and three well layers formed of Ga _0.85 In _0.15 N layers having a thickness of 3 nm. It has a multiple quantum well structure.

(Embodiment 5)
The method for producing a group III nitride laminate according to the present invention is a method for producing a group III nitride laminate 500 using the group III nitride crystal 1 of Embodiment 3 with reference to FIG. Preparing a group nitride crystal 1 and epitaxially growing at least one group III nitride layer 650 on the surface of the group III nitride crystal 1. By epitaxially growing one or more group III nitride layers on the surface of the group III nitride crystal, a group III nitride laminate having high light intensity (PL intensity) emitted by the PL method can be obtained. .

With reference to FIG. 5, for example, an n-type GaN crystal substrate (group III nitride crystal 1) is placed in an MOCVD apparatus and the n-type GaN manufacturing method of the group III nitride laminate of this embodiment is performed. On one main surface of the crystal substrate (group III nitride crystal 1), at least one group III nitride layer 650 is formed as an n-type semiconductor layer 620 by MOCVD (metal organic chemical vapor deposition). An n-type GaN layer 621 having a thickness of 1 μm, an n-type Al _0.1 Ga _0.9 N layer 622 having a thickness of 150 nm, a light emitting layer 640, a p-type Al _0.2 Ga _0.8 N layer 631 having a thickness of 20 nm as a p-type semiconductor layer 630, and a thickness A 150 nm p-type GaN layer 632 is epitaxially grown sequentially. Here, the light emitting layer 640 is formed by alternately laminating four barrier layers formed of GaN layers having a thickness of 10 nm and three well layers formed of Ga _0.85 In _0.15 N layers having a thickness of 3 nm. A multi-quantum well structure.

(Embodiment 6)
Referring to FIG. 6, a group III nitride semiconductor device according to the present invention includes a group III nitride crystal 1 of embodiment 3 and at least one layer of group III epitaxially grown on the surface of group III nitride crystal 1. Nitride layer 650 and electrodes 661 and 662 formed on the outermost surface of group III nitride layer 650 and at least one surface of group III nitride crystal 1 are included. Since the group III nitride semiconductor device 600 of this embodiment has at least one group III nitride layer 650 epitaxially grown on the surface of the group III nitride crystal of embodiment 3, the emission intensity is high.

More specifically, referring to FIG. 6, the group III nitride semiconductor device of this embodiment is at least epitaxially grown on one main surface of an n-type GaN crystal substrate (group III nitride crystal 1). As one group III nitride layer 650, an n-type GaN layer 621 having a thickness of 1 μm as an n-type semiconductor layer 620, an n-type Al _0.1 Ga _0.9 N layer 622 having a thickness of 150 nm, a light emitting layer 640, and a p-type semiconductor A p-type Al _0.2 Ga _0.8 N layer 631 having a thickness of 20 nm and a p-type GaN layer 632 having a thickness of 150 nm are sequentially disposed as the layer 630. Here, the light emitting layer 640 is formed by alternately laminating four barrier layers formed of GaN layers having a thickness of 10 nm and three well layers formed of Ga _0.85 In _0.15 N layers having a thickness of 3 nm. It has a multiple quantum well structure.

  In addition, the group III nitride semiconductor device of the present embodiment has a group III nitride layer 650 as an electrode formed on at least one surface of the group III nitride layer 650 and at least one surface of the group III nitride crystal 1. A second electrode 662 (p-side electrode) is placed on p-type GaN layer 632 which is the outermost layer, and first electrode 661 is placed on the other main surface of n-type GaN crystal substrate (Group III nitride crystal 1). (N-side electrode) is placed.

  Note that in the semiconductor device 700 including an LED (light emitting diode, hereinafter the same) as the group III nitride semiconductor device 600 described above, the second electrode (p-side electrode) of the group III nitride semiconductor device 600 is the solder layer 670. Bonded to the conductor 682, the first electrode (n-side electrode) is bonded to the conductor 681 with a wire 690.

(Embodiment 7)
A method for producing a group III nitride semiconductor device according to the present invention is a method for producing a semiconductor device using a group III nitride crystal of Embodiment 3, comprising the step of preparing a group III nitride crystal 1, and a group III Epitaxially growing at least one group III nitride layer 650 on the surface of nitride crystal 1 and forming an electrode on the outermost surface of group III nitride layer 650 and at least one surface of group III nitride crystal 1 A process. By epitaxially growing one or more group III nitride layers on the surface of the group III nitride crystal, a group III nitride semiconductor device can be obtained with high yield.

With reference to FIG. 6, for example, an n-type GaN crystal substrate (group III nitride crystal 1) is placed in an MOCVD apparatus and the n-type GaN manufacturing method of the group III nitride semiconductor device of this embodiment is performed. On one main surface of the crystal substrate (group III nitride crystal 1), at least one group III nitride layer 650 is formed as an n-type semiconductor layer 620 by MOCVD (metal organic chemical vapor deposition). An n-type GaN layer 621 having a thickness of 1 μm, an n-type Al _0.1 Ga _0.9 N layer 622 having a thickness of 150 nm, a light emitting layer 640, a p-type Al _0.2 Ga _0.8 N layer 631 having a thickness of 20 nm as a p-type semiconductor layer 630, and a thickness A 150 nm p-type GaN layer 632 is epitaxially grown sequentially. Here, the light emitting layer 640 is formed by alternately laminating four barrier layers formed of GaN layers having a thickness of 10 nm and three well layers formed of Ga _0.85 In _0.15 N layers having a thickness of 3 nm. A multi-quantum well structure.

  Next, an n-side electrode having a diameter of 100 μm is formed as the first electrode 661 on the other main surface of the n-type GaN crystal substrate (group III nitride crystal 1). On the other hand, a p-side electrode is formed as the second electrode 662 on the p-type GaN layer 632. The laminated body is made into a chip of 400 μm square to obtain an LED (light emitting diode) as a group III nitride semiconductor device 600.

  After that, the p-side electrode is bonded to the conductor 682 with the solder layer 670, and the n-side electrode and the conductor 681 are bonded with the wire 690 to obtain the semiconductor device 700 including the LED.

(Examples A1 to A7, Comparative Examples AR1 and AR2)
1. Lapping process An n-type GaN crystal grown by the HVPE method is sliced along a plane parallel to the {0001} plane to obtain an n-type GaN crystal substrate (group III nitride crystal 1) having a diameter of 50 mm and a thickness of 0.5 mm. It was. Referring to FIG. 1, the back surface of this n-type GaN crystal substrate (group III nitride crystal 1) (N atom surface; this surface is defined as (000-1) surface) is placed on a ceramic crystal holder 11 with wax. Pasted with. A surface plate 15 having a diameter of 300 mm is installed in a lapping apparatus (not shown), and diamond abrasive grains (hard abrasive grains 16) having a particle diameter of 2 μm are sprayed on the surface plate 15 made of Sn (tin) from the abrasive grain supply port 19. However, while rotating the platen 15 around the rotation axis 15c and placing the weight 14 on the crystal holder 11, the n-type GaN crystal substrate (Group III nitride crystal 1) is pressed against the platen 15, By rotating the n-type GaN crystal substrate (Group III nitride crystal 1) about the rotation axis 11c of the crystal holder 11, the surface of the n-type GaN crystal (Ga atom surface. This surface is defined as the (0001) plane. .) Was wrapped. The Mohs hardness of the diamond abrasive grains is 10.

Here, the lapping pressure is 29.4 kPa (300 gf / cm ² ), and the rotation speeds of the n-type GaN crystal substrate (Group III nitride crystal 1) and the surface plate 15 are both 30 rpm (times / min) to 100 rpm (times). / Min), and the wrapping time was 30 minutes. By such lapping, the surface of the n-type GaN crystal substrate became a mirror surface. After the lapping, the n-type GaN crystal substrate had a surface roughness Ry of 30 nm and a surface roughness Ra of 3.0 nm.

2. Next, referring to FIG. 1 and FIG. 2, the n-type GaN crystal substrate (group III nitride) after lapping while being fixed to the crystal holder 11 (corresponding to the crystal holder 21 in FIG. 2) Crystal 1) was polished without abrasive grains as follows. A polishing pad 28 is installed on a surface plate 25 having a diameter of 380 mm installed in a polishing apparatus (not shown), and a polishing liquid 27 containing no abrasive grains is supplied to the polishing pad 28 from a polishing liquid supply port 29 while rotating. The polishing pad 28 is rotated about the shaft 25c, and the n-type GaN crystal substrate (group III nitride crystal 1) after lapping fixed to the crystal holder 21 by placing the weight 24 on the crystal holder 21 is polished. The n-type GaN crystal substrate (Group III nitride crystal 1) is rotated about the rotation axis 21c of the crystal holder 21 while being pressed against the pad 28, so that the n-type GaN crystal substrate (Group III nitride crystal 1) is rotated. The surface (Ga atom surface) was polished.

Here, as the polishing liquid 27 containing no abrasive grains, a liquid containing acids and oxidizing agents shown in Table 1 and having pH and ORP shown in Table 1 was used. TCIA in Table 1 indicates trichloroisocyanuric acid, and DCIA-Na indicates sodium dichloroisocyanurate. Further, as the polishing pad 28, a polyurethane nonwoven fabric pad having a compression rate shown in Table 1 was used. Further, as the surface plate 25, a stainless steel surface plate was used. Regarding the polishing conditions, the polishing pressure is 29.4 kPa (300 gf / cm ² ), and the rotational speeds of the n-type GaN crystal substrate (group III nitride crystal 1) and the polishing pad 28 are both 30 rpm (times / min) to 100 rpm ( Times / min) and the polishing time was 30 minutes.

  Through the above steps, the surface treatment of the crystals of Examples A1 to A7 and Comparative Examples AR1 and AR2 shown in Table 1 was performed, and the impurity concentration and surface roughness Ra and Ry on the crystal surface after the surface treatment were measured. Here, the concentration of C (carbon) as an impurity was measured by an AES (Auger electron spectroscopy) method. This C is considered to be derived from diamond abrasive grains. The surface roughness Ra and Ry were calculated from AFM (atomic microscope) observation within a 10 μm × 10 μm square range on the crystal surface. The results are summarized in Table 1.

  Referring to Table 1, as shown in Examples A1 to A7, a lapping process using hard abrasive grains having a Mohs hardness greater than 7 (for example, diamond abrasive grains having a Mohs hardness of 10) and no abrasive grains are included. including a non-abrasive polishing step in which a polishing pressure is 0.98 kPa to 58.8 kPa using a polishing liquid having a pH of 1 to 6 and a polishing pad having a compressibility of 1.5% to 20%. By the surface treatment, a crystal surface having a low impurity concentration on the crystal surface and low surface roughness Ra and Ry was obtained. Moreover, in Comparative Example AR1, since the pH of the polishing liquid not containing abrasive grains was 0.5 and smaller than 1, the surface roughness Ra and Ry increased. In Comparative Example AR2, the pH was 7 and was higher than 6, so the concentration of C (carbon) that was an impurity remaining on the crystal surface was high.

(Examples B1 to B5, comparative example BR1)
1. Lapping Step Example A1 except that diamond abrasive grains having a particle diameter of 3 μm were used as the hard abrasive grains 16, and a surface plate made of Sn—Bi (Bi content: 2 mass%) alloy was used as the surface plate 15. In the same manner as described above, the lapping process was performed on the surface (Ga atom surface) of the n-type GaN crystal substrate (Group III nitride crystal 1). By such lapping, the surface of the n-type GaN crystal substrate became a mirror surface. After the lapping, the n-type GaN crystal substrate had a surface roughness Ry of 58 nm and a surface roughness Ra of 5.1 nm.

2. Abrasive-free polishing step Next, as the polishing liquid 27 not containing abrasive grains, a solution containing alkali and oxidizing agent shown in Table 2 and having pH and ORP shown in Table 2 was used, and as polishing pad 28 The use of a polyurethane suede pad having a compression rate shown in Table 2, the use of a stainless steel platen as the platen 25, and a polishing pressure of 19.6 kPa (200 gf / cm ² ) Except for this, an abrasive-free polishing process was performed on the surface (Ga atom surface) of the n-type GaN crystal substrate (Group III nitride crystal 1) in the same manner as in Example A1. Here, TCIA in Table 2 represents trichloroisocyanuric acid, and DCIA-Na represents sodium dichloroisocyanurate.

  Through the above steps, the crystals of Examples B1 to B5 and Comparative Example BR1 shown in Table 2 were subjected to surface treatment, and the impurity concentration and surface roughness Ry and Ra on the crystal surface after the surface treatment were measured. Here, the concentration of C (carbon), which is an impurity, and the surface roughnesses Ry and Ra were determined in the same manner as in Example A1. The results are summarized in Table 2.

  Referring to Table 2, as shown in Examples B1 to B5, a lapping process using hard abrasive grains having a Mohs hardness greater than 7 (for example, diamond abrasive grains having a Mohs hardness of 10) and no abrasive grains are included. A non-abrasive polishing step performed using a polishing solution having a pH of 8.5 to 14 and a polishing pad having a compressibility of 1.5% to 20% under a polishing pressure of 0.98 kPa to 58.8 kPa. By the surface treatment including the crystal surface, a crystal surface having a low impurity concentration on the crystal surface and low surface roughness Ry and Ra was obtained. In Comparative Example BR1, the pH was 7 and was higher than 6, so the concentration of C (carbon) that was an impurity remaining on the crystal surface was high.

(Examples C1 to C13)
1. Lapping process Use of an n-type GaN crystal substrate including a high dislocation density region and a low dislocation density region grown by forming facets by the HVPE method as the group III nitride crystal 1, and a hard abrasive grain 16 having a grain size of 3 μm In the same manner as in Example A1, except that SiC abrasive grains (Mohs's hardness: 9.5) were used and a stainless steel plate with a polyurethane non-woven pad was used as the platen 15, n A wrapping process of the surface of a type GaN crystal substrate (group III nitride crystal 1) (referring to a Ga atom surface in a low dislocation density region and an N atom surface in a high dislocation density region; this surface is referred to as a (0001) plane). I did it. By such lapping, the surface of the n-type GaN crystal substrate became a mirror surface. The n-type GaN crystal substrate after lapping had a surface roughness Ry of 30 nm and a surface roughness Ra of 3.2 nm.

2. Abrasive-free polishing step Next, as the polishing liquid 27 containing no abrasive grains, a solution containing alkalis shown in Table 3 and having pH and ORP shown in Table 3 was used. Example 3 except that the polyurethane foam pad having the compression ratio shown in FIG. 3 was used, that the surface plate made of aluminum was used as the surface plate 25, and that the polishing pressure was the pressure shown in Table 3. In the same manner as A1, a non-abrasive polishing process was performed on the Ga atom surface of the n-type GaN crystal substrate (Group III nitride crystal 1) (this surface is the (0001) plane).

  The surface treatment of Examples C1 to C13 shown in Table 3 is performed by the above-described steps, and the impurity concentration on the crystal surface after the surface treatment and the dent depth of the high dislocation density region (ie, the surface of the low dislocation density region 1k in FIG. And the surface area of the high dislocation density region 1h, the flat surface area ratio (that is, the ratio (percentage) of the area of the flat surface region 1ps of the low dislocation density region 1k to the area of the entire surface 1ks in the low dislocation density region 1k. )) And surface roughness Ry and Ra were measured. Here, the concentration of Si (silicon) as an impurity was measured by a TXRF (total reflection fluorescent X-ray) method. This Si was measured by an optical interference type step meter that is considered to be derived from SiC abrasive grains. Further, the depth of the dent in the high dislocation density region and the flat surface area ratio were calculated from the surface shape data obtained by the optical interference type step meter. The surface roughness Ry and Ra were determined in the same manner as in Example A1. The results are summarized in Table 3.

  Referring to Table 3, as shown in Examples C1 to C13, a lapping step using hard abrasive grains having a Mohs hardness greater than 7 (for example, SiC abrasive grains having a Mohs hardness of 9.5), and abrasive grains Abrasive-free grains with a polishing pressure of 0.98 kPa to 58.8 kPa using a polishing solution having a pH of 1 to 6.5 and a polishing pad having a compression ratio of 1.5% to 20%. By the surface treatment including the polishing step, a crystal surface having a low impurity concentration on the crystal surface, a small recess depth in the high dislocation density region, a large flat surface area ratio, and a low surface roughness Ry and Ra was obtained. In Example C1, the surface roughness Ry and Ra increased because the compression rate of the polishing pad was small. In Example C7, since the compressibility of the polishing pad was large, the dent depth in the high dislocation density region was large. In Example C8, since the polishing pressure was low, the impurity concentration was high. In Example C13, since the polishing pressure was large, the dent depth in the high dislocation density region was large.

(Examples D1 to D7)
1. Lapping process The use of an n-type GaN crystal substrate including a high dislocation density region and a low dislocation density region grown by forming facets by the HVPE method as the group III nitride crystal 1, and a hard abrasive grain 16 having a grain size of 4 μm The use of Al ₂ O ₃ abrasive grains (Mohs hardness: 9), the use of a stainless steel surface plate with a polyurethane non-woven pad attached as the surface plate 15, and a lapping pressure of 29.4 kPa (300 gf / Except for cm ² , it refers to the surface of the n-type GaN crystal substrate (Group III nitride crystal 1) (the Ga atom surface in the low dislocation density region and the N atom surface in the high dislocation density region) as in Example A1. The lapping process of this surface is defined as (0001) plane). By such lapping, the surface of the n-type GaN crystal substrate became a mirror surface. After the lapping, the n-type GaN crystal substrate had a surface roughness Ry of 26 nm and a surface roughness Ra of 2.4 nm.

2. Abrasive-free polishing step Next, as the polishing liquid 27 not containing abrasive grains, a solution containing acids and oxidizing agents shown in Table 4 and having pH and ORP shown in Table 4 was used. The polyurethane foam pad having the compression ratio shown in Table 4 was used, the stainless steel platen was used as the platen 25, and the polishing pressure was 39.2 kPa (400 gf / cm ² ). Except for this, an abrasive-free polishing process was performed on the Ga atom surface (this surface is the (0001) plane) of the n-type GaN crystal substrate (Group III nitride crystal 1) in the same manner as in Example A1. . Here, TCIA in Table 4 represents trichloroisocyanuric acid.

The surface treatment of Examples D1 to D7 shown in Table 4 is performed by the above steps, and the impurity concentration on the crystal surface after the surface treatment and the dent depth of the high dislocation density region (that is, the surface of the low dislocation density region 1k in FIG. 4) And the surface area of the high dislocation density region 1h, the flat surface area ratio (that is, the ratio (percentage) of the area of the flat surface region 1ps of the low dislocation density region 1k to the area of the entire surface 1ks in the low dislocation density region 1k. )) And surface roughness Ry and Ra were measured. Here, the concentration of Al (aluminum) as an impurity was measured by the TXRF (total reflection fluorescent X-ray) method. This Al is considered to be derived from Al ₂ O ₃ abrasive grains. Further, the depth of the dent in the high dislocation density region was measured with an optical interference type step meter. Further, the flat surface area ratio was calculated from surface shape data obtained by an optical interference level difference meter. The surface roughness Ry and Ra were determined in the same manner as in Example A1. The results are summarized in Table 4.

Referring to Table 4, as shown in Examples D1 to D7, a lapping process using hard abrasive grains having a Mohs hardness greater than 7 (for example, Al ₂ O ₃ abrasive grains having a Mohs hardness of 9), and abrasive grains No polishing with a polishing solution having a pH of 1 to 6.5 and a polishing pad having a compression ratio of 1.5% to 20% and a polishing pressure of 0.98 kPa to 58.8 kPa By the surface treatment including the grain polishing step, a crystal surface having a low impurity concentration on the crystal surface, a low dent depth in the high dislocation density region, a high flat surface area ratio, and a low surface roughness Ry and Ra was obtained. In Example D1, the surface roughness Ry and Ra increased because the compression rate of the polishing pad was small. In Example D7, since the compressibility of the polishing pad was large, the dent depth in the high dislocation density region was large.

(Examples E1 to E12)
1. Lapping process Diamond abrasive grains having a particle diameter of 2 μm (Mohs hardness: 10) were used as the hard abrasive grains 16, and a stainless steel surface plate with a polyurethane non-woven pad attached thereto as the surface plate 15, and lapping. Except that the pressure was 29.4 kPa (300 gf / cm ² ), the surface of the n-type GaN crystal substrate (Group III nitride crystal 1) (Ga atom surface. This surface is (0001) as in Example A1. ) Surface). By such lapping, the surface of the n-type GaN crystal substrate became a mirror surface. The n-type GaN crystal substrate after lapping had a surface roughness Ry of 25 nm and a surface roughness Ra of 2.3 nm.

2. Soft Abrasive Polishing Step Next, with reference to FIGS. 1 and 3, the n-type GaN crystal substrate (group III nitride) after lapping while being fixed to the crystal holder 11 (corresponding to the crystal holder 31 in FIG. 3) Crystal 1) was polished with soft abrasive grains as follows. A polishing pad 38 is installed on a surface plate 35 having a diameter of 300 mm installed in a polishing apparatus (not shown), and a polishing liquid 37 containing soft abrasive grains 36 is supplied to the polishing pad 38 from a polishing liquid supply port 39. The polishing pad 38 is rotated about the rotation shaft 35c, and the n-type GaN crystal substrate (Group III nitride crystal 1) fixed to the crystal holder 31 is placed on the polishing pad 38 by placing a weight 34 on the crystal holder 31. The surface of the n-type GaN crystal substrate (Group III nitride crystal 1) is rotated by rotating the n-type GaN crystal substrate (Group III nitride crystal 1) about the rotation axis 31c of the crystal holder 31 while pressing the The Ga atom surface) was polished.

Here, Fe ₂ O ₃ abrasive grains (Mohs hardness: 6) having a particle diameter of 0.5 μm were used as the soft abrasive grains 36. Further, as the polishing liquid 37 containing the soft abrasive grains 36, a liquid containing HCl (hydrochloric acid) as an acid and H ₂ O ₂ as an oxidizing agent and having a pH of 2 and an ORP of 700 mV was used. As the polishing pad 38, a polyurethane foam pad having a compression rate shown in Table 5 was used. Further, an aluminum surface plate was used as the surface plate 35. Regarding the polishing conditions, at the polishing pressure shown in Table 5, the rotational speeds of the n-type GaN crystal substrate (Group III nitride crystal 1) and the polishing pad 38 are both 30 rpm (times / min) to 100 rpm (times / min). The time was 60 minutes.

3. Abrasive-free polishing step Next, as a polishing solution 27 containing no abrasive grains, a solution containing HCl (hydrochloric acid) as an acid and H ₂ O ₂ as an oxidizing agent, having a pH of 2 and an ORP of 700 mV, In addition, a polyurethane suede pad having a compression rate shown in Table 5 was used as the polishing pad 28, a stainless steel surface plate was used as the surface plate 25, and the polishing pressure was 39.2 kPa ( The surface (Ga atom surface) of the n-type GaN crystal substrate (Group III nitride crystal 1) was subjected to abrasive-free polishing in the same manner as in Example A1 except that the amount was 400 gf / cm ² ).

The surface treatment of Examples E1 to E12 shown in Table 5 is performed by the above-described process, and the impurity concentration on the crystal surface after the surface treatment and the dent depth of the high dislocation density region (that is, the surface of the low dislocation density region and the high dislocation density) Difference in height from the surface of the region), flat surface area ratio (that is, the ratio (percentage) of the area of the flat surface region 1ps of the low dislocation density region 1k to the area of the entire surface 1ks in the low dislocation density region 1k), surface roughness Ry and Ra and the thickness of the work-affected layer were measured. Here, the concentration of C (carbon) as an impurity was measured by an AES (Auger electron spectroscopy) method. This C is considered to be derived from diamond abrasive grains that are hard abrasive grains. Further, the concentration of Fe (iron) as an impurity was measured by a TXRF (total reflection fluorescent X-ray) method. This Fe is considered to be derived from Fe ₂ O ₃ abrasive grains which are soft abrasive grains. Moreover, surface roughness Ra and Ry were calculated | required similarly to Example A1. The results are summarized in Table 5.

4). Next, referring to FIG. 5, the n-type GaN crystal substrate (group III nitride crystal 1) after the abrasive-free polishing in Examples E1 to E12 described above is MOCVDed. An n-type semiconductor layer 620 having a thickness of 1 μm is disposed on one main surface (Ga atom surface) of the n-type GaN crystal substrate (Group III nitride crystal 1) by MOCVD, and placed in the apparatus. Type GaN layer 621 (dopant: Si) and 150 nm thick n-type Al _0.1 Ga _0.9 N layer 622 (dopant: Si), light-emitting layer 640, and p-type Al _0.2 Ga _0.8 having a thickness of 20 nm as p-type semiconductor layer 630 An N layer 631 (dopant: Mg) and a 150-nm-thick p-type GaN layer 632 (dopant: Mg) were sequentially formed to obtain a group III nitride laminate 500. Here, the light emitting layer 640 is formed by alternately laminating four barrier layers formed of GaN layers having a thickness of 10 nm and three well layers formed of Ga _0.85 In _0.15 N layers having a thickness of 3 nm. A multi-quantum well structure was adopted.

  The intensity (PL intensity) of light emitted from the group III nitride laminate 500 thus obtained was measured by the PL (photofuminescence) method. The results are summarized in Table 5.

5. Manufacturing Process of Group III Nitride Semiconductor Device Furthermore, referring to FIG. 6, the other of the n-type GaN crystal (Group III nitride crystal 1) of group III nitride laminate 500 of Example E1 to Example E12 described above As a first electrode 661, a laminated structure formed of a 200 nm thick Ti layer, a 1000 nm thick Al layer, a 200 nm thick Ti layer, and a 2000 nm thick Au layer is formed on the main surface (N atom surface) And heated in a nitrogen atmosphere to form an n-side electrode having a diameter of 100 μm. On the other hand, on the p-type GaN layer 632 of the group III nitride stacked body 500, a stacked structure formed of a 4 nm thick Ni layer and a 4 nm thick Au layer is formed as the second electrode 662, and an inert gas is formed. A p-side electrode was formed by heating in an atmosphere. The laminated body was chipped to a size of 400 μm × 400 μm to obtain an LED (light emitting diode) as a group III nitride semiconductor device 600.

  Thereafter, the p-side electrode (second electrode 662) is bonded to the conductor 682 with the solder layer 670, the n-side electrode (first electrode 661) and the conductor 681 are bonded with the wire 690, and the LED A semiconductor device 700 including the above was obtained.

  200 group III nitride semiconductor devices 600 and semiconductor devices 700 as described above were manufactured for each example, and their physical properties were confirmed. Table 5 shows the yield (unit:%) of products having predetermined characteristics as products.

Referring to Table 5, as shown in Examples E1 to E12, a lapping process using hard abrasive grains having a Mohs hardness greater than 7 (for example, diamond abrasive grains having a Mohs hardness of 10), and a Mohs hardness of 7 or less A polishing pressure of 4.9 kPa to 98 kPa using a polishing liquid containing a soft abrasive grain (for example, Fe ₂ O ₃ abrasive grains having a Mohs hardness of 6) and a polishing pad having a compressibility of 0.8% to 5%. The polishing pressure is determined using a soft abrasive polishing process performed under the following conditions, a polishing liquid not containing abrasive grains and having a pH of 1 or more and 6.5 or less and a polishing pad having a compression ratio of 1.5% or more and 20% or less. By surface treatment including an abrasive-free polishing step performed under conditions of 0.98 kPa to 58.8 kPa, the impurity concentration on the crystal surface is low, and the depth of dent in the high dislocation density region Small, large flat surface area ratio, surface roughness Ry and surface roughness Ra smaller crystal surface was obtained.

  Here, in Example E1, the surface roughness Ry and Ra increased because the compression rate of the polishing pad used in the soft abrasive polishing process was small. In Example E6, since the polishing pressure in the soft abrasive polishing step was small, the concentration of impurities (C) derived from the hard abrasive was increased. In Example E12, the polishing pressure in the soft abrasive grain polishing step was large, so the concentration of impurities (Fe) derived from the soft abrasive grains was high.

  In Examples E2-E5 and E7-E12, the impurity concentration on the crystal surface is low, the surface roughness Ra and Ry, and the thickness of the work-affected layer are small, so that the group III nitride laminate has a high PL strength. Thus, a group III nitride semiconductor device was obtained with good yield. On the other hand, in Example E1, since the impurity concentration was high and the thickness of the work-affected layer was large, the PL strength of the group III nitride laminate was lowered, and the yield of the group III nitride semiconductor device was also reduced. In Example E6, since the impurity concentration on the crystal surface was high and the thickness of the work-affected layer was large, the PL strength of the group III nitride laminate was decreased, and the yield of the group III nitride semiconductor device was also decreased.

(Examples F1 to F12)
1. Lapping process The use of an n-type GaN crystal substrate including a high dislocation density region and a low dislocation density region grown by forming facets by the HVPE method as the group III nitride crystal 1, and a hard abrasive grain 16 having a grain size of 4 μm An n-type GaN crystal substrate (Group III nitriding) was performed in the same manner as in Example A1, except that SiC abrasive grains (Mohs's hardness: 9.5) were used and a platen made of phenol resin was used as the platen 15. The surface of the product crystal 1) (the Ga atom surface in the low dislocation density region and the N atom surface in the high dislocation density region) was lapped. By such lapping, the surface of the n-type GaN crystal substrate became a mirror surface. After the lapping, the n-type GaN crystal substrate had a surface roughness Ry of 32 nm and a surface roughness Ra of 3.4 nm.

2. Soft Abrasive Polishing Step Next, with reference to FIGS. 1 and 3, the n-type GaN crystal substrate (group III nitride) after lapping while being fixed to the crystal holder 11 (corresponding to the crystal holder 31 in FIG. 3) Crystal 1) was polished with soft abrasive grains as follows. A polishing pad 38 is installed on a surface plate 35 having a diameter of 300 mm installed in a polishing apparatus (not shown), and a polishing liquid 37 containing soft abrasive grains 36 is supplied to the polishing pad 38 from a polishing liquid supply port 39. The polishing pad 38 is rotated about the rotation shaft 35c, and the n-type GaN crystal substrate (Group III nitride crystal 1) fixed to the crystal holder 31 is placed on the polishing pad 38 by placing a weight 34 on the crystal holder 31. The surface of the n-type GaN crystal substrate (Group III nitride crystal 1) is rotated by rotating the n-type GaN crystal substrate (Group III nitride crystal 1) about the rotation axis 31c of the crystal holder 31 while pressing the The Ga atom surface in the low dislocation density region and the N atom surface in the high dislocation density region were polished.

Here, as the soft abrasive grains 36, SiO ₂ abrasive grains (Mohs hardness: 7) having a particle diameter of 0.1 μm were used. Further, as the polishing liquid 37 containing the soft abrasive grains 36, a liquid containing malic acid as an acid and H ₂ O ₂ as an oxidizing agent and having a pH of 2 and an ORP of 700 mV was used. As the polishing pad 38, a polyurethane foam pad having a compression rate shown in Table 6 was used. Further, an aluminum surface plate was used as the surface plate 35. Regarding the polishing conditions, at the polishing pressure shown in Table 6, the rotational speeds of the n-type GaN crystal substrate (Group III nitride crystal 1) and the polishing pad 38 are both 30 rpm (times / min) to 100 rpm (times / min). The time was 60 minutes.

3. Abrasive-free polishing step Next, as a polishing liquid 27 containing no abrasive grains, a liquid containing malic acid as an acid and TCIA (trichloroisocyanuric acid) as an oxidizing agent, having a pH of 2 and an ORP of 700 mV, Further, a polyurethane suede pad having a compression rate shown in Table 6 was used as the polishing pad 28, a stainless steel plate was used as the surface plate 25, and the polishing pressure was 19.6 kPa ( 200 gf / cm ² ) The surface of the n-type GaN crystal substrate (Group III nitride crystal 1) (the surface of the Ga atom in the low dislocation density region and the N in the high dislocation density region) in the same manner as in Example A1. Atom surface) was polished without abrasive grains.

  The surface treatment of Examples F1 to F12 shown in Table 6 is performed by the above process, and the impurity concentration on the crystal surface after the surface treatment and the dent depth of the high dislocation density region (that is, the surface of the low dislocation density region and the high dislocation density). Difference in height from the surface of the region), flat surface area ratio (that is, the ratio (percentage) of the area of the flat surface region 1ps of the low dislocation density region 1k to the area of the entire surface 1ks in the low dislocation density region 1k), surface roughness Ry and Ra and the thickness of the work-affected layer were measured. Here, the concentration of Si (silicon) as an impurity, the depth of the dent in the high dislocation density region, the flat surface area ratio, the surface roughness Ry and Ra were determined in the same manner as in Example C1. This Si is considered to be derived from SiC abrasive grains that are hard abrasive grains. Further, the thickness of the work-affected layer was measured by TEM (transmission electron microscope) observation of a cross section in which the crystal was broken at the cleavage plane. The results are summarized in Table 6. Here, TCIA in Table 6 represents trichloroisocyanuric acid.

4). Next, referring to FIG. 5, the n-type GaN crystal substrate (group III nitride crystal 1) after the abrasive-free polishing in Examples F1 to F12 described above is MOCVDed. The MOCVD method is carried out on one main surface (the Ga atom surface in the low dislocation density region and the N atom surface in the high dislocation density region) on one main surface of the n-type GaN crystal substrate (Group III nitride crystal 1). Thus, an n-type GaN layer 621 (dopant: Si) having a thickness of 1 μm as an n-type semiconductor layer 620, an n-type Al _0.1 Ga _0.9 N layer 622 (dopant: Si) having a thickness of 150 nm, a light emitting layer 640, and a p-type semiconductor p-type Al _0.2 Ga _0.8 N layer 631 having a thickness of 20nm as a layer 630 (dopant: Mg) and a thickness of 150 nm p-type GaN layer 632 of (dopant: Mg) are sequentially formed a, III-nitride To obtain a laminate 500. Here, the light emitting layer 640 is formed by alternately laminating four barrier layers formed of GaN layers having a thickness of 10 nm and three well layers formed of Ga _0.85 In _0.15 N layers having a thickness of 3 nm. A multi-quantum well structure was adopted.

  The intensity (PL intensity) of light emitted from the group III nitride laminate 500 thus obtained was measured by the PL (photofuminescence) method. The results are summarized in Table 6.

5. Process for Producing Group III Nitride Semiconductor Device Furthermore, referring to FIG. 6, the other of the n-type GaN crystal (Group III nitride crystal 1) of group III nitride laminate 500 of Example F1 to Example F12 described above As a first electrode 661 on the main surface (N atom surface in a low dislocation density region and Ga atom surface in a high dislocation density region), a Ti layer with a thickness of 200 nm, an Al layer with a thickness of 1000 nm, and a Ti layer with a thickness of 200 nm A layered structure formed of an Au layer having a thickness of 2000 nm was formed, and heated in a nitrogen atmosphere to form an n-side electrode having a diameter of 100 μm. On the other hand, on the p-type GaN layer 632 of the group III nitride stacked body 500, a stacked structure formed of a 4 nm thick Ni layer and a 4 nm thick Au layer is formed as the second electrode 662, and an inert gas is formed. A p-side electrode was formed by heating in an atmosphere. The laminated body was chipped to a size of 400 μm × 400 μm to obtain an LED (light emitting diode) as a group III nitride semiconductor device 600.

  Thereafter, the p-side electrode (second electrode 662) is bonded to the conductor 682 with the solder layer 670, the n-side electrode (first electrode 661) and the conductor 681 are bonded with the wire 690, and the LED A semiconductor device 700 including the above was obtained.

  200 group III nitride semiconductor devices 600 and semiconductor devices 700 as described above were manufactured for each example, and their physical properties were confirmed. Table 6 shows the yield (unit:%) of those having predetermined characteristics as products.

Referring to Table 6, as shown in Examples F1 to F12, a lapping process using hard abrasive grains having a Mohs hardness of greater than 7 (for example, SiC abrasive grains having a Mohs hardness of 9.5), and a Mohs hardness of A polishing pressure of 4.9 kPa to 98 kPa using a polishing liquid containing 7 or less soft abrasive grains (for example, SiO ₂ abrasive grains having a Mohs hardness of 7) and a polishing pad having a compressibility of 0.8% to 5%. The polishing pressure is determined using a soft abrasive polishing process performed under the following conditions, a polishing liquid not containing abrasive grains and having a pH of 1 or more and 6.5 or less and a polishing pad having a compression ratio of 1.5% or more and 20% or less. By surface treatment including an abrasive-free polishing step performed under conditions of 0.98 kPa to 58.8 kPa, the impurity concentration on the crystal surface is low and the dent depth in the high dislocation density region is small. A large flat surface area ratio, surface roughness Ry and surface roughness Ra less crystal surface was obtained.

  Here, in Example F1, since the compressibility of the polishing pad used in the soft abrasive polishing process was small, the surface roughness Ry and Ra increased. In Example F5, since the compression rate of the polishing pad used in the soft abrasive polishing process was large, the depth of the recess in the high dislocation density region was large. In Example F6, since the polishing pressure in the soft abrasive polishing process was small, the concentration of impurities (Si) derived from the hard abrasive increased. In Example F12, since the polishing pressure in the soft abrasive grain polishing step was large, the dent depth in the high dislocation density region was increased.

  In Examples F2 to F4 and F7 to F11, the impurity concentration on the crystal surface is low, the recess depth of the high dislocation density region is 3 μm or less, and the flat surface area ratio is 40% or more. The PL strength of the laminate was increased, and a group III nitride semiconductor device was obtained with good yield. On the other hand, in Example F1, since the surface roughnesses Ry and Ra and the thickness of the work-affected layer were large, the PL strength of the group III nitride laminate was lowered, and the yield of the group III nitride semiconductor device was also reduced. In Example F6, since the impurity concentration on the crystal surface was high, the PL intensity of the group III nitride laminate was decreased, and the yield of the group III nitride semiconductor device was also decreased. In Examples F5 and F12, the depth of recess in the high dislocation density region is larger than 3 μm and the flat surface area ratio is less than 40%. Therefore, the PL strength of the group III nitride laminate is reduced, and the group III The yield of nitride semiconductor devices also decreased.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Group III nitride crystal, 1h High dislocation density region, 1k Low dislocation density region, 1ks Total surface in low dislocation density region, 1ps flat surface region, 11, 21, 31 Crystal holder, 11c, 15c, 21c, 25c, 31c , 35c Rotating shaft, 14, 24, 34 Weight, 15, 25, 35 Surface plate, 16 Hard abrasive grain, 19 Abrasive grain supply port, 27, 37 Polishing liquid, 28, 38 Polishing pad, 29, 39 Polishing liquid supply port , 36 soft abrasive grains, 500 group III nitride laminate, 600 group III nitride semiconductor device, 620 n-type semiconductor layer, 621 n-type GaN layer, 622 n-type Al _0.1 Ga _0.9 N layer, 630 p-type semiconductor layer, 631 p-type Al _0.2 Ga _0.8 N layer, 632 p-type GaN layer, 640 light-emitting layer, 650 III-nitride layer, 661 a first electrode, 662 a second electrode, 70 solder layer, 681 and 682 conductors, 690 wire, 700 a semiconductor device.

Claims (11)

Lapping the surface of the group III nitride crystal with a hard abrasive having a Mohs hardness higher than 7,
A polishing-free polishing step of polishing the lapped surface of the group III nitride crystal using a polishing liquid that does not contain abrasive grains, and
The platen used in the lapping step is Sn, Sn—Bi alloy, Sn—Sb alloy, Sn—Pb alloy, Cu metal material, Al ₂ O ₃ , SiO ₂ , and CeO ₂ inorganic material, and A surface plate including at least one of an organic material such as a phenol resin, a urethane resin, an amide resin, and an imide resin, and a surface plate of any surface plate with a pad fixed thereon,
A surface treatment method for a group III nitride crystal, wherein the polishing liquid not containing abrasive grains has a pH of 1 to 6 or 8.5 to 14.   3. The group III nitride according to claim 1, wherein in the abrasive-free polishing step, polishing is performed at a polishing pressure of 0.98 kPa to 58.8 kPa using a polishing pad having a compression rate of 1.5% to 20%. Crystal surface treatment method.   A group III nitride crystal obtained by the surface treatment according to claim 1 or 2.   The group III nitride crystal according to claim 3, wherein the surface roughness Ra is 2 nm or less.   The group III nitride crystal according to claim 3 or 4, wherein the thickness of the work-affected layer is 50 nm or less.   The III-nitride crystal includes a high dislocation density region and a low dislocation density region, and a difference in height between the surface of the low dislocation density region and the surface of the high dislocation density region is 3 μm or less. The group III nitride crystal according to any one of 5 to 5.   The group III nitride crystal includes a high dislocation density region and a low dislocation density region, and the flat surface region of the low dislocation density region has an area of 40% or more with respect to the entire surface in the low dislocation density region. The group III nitride crystal according to any one of claims 3 to 5.   A group III nitride stack comprising the group III nitride crystal according to any one of claims 3 to 7, and at least one group III nitride layer epitaxially grown on a surface of the group III nitride crystal body. A method for producing a group III nitride laminate using the group III nitride crystal according to any one of claims 3 to 7,
Preparing the group III nitride crystal;
And a step of epitaxially growing at least one group III nitride layer on the surface of the group III nitride crystal.   A group III nitride crystal according to any one of claims 3 to 7, at least one group III nitride layer epitaxially grown on a surface of the group III nitride crystal, and the group III nitride layer. A group III nitride semiconductor device comprising: an outermost layer and an electrode formed on at least one surface of the group III nitride crystal. A method for producing a group III nitride semiconductor device using the group III nitride crystal according to any one of claims 3 to 7,
Preparing the group III nitride crystal;
Epitaxially growing at least one group III nitride layer on the surface of the group III nitride crystal;
And a step of forming an electrode on at least one surface of the group III nitride layer and at least one surface of the group III nitride crystal.

Images