JP2013128517A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which prevents misbehavior by making it difficult to read the generation timing of a jackpot random number generated by hardware.SOLUTION: The game machine includes: a hardware random number generation circuit 46 comprising a hardware counter 460; a control means 40 which controls a game along a game control program and includes RAM 404 that can contain data as a work field; and a clear switch 451 for clearing the RAM 404. If the clear switch 451 is operated after the completion of security check performed by the control means 40 when power is supplied, the game machine executes initialization that clears the RAM 404 and starts from an initial state. If the clear switch 451 is not operated after the completion, the game is made to be restarted from the state before power disconnection. When the clear switch 451 is turned from on to off, the counter 460 of the hardware random number generation circuit is restarted from a predetermined restart value to make the timing of the restart indefinite.

Description

  The present invention relates to a gaming machine provided with a hard random number generation circuit that generates a random number value that is a determination target of a winning / failing lottery when a hardware counter starts counting up when power is turned on.

  In general, in gaming machines such as pachinko machines and pachislot machines, random numbers are generated by software program processing and hardware count processing, and determination of whether or not the lottery is determined according to the random number value obtained at the start winning or lever operation. It is. For example, in a pachinko machine, a random number is acquired at the time of starting winning, and if this value is a predetermined jackpot random number value (for example, 7), a jackpot game is generated. The random number counter is configured to generate a big hit random number value with a predetermined probability, but is configured to generate a big hit random number value aperiodically so as not to be shot (such as initial value random number update processing) Has been. However, when the power is turned on, there are many gaming machines that generate a random number with an initial value that is unique to the random number counter. With this, the timing at which the jackpot random value is generated can be known only for the first time. Abuse of this may result in a fraudulent act of attaching a fraudulent board to a gaming machine and aiming at a big hit value by turning off and on the power.

  In order to prevent such an illegal act, Patent Document 1 discloses that a game is kept waiting until the value of a random number counter that is counted up by software program processing at power-on matches the identification number unique to the pachinko machine. The timing from when the jackpot is generated until the jackpot value is generated is changed for each pachinko machine.

JP 2005-40520 A

However, when extracting the random number for determination of success / failure by the soft random number generated by the software program processing as in Patent Document 1, the above means may be used, but when extracting the big hit random number by the hard random number Since the hard random numbers continue to be updated after the power is turned on, if the start time of the update and the position of the random number that becomes the big hit are known, there is a problem that fraud aimed at the big hit becomes possible.
In view of the above circumstances, an object of the present invention is to provide a gaming machine that can effectively prevent illegal acts using hard random numbers.

The invention described in claim 1 has a hardware counter that starts counting up from a predetermined count start value when the power is turned on, and obtains the count value from the counter to obtain a random number value to be determined in the lottery determination. A hard random number generation circuit to generate;
A control means for controlling the operation of the controlled object in accordance with the game control program, having a RAM capable of storing data as a work area of the game control program;
A clear switch operated when clearing the RAM;
A clear switch operation state judging means for judging whether or not the clear switch is operated after the security check at the time of power-on and before the normal game processing,
In a gaming machine that clears the RAM if the clear switch is operated and executes an initial setting process that starts from an initial state, and restores the game to the state before power-off if it is not operated,
The clear switch operation state determination means includes an on detection means for detecting that the clear switch is turned on, and an off detection means for detecting that the clear switch is turned off from the on state,
The hard random number generation circuit is configured to restart the counter of the hard random number generation circuit from a predetermined restart value based on detection of the off state of the off detection means.

  In order to clear the RAM in the gaming machine, the RAM clear switch is turned on while the gaming machine is turned off, the power is turned on in this state, and then the RAM clear switch is turned off. At this time, the timing at which the RAM clear switch is turned off differs depending on the operator. The present invention utilizes this timing difference to restart the counter of the hard random number generation circuit that started counting up when the power is turned on when the RAM clear switch is turned off. Thus, the timing of generating the big hit random number can be made difficult to read, and fraud can be prevented and security can be enhanced. Further, since the generation timing of the jackpot random number cannot be read, it is not meaningful to attach an illegal board or the like, so that illegal actions can be prevented.

The invention according to claim 2 is the gaming machine according to claim 1,
The RAM of the control means includes a maximum count value storage means capable of storing an arbitrary maximum count value,
The counter of the hard random number generation circuit executes the count-up after the restart with the value stored in the maximum count value storage means at the time of the initial setting process as the maximum value, and when the count value reaches the maximum value The count is continued after returning to the count start value.

According to this, the count range of the counter of the hard random number generation circuit can be narrowed. In general, the ratio of the big hit random number setting range to the count range is determined, and since the big hit random number range set in it becomes narrower as the count range becomes narrower, the big hit random number range is hard to be specified and security is improved. Can be strengthened.
Note that the count range of the counter of the hard random number generation circuit indicates, for example, a set composed of a total of 65536 consecutive counter values from “0000h to FFFFh”. The range (setting range) indicates, for example, a set composed of a total of six consecutive counter values from “0304h to 0309h”. The range of the jackpot random number needs to be controlled conveniently, and is set by a set of consecutive counter values as shown in the above example.

  In addition, by setting the maximum count value of the counter of the hard random number generation circuit, it is possible to easily develop a plurality of types of gaming machines having different specifications by using one type of hard random number generation circuit. More specifically, when developing gaming machines, products with the same basic structure but different specifications (such as high or low probability of hitting) are generally developed. In such a case, the range of the jackpot random number (a set of counter values (random number values) that are the jackpot) is, for example, the relatively first half of the counter of the hard random number generation circuit (in other words, the jackpot random number setting area). Set to correspond to. In this case, the second half of the counter is lost as the counter number increase / decrease area. The hard random number generation circuit functions while maintaining the total number of jackpot random numbers by changing the maximum count value within the range of the latter half and increasing / decreasing the counter value of the latter half where the range of jackpot random numbers is not set The total number of count values can be changed. In other words, the jackpot probability, which is the value obtained by dividing the total number of jackpot random numbers by the total number of count values that the hard random number generation circuit functions, can be easily changed, and there is no need to provide different types of hard random number generation circuits for each specification. .

In addition, for the performance of generating big hits, it is desirable to set the range of the big hit random numbers (a set of several consecutive big hit random numbers) as much as possible over the entire area of the functioning counter. Has been. However, for example, it is set over the entire counter of the hard random number generation circuit (for example, a total number of 65536 from “0000h to FFFFh”), and a hit determination table for determining big hits (a table in which a range of big hit random numbers is set as in the prior art) ) Is used, an enormous amount of data is used, resulting in inconvenience of constraining the ROM data area of the internal ROM. In addition, when trying to fit in the data amount of the current general success / failure determination table, the range of the big hit random number becomes remarkably large, and the area that does not hit and the area that does not hit in the entire functioning counter are not dispersed, Therefore, there is a problem that the hitting performance is likely to be aimed at or an abnormal wave of hitting may occur due to the performance of generating a big hit.
In this regard, even if hard random numbers are used by matching the maximum count value of the counter of the hard random number generation circuit with the maximum count value of soft random numbers conventionally used and applying the range of jackpot random numbers, It is possible to suppress the data area allocated to the determination table with the same amount of data used as when using soft random numbers, and it is possible to realize a good state in terms of performance for generating big hits.

In addition, even if the area that can be allocated to the success / failure determination table increases or decreases for each model to be developed, the determination table suitable for each model can be obtained by adjusting the maximum count value of the counter of the hard random number generator as appropriate. Can be configured.
Furthermore, even if the ROM data area of the built-in ROM is expanded in the future and the area that can be allocated to the success / failure determination table increases significantly, the maximum value of the counter range of the hard random number generation circuit (for example, the FFFFh) If it is within the following range, it is possible to sufficiently exhibit the effect produced by the expansion of the ROM data area by appropriately adjusting the maximum count value. In other words, the range of the big hit random number can be distributed within the range of the larger total count value while maintaining the big hit probability.
The above-described plural types of effects are not limited to the big hit random numbers related to the winning / failing lottery, but are also produced when other random numbers necessary for the game are generated by hard random numbers.
The arbitrary maximum count value of the counter of the hard random number generation circuit is determined by the manufacturer of the hard random number generation circuit made of a semiconductor chip, a gaming machine manufacturer (semiconductor chip user) using the semiconductor chip for a gaming machine, or a gaming machine. Although it can be set at any of the game stores, a configuration set by a gaming machine manufacturer is desirable.

The invention according to claim 3 is the gaming machine according to claim 1 or 2,
The control means includes a restart value setting means capable of setting an arbitrary restart value,
The restart value setting means is based on the count value generated by the hard random number generation circuit when the OFF detection means detects the OFF state and identification information unique to the control means, or among the count value and the identification information. Based on at least one of the above, the restart value is selected from a plurality of preset setting values, and the counter of the hard random number generation circuit is selected from the selected restart value. The configuration is to restart.

According to this, in addition to the configuration in which the counter of the hard random number generation circuit is restarted at an indefinite timing, the restart value can be selected from a plurality of numerical values, thereby making it difficult to predict the generation timing of the big hit random number. It becomes possible. It is desirable to use a CPU unique ID or the like as identification information unique to the control means.
The counter for generating the count value is not limited to the counter of the hard random number generation circuit, but may be a counter of other hardware or a soft counter by program processing of the control means.

It is a front view of a gaming machine to which the present invention is applied. It is a front view of the game board of the gaming machine. It is a rear view of the gaming machine. It is a front view which shows the power supply board of the said game machine. It is an electric block diagram of the gaming machine. It is a block diagram which shows the detailed electrical structure of the said gaming machine. It is an electrical block diagram of the hard random number generation circuit of the gaming machine. It is a flowchart which shows the control content of the process performed at the time of power activation in the main control apparatus of the said gaming machine. It is a flowchart which shows the control content of the random number generation circuit restart process in the said main controller. It is a flowchart which shows the control content of the restart value selection process in the said main controller. It is a figure which shows a restart value. It is a flowchart which shows the control content of the main routine performed with the said main controller. It is a timing chart which shows operation | movement of the said gaming machine. It is a flowchart which shows the control content of the delay process 2 process performed with the said main controller.

A pachinko machine as a gaming machine according to an embodiment to which the present invention is applied will be described. As shown in FIG. 1, the pachinko machine 1 has a structure in which each part of the configuration is held by an outer frame 10 that forms a vertically long fixed outer frame. The outer frame 10 is provided with a front frame (glass frame) 11 in which a plate glass 110 is fitted and an inner frame (not shown) that can be opened and closed via a hinge 101 provided at the upper and lower positions on the left side.
A game board 2 (FIG. 2) held by the inner frame is provided behind the plate glass 110 of the front frame 11.

  Speakers 112 are installed at both the left and right side positions at the upper part of the front frame 11 and the left and right side positions at the lower part of the outer frame 10, respectively, and game sounds are output thereby improving the player's preference. In addition to the frame-side decorative lamp 113 that emits light according to the gaming state, the front frame 11 is provided with LEDs that notify the gaming abnormality.

  An upper plate 12 and a lower plate 13 are integrally formed in the lower half of the front frame 11. A launching handle 14 is provided on the right side of the lower plate 13, and the launching device is operated by operating the firing handle 14 clockwise, so that the game ball supplied from the upper plate 12 faces the game board 2. Fired.

  The lower tray 13 is configured to receive award balls overflowing from the upper tray 12, and the game balls accumulated in the lower tray 13 can be moved to another box (dollar box) provided in the game store by operating the ball removal lever. An effect button 15 is provided on the left side of the lower plate 13.

The pachinko machine 1 is a so-called CR machine and includes a prepaid card unit (CR unit) 16 for reading and writing a prepaid card. The pachinko machine 1 has a lending button 171 and a checkout button 172 on the left side of the lower plate 13. And a balance indicator 173 is provided.
Reference numeral 18 in FIG. 1 denotes a cylinder lock that locks the front frame 11 and the inner frame to the outer frame 10. A predetermined key is inserted into the cylinder lock 18, and the key is operated clockwise to move the inner frame. The front frame 11 is opened by a counterclockwise operation.

As shown in FIG. 2, a substantially circular gaming area 20 surrounded by an outer rail 201 and an inner rail 202 is formed on the game board 2. A center case 210 is attached to the center of the game area 20.
The center case 210 is provided with an LCD panel of the effect symbol display device 21 (not shown in its entirety) in the center. On the outer periphery of the LCD panel, a first special figure display device 22A, a second special figure display device 22B, a special figure display device 23 for displaying a special figure, and a special figure A first special figure hold number display device 24A for displaying the hold memory, a second special figure hold number display device 24B, and a general figure hold number display device 25 for displaying the usual hold memory are provided. Further, the center case 210 is provided with a warp inlet, a warp rod, a stage and the like, as is well known.

On both the left and right sides of the center case 210, a normal design operating gate (operating port) 26 is provided.
Directly below the center case 210 is a first start opening 27A that allows a regular drawing (winning) to execute special drawing lottery, and a special start second start opening 27B made of a tulip-type ordinary electric accessory at a position directly below the first start opening 27B. is set up.
The second starting port 27B can enter a ball (winning) only when an ordinary electric accessory (hereinafter simply referred to as a general electric accessory) is opened. The general electric character is released for a predetermined time when a normal symbol (hereinafter simply referred to as “normal”) is drawn by a lottery of a normal symbol executed due to the game ball passing through the operation gate 26.

The normal winning opening 28 is arranged at the left and right side positions of the second start opening 27B. In addition, a large winning opening 29 that is opened and closed by an opening / closing plate is disposed below the second starting opening 27B, and an out opening 203 is provided at the bottom of the board surface.
Note that a large number of game nails and windmills are planted in the game area 20 of the game board 2.

As shown in FIG. 3, the back side of the pachinko machine 1 houses an inner frame 30 to which the game board 2 is detachably attached. As with the front frame 11, the inner frame 30 is installed so that the vertical position of one side edge (the right side in FIG. 3) is hinged to the outer frame 10 and can be opened and closed. The inner frame 30 is formed with a game ball flow-down passage, and a ball tank 31, a tank rail 32, and a payout unit 33 are provided from above (upstream), and a payout device is provided in the payout unit 33. . With this configuration, when a game ball wins the winning opening of the game board 2, a predetermined number of game balls (prize balls) are passed from the ball tank 31 via the tank rail 32 by the payout unit 33 through the payout ball flow path and the upper plate. 12 is paid out. In the present embodiment, the payout unit 33 for paying out the prize balls also pays out the balls to be paid out by operating the lending button.
Further, on the back side of the pachinko machine 1, a main control device 40, a payout control device 41, a sub integrated control device 42, an effect symbol control device 43, a launch control device 44, and a power supply board 45 are provided. The sub integrated control device 42 and the production symbol control device 43 correspond to sub control devices.

  The main control device 40, the sub integrated control device 42, and the effect symbol control device 43 are provided on the game board 2, and the payout control device 41, the launch control device 44, and the power supply board 45 are provided on the inner frame 30. Although the launch control device 44 is not depicted in FIG. 3, it is provided under the payout control device 41.

  Further, an external connection terminal plate 38 is provided on the right side of the ball tank 31, and a signal indicating a game state and a game result is sent to a hall computer (not shown) by the external connection terminal plate 38. Conventionally, the external connection terminal board for transmitting signals to the hall computer has a board (terminal for outputting signals output from the game board side to the hall computer) and a frame (frame side (outer frame)). 10, a terminal for outputting a signal output from the front frame 11 and the inner frame 30) to the hall computer), but in this embodiment, a game is played through one external connection terminal plate 38. A signal indicating the state and game result is transmitted to the hall computer.

  FIG. 4 is a view showing the front surface of the power supply board 45, and a power switch 450 for turning on / off the power of the pachinko machine 1 is provided on the front face of the power supply board 45 at an upper and lower intermediate position near its right edge. A RAM clear switch 451 for clearing contents stored in a RAM of a CPU (to be described later) of the main control device 40 and the payout control device 41 is provided at the lower portion near the right edge. Thus, both switches 450 and 451 are arranged close to each other and can be operated with one hand. The power supply substrate 45 is covered with a cover member made of a transparent resin, but both switches 450 and 451 can be operated from an operation hole formed in the cover member without removing the cover member.

  FIG. 5 shows an electrical configuration of the pachinko machine 1, and is mainly configured of a main controller 40 that controls the game. The main control device 40, the payout control device 41, the sub integrated control device 42, and the effect design control device 43 all have a CPU, ROM, RAM, input port, output port, etc. CPU, ROM, RAM, etc. are not provided. However, the present invention is not limited to this, and the launch control device 44 may be provided with a CPU, ROM, RAM, and the like. The main controller 40 corresponds to the control means described in the claims. Moreover, the structure controlled according to the game control program of the main controller 40 among the structures described below corresponds to the controlled object described in the claims.

  Main controller 40 is electrically connected to hall computer 500 of the game facility via back wiring relay terminal board 530 and external connection terminal board 38. Further, the main control device 40 has a glass frame opening SW (detecting whether or not the front frame (glass frame) 11 and the inner frame 30 are open) via the back wiring relay terminal plate 530 and the game board relay terminal plate 531. Switch) 501, inner frame opening SW502, first start port SW503 for detecting a ball entering the first special figure start port 27A, a second start port SW504 for detecting a ball entering the second special figure start port 27B, Fig. 6 shows a normal operation SW 505 for detecting a ball entering the start gate 26, a count SW 506 for detecting a ball entering the big winning port 29, left and right winning ports SW 507, 508 for detecting a ball entering the normal winning port 28, etc. A detection signal is input.

  The main control device 40 operates in accordance with the installed program, generates various commands related to the progress of the game based on the above-described detection signals, and the like, via the payout control device 41 and the production relay terminal board 532. A command is output to the sub-integrated control device 42 and the production symbol control device 43, and the first and second special symbol display devices 22A and 22B, the first and second special symbol reservation numbers are displayed via the symbol display device relay terminal board 533. Display control is performed on the devices 24A, 24B, the normal symbol display device 23, and the universal figure holding number display device 25.

The main control device 40 controls the big prize opening solenoid 509 that opens and closes the big prize opening 29 to open the big prize opening 29. In addition, the operation of the universal electric component solenoid 510 that opens and closes the electric combination of the second special figure start opening 27B is controlled to open and close the second special figure start opening 27B.
The output signal from the main control device 40 is also output from the test signal terminal, and a management signal such as symbol variation and jackpot is sent to the hall computer 500 through the external connection terminal plate 38. The main control device 40 and the payout control device 41 are capable of bidirectional communication.
The main controller 40 is given a unique ID as unique identification information. As the unique ID, a 4-byte chip number that is different for each CPU that is attached when the CPU of the main controller 40 is manufactured, or a 4-byte ROM code generated from a data value of “0000h to 1FBFh” in the CPU's built-in ROM. Have. These individual chip number and ROM code can be read from a user program for game control.

  The payout control device 41 is a ball break SW 520 that detects that the ball tank 31 is empty via the back wiring relay terminal plate 530 and the payout relay terminal plate 534, and a payout that detects that a game ball has been paid out. Detection signals such as SW 522 and full SW 523 for detecting that the game ball storage tray is full are input. In accordance with a command sent from the main controller 40, the payout motor 521 is operated to pay out the game ball. The CR unit 16 is electrically connected to the CR unit 16 via the CR unit terminal plate 535, accepts lending requests and settlement request operation signals from the ball lending and settlement SWs 171 and 172 via the settlement display device 173, Data is sent and received, and the payout motor 521 is operated in accordance with the loan request signal to pay out the rental balls, and the balance display of the prepaid card inserted in the CR unit 16 is controlled.

  The firing control device 44 receives detection signals such as a firing stop SW 524 and a touch SW 525 for detecting that the player is touching (operating) the firing handle 14. A firing motor based on a command sent from the main control device 40 via the payout control device 41 (reflecting a signal of the touch SW 525 and a game situation), a rotation signal of the firing handle 14 and a signal of the firing stop SW 524 The game ball is fired and stopped by controlling 526, and the lighting of the touch lamp is controlled.

  The sub integrated control device 42 receives detection signals such as the volume adjustment SW and the effect button 15. In accordance with a command sent from the main controller 40, the speaker 112 is driven to output sound, and various LEDs and various lamps 113 are turned on and off. Furthermore, a command for a pseudo effect for displaying a character or the like or a display pattern for a special symbol for the special symbol is transmitted to the effect symbol control device 43.

  The effect symbol control device 43 constitutes the effect symbol display device 21 together with the LCD panel unit and the accessory unit. The effect symbol control device 43 controls the display of the LCD panel of the effect symbol display device 21 in accordance with a command sent from the sub integrated control device 42.

  FIG. 6 shows a power supply path and a signal transmission path between the power supply board 45 and each part of the gaming machine including the main controller 40 and the payout controller 41. On the power supply board 45 of the pachinko machine, an AC 24V power source provided on the game shop side is fed to the power generation circuit 452 via the power switch 450, and includes the main controller 40 and the payout controller 41 from the power generation circuit 452. Power is supplied to each part of the gaming machine. The power switch 450 is of a type that maintains its state when turned on or off.

  The full-wave 24V output in the power generation circuit 452 is input to the power supply voltage monitoring circuit 453, and the reset signal generation circuit 455 outputs or cancels the reset signal based on the detection result of the presence / absence of the full-wave 24V output by the power supply voltage monitoring circuit 453. . That is, the power supply voltage monitoring circuit 453 determines that the full-wave 24V output is stopped if the non-output state in which a voltage higher than the predetermined reference voltage is not output continues for a predetermined time, and the reset signal generation circuit 455 determines that the full-wave 24V output is stopped. A reset signal is output according to the determination. On the other hand, when full wave 24V output is started, the reset signal is canceled. Here, the output of the reset signal is to output a low level signal, and the release is to change from the low level to the high level. The reset signal is released after a delay time (Ta in FIG. 13) from the time point when the full-wave 24V output is detected.

  The reset signal output of the reset signal generation circuit 455 is transmitted to the reset terminals of the CPUs 401 and 411 of the main control device 40 and the payout control device 41, respectively.

  A power failure signal generation circuit 454 that generates a power failure signal corresponding to the output of the power supply voltage monitoring circuit 453 is provided, and when a power failure such as a power failure occurs, the power failure signal is transmitted to the NMI terminals of the CPUs 401 and 411 of each control device. ing. The power failure signal is a signal that changes from a high level to a low level when the power is cut off, and the output timing is set so that it is output before the reset signal is output.

  The power supply board 45 is configured to generate a DC5V backup power supply (VBB) by a backup power supply generation circuit 457 including a capacitor. The backup power supply (VBB) output is output from the CPUs 401 and 411 of the control devices. The data is output to the backup terminal (VBB), and the contents stored in the RAMs of the CPUs 401 and 411 of the respective control devices are held in the event of a power failure, as will be described later.

The RAM clear switch 451 on the power supply board 45 clears the contents stored in the RAMs 404 and 414 of the CPUs 401 and 4111 of the control devices.
The RAM clear switch 451 is a push button type that is turned on only when pressed and turned off when released. If the RAM clear switch 451 is on, the RAM clear signal generation circuit 456 is a high-level signal RAM. The clear signal is output to the input ports 402 and 412 of the main control board 40 and the payout control board 41 until a predetermined time elapses or until the RAM clear switch 451 is turned off. Here, the delay time Ta from turning on the power switch 450 to releasing the reset signal is set to, for example, 100 ms. To generate the RAM clear signal, the power switch 450 is turned on while pressing the RAM clear switch 451. Note that the CPUs 401 and 411 of each control device monitor the presence or absence of a RAM clear signal at the input ports 402 and 412.

Like the CPU, the CPU 401 of the main control device 40 incorporates a random number generation circuit 46 that counts up a hardware counter made of a semiconductor to generate a hard random number.
An outline of the random number generation circuit 46 is shown in FIG. The hard random number generation circuit 46 includes a random number generation counter 460 therein, which is activated substantially simultaneously with the energization of the pachinko machine 1 (more specifically, the CPU 401), and is a system from a clock circuit provided in the main controller 40. The numerical value of the hard random number is updated at a timing obtained by appropriately dividing the clock signal (SCLK). The hard random number is composed of 2 bytes of data and is composed of 65536 values from “0000h to FFFFh”. The counter 460 of the hard random number generation circuit 46 starts counting from “0000h” at the start-up after power-on (count start value).

Further, the hard random number generation circuit 46 can shift to a predetermined “restart value” in the middle of counting in response to a command from the CPU 401 and can restart (restart) counting from now on. Can be selected from a plurality of types of numerical values preset by a CPU user (game machine manufacturer).
Further, the count range can be reduced by setting the “maximum count value”. To reduce the count range, set the “maximum count value” from “0000h to FFFFh”, and when the count reaches the “maximum count value”, this count is used to return to the count start value (0000h). Continue.
The “restart value” and “maximum count value” may be set in advance using a numerical value setting function in the program.

  The hard random number generation circuit 46 includes random value registers 461 to 463, and the hard random number generated by the random number generation counter 460 is stored in one of these random number value registers 461 to 463. The register to be stored is designated by setting a value corresponding to the random value fetch register 464 in advance. Specifically, when it is desired to store the random number value in the random value register 1, “1” is set in the random value acquisition register 464, and when it is desired to store in the random value register 2, “2” is set in the random value acquisition register 464. If it is desired to store in the random value register 3, “3” is set in the random value fetch register 464.

Next, processing executed by the CPU 401 of the main control device 40 when the power is turned on will be described with reference to FIG. First, when the power switch 450 is operated, the pachinko machine is energized, the reset signal is released, and the security check of the CPU 401 itself is completed, this processing is executed, and the power-on initial processing is executed (s100).
When the reset signal is released, the counter 460 of the hard random number generation circuit 46 starts counting from the count start value “0000h”.

Next, in step S101, it is confirmed whether or not the RAM clear signal is on. The RAM clear signal is turned on if the RAM clear switch 451 is in the on state when the reset signal is released, and it is substantially confirmed whether or not the RAM clear switch 451 is in the on state when the power is turned on. The process of S101 corresponds to the clear switch operation state determination means described in the claims.
If the RAM clear signal is not on (S101: no), "delay processing 1" is executed in S102. This process delays the progress of the process for the time until the value of the counter 460 of the hard random number generation circuit 46 reaches a numerical value based on the unique ID (identification information) unique to the main controller 40. The configuration may be such that the numerical value is delayed until reaching all or a part of the unique ID, and the numerical value may be delayed until reaching a numerical value obtained by performing a predetermined calculation based on the unique ID.
Further, the counter is not limited to the counter 460 of the hard random number generation circuit 46, but may be a hardware counter in the main controller 40 or a soft counter by program processing of the CPU 401.

  If the RAM clear signal is not on when the power is turned on (S101: no), the pachinko machine is restored to the power-off state (normal power-on). For this purpose, first, it is confirmed whether or not the occurrence information at the time of power-off at the time of power-off is normal (S103). If it is normal (S103: yes), the RAM judgment value is calculated (S104). It is confirmed whether or not the determination value is normal (S105). The determination value of the RAM is a value stored in the RAM when the power is shut off. In the process of S105, it is confirmed whether or not the value calculated in the process of S104 matches the value stored in the RAM.

  If the determination value of the RAM is normal, that is, if the determination value matches the stored value (S105: yes), processing at the time of power recovery is performed (S106). In this process, for example, information generated when the power is turned off is cleared, and a command is transmitted to return the sub integrated control device 43 to the gaming state when the power is turned off. In the subsequent process of S107, the hard random number generation circuit 46 is restarted.

  As shown in FIG. 9, in the “random number generation circuit restart process”, first, it is confirmed whether or not the maximum count value that is the upper limit value of the hard random number count is set (S200). The maximum count value can be set in advance as a user by, for example, a gaming machine manufacturer, and the set maximum count value is stored in the RAM 404 of the main controller 40. The RAM 404 corresponds to the maximum count value storage means described in the claims.

  If the maximum count value is set (S200: yes), it is subsequently checked whether or not the restart value for starting counting at the time of restart is set (S201). If a restart value is set (S201: yes), the process proceeds to “restart value selection processing” to select a restart value.

As shown in FIG. 10, in the “restart value selection process”, first, a hard random value at the present time is acquired (S300), and the unique ID unique to the main controller 40 is read (S301). Next, the hard random number value and the unique ID are added to calculate a lower two-digit numerical value when the addition result is converted into a binary number (S302). Then, a restart value is selected from a reference table according to the last two digits (S303). For example, as shown in FIG. 11, if the last two digits are “00b”, the restart value is “0007h”, and if the last two digits is “10b”, the restart value is “0021h”. select. A table set by the user (game machine manufacturer) is used as the reference table. The “restart value selection process” corresponds to restart value setting means described in the claims.
Note that the selection process related to the selection of the restart value is not limited to the above-described method, and may be a method using another calculation or the like.

  Returning to FIG. 9, in the process of S203, when the count value is reached by returning to the selected restart value and starting counting up from now on, and setting the upper limit value of the count as the set maximum count value, The count is continued to return to the count start value (0000h). That is, the selected restart value is set, and the set maximum count value is set as the upper limit value of the count, thereby starting the count up from the restart value, and the count value becomes the maximum count value. When it reaches, it returns to the count start value and continues counting up.

  If the restart value is not set in the process of S201 (S201: no), that is, if any numerical value is not set by the user, “0001h” is set as the restart value in the subsequent process of S204. ”And return to“ 0001h ”and start counting up. When the count reaches the maximum count value set as the upper limit value of the count, it returns to the count start value (0000h) and continues counting up. .

  If the maximum count value is not set in the process of S200 (S200: no), that is, if any numerical value is not set by the user, the restart value is set in the process of S205 as in the process of S201. Check if it exists. If the restart value is not set (S205: no), “0001h” is set as the restart value in the subsequent processing of S206, and the count value is started again after returning to “0001h”. In this case, the upper limit value of the count is “FFFFh”, and when it reaches “FFFFh”, it returns to the count start value (0000h) and continues counting up.

If the restart value is set in the process of S205 (S205: yes), the process of the subsequent S207 shifts to the “restart value selection process” in the same manner as the process of S202, selects the restart value, and in S208. In the process, the process returns to the selected restart value and starts counting up. The upper limit value of the count is “FFFFh”. When this value is reached, the count is returned to the count start value (0000h) and the count is continued.
Thereafter, returning to FIG. 8, interrupt setting is performed (S108), and the process proceeds to the main routine.
In the “random number generation circuit restart process” in S107, unlike S114, which will be described later, the process is executed based on the restart value and the maximum count value set at the previous power-on and stored in the RAM. You may comprise as follows.

  As shown in FIG. 12, the “main routine” is composed of the main processing (S400 to S409, S420) and the remaining processing (S410). First, the main routine is started due to an interrupt signal having a period of 2 ms or 4 ms, and is first normal. It is determined whether or not it is an interrupt (S400). This determination is made based on whether or not a specific numerical value is written at a specific address in the RAM. If the determination is negative (S400: no), the initial setting (S420) is executed. The numerical value for determining whether or not it is a normal interrupt is written in the RAM as part of this initial setting.

  If the interrupt is normal (S400: yes), the initial random number update process (S401), the big hit symbol determination random number update process (S402), the regular hit determination random number update process (S403), the reach determination regarding the reach of the special figure Random number update processing (S404), fluctuation pattern determination random number update processing related to the special pattern variation pattern (S405), winning confirmation processing (S406), success / failure determination processing (S407), each output processing (S408), fraud monitoring The process (S409) is performed, and the initial random number update process (S410) is looped within the remaining time until the next interrupt signal is input.

Next, a state where the RAM clear signal is turned on when the power is turned on will be described. As shown in FIG. 13, the RAM clear signal is turned on when the operator turns on the RAM clear switch 451 and the power is turned on and the reset signal is released after a lapse of Ta time.
When the reset signal is released, the CPU 401 starts the security check (T1) in the main controller 40, and the hard random number generation circuit 46 starts counting from the count start value (0000h). In the security check of the CPU 401, it is checked whether or not the contents of the ROM are regular contents. If the contents are regular, the CPU 401 starts control of the game according to the ROM program.
The RAM clear signal is turned off when the operator finishes the operation of the RAM clear switch 451.

Returning to FIG. 8, if the RAM clear signal is ON in the processing of S101 (S101: yes), "delay processing 2" is executed (S106). As shown in FIG. 14, in this process, it is confirmed whether or not the RAM clear signal is turned off (S500), this process is repeated until it is turned off, and the progress of other processes is delayed during this time. Thereby, the timing of subsequent processing becomes indefinite. Therefore, when the RAM clear signal is turned off (S500: yes), the process returns and the process proceeds to S111 in FIG.
The delay process 2 in S110 has a different configuration from the delay process 1 in S102 described above, but may have the same configuration as the delay process 1. The delay processes 1 and 2 may use other delay time generation methods.

In the process of S111, all the stored contents of the RAM are cleared to 0, and then an initial value random number setting process of soft random numbers generated by the program process is executed (S112). In this process, it is desirable to calculate the initial value of the soft random number by performing a predetermined arithmetic process on a plurality of hard random values acquired from the random number registers 1 and 2 (461, 462) of the hard random number generation circuit 46.
When the initial value random number setting process is completed in this way, the RAM is initialized (S113), and thereafter, the process proceeds to the “random number generation circuit restart process” (FIG. 9) in the same manner as the power recovery process when the RAM is not cleared. Then, the hard random number generation circuit 46 is restarted (S114). Subsequently, interrupt setting is performed (S115), and the process proceeds to the main routine (FIG. 12). The processing of S111 to S115 corresponds to the initial setting processing described in the claims.

  In the process at the time of power-on, when the information generated at the time of power-off in the process of S103 is abnormal (S103: no), or the RAM judgment value in the process of S105 is abnormal (S105: no). Since the recovery to the power-off state is impossible, the processes of S111 to S115 are executed in the same manner as when the RAM is cleared.

  When turning on the power accompanied by the RAM clear, the RAM clear switch is turned on in the power off state, the power is turned on in this state, and then the RAM clear switch 451 is turned off. According to the pachinko machine 1 of the present embodiment, the counter of the hard random number generation circuit 46 that has started counting up when the power is turned on is restarted when the RAM clear signal is turned off when the RAM clear switch 451 is turned off. At this time, the timing at which the operator turns off the RAM clear switch 451 varies, and the time from power-on to restart of the hard random number generation circuit 46 (T2, see FIG. 13) is different and delayed (in each case). Delay processing 2). Therefore, since the restart timing is irregular, it is possible to make it difficult to read the timing of generating the big hit random number.

  Further, in the pachinko machine 1, a restart value for restarting the hard random number generation circuit 46 can be set, and the unique information of the gaming machine and the current situation of the gaming machine from a plurality of preset numerical values. Since the restart timing is unknown as described above, and the restart start position (numerical value) is also unknown, it is possible to reliably aim at the timing of generating a big hit random number. It becomes difficult. In this way, the pachinko machine 1 has strong security and can reliably prevent fraud.

  Further, the pachinko machine 1 can set the maximum count value of the counter of the hard random number generation circuit 46, and by setting this, the count range is narrower than “0000h to FFFFh” that the counter can count (counting) Range). In general, the random number generation configuration in a pachinko machine has a ratio of the big hit random number range for all random number ranges (count ranges), and the total random number range becomes narrower by setting the maximum count value, The jackpot random number range can also be narrowed. Therefore, it is difficult to guess and aim at big hit random numbers, strengthen the security of pachinko machines and prevent fraud.

  Furthermore, by setting the maximum count value of the counter of the hard random number generation circuit 46, it is possible to easily develop a plurality of types of gaming machines having different specifications by using one type of hard random number generation circuit. In general, when developing a pachinko machine, a plurality of products with different specifications such as a big hit probability are developed with the same model. In this case, the range of the big hit random number is set, for example, in the relatively first half of the counter of the hard random number generation circuit. The hard count generation circuit maintains the total number of jackpot random numbers by changing the maximum count value within the range of the second half and increasing or decreasing the counter value of the second half where the range of the jackpot random number is not set. It is possible to change the total number of count values (which can be extracted at the time of starting port winning). In other words, the jackpot probability can be easily changed by changing the total number of count values that the hard random number generation circuit functions without changing the total number of jackpot random numbers, and therefore different types of hard random number generation circuits are provided for each specification. There is no need.

Further, in the pachinko machine, it is desirable to set the range of the big hit random number as uniformly as possible over the entire range of the functioning counter. However, if the total number of counters of the hard random number generation circuit (for example, a total number of 65536 from “0000h to FFFFh”) is set and a big hit determination table for jackpot determination is set as in the past, a huge amount of data This results in the inconvenience of squeezing the ROM data area of the built-in ROM. In addition, when trying to fit in the data amount of the current general success / failure determination table, the range of the big hit random number becomes remarkably large, and the area that does not hit and the area that does not hit in the entire functioning counter are not dispersed, Therefore, there is a problem that the hitting performance is likely to be aimed at or an abnormal wave of hitting may occur due to the performance of generating a big hit.
In this regard, even if hard random numbers are used by matching the maximum count value of the counter of the hard random number generation circuit with the maximum count value of soft random numbers conventionally used and applying the range of jackpot random numbers, It is possible to suppress the data area allocated to the determination table to the same amount of data used as when using soft random numbers, and it is possible to realize a good state in terms of performance for generating big hits.

Even if the area that can be allocated to the success / failure determination table for each model increases or decreases, a determination table that is suitable for each model can be configured by adjusting the maximum count value of the counter of the hard random number generation circuit as appropriate. can do.
Furthermore, even if the ROM data area of the built-in ROM is expanded in the future and the area that can be allocated to the success / failure determination table increases significantly, the maximum value of the counter range of the hard random number generation circuit (for example, the FFFFh) If it is within the following range, it is possible to sufficiently exhibit the effect produced by the expansion of the ROM data area by appropriately adjusting the maximum count value. In other words, the range of the big hit random number can be distributed within the range of the larger total count value while maintaining the big hit probability.

  When normal power recovery without clearing RAM of this pachinko machine, the hard random number generation circuit 46 is restarted until the counter that started counting up when the power was turned on reaches a value based on the unique ID unique to the main controller 40 Is delayed (delay processing 1), making it difficult to read the timing of generating the big hit random number. In addition, the restart value and the maximum count value are set in the same way as when the power is turned on with the RAM clear, and these actions and effects combine to make it difficult to guess and shoot a big hit random number even when normal power is restored. To prevent fraud.

It should be noted that the present invention described in the claims is not limited to the configuration of the embodiment described above, and can of course be implemented in various ways without departing from the gist of the present invention. For example, in the restart process of the hard random number generation circuit 46 when the power is turned on accompanied by the RAM clear, “delay process 2” waiting for the RAM clear signal to be turned off, and “delay waiting until the counter reaches a numerical value based on the unique ID” The processing 1 ”may be combined to make the restart timing indefinite. Further, “delay processing 2” may be combined with delay processing by a timer that simply waits for a predetermined time. Also in the restart process of the hard random number generation circuit 46 at the time of normal power recovery, the restart may be delayed not only by “delay process 1” but by another delay process.
Further, the “restart value” may be selected from a predetermined numerical value instead of being selected from a plurality of set values.
The “maximum count value” is not limited to a predetermined numerical value, and may be set by a program process according to the state of the gaming machine, the unique ID, or the like.
Further, the present invention is not limited to pachinko machines, but may be applied to other gaming machines such as pachislot machines, enclosed pachinko machines, and pachislot machines as long as they use hard random numbers.

1 Pachinko machine (game machine)
40 Main controller (control means, clear switch operation state judgment means, on detection means, off detection means, restart value setting means)
404 RAM (maximum count value storage means)
451 Clear switch 46 Hard random number generation circuit 460 Counter

Claims (3)

A hardware random number generation circuit that has a hardware counter that starts counting up from a predetermined count start value when the power is turned on, acquires a count value from the counter, and generates a random number value that is a determination target of the success / failure lottery;
A control means for controlling the operation of the controlled object in accordance with the game control program, having a RAM capable of storing data as a work area of the game control program;
A clear switch operated when clearing the RAM;
A clear switch operation state judging means for judging whether or not the clear switch is operated after the security check at the time of power-on and before the normal game processing,
In a gaming machine that clears the RAM if the clear switch is operated and executes an initial setting process that starts from an initial state, and restores the game to the state before power-off if it is not operated,
The clear switch operation state determination means includes an on detection means for detecting that the clear switch is turned on, and an off detection means for detecting that the clear switch is turned off from the on state,
The hard random number generation circuit restarts a counter of the hard random number generation circuit from a predetermined restart value based on detection of an off state of the off detection means. In the gaming machine according to claim 1,
The RAM of the control means includes a maximum count value storage means capable of storing an arbitrary maximum count value,
The counter of the hard random number generation circuit executes the count-up after the restart with the value stored in the maximum count value storage means at the time of the initial setting process as the maximum value, and when the count value reaches the maximum value A gaming machine, wherein the counting is continued by returning to the count start value. In the gaming machine according to claim 1 or 2,
The control means includes a restart value setting means capable of setting an arbitrary restart value,
The restart value setting means is based on the count value generated by the hard random number generation circuit when the OFF detection means detects the OFF state and identification information unique to the control means, or among the count value and the identification information. Based on at least one of the above, the restart value is selected from a plurality of preset setting values, and the counter of the hard random number generation circuit is selected from the selected restart value. A gaming machine characterized by restarting.

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