JP2013128062A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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JP2013128062A
JP2013128062A JP2011277346A JP2011277346A JP2013128062A JP 2013128062 A JP2013128062 A JP 2013128062A JP 2011277346 A JP2011277346 A JP 2011277346A JP 2011277346 A JP2011277346 A JP 2011277346A JP 2013128062 A JP2013128062 A JP 2013128062A
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film
titanium nitride
nitride film
titanium
via hole
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Katsuhiko Tanaka
克彦 田中
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Micron Memory Japan Ltd
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Elpida Memory Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which enables a tungsten film to be successfully buried in a via hole via a barrier layer and which can reduce in-plane variation of contact resistance between copper wiring and a plug in a semiconductor substrate to obtain favorable contact resistance.SOLUTION: A semiconductor device manufacturing method comprises: forming a via hole 18 in an interlayer insulation layer 17 covering copper wiring 15 on a semiconductor substrate 11; subsequently, forming a titanium film 21 on a bottom face 18a of the via hole 18 and on a top face 17a of the interlayer insulation layer 17 in a sputter chamber having strong directivity; subsequently, forming a first titanium nitride film on the titanium film 21 in the sputter chamber having strong directivity; subsequently, forming a second titanium nitride film 24 on the first titanium nitride film 22 in the sputter chamber having strong directivity; and subsequently, forming a tungsten film 27 to be buried in the via hole 18.

Description

本発明は、半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

従来、半導体基板（例えば、シリコン基板）やアルミニウム配線（アルミニウム膜）とコンタクトプラグとの接触抵抗を低減する目的で、コンタクトプラグのうち、半導体基板及びアルミニウム配線と接触する部分にチタン膜（Ｔｉ膜）が用いられている。   Conventionally, in order to reduce contact resistance between a semiconductor substrate (for example, a silicon substrate) or an aluminum wiring (aluminum film) and a contact plug, a titanium film (Ti film) is formed on a portion of the contact plug in contact with the semiconductor substrate and the aluminum wiring. ) Is used.

また、コンタクトプラグを構成するタングステン膜の成膜反応を安定させ、かつ下地層間絶縁層との密着性を確保するために、コンタクトプラグに構成要素の１つとして窒化チタン膜（ＴｉＮ膜）が用いられている。   In addition, a titanium nitride film (TiN film) is used as one of the constituent elements in the contact plug in order to stabilize the film formation reaction of the tungsten film constituting the contact plug and to secure the adhesion with the underlying interlayer insulating layer. It has been.

また、タングステン膜を形成する際に用いるＷＦ６ガスは、チタン（Ｔｉ）やシリコン（Ｓｉ）或いはアルミニウム（Ａｌ）と反応して膜はがれを生じさせるため、これらの材料を窒化チタン膜（ＴｉＮ膜）で覆い保護する必要がある。 Further, since the WF 6 gas used for forming the tungsten film reacts with titanium (Ti), silicon (Si), or aluminum (Al) to cause film peeling, these materials are used as titanium nitride films (TiN films). ) Must be covered and protected.

特許文献１には、コンタクト孔内にバリアメタルを介してタングステン膜を埋め込む際に、バリアメタル膜の膜剥がれを抑制する半導体装置の製造方法として、コンタクト孔を含む基板上面にチタン膜をスパッタ形成し、次いで、チタン膜上に窒素雰囲気中で高温のＡｒガスで加熱しながら第１のチタンナイトライド膜をスパッタ形成し、次いで、第１のチタンナイトライド膜を被覆するように１００％の窒素雰囲気中で第２のチタンナイトライド膜をスパッタ形成し、その後、チタン膜、第１のチタンナイトライド膜、及び第２のチタンナイトライド膜の積層膜からなるバリアメタル膜を介して、コンタクト孔をタングステン膜で埋め込むことが開示されている。   In Patent Document 1, as a method for manufacturing a semiconductor device that suppresses film peeling of a barrier metal film when a tungsten film is embedded in a contact hole through a barrier metal, a titanium film is formed by sputtering on the upper surface of the substrate including the contact hole. Then, a first titanium nitride film is sputter-formed on the titanium film while heating with a high-temperature Ar gas in a nitrogen atmosphere, and then 100% nitrogen so as to cover the first titanium nitride film. A second titanium nitride film is formed by sputtering in an atmosphere, and then contact holes are formed through a barrier metal film composed of a laminated film of a titanium film, a first titanium nitride film, and a second titanium nitride film. Is buried with a tungsten film.

特許文献２には、ＴｉＮ膜上に良質なタングステン膜を成膜可能な製造方法として、シリコン基板上にシリコン酸化膜上を形成し、次いで、コンタクトホールの形状にパターニングして下地基板を作成し、次いで、露出したシリコン基板上、及びシリコン酸化膜上にスパッタ法により、膜厚３０ｎｍのＴｉ膜を形成し、次いで、温度４００℃、気圧１Ｔｏｒｒ、電力３００Ｗの条件で、６０秒間の窒素プラズマ処理を行い、Ｔｉ膜表面を窒化し、次いで、スパッタ法により膜厚５０ｎｍのＴｉＮ膜を成膜し、その後、ＣＶＤ法により、ＴｉＮ膜上に膜厚３５０ｎｍのタングステン膜を成膜することが開示されている。   In Patent Document 2, as a manufacturing method capable of forming a high-quality tungsten film on a TiN film, a silicon oxide film is formed on a silicon substrate, and then patterned into a contact hole shape to form a base substrate. Next, a 30 nm-thick Ti film is formed on the exposed silicon substrate and silicon oxide film by sputtering, and then a nitrogen plasma treatment for 60 seconds under the conditions of a temperature of 400 ° C., an atmospheric pressure of 1 Torr, and a power of 300 W. And nitriding the surface of the Ti film, then forming a 50 nm thick TiN film by sputtering, and then forming a 350 nm thick tungsten film on the TiN film by CVD. ing.

また、特許文献２には、スパッタ法により、膜厚８００ｎｍのＡｌ膜を形成し、該Ａｌ膜上に、スパッタ法により、膜厚３０ｎｍのＴｉ膜（チタン膜）を形成し、次いで、温度４００℃、気圧１Ｔｏｒｒ、電力３００Ｗの条件で、６０秒間の窒素プラズマ処理を行い、Ｔｉ膜表面を窒化し、次いで、スパッタ法により、膜厚１００ｎｍのＴｉＮ膜（窒化チタン膜）を形成し、次いで、ＴｉＮ膜上に、プラズマＣＶＤ法により、シリコン酸化膜を形成し、コンタクトホールの形状にパターニングし、次いで、露出したＴｉＮ膜上、及びシリコン酸化膜上にスパッタ法により膜厚５０ｎｍのＴｉＮを形成し、その後、ＣＶＤ法により、ＴｉＮ膜上に膜厚８００ｎｍのタングステン膜を成膜することが開示されている。   In Patent Document 2, an Al film having a thickness of 800 nm is formed by a sputtering method, and a Ti film (titanium film) having a thickness of 30 nm is formed on the Al film by a sputtering method. Nitrogen plasma treatment is performed for 60 seconds under the conditions of ° C., atmospheric pressure 1 Torr, and power 300 W, the Ti film surface is nitrided, and then a 100 nm thick TiN film (titanium nitride film) is formed by sputtering, A silicon oxide film is formed on the TiN film by a plasma CVD method and patterned into the shape of a contact hole, and then a 50 nm-thick TiN film is formed on the exposed TiN film and the silicon oxide film by a sputtering method. Thereafter, it is disclosed that a tungsten film having a thickness of 800 nm is formed on the TiN film by a CVD method.

特開２００１−１６８０５７号公報JP 2001-168057 A 特開平１１−８７２７２号公報JP-A-11-87272

しかしながら、特許文献１，２に記載の加熱処理を行わないと、シリコン上またはアルミニウム配線上に形成されたチタン膜を覆うチタンナイトライド膜の膜厚が不十分な箇所がある場合には、タングステン膜の膜はがれやＷＦ６と反応してボルケーノが生じる恐れがあった。 However, if the heat treatment described in Patent Documents 1 and 2 is not performed, if there is a portion where the thickness of the titanium nitride film covering the titanium film formed on silicon or aluminum wiring is insufficient, tungsten there is a possibility that Volcano occurs react with membrane peeling and WF 6 of the membrane.

また、本発明者が鋭意検討を行ったところ、銅配線（Ｃｕ膜）上に、チタン膜（Ｔｉ膜）を接触させた状態で加熱処理（つまり、特許文献１，２の半導体装置の製造方法を適用すると）を行うと、Ｃｕ膜とＴｉ膜との接触が不安定となるため、Ｔｉ膜を構成要素の１つとするプラグ（コンタクトプラグやビアプラグ等）と銅配線との間の接触抵抗が上昇し、半導体基板面内において該接触抵抗がばらついてしまうことが分かった。   In addition, when the present inventors diligently studied, heat treatment was performed in a state where a titanium film (Ti film) was in contact with a copper wiring (Cu film) (that is, a method for manufacturing a semiconductor device in Patent Documents 1 and 2). Is applied, the contact between the Cu film and the Ti film becomes unstable, so that the contact resistance between the plug (contact plug, via plug, etc.) having the Ti film as one of the constituent elements and the copper wiring is reduced. It has been found that the contact resistance varies within the surface of the semiconductor substrate.

また、窒化チタン膜（ＴｉＮ膜）を銅配線（Ｃｕ膜）上に形成後、加熱処理を行うと、窒化チタン膜（ＴｉＮ膜）のＣｕに対するバリア性が低下して、銅原子が拡散し易くなった。
これにより、プラグの底部のエレクトロマイグレーション（ＥＭ）耐性が低下すると共に、窒化チタン膜（ＴｉＮ膜）表面におけるタングステン膜（プラグの母材）の核形成反応が不安定となり、タングステン膜の異常成長の要因となることが分かった。 Further, when a heat treatment is performed after the titanium nitride film (TiN film) is formed on the copper wiring (Cu film), the barrier property against Cu of the titanium nitride film (TiN film) is lowered, and copper atoms are easily diffused. became.
As a result, the electromigration (EM) resistance at the bottom of the plug is lowered, and the nucleation reaction of the tungsten film (plug base material) on the surface of the titanium nitride film (TiN film) becomes unstable, resulting in abnormal growth of the tungsten film. It turned out to be a factor.

本発明の一観点によれば、配線を覆う層間絶縁層にビアホールを形成し、該ビアホールにバリア層を介してプラグを形成する半導体装置の製造方法であって、前記バリア層を、第１の窒化チタン膜と、該第１の窒化チタン膜上に第２の窒化チタン膜と、順次積層させることで形成し、前記第２の窒化チタン膜は、前記第１の窒化チタン膜を形成する時よりも弱い指向性で形成することを特徴とする半導体装置の製造方法が提供される。   According to one aspect of the present invention, there is provided a semiconductor device manufacturing method in which a via hole is formed in an interlayer insulating layer covering a wiring, and a plug is formed in the via hole through a barrier layer. A titanium nitride film and a second titanium nitride film are sequentially stacked on the first titanium nitride film, and the second titanium nitride film is formed when the first titanium nitride film is formed. A method for manufacturing a semiconductor device is provided, which is formed with a weaker directivity.

本発明の半導体装置の製造方法によれば、配線を覆う層間絶縁層にビアホールを形成し、ビアホール内に、第１の窒化チタン膜を形成し、次いで、該第１の窒化チタン膜上に第１の窒化チタン膜を形成する時よりも弱い指向性をもって第２の窒化チタン膜を形成することで、第１及び第２の窒化チタン膜の形成に加熱処理を行うことなく、第１及び第２の窒化チタン膜を介して、ビアホールを埋め込むように、タングステン膜を埋め込んだ際、エレクトロマイグレーション（ＥＭ）耐性を確保した上で、タングステン膜の成膜に起因するボルケーノの発生を抑制可能となる。   According to the method for manufacturing a semiconductor device of the present invention, a via hole is formed in an interlayer insulating layer covering a wiring, a first titanium nitride film is formed in the via hole, and then a first titanium nitride film is formed on the first titanium nitride film. By forming the second titanium nitride film with a weaker directivity than when forming the first titanium nitride film, the first and second titanium nitride films can be formed without performing heat treatment on the first and second titanium nitride films. When a tungsten film is embedded so as to embed a via hole through the titanium nitride film 2, it is possible to suppress the occurrence of volcano caused by the formation of the tungsten film while ensuring the electromigration (EM) resistance. .

これにより、ビアホール内をタングステン膜で良好に埋め込むことができると共に、配線とプラグとの間の接触抵抗の半導体基板面内のばらつきを小さくでき、かつ良好な接触抵抗を得ることができる。   Thereby, the inside of the via hole can be satisfactorily filled with the tungsten film, variation in the contact resistance between the wiring and the plug can be reduced in the semiconductor substrate surface, and a good contact resistance can be obtained.

なお、ここでの「指向性が弱い」とは、スパッタ装置のターゲットと半導体基板との距離が近いことをいう。   Note that “weak directivity” here means that the distance between the target of the sputtering apparatus and the semiconductor substrate is short.

本発明の実施の形態に係る半導体装置の製造工程を説明するための断面図（その１）である。It is sectional drawing (the 1) for demonstrating the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を説明するための断面図（その２）である。It is sectional drawing (the 2) for demonstrating the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を説明するための断面図（その３）である。It is sectional drawing (the 3) for demonstrating the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を説明するための断面図（その４）である。It is sectional drawing (the 4) for demonstrating the manufacturing process of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造工程を説明するための断面図（その５）である。It is sectional drawing (the 5) for demonstrating the manufacturing process of the semiconductor device which concerns on embodiment of this invention.

以下、図面を参照して本発明を適用した実施の形態について詳細に説明する。なお、以下の説明で用いる図面は、本発明の実施形態の構成を説明するためのものであり、図示される各部の大きさや厚さや寸法等は、実際の半導体装置の寸法関係とは異なる場合がある。   Embodiments to which the present invention is applied will be described below in detail with reference to the drawings. Note that the drawings used in the following description are for explaining the configuration of the embodiment of the present invention, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the dimensional relationship of an actual semiconductor device. There is.

（実施の形態）
図１〜図５は、本発明の実施の形態に係る半導体装置の製造工程を示す断面図である。
図１〜図５を参照して、本実施の形態の半導体装置１０（図５参照）の製造方法（具体的には、プラグ３１の形成方法）について説明する。 (Embodiment)
1-5 is sectional drawing which shows the manufacturing process of the semiconductor device based on Embodiment of this invention.
With reference to FIGS. 1-5, the manufacturing method (specifically, the formation method of the plug 31) of the semiconductor device 10 (refer FIG. 5) of this Embodiment is demonstrated.

始めに、図１に示す工程では、周知の手法により、半導体基板１１（例えば、単結晶シリコン基板）の主面１１ａ（表面）に下地絶縁膜１２（例えば、酸化シリコン膜（ＳｉＯ２膜））を形成する。次いで、フォトリソグラフィ技術及びドライエッチング技術により、下地絶縁膜１２に溝１４を形成する。 First, in the process shown in FIG. 1, a base insulating film 12 (for example, a silicon oxide film (SiO 2 film)) is formed on a main surface 11a (front surface) of a semiconductor substrate 11 (for example, a single crystal silicon substrate) by a known method. Form. Next, a trench 14 is formed in the base insulating film 12 by photolithography technology and dry etching technology.

次いで、周知の手法（ダマシン法）により、溝１４を埋め込む銅配線１５を形成する。次いで、周知の手法（例えば、ＣＶＤ法）により、下地絶縁膜１２の上面１２ａ及び銅配線１５の上面１５ａを覆う層間絶縁層１７を形成する。
次いで、銅配線１５上に位置する層間絶縁層１７に、フォトリソグラフィ技術及びドライエッチング技術により銅配線１５の一部を露出するビアホール１８を形成（開口）する。 Next, a copper wiring 15 that fills the groove 14 is formed by a known method (damascene method). Next, an interlayer insulating layer 17 that covers the upper surface 12a of the base insulating film 12 and the upper surface 15a of the copper wiring 15 is formed by a known method (for example, CVD method).
Next, a via hole 18 exposing a part of the copper wiring 15 is formed (opened) in the interlayer insulating layer 17 located on the copper wiring 15 by a photolithography technique and a dry etching technique.

次いで、後述する図２に示すチタン膜２１を形成する前に、ビアホール１８に露出された銅配線１５の表面に形成された酸化物を除去する。具体的には、図１に示す構造体を水素雰囲気中にて還元処理するか、或いは、Ａｒを用いたスパッタエッチングにより該酸化物を除去する。   Next, before forming a titanium film 21 shown in FIG. 2 described later, the oxide formed on the surface of the copper wiring 15 exposed in the via hole 18 is removed. Specifically, the structure shown in FIG. 1 is reduced in a hydrogen atmosphere, or the oxide is removed by sputter etching using Ar.

次いで、図２に示す工程では、銅配線１５の一部を実質的に完全に覆う部分を少なくとも有するようにチタン膜２１を形成する。
具体的には、少なくともビアホール１８の底面１８ａ及び層間絶縁層１７の上面１７ａ（上表面）に指向性の強いスパッタチャンバー内でチタン膜２１を形成する。ここでの「指向性が強いスパッタチャンバー」とは、スパッタ装置のＴｉターゲットと半導体基板１１との距離が遠いスパッタチャンバーのことをいう。 Next, in the process shown in FIG. 2, the titanium film 21 is formed so as to have at least a part that covers a part of the copper wiring 15 substantially completely.
Specifically, the titanium film 21 is formed at least on the bottom surface 18 a of the via hole 18 and the upper surface 17 a (upper surface) of the interlayer insulating layer 17 in a highly directional sputtering chamber. Here, the “sputter chamber with strong directivity” refers to a sputter chamber in which the distance between the Ti target of the sputtering apparatus and the semiconductor substrate 11 is long.

上記チタン膜２１を形成する際には、基板バイアスが１００ワット乃至４００ワットとされたロングスロースパッタ法を用いる。基板バイアスが高すぎると（４００ワットよりも大きいと）銅配線１５とチタン膜２１との接触抵抗が増加するため好ましくない。   When the titanium film 21 is formed, a long throw sputtering method with a substrate bias of 100 watts to 400 watts is used. If the substrate bias is too high (greater than 400 watts), the contact resistance between the copper wiring 15 and the titanium film 21 increases, which is not preferable.

また、上記チタン膜２１は、ビアホール１８の底面１８ａ（言い換えれば、ビアホール１８に露出された銅配線１５の表面）に形成される厚さが２ｎｍ乃至７．５ｎｍとなるように形成するとよい。
また、チタン膜２１は、少なくともビアホール１８に露出された銅配線１５の表面に形成されておればよく、ビアホール１８の側壁面１８ｂには成膜されない方がよい。
なお、図２では、一例として、ビアホール１８の側壁面１８ｂにチタン膜２１が成膜されていない場合を図示している。 The titanium film 21 is preferably formed so that the thickness formed on the bottom surface 18a of the via hole 18 (in other words, the surface of the copper wiring 15 exposed in the via hole 18) is 2 nm to 7.5 nm.
The titanium film 21 only needs to be formed on at least the surface of the copper wiring 15 exposed in the via hole 18 and should not be formed on the side wall surface 18 b of the via hole 18.
In FIG. 2, as an example, a case where the titanium film 21 is not formed on the side wall surface 18 b of the via hole 18 is illustrated.

このように、基板バイアスが１００ワット乃至４００ワットとされたロングスロースパッタ法を用いて、ビアホール１８の底面１８ａに形成される厚さが２ｎｍ乃至７．５ｎｍとなるようにチタン膜２１を形成することで、銅配線１５とチタン膜２１との間の接触抵抗を低くすることができると共に、半導体基板１１面内における該接触抵抗のばらつきを小さくすることができる。   As described above, the titanium film 21 is formed using the long throw sputtering method in which the substrate bias is set to 100 watts to 400 watts so that the thickness formed on the bottom surface 18a of the via hole 18 is 2 nm to 7.5 nm. As a result, the contact resistance between the copper wiring 15 and the titanium film 21 can be reduced, and variations in the contact resistance in the surface of the semiconductor substrate 11 can be reduced.

次いで、指向性の強いスパッタチャンバー内で、ビアホール１８の底面１８ａに形成されたチタン膜２１（言い換えれば、チタン膜２１のうち、銅配線１５の一部（ビアホール１８に露出された部分）を実質的に完全に覆う部分）上から、ビアホール１８を区画する層間絶縁層１７の側面１７ｂ（言い換えれば、ビアホール１８の側壁面１８ｂ）を経由して層間絶縁層１７の上面１７ａ（表面）に延在する第１窒化チタン膜２２を形成する。   Next, the titanium film 21 formed on the bottom surface 18a of the via hole 18 (in other words, a part of the copper wiring 15 in the titanium film 21 (the portion exposed to the via hole 18) is substantially formed in the sputtering chamber having strong directivity. Part of the interlayer insulating layer 17 that divides the via hole 18 (in other words, the side wall surface 18b of the via hole 18) that extends to the upper surface 17a (front surface) of the interlayer insulating layer 17 from above. A first titanium nitride film 22 is formed.

これにより、ビアホール１８の底面１８ａ及び層間絶縁層１７の上面１７ａに形成されたチタン膜２１と、チタン膜２１が形成されていないビアホール１８の側壁面１８ｂと、が第１窒化チタン膜２２で覆われる。   As a result, the titanium film 21 formed on the bottom surface 18 a of the via hole 18 and the upper surface 17 a of the interlayer insulating layer 17 and the side wall surface 18 b of the via hole 18 where the titanium film 21 is not formed are covered with the first titanium nitride film 22. Is called.

具体的には、ロングスロースパッタ法により、窒素雰囲気中の反応性スパッタを利用して、第１窒化チタン膜２２を形成する。このときの基板バイアスとしては、４００ワット乃至１０００ワットを印加する。
第１窒化チタン膜２２を形成する際に使用する上記基板バイアスでは、下層に形成されたチタン膜２１よりも指向性が強くなるが、膜厚を厚くすることでビアホール１８の底面１８ａに形成されたチタン膜２１を覆うことができる。 Specifically, the first titanium nitride film 22 is formed by reactive sputtering in a nitrogen atmosphere by a long throw sputtering method. As the substrate bias at this time, 400 watts to 1000 watts are applied.
The substrate bias used when forming the first titanium nitride film 22 has higher directivity than the titanium film 21 formed in the lower layer, but is formed on the bottom surface 18a of the via hole 18 by increasing the film thickness. The titanium film 21 can be covered.

また、第１窒化チタン膜２２は、ビアホール１８の底面１８ａに配置されたチタン膜２１上において、その厚さが１５ｎｍ乃至３０ｎｍとなるように形成するとよい。
さらに、第１窒化チタン膜２２を構成するチタンと窒素の組成比が１：１に近くなるように、第１窒化チタン膜２２を形成するとよい。 The first titanium nitride film 22 is preferably formed on the titanium film 21 disposed on the bottom surface 18a of the via hole 18 so that the thickness thereof is 15 nm to 30 nm.
Further, the first titanium nitride film 22 is preferably formed so that the composition ratio of titanium and nitrogen constituting the first titanium nitride film 22 is close to 1: 1.

このように、基板バイアスとして４００ワット乃至１０００ワットを用い、ロングスロースパッタ法により、ビアホール１８の底面１８ａに配置されたチタン膜２１上において、厚さが１５ｎｍ乃至３０ｎｍとなるように第１窒化チタン膜２２を形成することで、ビアホール１８の底面１８ａにおける第１窒化チタン膜２２の被覆範囲を調整することができる。   As described above, the first titanium nitride is used so as to have a thickness of 15 nm to 30 nm on the titanium film 21 disposed on the bottom surface 18a of the via hole 18 by long throw sputtering using 400 to 1000 watts as the substrate bias. By forming the film 22, the coverage of the first titanium nitride film 22 on the bottom surface 18 a of the via hole 18 can be adjusted.

次いで、図３に示す工程では、第１窒化チタン膜２２上に、第１窒化チタン膜２２の形成に使用したスパッタチャンバーと比較して、指向性の弱いスパッタチャンバー（第１窒化チタン膜２２の形成に使用したチャンバーとは別のチャンバー）内で第２窒化チタン膜２４を形成する。
ここでの「指向性の弱いスパッタチャンバー」とは、スパッタ装置のＴｉターゲットと半導体基板１１との距離が近い通常のチャンバーのことをいう。 Next, in the process shown in FIG. 3, a sputter chamber having a low directivity (of the first titanium nitride film 22 is formed on the first titanium nitride film 22 as compared with the sputter chamber used for forming the first titanium nitride film 22. The second titanium nitride film 24 is formed in a chamber different from the chamber used for the formation.
The “sputter chamber with low directivity” here refers to a normal chamber in which the distance between the Ti target of the sputtering apparatus and the semiconductor substrate 11 is short.

具体的には、図３に示す工程では、ロングスロースパッタ法ではなく、通常のスパッタ法（具体的には、窒素ガスを用いた反応性スパッタ）により、層間絶縁層１７の側面１７ｂ（ビアホール１８の側壁面１８ｂ）から層間絶縁層１７の表面１７ａに至る肩の部分１７ｃに対応する第１窒化チタン膜２２の部分を当該部分よりも厚い厚さを持って少なくとも覆うように、第２窒化チタン膜２４を形成する。   Specifically, in the step shown in FIG. 3, the side surface 17b (via hole 18) of the interlayer insulating layer 17 is not formed by a long throw sputtering method but by a normal sputtering method (specifically, reactive sputtering using nitrogen gas). The second titanium nitride so as to cover at least the portion of the first titanium nitride film 22 corresponding to the shoulder portion 17c extending from the side wall surface 18b) to the surface 17a of the interlayer insulating layer 17 with a thickness greater than that portion. A film 24 is formed.

これにより、ビアホール１８内に、チタン膜２１、第１窒化チタン膜２２、及び第２窒化チタン膜２４を有し、かつ第１窒化チタン膜２２と、第２窒化チタン膜２４と、がこの順で積層されたバリア層２５が形成される。   Thus, the via hole 18 has the titanium film 21, the first titanium nitride film 22, and the second titanium nitride film 24, and the first titanium nitride film 22 and the second titanium nitride film 24 are in this order. Thus, the barrier layer 25 laminated with is formed.

なお、指向性の強いスパッタチャンバーにおけるＴｉターゲットと半導体基板１１の距離は、指向性の弱いスパッタチャンバーにおけるＴｉターゲットと半導体基板１１の距離よりも遠い。   Note that the distance between the Ti target and the semiconductor substrate 11 in the sputtering chamber with high directivity is longer than the distance between the Ti target and the semiconductor substrate 11 in the sputtering chamber with low directivity.

図３に示す工程では、層間絶縁層１７の上面１７ａ及び肩の部分１７ｃに形成された第２窒化チタン膜２４の厚さが１０ｎｍ乃至４０ｎｍとなるように、第２窒化チタン膜２４を形成する。
また、第２窒化チタン膜２４を構成するチタンと窒素の組成比が１：１に近くなるように、第２窒化チタン膜２４を形成するとよい。 In the step shown in FIG. 3, the second titanium nitride film 24 is formed so that the thickness of the second titanium nitride film 24 formed on the upper surface 17a and the shoulder portion 17c of the interlayer insulating layer 17 is 10 nm to 40 nm. .
Further, the second titanium nitride film 24 is preferably formed so that the composition ratio of titanium and nitrogen constituting the second titanium nitride film 24 is close to 1: 1.

上記第２窒化チタン膜２４は、後述する図４に示す工程において、タングステン膜２７を形成する際に使用するプロセスガスであるＷＦ６から層間絶縁層１７の肩の部分１７ｃから層間絶縁層１７の上面１７ａに形成されたチタン膜２１（言い換えれば、ビアホール１８の上端部近傍から層間絶縁層１７の表面に形成されたチタン膜２１）を保護する機能を有する。
なお、第２窒化チタン膜２４は、一定の膜厚で形成すればよく、一般的なスパッタ条件により形成できる。 The second titanium nitride film 24 is formed from the shoulder gas 17c of the interlayer insulating layer 17 from the WF 6 which is a process gas used when forming the tungsten film 27 in the step shown in FIG. It has a function of protecting the titanium film 21 formed on the upper surface 17a (in other words, the titanium film 21 formed on the surface of the interlayer insulating layer 17 from the vicinity of the upper end portion of the via hole 18).
The second titanium nitride film 24 may be formed with a constant film thickness, and can be formed under general sputtering conditions.

次いで、図４に示す工程では、プロセスガスとしてＷＦ６を用いたＣＶＤ法により、チタン膜２１、第１窒化チタン膜２２、及び第２窒化チタン膜２４を介して、ビアホール１８を埋め込むタングステン膜２７を形成する。
このとき、層間絶縁層１７の上面１７ａの上方に形成された第２窒化チタン膜２４を覆うように、タングステン膜２７が形成される。 Next, in the step shown in FIG. 4, the tungsten film 27 that fills the via hole 18 through the titanium film 21, the first titanium nitride film 22, and the second titanium nitride film 24 by a CVD method using WF 6 as a process gas. Form.
At this time, the tungsten film 27 is formed so as to cover the second titanium nitride film 24 formed above the upper surface 17 a of the interlayer insulating layer 17.

次いで、図５に示す工程では、ＣＭＰ法により、層間絶縁層１７の上面１７ａに形成された不要なチタン膜２１、第１窒化チタン膜２２、及び第２窒化チタン膜２４を除去して、研磨後のタングステン膜２７の上面２７ａを層間絶縁層１７の上面１７ａに対して位置にする。   Next, in the step shown in FIG. 5, unnecessary titanium film 21, first titanium nitride film 22, and second titanium nitride film 24 formed on upper surface 17a of interlayer insulating layer 17 are removed by CMP and polished. The upper surface 27 a of the later tungsten film 27 is positioned with respect to the upper surface 17 a of the interlayer insulating layer 17.

これにより、層間絶縁層１７の上面１７ａが露出されると共に、チタン膜２１、第１窒化チタン膜２２、第２窒化チタン膜２４、及びタングステン膜２７により構成され、かつビアホール１８を埋め込むプラグ３１が形成される。プラグ３１は、銅配線１５と電気的に接続されている。   As a result, the upper surface 17a of the interlayer insulating layer 17 is exposed, and the plug 31 composed of the titanium film 21, the first titanium nitride film 22, the second titanium nitride film 24, and the tungsten film 27 and burying the via hole 18 is formed. It is formed. The plug 31 is electrically connected to the copper wiring 15.

本実施の形態の半導体装置の製造方法によれば、下地絶縁膜１２に形成された銅配線１５を覆う層間絶縁層１７にビアホール１８を形成し、次いで、少なくともビアホール１８の底面１８ａ及び層間絶縁層１７の上面１７ａに指向性の強いスパッタチャンバー内でチタン膜２１を形成し、次いで、チタン膜２１上に指向性の強いスパッタチャンバー内で第１窒化チタン膜２２を形成し、次いで、第１窒化チタン膜２２上に指向性の弱いスパッタチャンバー内で第２窒化チタン膜２４を形成し、その後、チタン膜２１、第１窒化チタン膜２２、及び第２窒化チタン膜２４を介して、ビアホール１８を埋め込むタングステン膜２７を形成して、ビアホール１８内にチタン膜２１、第１窒化チタン膜２２、第２窒化チタン膜２４、及びタングステン膜２７よりなるプラグ３１を形成することで、チタン膜２１、第１窒化チタン膜２２、及び第２窒化チタン膜２４の形成に加熱処理を行うことなく、エレクトロマイグレーション（ＥＭ）耐性を確保した上で、タングステン膜２７の成膜に起因するボルケーノの発生を抑制可能となる。   According to the method of manufacturing a semiconductor device of the present embodiment, via holes 18 are formed in the interlayer insulating layer 17 covering the copper wiring 15 formed in the base insulating film 12, and then at least the bottom surface 18a of the via hole 18 and the interlayer insulating layer. The titanium film 21 is formed on the upper surface 17a of the substrate 17 in a highly directional sputtering chamber, and then the first titanium nitride film 22 is formed on the titanium film 21 in the directional sputtering chamber. A second titanium nitride film 24 is formed on the titanium film 22 in a sputtering chamber with low directivity, and then the via hole 18 is formed via the titanium film 21, the first titanium nitride film 22, and the second titanium nitride film 24. A buried tungsten film 27 is formed, and a titanium film 21, a first titanium nitride film 22, a second titanium nitride film 24, and tungsten are formed in the via hole 18. By forming the plug 31 made of 27, the electromigration (EM) resistance is ensured without performing heat treatment for the formation of the titanium film 21, the first titanium nitride film 22, and the second titanium nitride film 24. Further, it is possible to suppress the generation of volcano caused by the formation of the tungsten film 27.

これにより、ビアホール１８内をタングステン膜２７で良好に埋め込むことができると共に、銅配線１５とプラグ３１との間の接触抵抗の半導体基板１１面内のばらつきを小さくでき、かつ良好な接触抵抗を得ることができる。   As a result, the inside of the via hole 18 can be satisfactorily filled with the tungsten film 27, variation in the contact resistance between the copper wiring 15 and the plug 31 can be reduced in the semiconductor substrate 11, and a good contact resistance can be obtained. be able to.

なお、本発明においては、先に指向性の強い条件で第１窒化チタン膜２２を形成し、その後、指向性の弱い条件で第２窒化チタン膜２４を形成することが非常に重要である。   In the present invention, it is very important to first form the first titanium nitride film 22 under conditions with high directivity, and then form the second titanium nitride film 24 under conditions with low directivity.

ところで、指向性の弱い条件を用いて第１の窒化チタン膜を形成すると、ビアホール１８の上端近傍で第１の窒化チタン膜によりオーバーハング形状が形成されてしまう。
このように、オーバーハング形状とされた第１の窒化チタン膜を形成後に、指向性の強い条件で第２の窒化チタン膜を成膜すると、ビアホール１８の底面１８ａのパターン端部でのカバレージが悪くなり、膜はがれを誘発してしまう。 By the way, when the first titanium nitride film is formed using conditions with low directivity, an overhang shape is formed by the first titanium nitride film in the vicinity of the upper end of the via hole 18.
As described above, when the second titanium nitride film is formed under a highly directional condition after the first titanium nitride film having an overhang shape is formed, the coverage at the pattern end of the bottom surface 18a of the via hole 18 is reduced. It worsens and triggers film peeling.

したがって、半導体基板１１面内のばらつきが少なく、かつ良好なプラグ３１の抵抗値を得るためには、先に指向性の強い条件で第１窒化チタン膜２２を形成し、その後、指向性の弱い条件で第２窒化チタン膜２４を形成することが非常に重要である。   Therefore, in order to obtain a favorable resistance value of the plug 31 with little variation in the surface of the semiconductor substrate 11, the first titanium nitride film 22 is first formed under the condition of strong directivity, and then the directivity is weak. It is very important to form the second titanium nitride film 24 under conditions.

なお、本実施の形態では、プラグ３１の下端が接続される配線の一例として、銅配線１５を例に挙げて説明したが、銅配線１５に替えてアルミニウム配線（図示せず）を形成し、次いで、アルミニウム配線を覆う層間絶縁層１７を形成後、フォトリソグラフィ技術及びドライエッチング技術によりアルミニウム配線の一部を露出するビアホール１８を形成（開口）し、その後、図２〜図５に示す工程を順次行うことで、アルミニウム配線上にプラグ３１を形成してもよい。   In the present embodiment, the copper wiring 15 has been described as an example of the wiring to which the lower end of the plug 31 is connected. However, an aluminum wiring (not shown) is formed instead of the copper wiring 15, Next, after forming an interlayer insulating layer 17 covering the aluminum wiring, a via hole 18 exposing a part of the aluminum wiring is formed (opened) by photolithography technique and dry etching technique, and then the steps shown in FIGS. The plug 31 may be formed on the aluminum wiring by performing sequentially.

この場合、特許文献１，２では必要であった加熱処理を行うことなく、タングステン膜２７の膜はがれやＷＦ６と反応してボルケーノが生じることを抑制可能となる。
これにより、ビアホール１８内をタングステン膜２７で良好に埋め込むことができると共に、アルミニウム配線とプラグ３１との間の接触抵抗の半導体基板１１面内のばらつきを小さくでき、かつ良好な接触抵抗を得ることができる。 In this case, it is possible to prevent volcano from reacting with the peeling or WF 6 of the tungsten film 27 without performing the heat treatment required in Patent Documents 1 and 2.
Thereby, the inside of the via hole 18 can be satisfactorily filled with the tungsten film 27, the variation in the contact resistance between the aluminum wiring and the plug 31 can be reduced in the surface of the semiconductor substrate 11, and a good contact resistance can be obtained. Can do.

また、図示していないシリコン上（具体的には、ドープドポリシリコン膜上やイオン注入方により単結晶シリコン基板に形成された不純物拡散領域上）に、本実施の形態のプラグ３１の形成方法と同様な手法により、プラグ３１を形成してもよい。   Also, the method for forming plug 31 of the present embodiment on silicon (not shown) (specifically, on a doped polysilicon film or an impurity diffusion region formed in a single crystal silicon substrate by ion implantation) The plug 31 may be formed by the same method as described above.

この場合、特許文献１，２では必要であった加熱処理を行うことなく、タングステン膜２７の膜はがれやＷＦ６と反応してボルケーノが生じることを抑制可能となる。
これにより、ビアホール１８内をタングステン膜２７で良好に埋め込むことができると共に、シリコンとプラグ３１との間の接触抵抗の半導体基板１１面内のばらつきを小さくでき、かつ良好な接触抵抗を得ることができる。 In this case, it is possible to prevent volcano from reacting with the peeling or WF 6 of the tungsten film 27 without performing the heat treatment required in Patent Documents 1 and 2.
Thereby, the inside of the via hole 18 can be satisfactorily filled with the tungsten film 27, the variation in the contact resistance between the silicon and the plug 31 in the surface of the semiconductor substrate 11 can be reduced, and a good contact resistance can be obtained. it can.

以上、本発明の好ましい実施の形態について詳述したが、本発明はかかる特定の実施の形態に限定されるものではなく、特許請求の範囲内に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

例えば、本実施の形態では、銅配線１５と接触する金属膜としてチタン膜２１を例に挙げて説明したが、チタン膜２１の替わりに、指向性の強いスパッタチャンバー内で、Ｔａ膜、Ｗ膜、Ｒｕ膜、Ｃｏ膜、Ｍｏ膜、Ｚｒ膜、Ｖ膜、Ｎｂ膜、Ｃｒ膜、Ｓｎ膜のうち、少なくとも１種よりなる膜を形成してもよい。この場合、本実施の形態と同様な効果を得ることができる。また、バリア層２５は、窒化物、酸化物、ホウ化物、炭化物を含有してもよい。   For example, in the present embodiment, the titanium film 21 is described as an example of the metal film in contact with the copper wiring 15, but instead of the titanium film 21, a Ta film and a W film are used in a highly directional sputtering chamber. A film made of at least one of Ru film, Co film, Mo film, Zr film, V film, Nb film, Cr film, and Sn film may be formed. In this case, the same effect as this embodiment can be obtained. The barrier layer 25 may contain nitride, oxide, boride, and carbide.

本発明は、半導体装置の製造方法に適用可能である。   The present invention is applicable to a method for manufacturing a semiconductor device.

１０…半導体装置、１１…半導体基板、１１ａ…主面、１２…下地絶縁膜、１２ａ，１５ａ，１７ａ，２７ａ…上面、１５…銅配線、１７…層間絶縁層、１７ｂ…側面、１７ｃ…肩の部分、１８…ビアホール、１８ａ…底面、１８ｂ…側壁面、２１…チタン膜、２２…第１窒化チタン膜、２４…第２窒化チタン膜、２５…バリア層、２７…タングステン膜、３１…プラグ   DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... Semiconductor substrate, 11a ... Main surface, 12 ... Base insulating film, 12a, 15a, 17a, 27a ... Upper surface, 15 ... Copper wiring, 17 ... Interlayer insulating layer, 17b ... Side surface, 17c ... Shoulder Portion 18, via hole 18 a bottom surface 18 b side wall surface 21 titanium film 22 first titanium nitride film 24 second titanium nitride film 25 barrier layer 27 tungsten film 31 plug

Claims (6)

配線を覆う層間絶縁層にビアホールを形成し、該ビアホールにバリア層を介してプラグを形成する半導体装置の製造方法であって、
前記バリア層を、第１の窒化チタン膜と、該第１の窒化チタン膜上に第２の窒化チタン膜と、順次積層させることで形成し、
前記第２の窒化チタン膜は、前記第１の窒化チタン膜を形成する時よりも弱い指向性で形成することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device, wherein a via hole is formed in an interlayer insulating layer covering a wiring, and a plug is formed in the via hole via a barrier layer,
The barrier layer is formed by sequentially laminating a first titanium nitride film and a second titanium nitride film on the first titanium nitride film,
The method of manufacturing a semiconductor device, wherein the second titanium nitride film is formed with a weaker directivity than when the first titanium nitride film is formed. 配線を覆う層間絶縁層にビアホールを形成して該配線の一部を露出する工程と、
前記配線の一部を実質的に完全に覆う部分を少なくとも有するチタン膜を形成する工程と、
前記チタン膜の前記部分上から、前記ビアホールを区画する前記層間絶縁層の側面を経由して前記層間絶縁層の表面に延在する第１窒化チタン膜を形成する工程と、
前記層間絶縁層の前記側面から前記表面に至る肩の部分に対応する前記第１窒化チタン膜の部分を当該部分よりも厚い厚さを持って少なくとも覆う第２窒化チタン膜を形成する工程と、
前記チタン膜ならびに前記第１及び第２窒化チタン膜を介して前記ビアホールを導電体で埋める工程と、
を有することを特徴とする半導体装置の製造方法。 Forming a via hole in an interlayer insulating layer covering the wiring to expose a part of the wiring;
Forming a titanium film having at least a portion that substantially completely covers a part of the wiring;
Forming a first titanium nitride film extending from the portion of the titanium film to the surface of the interlayer insulating layer via a side surface of the interlayer insulating layer defining the via hole;
Forming a second titanium nitride film covering at least a portion of the first titanium nitride film corresponding to a shoulder portion from the side surface to the surface of the interlayer insulating layer with a thickness greater than that portion;
Filling the via hole with a conductor via the titanium film and the first and second titanium nitride films;
A method for manufacturing a semiconductor device, comprising: 半導体基板上の銅配線を覆う層間絶縁層にビアホールを開口する工程と、
少なくとも前記ビアホールの底面および前記層間絶縁層の表面に指向性の強いスパッタチャンバー内でチタン膜を形成する工程と、
チタン膜上に前記指向性の強いスパッタチャンバー内で第１窒化チタン膜を形成する工程と、
前記第１窒化チタン膜上に指向性の弱いスパッタチャンバー内で第２窒化チタン膜を形成する工程と、
前記第２窒化チタン膜上にタングステン膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 Opening a via hole in an interlayer insulating layer covering the copper wiring on the semiconductor substrate;
Forming a titanium film in a highly directional sputtering chamber at least on the bottom surface of the via hole and the surface of the interlayer insulating layer;
Forming a first titanium nitride film on the titanium film in the highly directional sputtering chamber;
Forming a second titanium nitride film on the first titanium nitride film in a low directivity sputtering chamber;
Forming a tungsten film on the second titanium nitride film;
A method for manufacturing a semiconductor device, comprising: 前記指向性の強いスパッタチャンバーにおけるターゲットと前記半導体基板の距離は、前記指向性の弱いスパッタチャンバーにおけるターゲットと前記半導体基板の距離よりも遠いことを特徴とする請求項３に記載の半導体装置の製造方法。   4. The manufacturing method of a semiconductor device according to claim 3, wherein a distance between the target in the sputtering chamber with high directivity and the semiconductor substrate is longer than a distance between the target in the sputtering chamber with low directivity and the semiconductor substrate. Method. 前記チタン膜を１００ワット乃至４００ワットの基板バイアスを印加して形成し、前記第１窒化チタン膜を４００ワット乃至１０００ワットの基板バイアスを印加して形成することを特徴とする請求項３または４に記載の半導体装置の製造方法。   5. The titanium film is formed by applying a substrate bias of 100 watts to 400 watts, and the first titanium nitride film is formed by applying a substrate bias of 400 watts to 1000 watts. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. 前記チタン膜を前記銅配線の表面上で２ｎｍ乃至７．５ｎｍの膜厚で形成し、前記第１窒化チタン膜を前記チタン膜上で１５ｎｍ乃至３０ｎｍの膜厚で形成し、前記第２窒化チタン膜を前記ビアホール以外の領域で１０ｎｍ乃至４０ｎｍの膜厚で形成することを特徴とする請求項３ないし５のうち、いずれか１項に記載の半導体装置の製造方法。   The titanium film is formed with a thickness of 2 nm to 7.5 nm on the surface of the copper wiring, the first titanium nitride film is formed with a thickness of 15 nm to 30 nm on the titanium film, and the second titanium nitride is formed. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the film is formed with a film thickness of 10 nm to 40 nm in a region other than the via hole.
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