JP2013127826A - Driving method of variable resistive element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving method capable of reducing a load to be received by a variable resistive element at a reset operation.SOLUTION: In an operation for increasing the resistance (resetting) of a variable resistance element having a variable resistor structured of a metal oxide, a voltage applied across both electrodes of the variable resistive element is made to monotonously increase from the minimum voltage amplitude to the maximum voltage amplitude while taking a longer rising period than a predetermined minimum transition time, when applying a reset voltage pulse. Thereafter, the voltage applied across both electrodes of the variable resistive element is maintained to be at the maximum voltage amplitude during a predetermined maximum voltage applying period. Thereby, even if the maximum voltage amplitude is higher than a voltage required for the resetting voltage of the variable resistive element, a resetting operation starts in the middle of the rising period so that excessive spike current flowing in an early stage of a reset voltage application is suppressed.

Description

  The present invention relates to a driving method of a variable resistance element that stores resistance values as data, and more particularly to a voltage application method in a reset operation that changes the variable resistance element from a low resistance state to a high resistance state.

  With the spread of mobile devices such as portable electronic devices, flash memory is widely used as a large-capacity and inexpensive non-volatile memory capable of holding stored data even when the power is turned off. However, in recent years, the limit of miniaturization of flash memory has become apparent, and non-volatile such as MRAM (Magnetic Resistance Change Memory), PCRAM (Phase Change Memory), CBRAM (Solid Electrolyte Memory), Resistance Change Memory (see Patent Document 1), etc. Memory development is actively underway.

  Among these non-volatile memories, the resistance change memory is a resistance change type non-volatile memory that utilizes changes in oxygen vacancies in metal oxides, and it can be rewritten with a large resistance and can be rewritten at high speed. Expected to be inexpensive and large-capacity memory.

A memory cell of the resistance change memory is configured by a variable resistance element having a variable resistor sandwiched between a first electrode and a second electrode, and data writing to the memory cell is performed with the first electrode of the variable resistance element. By applying a voltage pulse between the second electrodes, the electrical resistance of the variable resistor is changed between a plurality of states to store information. As the material of the variable resistor, in addition to the hafnium oxide (HfO ₂ ) film described in Non-Patent Document 1, a perovskite oxide praseodymium / calcium / manganese oxide Pr _1-x Ca _x MnO ₃ ( PCMO) films, or oxides of transition metal elements such as titanium oxide (TiO ₂ ) films, nickel oxide (NiO) films, zinc oxide (ZnO) films, niobium oxide (Nb ₂ O ₅ ) films are reversible. It is known to show a resistance change.

  In recent years, taking the following Patent Document 1 as an example, a 1T1R type memory cell in which a transistor capable of current limiting and a variable resistance element are combined has been actively studied.

JP 2010-218603 A

H. Y. Lee et al., "Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO2 Based RRAM", IEDM Tech. Dig. Pp. 297-300, 2008

  In a 1T1R type memory cell, in a set operation in which a variable resistance element is transitioned from a high resistance state to a low resistance state, current limitation by a transistor is performed to suppress an increase in current flowing through the memory cell as the resistance of the element decreases. .

  On the other hand, in the reset operation for making a transition from the low resistance state to the high resistance state, the current is not limited by the transistor. This is because the responsiveness to the voltage and current of the variable resistance element changes due to a slight difference in the low resistance state, so that it is difficult to realize a stable resistance change with a constant current limit by the transistor.

  For this reason, in order to obtain a stable resistance change under the same voltage condition in consideration of variations in the low resistance state, in the conventional technique, a reset voltage pulse having a sufficiently large maximum voltage amplitude is applied to the variable resistance element during the reset operation. Therefore, depending on the low resistance state of the variable resistance element, a voltage higher than the voltage required for reset may be applied to the variable resistance element.

  As a result, excessive energy is released as a part of the reset current as a spike-like large current depending on the resistance value in the low resistance state at the initial stage of voltage application until the resistance change occurs. An example of the time change of the reset current flowing through the variable resistance element during the reset operation is schematically shown in FIG. As can be seen from the above description, the spike current can be generated regardless of the parasitic capacitance or the inductive component such as the variable resistance element or the wiring.

  Due to the generation of the spike current, the variable resistance element receives a large load. Furthermore, if the load is accumulated by repeating the reset operation, reliability such as the lifetime of the element becomes a problem.

  Therefore, in order to reduce the load that the variable resistance element receives during the reset operation, it is necessary to suppress a large current flowing in the initial stage of reset voltage application. However, as described above, since the responsiveness to the voltage and current of the variable resistance element changes depending on a slight difference in the low resistance state, it is difficult to realize a stable resistance change with a constant current limit by the transistor.

  In view of the above-described problems in the prior art, the present invention provides a driving method capable of reducing an excessive current more than a current necessary for a resistance change in a reset operation and reducing a load that the variable resistance element receives during the reset operation. The purpose is to provide.

In order to achieve the above object, a variable resistance element driving method according to the present invention includes:
A first electrode, a second electrode, and a variable resistor sandwiched between the first electrode and the second electrode and configured to include a metal oxide; the first electrode and the second electrode; By applying an electrical stress in between, the resistance state between the electrodes transits between two or more different states, and the resistance state after the transition is a driving method of a variable resistance element used for storing information,
In a reset operation in which a reset voltage pulse is applied between the electrodes of the variable resistance element to change the resistance state of the variable resistance element from a low resistance state to a high resistance state,
Applying the reset voltage pulse comprises:
A first step of monotonically increasing a voltage applied between the electrodes of the variable resistance element from a minimum voltage amplitude to a maximum voltage amplitude over a rising period longer than a predetermined minimum transition time;
After the first step, the voltage applied between the electrodes of the variable resistance element includes a second step of maintaining the maximum voltage amplitude in a predetermined maximum voltage application period.

Furthermore, in addition to the above features, the variable resistance element driving method according to the present invention includes:
The rising period is preferably longer than the falling period in which the voltage applied between the electrodes of the variable resistance element falls from the maximum voltage amplitude to the minimum voltage amplitude after the second step.

Furthermore, in addition to the above features, the variable resistance element driving method according to the present invention includes:
In the first step, it is preferable that the voltage change applied between the electrodes of the variable resistance element is continuous. Alternatively, in the first step, it is preferable that the voltage applied between the electrodes of the variable resistance element changes stepwise.

  Furthermore, in the variable resistance element driving method according to the present invention, in addition to the above characteristics, the rising period can be set to 1/5 or more of the maximum voltage application period.

  Furthermore, in addition to the above features, the variable resistance element driving method according to the present invention can have the rising period in the range of 10 nsec to 1 msec.

Furthermore, in addition to the above features, the variable resistance element driving method according to the present invention includes metal oxides constituting the variable resistor, hafnium oxide (HfO _X ), aluminum oxide (AlO _X ), and titanium oxide (TiO _X ). ) Or tantalum oxide (TaO _x ).

  In the driving method of the present invention, in the reset operation for changing the resistance state of the variable resistance element from the low resistance state to the high resistance state, the rising of the reset voltage pulse applied to both ends of the variable resistance element is lengthened, and the absolute voltage pulse is output. The reset voltage pulse is applied so that the value gradually increases from the minimum voltage amplitude to the maximum voltage amplitude.

  Thereby, even if the voltage required for the reset operation is a variable resistance element whose voltage is lower than the maximum voltage amplitude of the reset voltage pulse, before the voltage amplitude reaches the maximum voltage amplitude during the rise of the reset voltage pulse, Since the reset operation is started when the voltage amplitude matches the voltage required for the reset operation, the reset operation is performed under voltage conditions suitable for the low resistance state of the variable resistance element, regardless of the low resistance state of the variable resistance element. Can be implemented.

  On the other hand, when the reset voltage pulse rises rapidly, the voltage amplitude reaches the maximum voltage amplitude and the reset operation starts, so the maximum voltage amplitude that is higher than the voltage required for reset is low resistance. When applied to the variable resistance element in the state, a spike-like excessive current is generated. In the present invention, this can be avoided.

  As a result, it is possible to suppress a large current depending on the resistance value of the immediately previous low resistance state that flows in the initial stage of reset voltage pulse application, and that excessive energy is applied to the variable resistance element as stress during the reset operation. I can prevent it. As a result, the load that the variable resistance element receives during the reset operation is reduced, the life of the variable resistance element can be extended, and the reliability can be improved.

  Therefore, by using the driving method of the present invention, the reset current is controlled in a self-aligning manner by the variable resistance element itself during the reset operation, thereby suppressing the occurrence of excessive reset current and the life of the variable resistance element. The reliability of the variable resistance element can be improved.

Circuit diagram showing configuration around memory cell array of semiconductor memory device Sectional structure diagram showing an example of an element structure of a variable resistance element to which the driving method of the present invention can be applied A block diagram showing a schematic configuration of a semiconductor memory device The figure which shows the time change of the reset voltage applied between both electrodes of a variable resistance element, and the reset current which flows through a variable resistance element in the conventional reset operation method The figure which shows the time change of the reset voltage applied between both electrodes of a variable resistance element, and the reset current which flows through a variable resistance element in the reset operation | movement method of this invention. The figure which shows the relationship between the rising period of a reset voltage pulse, and the maximum value of a reset current in the reset operation method of this invention. The figure which shows an example of the rising shape of the reset voltage pulse applied to a variable resistance element in the reset operation method of this invention The figure which shows an example of the rising shape of the reset voltage pulse applied to a variable resistance element in the reset operation method of this invention

<First Embodiment>
FIG. 1 shows a memory cell provided with a variable resistance element to which a variable resistance element driving method of the present invention (hereinafter referred to as “method of the present invention” as appropriate) can be applied, and a plurality of such memory cells are arranged in a matrix. The circuit block diagram of the semiconductor memory device comprised by this is shown. In FIG. 1, the circuit configuration around the memory cell array will be described in detail, and the circuit configuration of the entire storage device will be described later with reference to FIG. In the drawings shown below, for the convenience of explanation, the main part is shown with emphasis, and the dimensional ratio of each part of the element may not always match the actual dimensional ratio.

  As shown in FIG. 1, in the semiconductor memory device 10, a memory cell 23 is configured by connecting one end of a variable resistance element 21 and the drain of a cell transistor 22 (one end of an input / output terminal pair). The memory cell array 11 is configured by arranging a plurality of memory cells 23 in a matrix in the row and column directions. The gates (control terminals) of the cell transistors 22 of the memory cells 23 arranged in the same row are connected to word lines (WL1 to WLn) extending in the row direction (n is a natural number) and arranged in the same column. The other end of the variable resistance element 21 of each memory cell 23 is connected to bit lines (BL1 to BLm) extending in the column direction (m is a natural number). The source of the cell transistor 22 (the other end of the input / output terminal pair) of each memory cell 23 arranged in the same row is connected to source lines (SL1 to SLn) extending in the row direction.

  Each word line WL1 to WLn is connected to the word line voltage application circuit 12, each bit line BL1 to BLm is connected to the bit line voltage application circuit 13, and each source line SL1 to SLn is respectively connected to the word line voltage application circuit 12. The source line voltage application circuit 14 is connected. Each of these voltage application circuits 12, 13, and 14 selects a memory cell to be operated based on an instruction from a control circuit 16 to be described later, a word line connected to the selected memory cell 23, a bit line, and A voltage necessary for the operation of the memory cell is applied to each of the source lines.

  The element structure of the variable resistance element 21 that is used in the semiconductor memory device 10 and to which the method of the present invention can be applied is schematically shown in FIG. 2 as an example. In the variable resistance element 21a shown in the cross-sectional structure diagram of FIG. 2, a variable resistor 27 using a metal oxide and an upper electrode (second electrode) 28 are sequentially laminated on a lower electrode (first electrode) 26. The memory cell 23 of FIG. 1 can be realized by connecting the lower electrode 26 to the drain of the cell transistor 22 formed below, which is an element having a three-layer structure.

In this embodiment, hafnium oxide (HfO _X ), which is an insulator having a large band gap, is selected and used as the material of the variable resistor 27. However, the present invention is not limited to this configuration. Zirconium oxide (ZrO _X ), aluminum oxide (AlO _X ), titanium oxide (TiO _X ), tantalum oxide (TaO _X ), vanadium oxide (VO _X ), niobium oxide (NbO _X ), tungsten oxide (WO) as variable resistors _X), or it may be used strontium titanate (SrTiO _X) or the like.

  When these metal oxides are used as the material of the variable resistor 27, the variable resistance element immediately after manufacture is changed to a state in which the high resistance state and the low resistance state can be switched by electrical stress. In addition, a so-called forming process is performed in which a voltage pulse having a larger voltage amplitude and a longer pulse width than a voltage pulse used for a normal rewrite operation is applied to a variable resistance element in an initial state immediately after manufacturing to form a current path in which resistance switching occurs. It is necessary to have done. In the present embodiment, a forming process is performed by applying a pulse of 2.5 V and 50 μs across the memory cell 23. It is known that a current path (called a filament path) formed by this forming process determines the electrical characteristics of the subsequent element.

  As materials for the lower electrode 26 and the upper electrode 28, various conductive materials can be used. Preferably, materials having different work functions are used for the lower electrode 26 and the upper electrode 28, and the material having a larger work function is variable. The resistor 27 is configured to be a Schottky junction. Here, the electrode having the higher work function is selected from a conductive material having a work function of 4.5 eV or higher, and the electrode having a lower work function is selected from a conductive material having a work function lower than 4.5 eV. More preferably. For example, it is preferable to use TiN as the lower electrode 26 and Ti or Ta as the upper electrode 28 in terms of ease of integration processing.

  FIG. 3 is a circuit block diagram showing a schematic configuration example of the semiconductor memory device 10. As shown in FIG. 3, the semiconductor memory device 10 includes a memory cell array 11, a word line voltage application circuit 12, a bit line voltage application circuit 13, a source line voltage application circuit 14, a voltage generation circuit 15, and a control circuit 16. Configured. Among them, the configuration of the memory cell array 11 has already been described with reference to FIG.

  The control circuit 16 controls each memory operation of rewriting (setting and resetting), reading, and forming of the memory cell array 11. Specifically, the control circuit 16 is based on the address signal input from the address line, the data signal input / output from the data line, and the control input signal input from the control signal line. The line voltage application circuit 13 and the source line voltage application circuit 14 are controlled to control each memory operation of the memory cell. In the example shown in FIG. 3, the control circuit 16 has functions as a general address buffer circuit, data input / output buffer circuit, and control input buffer circuit.

  The voltage generation circuit 15 generates a selected word line voltage and a non-selected word line voltage necessary for selecting a memory cell to be operated in each memory operation of rewriting (set and reset), reading, and forming to generate a word line. The selected bit line voltage and the unselected bit line voltage necessary for selecting the operation target memory cell are generated and supplied to the bit line voltage applying circuit 13. In addition, a selected source line voltage and a non-selected source line voltage necessary for selecting a memory cell to be operated are generated and supplied to the source line voltage application circuit 14.

  In particular, in the present embodiment, the voltage generation circuit 15 generates a reset voltage pulse having a long rising period during the reset operation and supplies the reset voltage pulse to the bit line voltage application circuit 13 as a selected bit line voltage.

  When the memory cell to be operated is input to the address line and specified in each of the rewrite (set and reset), read, and forming memory operations, the word line voltage application circuit 12 is based on an instruction from the control circuit 16. A word line corresponding to an address signal input to the address line is selected, and a selected word line voltage and a non-selected word line voltage are respectively applied to the selected word line and the non-selected word line. The same applies to the bit line voltage application circuit 13 and the source line voltage application circuit 14. As a result, for each memory operation, a desired voltage can be applied only to the selected word line, the selected bit line, and the selected source line to which the memory cell 23 to be operated is connected.

  The detailed circuit configuration, device structure, and manufacturing method of the control circuit 16, the voltage generation circuit 15, the word line voltage application circuit 12, the bit line voltage application circuit 13, and the source line voltage application circuit 14 are publicly known. The description is omitted because it can be realized using the circuit configuration described above and can be manufactured using a known semiconductor manufacturing technique. The device structure and manufacturing method of the memory cell array 11 can also be realized by using a known circuit configuration and can be manufactured by using a known semiconductor manufacturing technique, and will not be described.

  Hereinafter, the method of the present invention will be described in detail.

  4 and 5 show the time change of the reset voltage applied between both electrodes of the variable resistance element and the time change of the reset current flowing through the variable resistance element in the reset operation of the variable resistance element. Here, the reset operation uses a circuit similar to that of the memory cell 23 of FIG. 1, applies a high voltage to the gate of the cell transistor 22, and does not limit the current by the cell transistor 22. A fixed voltage (ground potential) is applied to the source, and a reset voltage pulse is applied from the other end side of the variable resistance element 21.

  FIG. 4 shows the voltage waveform of the reset voltage applied to both ends of the variable resistance element (FIG. 4A) and the reset current flowing through the variable resistance element in the conventional method in which the rising period of the reset voltage pulse is not set. It is a figure which shows a current waveform (FIG.4 (b)) typically. In the method shown in FIG. 4, the voltage pulse except for the finite rise period or fall period (hereinafter referred to as “minimum transition time”) that minimizes the rising period and the falling period of the reset voltage pulse and is unavoidable in terms of the circuit configuration. Rises vertically from the minimum voltage amplitude to the maximum voltage amplitude, and falls vertically. At this time, as shown in FIG. 4B, the reset current waveform flowing in the variable resistance element has a spike-like rapid current increase in the initial stage of voltage pulse application. The maximum value of the spike current at this time was approximately 125 μA.

  On the other hand, FIG. 5 shows a voltage waveform (FIG. 5A) of the reset voltage applied between both electrodes of the variable resistance element when the method of the present invention is used, and the reset current flowing through the variable resistance element. Each of the current waveforms (FIG. 5B) is schematically shown. The method shown in FIG. 5 sets the rising period of the reset voltage pulse to 100 nsec, gradually increases the reset voltage from the minimum voltage amplitude to the maximum voltage amplitude, and maintains the maximum voltage amplitude for 50 nsec. This is an example in which the reset voltage falls vertically to the minimum voltage amplitude with the minimum transition time. Therefore, the rising period of the reset voltage is longer than the falling period.

  As shown in FIG. 5B, when the method of the present invention is used, the change in the reset current flowing through the variable resistance element is gentle, and the spike-like rapid current as seen when the rising period is not set. Change is suppressed. The maximum value of the reset current at this time was approximately 110 μA.

  Moreover, the variable resistance element 21 showed the resistance change to the same high resistance state, when not setting the rising period of a reset voltage pulse (FIG. 4), and setting to 100 nsec (FIG. 5).

  From the above, by setting the rising period of the reset voltage pulse, high resistance is started under the voltage condition that matches the low resistance state of the variable resistance element in the middle of the rising period, and as a result, the reset voltage pulse is applied. It is thought that the initial excessive current increase was suppressed.

  FIG. 6 shows the relationship between the rising period of the reset voltage pulse and the maximum value of the reset current in the reset operation of the variable resistance element 21 of the present embodiment. When the rising period is not set in the reset voltage pulse, the reset current is about 125 μA. However, when the rising period of the reset voltage pulse is 10 nsec (that is, the rising period is 50 nsec while maintaining the maximum voltage amplitude). The reset current is approximately 115 μA and the reset current is approximately 100 μA when the rising period is 1 ms. It can be seen that the reset current can be reduced as the rising period is increased. Note that after the maximum reset current flows, the reset current that flows after the resistance change is about 80 μA regardless of the rising period.

  From FIG. 6, the longer the rising period of the reset voltage pulse, the lower the reset current. However, in consideration of high-speed operation as a large-capacity memory, it is practically preferable to be about 1 msec or less.

  Further, the rising shape of the reset voltage pulse during the rising period may be continuously increased from the minimum voltage amplitude to the maximum voltage amplitude as shown in FIG. 7A, or as shown in FIG. 7B. As such, it may be increased stepwise. In the case of a reset voltage pulse whose rising gradually increases stepwise, it is desirable that the amount of increase in voltage amplitude of each voltage step of the reset voltage pulse rising in a stepwise manner be 0.01 V or less. Therefore, for example, when the rising period is set to 50 ns which is the same as the maximum voltage application period, when the voltage amplitude in the maximum voltage application period is 2 V, the time width of the pulses constituting each voltage step is 0.25 ns or less. Is desirable.

  From the above results, it can be seen that by performing the reset operation using the method of the present invention, it is possible to reduce the spike-like excess current that flows until the high resistance occurs after the application of the reset voltage pulse. Therefore, by using the method of the present invention, the lifetime of the variable resistance element can be extended and the reliability of the variable resistance element can be improved.

  Hereinafter, another embodiment of the present invention will be described.

  <1> In the above embodiment, when the reset voltage pulse is applied, the reset voltage pulse is applied from the variable resistance element 21 side while a fixed voltage (ground potential) is applied to the source of the cell transistor 22. Conversely, a reset voltage pulse may be applied from the cell transistor 22 side in a state where a fixed voltage is applied to the other end of the variable resistance element 21 that is not connected to the cell transistor 22. Further, different voltage pulses may be applied from both sides of the variable resistance element 21 and the cell transistor 22. As long as the voltage applied to both ends of the variable resistance element has a rising period as shown in FIG. 5A as a result of applying both voltage pulses, the effects of the present invention can be achieved.

  <2> The method of the present invention can be applied as long as a variable resistance element using a metal oxide as a variable resistor is provided, and is not limited to the configuration of the variable resistance element 23 or the semiconductor memory device 10 described above. . In the above embodiment, the variable resistance element 23 is exemplified by the element structure shown in FIG. 2, but the present invention is not limited to the element having the structure. In the above embodiment, the case where the memory cell array 11 extends as the semiconductor memory device 10 in the row direction and in the direction perpendicular to the bit line is described as an example. However, the present invention is not limited to this. For example, the bit line and the source line may extend in parallel.

  <3> In the above embodiment, when applying the reset voltage pulse, the voltage amplitude is gradually increased from the minimum voltage amplitude (zero) to the maximum voltage amplitude during the rising period, thereby reducing the spike-like excess current. ing. Here, the spike-like excess current is caused by applying a reset voltage more than necessary to the variable resistance element due to variations in the low resistance state before the reset operation as described above. In other words, the spike-like excess current is generated in the variable resistance element to which the reset voltage more than necessary is applied as a result of the reset voltage necessary for the reset operation being varied by the variable resistance element.

  Therefore, when applying the reset voltage pulse, it is not always necessary to gradually increase the voltage amplitude in the rising period from the minimum voltage amplitude (zero) to the maximum voltage amplitude, as shown in FIGS. 8 (a) and 8 (b). As described above, the reset voltage pulse rises vertically with the minimum transition time from the minimum voltage amplitude to the predetermined minimum reset voltage in consideration of the required reset voltage variation, and rises from the minimum reset voltage to the maximum voltage amplitude. You may make it increase gradually in a period. At this time, as shown in FIG. 8A, the voltage may be continuously increased from the minimum reset voltage to the maximum voltage amplitude, or may be increased stepwise as shown in FIG. 8B. Absent. With this configuration, it is possible to reduce the spike-like excess current and shorten the time required for the reset operation.

  The present invention is applicable to a nonvolatile variable resistance element in which a resistance state transitions by application of electrical stress and the resistance state after the transition is held in a nonvolatile manner.

DESCRIPTION OF SYMBOLS 10: Semiconductor memory device 11: Memory cell array 12: Word line voltage application circuit 13: Bit line voltage application circuit 14: Source line voltage application circuit 15: Voltage generation circuit 16: Control circuit 21: Variable resistance element 22: Cell transistor 23: Memory cell 26: First electrode 27: Variable resistor 28: Second electrode BL1-BLm: Bit lines SL1-SLn: Source lines WL1-WLn: Word lines

Claims (7)

A first electrode, a second electrode, and a variable resistor sandwiched between the first electrode and the second electrode and configured to include a metal oxide; the first electrode and the second electrode; By applying an electrical stress in between, the resistance state between the electrodes transits between two or more different states, and the resistance state after the transition is a driving method of a variable resistance element used for storing information,
In a reset operation in which a reset voltage pulse is applied between the electrodes of the variable resistance element to change the resistance state of the variable resistance element from a low resistance state to a high resistance state,
Applying the reset voltage pulse comprises:
A first step of monotonically increasing a voltage applied between the electrodes of the variable resistance element from a minimum voltage amplitude to a maximum voltage amplitude over a rising period longer than a predetermined minimum transition time;
After the first step, the voltage applied between the electrodes of the variable resistance element includes a second step of maintaining the maximum voltage amplitude in a predetermined maximum voltage application period. Driving method.   The rising period is longer than a falling period in which a voltage applied between the electrodes of the variable resistance element falls from the maximum voltage amplitude to the minimum voltage amplitude after the second step. Item 8. A variable resistance element driving method according to Item 1.   3. The variable resistance element driving method according to claim 1, wherein in the first step, a voltage change applied between the electrodes of the variable resistance element is continuous. 4.   3. The variable resistance element driving method according to claim 1, wherein in the first step, a voltage applied between the electrodes of the variable resistance element changes stepwise. 4.   5. The variable resistance element driving method according to claim 1, wherein the rising period is １ ／ or more of the maximum voltage application period. 6.   5. The variable resistance element driving method according to claim 1, wherein the rising period is in a range of 10 nsec to 1 msec. 6. The metal oxide constituting the variable resistor is any one of hafnium oxide (HfO _X ), aluminum oxide (AlO _X ), titanium oxide (TiO _X ), or tantalum oxide (TaO _X ). The method for driving a variable resistance element according to claim 1.

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