JP2014086692A - Nonvolatile memory element and drive method of nonvolatile memory element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile memory element having a satisfactory rewriting performance.SOLUTION: The nonvolatile memory element comprises: a resistance change layer 3 having a first electrode 2, a second electrode 4, a first resistance change layer 3a constituted of a first metal oxide, the first resistance change layer 3a being formed between the first electrode 2 and the second electrode 4, and a second resistance change layer 3b constituted of a second metal oxide with the oxygen shortage smaller than the first metal oxide, the first resistance change layer 3a and the second resistance change layer 3b being laminated one after another, in which the resistance value changes reversibly according to the applied voltage pulse; and a field effect transistor 20 as a control unit which is inserted in a path of a current flowing to the resistance change layer 3 to control a first current value flowing to the resistance change layer 3 at completion of a deleting step in which a deleting voltage pulse of a first polarity is applied to increase the resistance of the resistance change layer 3, and to a second current value or lower which flows to the resistance change layer 3 at completion of a writing step in which a writing voltage pulse having a second polarity different from the first polarity is applied to reduce the resistance of the resistance change layer 3.

Description

  The present invention relates to a variable resistance nonvolatile memory element.

  In recent years, with the advancement of digital technology, electronic devices such as portable information devices and information home appliances have become more sophisticated. As these electronic devices have higher functions, the semiconductor elements used have been rapidly miniaturized and increased in speed. Among them, the use of a large-capacity nonvolatile storage device represented by a flash memory is rapidly expanding. Furthermore, as a next-generation nonvolatile memory device that replaces this flash memory, research and development of a nonvolatile memory device including a resistance change type nonvolatile memory element having a property that a resistance value is reversibly changed by an electrical signal has been developed. Progressing.

  FIG. 20 is a cross-sectional view showing a configuration of a conventional example of such a nonvolatile memory element (see, for example, Patent Document 1 and Non-Patent Document 1). As shown in FIG. 20, the nonvolatile memory element 1030 includes a transistor 1020 and a nonvolatile memory portion 1010 formed on the main surface of a semiconductor substrate 1024.

  The transistor 1020 constitutes a circuit that controls conduction of the nonvolatile memory portion 1010 to the bit line. The transistor 1020 includes a first diffusion layer 1025a, a second diffusion layer 1025b, a gate insulating film 1026, and a gate electrode 1027. Yes. The nonvolatile memory unit 1010 includes a first electrode 1002 connected to the first diffusion layer 1025a, a resistance change layer 1003 whose resistance is reversibly changed by a voltage pulse or a current pulse, and a second electrode 1004. I have. Further, the transistor 1020 and the nonvolatile memory portion 1010 formed over the semiconductor substrate 1024 are covered with an interlayer insulating layer 1028, and the second electrode 1004 is connected to the electrode wiring 1029.

In Patent Document 1, as a material constituting the resistance change layer 1003, nickel oxide (NiO), vanadium oxide (V ₂ O ₅ ), zinc oxide (ZnO), niobium oxide (Nb ₂ O ₅ ), titanium An oxide (TiO ₂ ), tungsten oxide (WO ₃ ), cobalt oxide (CoO), or the like is used. Such a transition metal oxide exhibits a specific resistance value when a voltage or current exceeding a threshold value is applied, and the resistance value maintains the resistance value until a new voltage or current is applied. It is known. In Non-Patent Document 1, PCMO (Pr _1-x Ca _x MnO ₃ ) is used as a material constituting the resistance change layer 1003. Perovskite-type metal oxides are also known to exhibit the above resistance change characteristics.

JP 2004-363604 A

W. W. Zhuang et al. , “Novel Cossal Magnetoretic Thin Film Nonvolatile Resilience Random Access Memory (RRAM®)”, IEDM Technical Digest, pp. 193-196, December 2002

  By the way, in the case of a resistance change type nonvolatile memory element, rewriting characteristics may be a problem. In other words, when the writing is repeated a predetermined number of times, the change in the resistance value of the variable resistance layer becomes unstable, so that a writing error is likely to occur. Therefore, it is desirable from the viewpoint of reliability to show stable rewriting characteristics even after rewriting the nonvolatile memory element many times (for example, 10,000 times or 100,000 times).

  The present invention has been made in view of such circumstances, and a main object thereof is to provide a nonvolatile memory element capable of improving the rewrite characteristics.

  In order to solve the above-described problem, a nonvolatile memory element of the present invention is provided between a first electrode, a second electrode, and a first electrode and a second electrode, and a first metal A first variable resistance layer composed of an oxide and a second variable resistance layer composed of a second metal oxide whose oxygen deficiency is smaller than the first metal oxide; A resistance change layer whose resistance value reversibly changes in response to a voltage pulse applied between the first electrode and the second electrode, and a current path flowing through the resistance change layer, The resistance change upon completion of an erase step of applying an erase voltage pulse of a first polarity between the first electrode and the second electrode to change the resistance change layer from a low resistance state to a high resistance state. The first current value flowing through the layer is changed from the high resistance state to the low resistance state of the variable resistance layer. Therefore, a second current flowing in the resistance change layer upon completion of a write step of applying a write voltage pulse having a second polarity different from the first polarity between the first electrode and the second electrode is provided. A controller that suppresses the current value to be equal to or lower than the current value.

  According to the nonvolatile memory device of the present invention, a memory device having good rewrite characteristics can be realized. In addition, according to this nonvolatile memory device, good rewrite characteristics are maintained even after a large number of rewrite operations, so that a stable storage operation can be realized.

FIG. 1 is a cross-sectional view showing a configuration of a variable resistance element included in the nonvolatile memory element according to Embodiment 1 of the present invention. FIG. 2A is a diagram showing resistance change characteristics of a resistance change element in which the second resistance change layer is made of Ta ₂ O ₅ . FIG. 2B is a diagram showing resistance change characteristics of a resistance change element in which the _second resistance change layer is made of HfO ₂ . FIG. 2C is a diagram showing resistance change characteristics of a resistance change element in which the second resistance change layer is made of Al ₂ O ₃ . FIG. 3 is a diagram showing current-voltage characteristics of the variable resistance element included in the nonvolatile memory element according to Embodiment 1 of the present invention. FIG. 4A is an equivalent circuit diagram of the nonvolatile memory element according to Embodiment 1 of the present invention. FIG. 4B is a circuit diagram of a resistance change element included in the nonvolatile memory element. FIG. 4C is a circuit diagram of a field effect transistor included in the nonvolatile memory element. FIG. 5 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 1 of the present invention. FIG. 6 is a diagram schematically showing the load curve of the N-type MISFET and the current-voltage characteristics of the resistance change element in the write step. FIG. 7 is a diagram comparing the standard deviation value of the read current variation in the nonvolatile memory element between the example and the reference example. FIG. 8 is a diagram schematically showing the load curve of the N-type MISFET and the current-voltage characteristics of the resistance change element in the erasing step. FIG. 9 is a diagram showing the relationship between the voltage applied to the nonvolatile memory element in the erasing step and the resistance value of the resistance change element. FIG. 10 is a diagram illustrating a relationship between a voltage applied to the variable resistance element in the high resistance state and a current value flowing through the variable resistance element. FIG. 11 is a diagram showing the relationship between the value of the current flowing through the variable resistance element upon completion of the erase step and the standard deviation value of the read current variation in the low resistance state. FIG. 12 is a diagram showing a load curve of the N-type MISFET in the erasing step when the width of the diffusion layer of the N-type MISFET as the controller is 1.0 μm or 1.5 μm. FIG. 13 is a diagram showing a load curve of the N-type MISFET in the erasing step when the voltage applied to the gate terminal of the N-type MISFET as the controller is set to 3.0V or 3.3V. FIG. 14A is a diagram schematically showing the load curve of the N-type MISFET and the current-voltage characteristics of the resistance change element in the erase step and the write step. FIG. 14B is a diagram schematically illustrating the load curve of the N-type MISFET and the current-voltage characteristics of the resistance change element in the erase step and the write step. FIG. 15 is a diagram showing a load curve in the erasing step when a fixed resistor of 1000Ω or 5000Ω is used as the controller. FIG. 16 is a diagram showing a modification of the configuration of the variable resistance element included in the nonvolatile memory element according to Embodiment 1 of the present invention. FIG. 17 is a cross-sectional view showing a modified example of the configuration of the nonvolatile memory element according to Embodiment 1 of the present invention. FIG. 18 is a block diagram showing an example of the configuration of the nonvolatile memory device according to Embodiment 2 of the present invention. FIG. 19 is a block diagram showing a modified example of the configuration of the nonvolatile memory device according to Embodiment 2 of the present invention. FIG. 20 is a cross-sectional view showing a configuration of a conventional nonvolatile memory element.

  A nonvolatile memory element according to one embodiment of the present invention is provided between a first electrode, a second electrode, and the first electrode and the second electrode, and includes a first metal oxide. A first resistance change layer, and a second resistance change layer made of a second metal oxide having a lower oxygen deficiency than the first metal oxide, and the first electrode. A resistance change layer whose resistance value reversibly changes according to a voltage pulse applied between the first electrode and the second electrode; a first input / output terminal connected to the first electrode; And a field effect transistor having a gate terminal for controlling conduction between the first input / output terminal and the second input / output terminal. An erase voltage pulse having a first polarity is applied between the first electrode and the second electrode via an effect transistor. The resistance change layer changes from the low resistance state to the high resistance state, and the resistance change layer has the first polarity between the first electrode and the second electrode via the field effect transistor. Changes from a high resistance state to a low resistance state by applying a write voltage pulse of a different second polarity, and when the write voltage pulse is applied, the second input / output terminal of the field effect transistor is a source terminal The field effect transistor has a first current value that flows through the resistance change layer when the resistance change layer completes a change from a low resistance state to a high resistance state by application of the erase voltage pulse. Is suppressed to a value equal to or lower than a second current value flowing through the resistance change layer when the change from the high resistance state to the low resistance state is completed by application of the erase voltage pulse.

  According to this aspect, since the value of the current flowing through the nonvolatile memory element in the writing step can be controlled based on the saturation characteristics of the field effect transistor, a nonvolatile memory element having excellent rewriting characteristics can be obtained. Further, based on the source follower characteristics of the field effect transistor, the first current value that flows to the nonvolatile memory element when the erasing step is completed is changed to the first current value that flows to the nonvolatile memory element when the write step is completed. 2 or less.

  As a result, good rewriting characteristics of the nonvolatile memory element are maintained even after a large number of rewriting operations, so that a nonvolatile memory element having excellent rewriting characteristics can be obtained. The nonvolatile memory element configured as described above can maintain stable rewriting characteristics even after rewriting 100,000 times or more, for example.

  In addition, since the first current value can be controlled using a field effect transistor as a switch for switching between selection and non-selection of the nonvolatile memory element, a nonvolatile memory element having a simple structure can be realized. Suitable for high-density integration of nonvolatile memory elements.

  The field effect transistor may be an N-type MISFET, and the second variable resistance layer may be in contact with the first electrode.

  According to this aspect, a nonvolatile memory element having excellent rewriting characteristics can be obtained, and the nonvolatile memory element can be integrated at a higher density by using the N-type MISFET.

  The field effect transistor may be a P-type MISFET, and the second variable resistance layer may be in contact with the second electrode.

  According to this aspect, it is possible to obtain a nonvolatile memory element that can easily process the variable resistance element.

  Further, if the field effect transistor is an N-type MISFET and the standard electrode potential of the first electrode is E1, and the standard electrode potential of the second electrode is E2, E1> E2 may be satisfied.

  According to this aspect, a nonvolatile memory element having excellent rewriting characteristics can be obtained, and the nonvolatile memory element can be integrated at a higher density by using the N-type MISFET.

  Further, when the field effect transistor is a P-type MISFET and the standard electrode potential of the first electrode is E1, and the standard electrode potential of the second electrode is E2, E2> E1 may be satisfied.

  According to this aspect, it is possible to obtain a nonvolatile memory element that can easily process the variable resistance element.

In addition, the first metal oxide and the second metal oxide are oxides of the same metal, the composition of the first metal oxide is expressed as MO _x, and the second metal oxide When the composition is expressed as MO _y , y> x may be satisfied.

  According to this aspect, a stable resistance changing operation of the nonvolatile memory element can be realized.

  Further, the first metal oxide and the second metal oxide may be tantalum oxide.

  According to this aspect, a stable resistance changing operation of the nonvolatile memory element can be realized.

  Further, the first metal oxide and the second metal oxide may be hafnium oxide.

  According to this aspect, a stable resistance changing operation of the nonvolatile memory element can be realized.

  Further, the first metal oxide and the second metal oxide may be zirconium oxide.

  According to this aspect, a stable resistance changing operation of the nonvolatile memory element can be realized.

  Further, the first metal oxide and the second metal oxide layer are different metal oxides, and the standard electrode potential of the metal constituting the first metal oxide is EN, If the standard electrode potential of the metal constituting the second metal oxide is EM, EN <EM may be satisfied.

  According to this aspect, compared with the case where the first metal oxide and the second metal oxide are oxides of the same metal, a more stable resistance change operation of the nonvolatile memory element can be realized.

  The first metal oxide may be tantalum oxide, and the second metal oxide may be aluminum oxide.

  According to this aspect, a stable resistance changing operation of the nonvolatile memory element can be realized.

  Further, the first metal oxide may be tantalum oxide, and the second metal oxide may be hafnium oxide.

  According to this aspect, a stable resistance changing operation of the nonvolatile memory element can be realized.

  In addition, the nonvolatile memory element according to one embodiment of the present invention includes a first electrode, a second electrode, and the first metal oxide provided between the first electrode and the second electrode. A first resistance change layer made of a material and a second resistance change layer made of a second metal oxide having a lower oxygen deficiency than the first metal oxide, A resistance change layer whose resistance value reversibly changes according to a voltage pulse applied between the first electrode and the second electrode, and a resistance portion inserted in a path of a current flowing through the resistance change layer The resistance change layer is in a low resistance state by applying an erasing voltage pulse having a first polarity between the first electrode and the second electrode via the resistance portion. The resistance change layer changes between the first electrode and the second electrode via the resistance portion. When a write voltage pulse having a second polarity different from the first polarity is applied, the resistance portion changes from a high resistance state to a low resistance state, and the resistance change layer is applied to the erase voltage pulse by the resistance change layer. When the change in the resistance change layer from the low resistance state to the high resistance state is completed, the resistance change layer completes the change from the high resistance state to the low resistance state by the application of the write voltage pulse. May be suppressed to a value equal to or lower than a second current value flowing through the resistance change layer.

  According to this aspect, in the erasing step, a high voltage can be applied to the nonvolatile memory element, and the current value flowing through the nonvolatile memory element when the erasing step is completed can be limited. Therefore, a more stable resistance changing operation of the nonvolatile memory element can be realized.

  A method for driving a nonvolatile memory element according to one embodiment of the present invention includes a first electrode, a second electrode, a first metal provided between the first electrode and the second electrode. A first variable resistance layer composed of an oxide and a second variable resistance layer composed of a second metal oxide whose oxygen deficiency is smaller than the first metal oxide; A resistance change layer whose resistance value reversibly changes in response to a voltage pulse applied between the first electrode and the second electrode, and a current path flowing through the resistance change layer, A first input / output terminal connected to the first electrode, a second input / output terminal, and a gate terminal for controlling conduction between the first input / output terminal and the second input / output terminal; And in the writing step, the second input / output terminal of the field effect transistor is a source terminal. A non-volatile memory element driving method including the first electrode and the second electrode for changing the resistance change layer from a low resistance state to a high resistance state. An erasing step of applying an erasing voltage pulse of a first polarity between the electrode and the first electrode and the second electrode to change the resistance change layer from a high resistance state to a low resistance state. A write step of applying a write voltage pulse of a second polarity different from the first polarity in between, and a first current value flowing through the variable resistance layer upon completion of the erase step by the field effect transistor, And a control step of suppressing the value to a second current value flowing through the resistance change layer when the writing step is completed.

  According to this aspect, based on the substrate bias effect of the field effect transistor, the first current value that flows through the nonvolatile memory element when the erasing step is completed is changed to the nonvolatile memory element when the writing step is completed. Or less than the second current value flowing through the. As a result, good rewrite characteristics can be maintained even after a large number of rewrite operations are performed in the nonvolatile memory element, so that a stable memory operation by the nonvolatile memory element can be realized.

  Further, the voltage Vw may be applied to the gate terminal of the field effect transistor in the writing step, and the voltage Ve having an absolute value larger than the voltage Vw may be applied to the gate terminal in the erasing step.

  According to this aspect, the resistance of the nonvolatile memory element can be increased more reliably, so that a nonvolatile memory element having excellent rewriting characteristics can be provided.

(Embodiment 1)
[Configuration of variable resistance element]
First, the configuration of the variable resistance element included in the nonvolatile memory device according to Embodiment 1 will be described.

  FIG. 1 is a cross-sectional view showing a configuration of a resistance change element 10 included in the nonvolatile memory element according to this embodiment. As shown in FIG. 1, the resistance change element 10 according to the present exemplary embodiment includes a substrate 1, a first electrode 2 formed on the substrate 1, and a resistor formed on the first electrode 2. A change layer 3 and a second electrode 4 formed on the resistance change layer 3 are provided. The first electrode 2 and the second electrode 4 are electrically connected to the resistance change layer 3.

  The substrate 1 is composed of, for example, a silicon substrate. The first electrode 2 and the second electrode 4 are, for example, Au (gold), Pt (platinum), Ir (iridium), Cu (copper), TiN (titanium nitride), and TaN (tantalum nitride). Or one or more materials.

  The resistance change layer 3 is interposed between the first electrode 2 and the second electrode 4 and reversibly based on an electrical signal applied between the first electrode 2 and the second electrode 4. It is a layer whose resistance value changes. For example, it is a layer that reversibly transitions between a high resistance state and a low resistance state in accordance with the polarity of the voltage applied between the first electrode 2 and the second electrode 4. The resistance change layer 3 is configured by laminating at least two layers of a second resistance change layer 3 b connected to the first electrode 2 and a first resistance change layer 3 a connected to the second electrode 4.

  The first resistance change layer 3a is composed of an oxygen-deficient first metal oxide, and the second resistance change layer 3b is a second metal having a lower degree of oxygen deficiency than the first metal oxide. It is composed of oxide. In the second resistance change layer 3b of the resistance change element 10, a minute local region in which the degree of oxygen deficiency reversibly changes according to the application of the electric pulse is formed. The local region is considered to include a filament composed of oxygen defect sites.

  Oxygen deficiency is an oxide of a metal oxide that has a stoichiometric composition (if there are multiple stoichiometric compositions, the stoichiometric composition having the highest resistance value among them). This refers to the proportion of oxygen that is deficient with respect to the amount of oxygen that is produced. A metal oxide having a stoichiometric composition is more stable and has a higher resistance value than a metal oxide having another composition.

For example, when the metal is tantalum (Ta), the oxide having the stoichiometric composition according to the above definition is Ta ₂ O ₅ , and can be expressed as TaO _2.5 . The oxygen deficiency of TaO _2.5 is 0%, and the oxygen deficiency of TaO _1.5 is oxygen deficiency = (2.5−1.5) /2.5=40%. In addition, the oxygen excess metal oxide has a negative oxygen deficiency. In the present specification, unless otherwise specified, the oxygen deficiency is described as including a positive value, 0, and a negative value.

  An oxide having a low degree of oxygen deficiency has a high resistance value because it is closer to an oxide having a stoichiometric composition, and an oxide having a high degree of oxygen deficiency has a low resistance value because it is closer to the metal constituting the oxide.

The oxygen content is the ratio of oxygen atoms to the total number of atoms. For example, the oxygen content of Ta ₂ O ₅ is the ratio of oxygen atoms to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content greater than 0 and less than 71.4 atm%. For example, when the metal constituting the first metal oxide and the metal constituting the second metal oxide are of the same type, the oxygen content has a corresponding relationship with the degree of oxygen deficiency. That is, when the oxygen content of the second metal oxide is greater than the oxygen content of the first metal oxide, the oxygen deficiency of the second metal oxide is that of the first metal oxide. Less than oxygen deficiency.

When the variable resistance layer 3 is configured using tantalum, when the composition of the first metal oxide that configures the first variable resistance layer 3a is TaO _x , x is 0.8 or more and 1.9 or less. If the composition of the second metal oxide constituting the second resistance change layer 3b is TaO _y and y is 2.1 or more, the resistance value of the resistance change layer 3 is stabilized. Can be changed at high speed. In this case, the thickness of the second resistance change layer 3b may be 1 nm or more and 8 nm or less.

  The metal constituting the resistance change layer 3 may be a metal other than tantalum. As a metal constituting the resistance change layer 3, a transition metal or aluminum (Al) can be used. As the transition metal, tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), nickel (Ni), or the like can be used. Since transition metals can take a plurality of oxidation states, different resistance states can be realized by oxidation-reduction reactions.

For example, in the case of using hafnium oxide, when the composition of the first metal oxide constituting the first resistance change layer 3a is HfO _x , x is 0.9 or more and 1.6 or less, and the first When the composition of the second metal oxide constituting the second resistance change layer 3b is HfO _y and y is larger than the value of x, the resistance value of the resistance change layer 3 is stably increased at high speed. Can be changed. In this case, the film thickness of the second resistance change layer 3b may be 1 nm or more and 5 nm or less.

Further, when zirconium oxide is used, x is 0.9 or more and 1.4 or less when the composition of the first metal oxide constituting the first resistance change layer 3a is ZrO _x , and When the composition of the second metal oxide constituting the second resistance change layer 3b is ZrO _y and y is larger than the value of x, the resistance value of the resistance change layer 3 is stably increased at high speed. Can be changed. In this case, the film thickness of the second resistance change layer 3b may be 1 nm or more and 5 nm or less.

  A different metal may be used for the first metal constituting the first metal oxide and the second metal constituting the second metal oxide. In this case, the second metal oxide may have a lower degree of oxygen deficiency than the first metal oxide, that is, may have a higher resistance. By adopting such a configuration, the voltage applied between the first electrode 2 and the second electrode 4 at the time of resistance change is a second voltage composed of the second metal oxide having a higher resistance. It can be distributed more in the resistance change layer 3b and the oxidation-reduction reaction generated in the second resistance change layer 3b can be more easily caused.

  In addition, when different materials are used for the first metal constituting the first metal oxide and the second metal constituting the second metal oxide, the standard electrode of the second metal is used. The potential may be lower than the standard electrode potential of the first metal. The standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize. Thereby, an oxidation-reduction reaction easily occurs in the second metal oxide having a relatively low standard electrode potential. Note that the resistance change phenomenon is caused by a second resistance change caused by a redox reaction occurring in a minute local region formed in the second resistance change layer 3b having a high resistance to change the filament (conductive path). It is considered that the resistance value (oxygen deficiency) of the layer 3b changes.

For example, by using oxygen-deficient tantalum oxide (TaO _x ) for the first metal oxide and titanium oxide (TiO ₂ ) for the second metal oxide, stable resistance change operation can be achieved. can get. Titanium (standard electrode potential = −1.63 eV) is a material having a lower standard electrode potential than tantalum (standard electrode potential = −0.6 eV). As described above, by using a metal oxide having a standard electrode potential lower than that of the first metal oxide as the second metal oxide, a redox reaction occurs more in the second resistance change layer 3b. It becomes easy.

As another combination, an aluminum oxide (Al ₂ O ₃ ) can be used for the second resistance change layer 3b serving as a high resistance layer. For example, oxygen-deficient tantalum oxide (TaO _x ) may be used for the first metal oxide, and aluminum oxide (Al ₂ O ₃ ) may be used for the second metal oxide.

  As for the resistance change phenomenon in the resistance change layer 3 having the laminated structure, the oxidation-reduction reaction occurs in a minute local region formed in the second resistance change layer 3b having a high resistance in both the high resistance and the low resistance. Thus, it is considered that the resistance value of the second resistance change layer 3b changes as the filament (conductive path) in the local region changes.

  That is, when a positive voltage is applied to the first electrode 2 connected to the second resistance change layer 3b with reference to the second electrode 4, the oxygen ions in the resistance change layer 3 change to the second resistance change. It is drawn toward the layer 3b side. As a result, an oxidation reaction occurs in a minute local region formed in the second resistance change layer 3b, and the degree of oxygen deficiency is reduced. As a result, it is considered that the filaments in the local region are not easily connected and the resistance value is increased.

  Conversely, when a negative voltage is applied to the first electrode 2 connected to the second resistance change layer 3b with reference to the second electrode 4, oxygen ions in the second resistance change layer 3b 1 is pushed to the resistance change layer 3a side. As a result, a reduction reaction occurs in the minute local region formed in the second resistance change layer 3b, and the degree of oxygen deficiency increases. As a result, it is considered that the filaments in the local region are easily connected and the resistance value decreases.

  The first electrode 2 connected to the second resistance change layer 3b made of the second metal oxide having a lower oxygen deficiency is, for example, platinum (Pt), iridium (Ir), palladium ( Pd) or the like, and the metal constituting the second metal oxide and the material constituting the second electrode 4 are made of a material having a higher standard electrode potential.

  Further, the second electrode 4 connected to the first resistance change layer 3a made of the first metal oxide having a larger oxygen deficiency may be, for example, tungsten (W), nickel (Ni), A material having a lower standard electrode potential than tantalum (Ta), titanium (Ti), aluminum (Al), tantalum nitride (TaN), titanium nitride (TiN), or other metal constituting the first metal oxide. It may be configured. The standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize.

That is, the standard electrode potential E2 of the material constituting the second electrode 4, the standard electrode potential EM of the metal constituting the second metal oxide to be the second resistance change layer 3b, and the first metal oxide are constituted. standard electrode potentials EN of the metal, between the standard electrode potential E1 of the material constituting the first electrode, EM _<E1, and may satisfy the E2 <E1 becomes relevant. Furthermore, E1> EM and EN ≧ E2 may be satisfied.

  With the above configuration, a redox reaction occurs selectively in the second metal oxide in the vicinity of the interface between the first electrode 2 and the second resistance change layer 3b, and a stable resistance change phenomenon. Is obtained.

2A, 2B, and 2C, the first resistance change layer 3a is made of tantalum oxide having a composition represented by TaO _1.6 , and the second resistance change layer 3b is made of Ta ₂ O ₅ , The resistance change characteristics when the variable resistance element 10 composed of HfO ₂ and Al ₂ O ₃ is operated under the same conditions are shown. When an oxide of Al or Hf having a standard electrode potential lower than that of Ta is used for the second resistance change layer 3b, the resistance value in the high resistance state is high, and the resistance change phenomenon occurs more stably. I can confirm.

[Method of manufacturing variable resistance element]
Next, an example of a method for manufacturing the variable resistance element 10 will be described.

  First, a film of a material (for example, iridium (Ir)) constituting the first electrode 2 is formed on the substrate 1 by a sputtering method.

  Thereafter, a second metal oxide film constituting the second resistance change layer 3b is formed on the material film. The second metal oxide film may be formed, for example, by sputtering a tantalum oxide target in argon gas or argon gas and oxygen gas. CVD (Chemical Vapor Deposition): chemical vapor deposition ) Method or ALD (Atomic Layer Deposition) method.

  Next, a first metal oxide film constituting the first variable resistance layer 3a is formed on the second metal oxide film. The first metal oxide film may be formed by, for example, a so-called reactive sputtering method in which a Ta target is sputtered in argon gas and oxygen gas. Here, the oxygen deficiency of the first metal oxide may be adjusted by changing a flow rate ratio of oxygen gas to argon gas used for sputtering. The substrate can be formed at room temperature without any particular heating.

  Next, a film of a material (for example, tantalum nitride (TaN)) constituting the second electrode 4 is formed on the first metal oxide film by a sputtering method.

  By patterning the first electrode material film, the second metal oxide film, the first metal oxide film, and the second electrode material film, the first having a desired size and shape respectively. Electrode 2, second variable resistance layer 3 b, first variable resistance layer 3 a, and second electrode 4 are formed.

  The variable resistance element 10 is obtained through the above steps.

  In the example of the nonvolatile memory device described later, the following resistance change element 10 is used.

In the resistance change element 10 of the example, the size of the second electrode 4 and the resistance change layer 3 is 0.5 μm × 0.5 μm (area 0.25 μm ² ). The size of the portion in contact with is also 0.5 μm × 0.5 μm (area 0.25 μm ² ). The thicknesses of the second electrode 4 and the first electrode 2 are both 50 nm.

The composition of the first metal oxide used for the first resistance change layer 3a is TaO _x (x = 1.57), and the composition of the second metal oxide used for the second resistance change layer 3b is TaO _y. (Y = 2.47). The thickness of the resistance change layer 3 is 50 nm, the thickness of the first resistance change layer 3a is 44 nm, and the thickness of the second resistance change layer 3b is 6 nm.

[Characteristics of variable resistance element]
Next, characteristics of the variable resistance element 10 according to the present embodiment configured as described above will be described.

  FIG. 3 is a diagram showing current-voltage characteristics of the variable resistance element 10 included in the nonvolatile memory element 30 according to the present embodiment. The horizontal axis indicates the voltage value of the first electrode 2 with respect to the second electrode 4, and the vertical axis indicates the value of current flowing from the first electrode 2 to the second electrode 4.

  Referring to FIG. 3, when a voltage pulse having a polarity that applies a negative voltage to the first electrode 2 with respect to the second electrode 4 is applied to the resistance change layer 3, the resistance change layer 3 is reduced in resistance. In addition, it can be confirmed that the absolute value of the current increases.

  On the other hand, when a voltage pulse having a polarity for applying a positive voltage to the first electrode 2 with respect to the second electrode 4 is applied to the resistance change layer 3, the resistance change layer 3 increases in resistance, It can be confirmed that the absolute value becomes smaller.

  Such a resistance change phenomenon is presumed to be manifested by the mechanism described above.

[Configuration of Nonvolatile Memory Element]
FIG. 4A is a circuit diagram showing a configuration of a so-called 1T1R nonvolatile memory element 30 including one transistor and one resistance change element according to the present embodiment. The nonvolatile memory element 30 includes a resistance change element 10 and a field effect transistor 20. WL indicates a word line, SL indicates a source line, and BL indicates a bit line. The field effect transistor 20 is a switch that switches between selection and non-selection of the nonvolatile memory element 30, and is an example of a controller for controlling a current value flowing through the nonvolatile memory element 30.

  FIG. 4B is a circuit diagram illustrating a configuration of the variable resistance element 10 included in the nonvolatile memory element 30. FIG. 4C is a circuit diagram illustrating a configuration of the field effect transistor 20 included in the nonvolatile memory element 30. In other words, when the resistance change element 10 shown in FIG. 4B and the field effect transistor 20 shown in FIG. 4C are connected, the nonvolatile memory element 30 shown in FIG. 4A is obtained.

  As shown in FIG. 4B, the resistance change element 10 is a two-terminal structure element having two terminals connected to the second electrode 4 and the first electrode 2, respectively. One terminal of the variable resistance element 10 is connected to one terminal of the field effect transistor 20. In the present specification, of the two terminals of the variable resistance element 10, one terminal connected to the field effect transistor 20 is referred to as a second terminal 12 and the other terminal not connected to the field effect transistor 20. These terminals are referred to as first terminals 11.

  As shown in FIG. 4C, the field effect transistor 20 is an element having at least three terminals of a source terminal, a drain terminal, and a gate terminal. In the present specification, of these three terminals, the terminal connected to the resistance change element 10 is referred to as a first input / output terminal 21, and the other is capable of conducting with the first input / output terminal 21 by transistor operation. These terminals are referred to as second input / output terminals 22. In the transistor operation, a terminal that controls conduction between the first input / output terminal 21 and the second input / output terminal 22 is referred to as a gate terminal 23.

  In the on state, the field effect transistor 20 has one of the first input / output terminal 21 and the second input / output terminal 22 serving as a source terminal and the other serving as a drain terminal. However, as will be described in detail later, which is the source terminal (or drain terminal) is determined by the direction of current flow and the polarity of carriers.

  The field-effect transistor 20 is, for example, a MISFET (metal-insulator-semiconductor field-effect transistor) or a MOSFET (metal-oxide-semiconductor field-effect transistor: Metal that is a kind of MISFET). -Oxide-Semiconductor Field-Effect Transistor).

  Hereinafter, for the sake of simplicity, the field effect transistor 20 may be simply referred to as the transistor 20. Further, the field effect transistor 20 may be referred to as a MISFET 20, an N-type MISFET 20, or a P-type MISFET 20 according to a specific example in the present embodiment.

  4B and 4C, the variable resistance element 10 and the field effect transistor 20 have been described separately and independently, but this is an expression on a circuit diagram for simple description. Therefore, for example, the resistance change element 10 and the field effect transistor 20 may be integrated as a device.

  For example, the first input / output terminal 21 of the field effect transistor 20 may also serve as the first electrode 2 of the resistance change element 10. In addition, the second terminal 12 of the resistance change element 10 and the first input / output terminal 21 of the field effect transistor 20 may be electrically connected. For example, another conductive member may be interposed between the variable resistance element 10 and the field effect transistor 20.

  FIG. 5 is a cross-sectional view showing an example of the configuration of the nonvolatile memory element 30 according to the present embodiment. The nonvolatile memory element 30 includes a resistance change element 10 and a field effect transistor 20. Note that FIG. 5 shows a case where the field effect transistor 20 is an N-type MISFET as an example.

  Further, when the field effect transistor 20 is an N-type MISFET, the majority carriers are electrons. On the other hand, when the field effect transistor 20 is a P-type MISFET, the majority carriers are holes.

  In general, since the mobility of electrons is larger than the mobility of holes, when the MISFET 20 having the same gate insulating film 26 structure (material and film thickness) and the same size is formed, the N-type MISFET is more P Current drive capability is larger than type MISFET. Therefore, when manufacturing the MISFET 20 having the same current drive capability, the N-type MISFET can be made smaller in size, and is suitable for integrating the nonvolatile memory elements 30 at a high density.

  Similar to the variable resistance element 10 shown in FIG. 1, the variable resistance element 10 includes the first electrode 2, the variable resistance layer 3, and the second electrode 4, and the variable resistance layer 3 includes the first variable resistance element 3. It has a resistance change layer 3a and a second resistance change layer 3b. Therefore, when a voltage pulse having a polarity that applies a negative voltage to the second electrode 4 with respect to the first electrode 2 is applied to the resistance change layer 3, the resistance change layer 3 increases in resistance. On the other hand, when a voltage pulse having a polarity that applies a positive voltage to the second electrode 4 with respect to the first electrode 2 is applied to the resistance change layer 3, the resistance change layer 3 is reduced in resistance.

  The N-type MISFET 20 includes a semiconductor substrate 24, a first diffusion layer 25a and a second diffusion layer 25b disposed on the semiconductor substrate 24, and a first diffusion layer 25a and a second diffusion layer on the semiconductor substrate 24. The gate insulating film 26 is disposed so as to straddle 25b, and the gate electrode 27 is disposed on the gate insulating film 26. When the gate insulating film 26 is an oxide film, the N-type MISFET 20 is also called an N-type MOSFET.

  The MISFET 20 can be formed by various known methods. An interlayer insulating layer 28 is formed on the N-type MISFET 20, and penetrates through the interlayer insulating layer 28 to connect the first electrode 2 of the resistance change element 10 and the first diffusion layer 25 a of the MISFET 20. Conductive vias 29 are formed.

  In the N-type MISFET 20, the semiconductor substrate 24 and the first diffusion layer 25a and the second diffusion layer 25b are of the opposite conductivity type. When the semiconductor substrate 24 is P-type, the first diffusion layer 25a and the second diffusion layer 25b are N-type. In this case, the MISFET 20 is an N-type MISFET. On the contrary, when the semiconductor substrate 24 is N-type, the first diffusion layer 25a and the second diffusion layer 25b are P-type. In this case, the MISFET 20 is a P-type MISFET.

  FIG. 4A and FIG. 5 show the connection relationship when the MISFET 20 is an N-type MISFET 20. As will be described later, when the MISFET 20 is a P-type MISFET 20, the vertical arrangement of the resistance change layer 3 is opposite to the vertical arrangement of the resistance change layer 3 when the MISFET 20 is an N-type MISFET 20. Connected.

  The cross-sectional structure of the nonvolatile memory element 30 shown in FIG. 5 is an example, and the structure of the variable resistance element 10, the structure of the field effect transistor 20, and the variable resistance element in the nonvolatile memory element 30 according to the present embodiment. The structure of the connection portion between the field effect transistor 10 and the field effect transistor is not limited to the example shown in FIG. In the following, for the sake of simplicity of explanation, the field-effect transistor 20 shown in FIGS. 4A and 5 will be described as an N-type MISFET 20 unless otherwise specified.

  In the nonvolatile memory element 30 shown in FIG. 5, it is desirable that E1> E2 is satisfied, where E1 is the standard electrode potential of the first electrode 2 and E2 is the standard electrode potential of the second electrode 4. By satisfying the standard electrode potential requirement as described above, a resistance change phenomenon appears stably in the vicinity of the interface between the first electrode 2 and the second resistance change layer 3b.

[Driving Method of Nonvolatile Memory Element]
Next, a method for driving the nonvolatile memory element 30 configured as described above will be described. Hereinafter, a case where the resistance value of the variable resistance element 10 is a predetermined high value (for example, 500000Ω) is referred to as a high resistance state, and a case where the resistance value is a predetermined low value (for example, 10,000Ω) is referred to as a low resistance state. . In the present specification, the change of the resistance change element 10 (or the resistance change layer 3) from the high resistance state to the low resistance state is referred to as low resistance, and the change from the low resistance state to the high resistance state. Sometimes called high resistance.

  In the present embodiment, the resistance state of the resistance change layer 3 can be changed as follows by applying a voltage to the nonvolatile memory element 30 using a power supply or the like.

  First, a voltage pulse having a first polarity, a voltage value of VLR, and a pulse width of PWLR is applied between the first terminal 11 of the resistance change element 10 and the second input / output terminal 22 of the transistor 20 to thereby generate resistance. The change layer 3 is changed from the high resistance state to the low resistance state. Hereinafter, this is referred to as a writing step. In the present specification, the first polarity means the polarity of a voltage pulse required to change the resistance change layer 3 from the high resistance state to the low resistance state.

  For example, in the connection relationship shown in FIGS. 4A and 5, the potential of the second electrode 4 in the resistance change element 10 is relative to the potential of the second diffusion layer 25 b of the N-type MISFET 20. The polarity of the voltage that becomes higher is the first polarity. At this time, the voltage applied to the resistance change element 10 is a voltage having a polarity that applies a negative voltage to the first electrode 2 with respect to the second electrode 4. Change to resistance state.

  Next, a voltage pulse having a second polarity different from the first polarity and a voltage value of VHR and a pulse width of PWHR is applied to the first terminal 11 of the resistance change element 10 and the second input / output terminal 22 of the transistor 20. Apply between. Thereby, the resistance change layer 3 is changed from the low resistance state to the high resistance state. Hereinafter, this is referred to as an erasing step. In the present specification, the second polarity means the polarity of a voltage pulse required to change the resistance change layer 3 from the low resistance state to the high resistance state.

  For example, in the connection relationship shown in FIGS. 4A and 5, the potential of the second electrode 4 in the resistance change element 10 is relative to the potential of the second diffusion layer 25 b of the N-type MISFET 20. The polarity of the voltage that becomes low is the second polarity. At this time, since the voltage applied to the resistance change element 10 is a voltage having a polarity that gives a positive voltage to the first electrode 2 with respect to the second electrode 4, the resistance change layer 3 is changed from a low resistance state to a high voltage. Change to resistance state.

  By repeating the above writing step and erasing step, the nonvolatile memory element 30 operates. The pulse widths PWLR and PWHR are each 50 ns, for example.

  Whether the resistance change layer 3 is in a low resistance state or a high resistance state is determined by applying a voltage pulse for reading with a predetermined value (hereinafter referred to as a reading voltage pulse). Specifically, by applying a read voltage pulse between the first terminal 11 of the resistance change element 10 and the second input / output terminal 22 of the transistor 20, the current flowing through the resistance change layer 3 ( Hereinafter, whether the resistance change element 10 is in the high resistance state or the low resistance state is determined according to the current value of the read current).

  The magnitude (absolute value) of the voltage value applied to the resistance change element 10 by the read voltage pulse is smaller than the threshold voltage that causes resistance change in the resistance change layer 3. Therefore, the read voltage pulse does not affect the resistance state of the resistance change element 10. For example, when the resistance change layer 3 is in a low resistance state, even if a read voltage pulse having the first polarity is applied between the resistance change element 10 and the transistor 20, the resistance state of the resistance change layer 3 does not change. , Maintained in a low resistance state. Similarly, when the resistance change layer 3 is in a high resistance state, even if a read voltage pulse having the second polarity is applied between the resistance change element 10 and the transistor 20, the resistance state of the resistance change layer 3 changes. Without being maintained in a high resistance state.

  When the above driving method is executed on the nonvolatile memory element 30 according to the present embodiment, the nonvolatile memory element 30 can be used as one memory cell. For example, a case where the resistance change layer 3 is in a low resistance state is associated with “1”, and a case where the resistance change layer 3 is in a high resistance state is associated with “0”, thereby forming a 1-bit memory cell.

[Non-volatile memory element connection and substrate bias effect]
The nonvolatile memory element 30 according to the present embodiment is connected so that the second input / output terminal 22 becomes a source terminal in the writing step. In other words, in the writing step, the terminal on the side connected to the resistance change element 10 among the terminals of the field effect transistor 20 is the drain terminal.

  In this specification, the “source” means a majority carrier supply source in the field effect transistor 20. On the other hand, the “drain” means an outlet for majority carriers in the field effect transistor 20. When one of the first input / output terminal 21 and the second input / output terminal 22 is a source terminal, the other is a drain terminal. Similarly, when one of the first diffusion layer 25a and the second diffusion layer 25b is a source region, the other is a drain region. When the field effect transistor 20 is N-type, the majority carriers are electrons. On the other hand, when the field effect transistor 20 is P-type, the majority carriers are holes.

  When the current flows in both directions like the field effect transistor 20 according to the present embodiment, the source and the drain are switched depending on the direction in which the current flows. In the present embodiment, since the polarity of the voltage applied to the nonvolatile memory element 30 is opposite in the writing step and the erasing step, the source and the drain are reversed accordingly. That is, the source and drain in the writing step become the drain and source in the erasing step, respectively.

  When the field effect transistor 20 is an N-type MISFET 20, when the on-current flows from the first input / output terminal 21 to the second input / output terminal 22, the first input / output terminal 21 is a drain terminal, The input / output terminal 22 is a source terminal. On the other hand, when the on-current flows from the second input / output terminal 22 to the first input / output terminal 21, the first input / output terminal 21 is a source terminal, and the second input / output terminal 22 is a drain terminal.

  When the field effect transistor 20 is a P-type MISFET 20, when an on-current flows from the first input / output terminal 21 to the second input / output terminal 22, the first input / output terminal 21 is a source terminal, The input / output terminal 22 is a drain terminal. On the other hand, when the on-current flows from the second input / output terminal 22 to the first input / output terminal 21, the first input / output terminal 21 is a drain terminal, and the second input / output terminal 22 is a source terminal.

  When the field effect transistor 20 is the N-type MISFET 20, the write voltage pulse applied to the nonvolatile memory element 30 in FIGS. 4A and 5 in the write step is the second electrode in the resistance change element 10 as described above. 4 (potential of the first terminal 11) is a voltage pulse relatively higher than the potential of the second diffusion layer 25b of the N-type MISFET 20 (potential of the second input / output terminal 22). At this time, current flows in the order from the first terminal 11 to the second terminal 12, the first input / output terminal 21, and the second input / output terminal 22. That is, in the writing step, the second input / output terminal 22 of the N-type MISFET 20 becomes the source terminal.

  Considering the same, the erase voltage pulse applied to the nonvolatile memory element 30 in FIGS. 4A and 5 in the erase step has the opposite polarity to that in the write step. 1 input / output terminal 21 becomes a source terminal.

  When the field effect transistor 20 is a P-type MISFET 20, the upper and lower arrangements of the resistance change layer 3 are opposite to those when the field effect transistor 20 is a P-type MISFET 20, as will be described later. Therefore, in the write step, the write voltage pulse applied to the nonvolatile memory element 30 is such that the potential of the second electrode 4 in the resistance change element 10 (the potential of the first terminal 11) is the second potential of the P-type MISFET 20. The voltage pulse is relatively low with respect to the potential of the diffusion layer 25b (the potential of the second input / output terminal 22). At this time, the current flows in the order from the second input / output terminal 22 to the first input / output terminal 21, the second terminal 12, and the first terminal 11. At this time, the majority carriers flowing through the P-type MISFET 20 are holes. Therefore, in the writing step, the second input / output terminal 22 of the P-type MISFET 20 becomes the source terminal.

  Considering the same, the erase voltage pulse applied to the nonvolatile memory element 30 in the erase step has a voltage polarity opposite to that in the write step, and therefore the first input / output terminal 21 of the P-type MISFET 20. Becomes the source terminal.

  Hereinafter, the relationship between the connection relationship of the nonvolatile memory element 30 of this embodiment and the substrate bias effect (body effect) will be described using the nonvolatile memory element 30 of FIGS. 4A and 5. The influence of the substrate bias effect described below will be described by taking the case where the field effect transistor 20 is an N-type MISFET 20 as an example, but is not limited to the case where the field effect transistor 20 is an N-type MISFET 20 as will be described later.

[Driving Method of Nonvolatile Memory Element in Writing Step]
In the write step, the write voltage applies a relatively high potential to the first terminal 11 of the variable resistance element 10 and a relatively low potential to the second input / output terminal 22 of the N-type MISFET 20. At this time, the source potential of the N-type MISFET 20 (the potential of the second input / output terminal 22) is not affected by the voltage drop due to the resistance change element 10, and is determined by the potential applied to the second input / output terminal 22.

  This is because the source terminal (second input / output terminal 22) of the N-type MISFET 20 is one end of the nonvolatile memory element 30. For example, the source potential of the N-type MISFET 20 (the potential of the second input / output terminal 22) is maintained substantially the same as the potential of the semiconductor substrate 24. Therefore, the influence of the substrate bias effect generated in the N-type MISFET 20 is small, and the on-current value of the N-type MISFET 20 can be controlled.

  FIG. 6 schematically shows the load curve of the N-type MISFET 20 and the current-voltage characteristics of the resistance change element 10 in the write step. In the writing step, the N-type MISFET 20 functions as a current limiting element as shown in FIG. In other words, the N-type MISFET 20 can be operated in the saturation region by connecting the resistance change element 10 and the N-type MISFET 20 so that the second input / output terminal 22 becomes the source terminal in the writing step.

  As described above, the stable storage operation of the nonvolatile memory element 30 can be realized by operating the N-type MISFET 20 in the saturation region in the writing step.

  FIG. 7 shows, as an example of the nonvolatile memory element 30, the voltage applied to the gate terminal 23 of the N-type MISFET 20 in the write step and the standard deviation of the read current value when the resistance change element 10 is resistance-changed 100 times. Indicates. The current flowing through the resistance change element 10 in the writing step is controlled by the voltage applied to the gate terminal 23 of the N-type MISFET 20.

  As a reference example for comparison, the resistance change element 10 and the N-type MISFET 20 are connected so that the first input / output terminal becomes the source terminal in the writing step (that is, the nonvolatile memory element 30 of the present embodiment). Indicates a standard deviation between the current value flowing through the resistance change element 10 and the read current value of the resistance change element 10 of the nonvolatile memory element (the connection between the resistance change element and the MISFET is different).

  As is clear from FIG. 7, in the example using the nonvolatile memory element 30 in which the writing step was performed using the second input / output terminal 22 as the source terminal, the standard deviation value of the read current variation was small compared to the reference example, Variation is small. Therefore, according to the present embodiment, the nonvolatile memory element 30 having excellent rewriting characteristics can be obtained.

[Driving Method of Nonvolatile Memory Element in Erase Step]
On the other hand, in the erasing step, the erasing voltage gives a relatively low potential to the first terminal 11 of the variable resistance element 10 and gives a relatively high potential to the second input / output terminal 22 of the N-type MISFET 20. At this time, the absolute value of the source potential of the N-type MISFET 20 (the potential of the first input / output terminal 21) is relatively higher than the potential of the semiconductor substrate 24. Therefore, the influence of the substrate bias effect is increased, and the load curve of the N-type MISFET 20 is as schematically shown in FIG. In other words, in the erase step, the N-type MISFET 20 operates with a source follower.

  Further, because of the substrate bias effect, the voltage applied between the first terminal 11 and the second input / output terminal 22 is smaller than the voltage applied to the gate terminal 23.

  In the erasing step, it is desirable to apply as high a voltage as possible to the variable resistance element 10. As shown in FIG. 9, the resistance value of the variable resistance element 10 in the high resistance state increases as the voltage applied between the first terminal 11 and the second input / output terminal 22 increases. In FIG. 9, Vth is a threshold voltage (that is, a point indicated by C in FIG. 3) at which the resistance increase starts. Therefore, by applying a voltage higher than the threshold voltage at which the high resistance is started, the difference in resistance value between the high resistance state and the low resistance state of the resistance change element 10 is further expanded, and the nonvolatile memory having good rewriting characteristics. An element is obtained.

  For the above reason, in the present embodiment, the voltage applied to the nonvolatile memory element 30 during the erasing step is set to be higher than the high resistance start voltage.

  By the way, the voltage-current characteristic of the variable resistance element 10 in the high resistance state exhibits nonlinearity as shown in FIG. Therefore, in the erasing step, the current flowing through the resistance change element 10 increases exponentially as the voltage applied to the resistance change element 10 increases.

  As a result of intensive studies by the present inventors, the current value flowing through the resistance change element 10 at the completion of the erasing step is made smaller than the current value flowing through the resistance change element 10 at the completion of the write step. It has been found to improve reliability. Here, the current flowing through the resistance change element 10 upon completion of the erasing step is a current value that flows when the resistance change of the resistance change element 10 is completed, and is a current value at a point indicated by A in FIG. . Similarly, the current that flows when the write step is completed is a current value that flows when the resistance reduction is completed, and is a current value at a point indicated by B in FIG.

  FIG. 11 shows the standard deviation of the read current value in the low resistance state after the resistance change element 10 is rewritten 1000 times and 100,000 times. In FIG. 11, the horizontal axis represents the current value flowing through the resistance change element 10 in the erasing step when the current value flowing through the resistance change element 10 in the writing step is 1. That is, when the value on the horizontal axis is larger than 1, it means that the current value that flows when the erase step is completed is larger than the current value that flows when the write step is completed. The vertical axis represents the standard deviation of the read current value in the low resistance state.

  As is clear from FIG. 11, when the current in the erasing step is smaller than the current flowing in the writing step, the standard deviation of the read current value in the low resistance state hardly increases even after rewriting 100,000 times. On the other hand, when the current in the erasing step is larger than the current flowing in the writing step, the standard deviation of the read current value in the low resistance state after rewriting 100,000 times greatly increases.

  The reason for this is considered as follows. When the resistance change element 10 is increased in resistance in the erasing step, the ratio of the voltage distributed to the resistance change element 10 among the voltages applied between the first terminal 11 and the second input / output terminal 22 increases. In addition, when the current value flowing through the resistance change element 10 at the completion of the erase step becomes larger than the current value flowing at the completion of the write step, the voltage and current applied to the resistance change element 10 at the erase step are extremely large. Become. That is, the energy given to the resistance change element 10 becomes maximum during the erasing step. As a result, a large Joule heat is generated in the filament in the above-mentioned local region, and the filament where the resistance change appears is likely to deteriorate.

  Therefore, in order to obtain a nonvolatile memory element having excellent rewriting characteristics, it is necessary to control the current value flowing when the erase step is completed to be lower than the current value flowing when the write step is completed.

[Erase step current suppression by field effect transistor as controller]
In the nonvolatile memory element 30 in the present embodiment, the current that flows when the erase step is completed can be suppressed by using the N-type MISFET 20 as a controller.

  FIG. 12 is a diagram illustrating, as an example, a load curve of the N-type MISFET 20 when the voltage VG applied to the gate terminal 23 is 3.3 V and the width of the diffusion layer is 1.0 μm and 1.5 μm, respectively. FIG. 12 shows the current-voltage characteristics of the variable resistance element 10 shown in FIG. 3 together with the load curve. The load curve of the N-type MISFET 20 was calculated using SPICE simulation. The current that flows when the erase step is completed is limited at the intersection of the load curve and the current-voltage characteristics of the resistance change element 10. As shown in FIG. 12, by adjusting the width of the diffusion layer, the value of the current flowing through the resistance change element 10 when the erase step is completed can be controlled.

  Also, the load curve of the N-type MISFET 20 can be controlled by changing the voltage VG applied to the gate terminal 23.

  FIG. 13 is a diagram illustrating, as an example, load curves of the N-type MISFET 20 when the voltages VG are 3.3 V and 3.0 V, respectively. As shown in FIG. 13, by changing the voltage VG applied to the gate terminal 23, the value of the current flowing through the resistance change element 10 after the erase step is completed can be controlled. Further, the load curve of the N-type MISFET 20 does not intersect with the starting point of increasing resistance (the point indicated by C in FIG. 12).

  As described above, by adjusting the width of the diffusion layer of the N-type MISFET 20 serving as the controller and the voltage VG applied to the gate terminal 23, the value of the current flowing through the resistance change element 10 upon completion of the erasing step is completed. It is possible to control to a desired value smaller than the current value at the time.

[Control of gate voltage of field effect transistor]
In order to stably drive the nonvolatile memory element, Vw> Ve may be satisfied, where Vw is a voltage applied to the gate terminal 23 in the erase step and Ve is a voltage applied to the gate terminal 23 in the write step. Here, Vw and Ve are voltages based on the well (not shown) of the N-type MISFET. The effect when Vw> Ve is described below.

  FIG. 14A shows current-voltage characteristics of the variable resistance element 10 (that is, the current-voltage characteristics shown in FIG. 3) and load curves in the erase step and the write step of the N-type MISFET 20 when Vw = Ve. Show. The starting point for increasing the resistance of the variable resistance element 10 indicated by an arrow in FIG. 14A is on the higher voltage side than the load curve of the N-type MISFET. In this case, in the erasing step, the voltage applied to the variable resistance element 10 is limited by the N-type MISFET 20 before reaching the high resistance start, and there is a concern that the variable resistance element 10 will not increase in resistance. . That is, in the erasing step, it is desirable that the starting point for increasing the resistance is located on the lower voltage side than the load curve of the N-type MISFET 20.

  FIG. 14B shows load curves in the erase step and the write step of the N-type MISFET 20 when Vw = Ve + 0.3V. By setting Vw> Ve, the starting point for increasing the resistance is located on the lower voltage side than the load curve of the N-type MISFET. Thus, by controlling the voltage applied to the gate terminal 23 during the erasing step, the resistance change element can be reliably increased in resistance.

  This driving method is the same when the field effect transistor 20 is a P-type MISFET 20. When the field effect transistor 20 is a P-type MISFET 20, a negative voltage is applied to the gate terminal 23 with reference to the well of the P-type MISFET 20. If the absolute values of the voltages applied to the gate terminal 23 in the writing step and the erasing step are | Ve | and | Vw |, respectively, by setting | Vw |> | Ve |, the resistance change element is reliably increased in resistance. be able to.

[Other controller configuration examples]
In the above description, the N-type MISFET 20 is used as a controller. However, the present invention is not limited to this. As the controller, a fixed resistor connected in series to the variable resistance element 10 may be used.

  FIG. 15 shows a load curve of the load resistance when a fixed resistance of 5000Ω or 1000Ω as a controller is connected in series with the variable resistance element 10. The resistance value of the fixed resistor may be smaller than the resistance value that the variable resistance element 10 can take in the low resistance state.

  As shown in FIG. 15, the value of the current flowing through the variable resistance element 10 when the erase step is completed can also be controlled by the fixed resistance connected in series with the variable resistance element 10. Thus, by using a fixed resistor as a controller, a larger voltage can be applied to the resistance change element 10 than when the N-type MISFET 20 is used as a controller, and when the erase step is completed, the resistance change element 10 can be controlled. Therefore, the nonvolatile memory element 30 having excellent rewriting characteristics and excellent reliability can be obtained.

  Further, the fixed resistance as the resistance portion may be inside the resistance change element 10. For example, the first resistance change layer 3a can be used as a fixed resistance. By arranging the fixed resistor in the variable resistance element 10 in this way, the manufacturing process is simplified, and the manufacturing cost can be reduced.

  Further, the resistance unit may be a variable resistor connected in series to the nonvolatile memory element 30 shown in FIG. For example, a field effect transistor can be used as the variable resistor. By controlling the current value at the time of completion of the erasing step by the resistance of the field effect transistor, a high voltage can be applied to the resistance change element 10, and thus the nonvolatile memory element 30 having excellent reliability can be obtained.

[Variation of configuration of variable resistance element]
In the variable resistance element 10 shown in FIG. 1, the first variable resistance layer 3a is disposed on the second variable resistance layer 3b.

  FIG. 16 shows a variable resistance element 40 which is a modification of the variable resistance element 10. The variable resistance element 40 differs from the variable resistance element 10 in the arrangement of the second variable resistance layer 3b and the first variable resistance layer 3a.

[Variation of non-volatile memory element]
As described above, an example in which an N-type MISFET is used as the field effect transistor 20 has been described, but the field effect transistor 20 is not limited thereto. Of course, a P-type MISFET 20 may be used instead of the N-type MISFET 20.

  FIG. 17 is a cross-sectional view showing an example of the configuration of the nonvolatile memory element 31 using the P-type MISFET 20. The difference from the nonvolatile memory element 30 using the N-type MISFET 20 shown in FIG. 5 is that a variable resistance element 40 having a different arrangement of the second variable resistance layer 3b and the first variable resistance layer 3a is used. It is in. The second electrode 4 in contact with the second resistance change layer 3b preferably has a high standard electrode potential, for example, Pt (platinum) or Ir (iridium). Such a noble metal material is generally difficult to process, but can be relatively easily processed by disposing it above the resistance change element 40 like the nonvolatile memory element 31.

  In the nonvolatile memory element 31 shown in FIG. 17, it is preferable that E2> E1 is satisfied, where E1 is the standard electrode potential of the first electrode 2 and E2 is the standard electrode potential of the second electrode 4. By satisfying the standard electrode potential requirement in this manner, the resistance change phenomenon appears stably in the vicinity of the interface between the second electrode 4 and the second resistance change layer 3b.

(Embodiment 2)
The second embodiment is a one-transistor / one resistance change element type (1T1R type) nonvolatile memory device including the resistance change element 10 described in the first embodiment. The configuration and operation of this nonvolatile memory device will be described below.

[Configuration of non-volatile storage device]
FIG. 18 is a block diagram showing an example of the configuration of the nonvolatile memory device 100 according to Embodiment 2 of the present invention. As shown by a broken line in FIG. 18, the nonvolatile memory device 100 includes a memory cell array 101 and a voltage application unit 102. In the memory cell array 101, a plurality of the nonvolatile memory elements shown in Embodiment Mode 1 are arranged in an array, and each nonvolatile memory element constitutes a memory cell. The voltage application unit 102 includes an address input circuit 103, a control circuit 104, a write power supply unit 105, and a memory drive circuit 106.

  As another view, if a region including the memory cell array 101 and the memory driving circuit 106 is defined as a memory main body 107 as shown by a one-dot chain line in FIG. 18, the nonvolatile memory device 100 includes the memory main body 107, the address An input circuit 103, a control circuit 104, and a writing power supply unit 105 are provided.

  The memory drive circuit 106 selects a predetermined memory cell of the memory cell array 101 based on an address signal and a data signal input from the external circuit to the address input circuit 103 and the data input / output circuit 110, and from the write power supply unit 105 and the like. Predetermined data is programmed in the selected memory cell using the input write voltage and erase voltage, or read data is applied to the selected memory to read information in the memory cell, and the read data is externally transmitted from the data input / output circuit 110. Output to. The memory drive circuit 106 includes, for example, a row selection circuit 108, a row driver 109, a data input / output circuit 110, a write circuit 111, a column selection circuit 112, a column driver 113, and a read circuit 114. The write power supply unit 105 sets a write voltage pulse and an erase voltage pulse. The write power supply unit 105 includes, for example, a pulse width setting circuit 115, an LR power supply 116, and an HR power supply 117.

  As shown in FIG. 18, the memory cell array 101 includes two word lines W1 and W2 extending in the horizontal direction, two bit lines B1 and B2 extending in the vertical direction across the word lines W1 and W2, A matrix shape corresponding to each intersection of two source lines S1 and S2 extending in the vertical direction provided in one-to-one correspondence with the bit lines B1 and B2, and the word lines W1 and W2 and the bit lines B1 and B2. Are provided with four memory cells MC111, MC112, MC121, and MC122.

  Note that the number or number of these components is not limited to the above. For example, although four memory cells are described in the memory cell array 101 of FIG. 18 as described above, this is an example, and a configuration including five or more memory cells may be employed. In the following, a case where there are four memory cells will be described for the sake of simplicity.

  Memory cells MC111, MC112, MC121, and MC122 described above include resistance change element 10 in the first embodiment. The configuration of the memory cell array 101 will be further described with reference to FIG. 4A. A memory cell MC111 is provided between the bit line B1 and the source line S1, and the memory cell MC111 is formed of a nonvolatile memory element in which a transistor T111 and a resistance change element R111 are connected in series. More specifically, the transistor T111 is connected to the bit line B1 and the resistance change element R111 between the bit line B1 and the resistance change element R111. The resistance change element R111 is connected to the transistor T111 and the source line S1. In the meantime, the transistor T111 and the source line S1 are connected. The gate terminal of the transistor T111 is connected to the word line W1.

  The connection states of the transistors T112, T121, and T122 and the resistance change elements R112, R121, and R122 that constitute the other three memory cells MC112, MC121, and MC122 are the same as the transistor T111 and the resistance change element that constitute the memory cell MC111. Since it is the same as that of R111, description is abbreviate | omitted.

  With the above configuration, when a predetermined voltage (gate voltage) is supplied to the gates of the transistors T111, T112, T121, and T122 via the word lines W1 and W2, the drains of the transistors T111, T112, T121, and T122 are provided. And conduction between the sources.

  The address input circuit 103 receives an address signal from an external device (not shown), outputs a row address signal to the row selection circuit 108 based on the address signal, and outputs a column address signal to the column selection circuit 112. Here, the address signal is a signal indicating the address of the selected memory cell among the memory cells MC111, MC112, MC121, and MC122. The row address signal is a signal indicating a row address among the addresses indicated by the address signal, and the column address signal is also a signal indicating a column address.

  The row selection circuit 108 receives the row address signal supplied from the address input circuit 103, and determines a word line (for example, word line W1) of a row to be selected based on the row address signal. Specifically, the row driver 109 is controlled to apply a predetermined voltage (gate voltage) for turning on the transistors (transistors T111 and T112). On the other hand, the row driver 109 applies a predetermined voltage for turning off the transistors constituting the memory cell to the word line (for example, the word line W2) of the non-selected row, or does not apply the voltage. To control. The row driver 109 includes a word line driver WLD connected to each word line, and a voltage is applied to the word line by the word line driver WLD.

  The column selection circuit 112 receives the column address signal supplied from the address input circuit 103, and determines the source line (for example, source line S1) and bit line (for example, bit line B1) of the column to be selected based on the column address signal. To do. Specifically, the column driver 113 is controlled so that a writing voltage, an erasing voltage, or a reading voltage is applied between the source line and the bit line, and a transistor connected between the source line and the bit line ( For example, a predetermined voltage (for example, source voltage / drain voltage) is applied to the transistors T111 and T121). On the other hand, the column driver 113 is controlled to apply a non-selection voltage to the source line (for example, the source line S2) and the non-selected bit line (for example, the bit line B2) of the non-selected column. The column driver 113 includes a source line driver SLD connected to each source line, and a voltage is applied to the source line by the source line driver SLD.

  As described above, the memory cell (for example, the memory cell MC111) connected to the position where the selected row and column intersect is selected.

  The read circuit 114 determines whether the selected memory cell is in a low resistance state or a high resistance state, outputs this as a logical result, and determines the state of data stored in the memory cell. . The output data obtained here is output to an external device via the data input / output circuit 110.

  The write circuit 111 applies a write voltage corresponding to the input data input from the external device to the source line and the bit line selected by the column selection circuit 112 via the data input / output circuit 110.

  The control circuit 104 selects one of a write mode (corresponding to the above “write step” and “erase step”) and a read mode in accordance with a control signal received from the external device or the read circuit 114. select. Specifically, the control circuit 104 controls the write power supply unit 105 and the write circuit 111 so that data is written to the selected memory cell. Here, the control circuit 104 supplies a voltage / pulse width setting signal indicating the voltage level of the voltage pulse at the time of writing to the power supply unit 105 for writing.

  In the write mode, the control circuit 104 outputs a control signal instructing “write voltage pulse application” to the write circuit 111 and the column driver 113 in accordance with the input data received from the external circuit.

  In the read mode, the control circuit 104 outputs a control signal instructing “application of read voltage pulse” to the column driver 113. In this read mode, the control circuit 104 further receives a signal indicating the value of the current flowing through the source lines S1 and S2 from the column driver 113. This current value is measured by a sense amplifier or the like (not shown). The control circuit 104 converts the received signal into output data indicating a bit value and outputs it to an external device. This output data corresponds to the value of the write voltage pulse applied to the selected / unselected source line.

[Operation of non-volatile storage device]
As described above, in the nonvolatile memory device of this embodiment, the “write step” and “erase step” described in the first embodiment are executed in the write mode. The voltage value VLR of the write voltage pulse applied to each memory cell in the “write step” and the voltage value VHR of the erase voltage pulse similarly applied in the “erase step” are | VLR |> | VHR | Controlled to meet. Thereby, the non-volatile storage device 100 can realize good endurance characteristics.

[Other configuration of non-volatile storage device]
FIG. 19 is a block diagram showing a modified example of the configuration of the nonvolatile memory device according to Embodiment 2 of the present invention. The nonvolatile storage device 200 of FIG. 19 is partially different from the nonvolatile storage device 100 described above in the structure of the memory main body 207. Specifically, the configuration of the memory cell array 201 is different, and accordingly, the voltage application unit 202 including the memory drive circuit 206 is different. Note that portions having the same configuration as the nonvolatile storage device 100 are denoted by the same reference numerals, and description thereof is omitted.

  Note that twelve memory cells are described in the memory cell array 201 of FIG. 18, but this is an example, and a configuration including other numbers of memory cells may be employed. In the following, a case where there are 12 memory cells will be described for the sake of simplicity.

  In the memory cell array 201 of the nonvolatile memory device 200, adjacent two rows of memory cells are connected to a common source line extending in the horizontal direction. For example, the memory cell MC211 and the memory cell MC221 adjacent to the memory cell MC211 are connected to the common source line S1. Further, the source driver circuit SLD is arranged on the row driver 209 side.

  The row selection circuit 108 receives the row address signal supplied from the address input circuit 103, and determines a word line (for example, word line W1) and a source line (for example, source line S1) of a row to be selected based on the row address signal. To do. Specifically, a predetermined voltage (gate voltage) for turning on the transistors (transistors T211, T212, T213) is applied to a word line (for example, the word line W1), and a write voltage and an erase voltage are applied. The row driver 209 is controlled so that a voltage or a reading voltage is applied to the source line (for example, S1). On the other hand, a predetermined voltage for turning off the transistors constituting the memory cell is applied to the word lines (for example, word lines W2, W3, W4) of the non-selected rows, or no voltage is applied. The row driver 209 is controlled. Further, the row driver 209 is controlled so that a non-selection voltage is applied to the source lines (for example, the source lines S1 and S2) of the non-selected rows.

  The column selection circuit 112 receives the column address signal supplied from the address input circuit 103, and selects a bit line of a column to be selected based on the column address signal. Specifically, a write voltage, an erase voltage, or a read voltage is applied to a bit line (for example, bit line B1) in a selected column, and a non-selected bit line (for example, bit lines B2 and B3) is applied. Apply a non-selection voltage.

  As described above, the memory cell (for example, the memory cell MC211) connected to the position where the selected row and column intersect is selected.

  Also in the nonvolatile memory device 200, similarly to the nonvolatile memory device 100, control is performed such that the voltage value VLR of the write voltage pulse and the voltage value VHR of the erase voltage pulse satisfy | VLR |> | VHR |. Can do. Thereby, good endurance characteristics can be realized also in the nonvolatile memory device 200.

  Note that the configuration and circuit configuration of the memory cell array in Embodiment 2 are merely examples, and are not limited to the above. A known circuit can be used as the circuit in each block diagram. Further, a new embodiment can be realized by appropriately combining the above-described embodiment and a known configuration.

  The nonvolatile memory element and the driving method of the nonvolatile memory element according to the present invention are useful as a memory device used in various electronic devices such as a personal computer or a portable phone.

DESCRIPTION OF SYMBOLS 1 Board | substrate 2,1002 1st electrode 3,1003 Resistance change layer 3a 1st resistance change layer 3b 2nd resistance change layer 4,1004 2nd electrode 10,40,1010 Resistance change element 11 1st terminal 12 Second terminal 20, 1020 Field effect transistor (transistor, MISFET)
21 First Input / Output Terminal 22 Second Input / Output Terminal 23 Gate Terminal 24, 1024 Semiconductor Substrate 25a, 1025a First Diffusion Layer 25b, 1025b Second Diffusion Layer 26, 1026 Gate Insulating Film 27, 1027 Gate Electrode 28 DESCRIPTION OF SYMBOLS 1028 Interlayer insulating layer 29 Conductive via 30, 31, 1030 Nonvolatile memory element 100, 200 Nonvolatile memory device 101, 201 Memory cell array 102, 202 Voltage application unit 103 Address input circuit 104 Control circuit 105 Power supply unit for writing 106,206 Memory drive circuit 107, 207 Memory main body 108 Row selection circuit 109, 209 Row driver 110 Data input / output circuit 111 Write circuit 112 Column selection circuit 113 Column driver 114 Read circuit 115 Pulse width setting circuit 116 LR conversion power Source 117 HR power source 1029 Electrode wiring

Claims (15)

A first electrode;
A second electrode;
A first resistance change layer formed between the first electrode and the second electrode and made of a first metal oxide; and an oxygen deficiency smaller than that of the first metal oxide. And a second resistance change layer composed of two metal oxides, and the resistance value reversibly changes according to a voltage pulse applied between the first electrode and the second electrode. A resistance change layer;
A first input / output terminal connected to the first electrode, a second input / output terminal, and a gate terminal for controlling conduction between the first input / output terminal and the second input / output terminal; A field effect transistor having:
With
The variable resistance layer is changed from a low resistance state to a high resistance state by applying an erase voltage pulse having a first polarity between the first electrode and the second electrode via the field effect transistor. Change to
A write voltage pulse having a second polarity different from the first polarity is applied to the variable resistance layer between the first electrode and the second electrode via the field effect transistor. To change from a high resistance state to a low resistance state,
When the write voltage pulse is applied, the second input / output terminal of the field effect transistor is a source terminal;
The field effect transistor has a first current value that flows through the resistance change layer when the resistance change layer is completely changed from a low resistance state to a high resistance state by application of the erase voltage pulse, and the resistance change layer has the erase value. When the change from the high resistance state to the low resistance state is completed by application of the voltage pulse, the second current value flowing in the resistance change layer is suppressed to be equal to or less than the second current value.
Nonvolatile memory element. The field effect transistor is an N-type FET, the first variable resistance layer is in contact with the second electrode, and the second variable resistance layer is in contact with the first electrode;
The nonvolatile memory element according to claim 1. The field effect transistor is a P-type FET, the first variable resistance layer is in contact with the first electrode, and the second variable resistance layer is in contact with the second electrode;
The nonvolatile memory element according to claim 1. When the field effect transistor is an N-type FET, the standard electrode potential of the first electrode is E1, and the standard electrode potential of the second electrode is E2, E1> E2 is satisfied.
The nonvolatile memory element according to claim 1. When the field effect transistor is a P-type FET, the standard electrode potential of the first electrode is E1, and the standard electrode potential of the second electrode is E2, E2> E1 is satisfied.
The nonvolatile memory element according to claim 1. The first metal oxide and the second metal oxide are oxides of the same metal;
When the composition of the first metal oxide is expressed as MO _x and the composition of the second metal oxide is expressed as MO _y , y> x is satisfied.
The nonvolatile memory element according to claim 1. The first metal oxide and the second metal oxide are tantalum oxides;
The nonvolatile memory element according to claim 6. The first metal oxide and the second metal oxide are hafnium oxides;
The nonvolatile memory element according to claim 6. The first metal oxide and the second metal oxide are zirconium oxides;
The nonvolatile memory element according to claim 6. The first metal oxide and the second metal oxide layer are different metal oxides;
When the standard electrode potential of the metal constituting the first metal oxide is EN and the standard electrode potential of the metal constituting the second metal oxide is EM, EN <EM is satisfied.
The nonvolatile memory element according to claim 1. The first metal oxide is a tantalum oxide, and the second metal oxide is an aluminum oxide;
The nonvolatile memory element according to claim 10. The first metal oxide is tantalum oxide, and the second metal oxide is hafnium oxide;
The nonvolatile memory element according to claim 10. A first electrode;
A second electrode;
A first resistance change layer formed between the first electrode and the second electrode and made of a first metal oxide; and an oxygen deficiency smaller than that of the first metal oxide. And a second resistance change layer composed of two metal oxides, and the resistance value reversibly changes according to a voltage pulse applied between the first electrode and the second electrode. A resistance change layer;
A resistance portion inserted in a path of a current flowing through the resistance change layer;
With
The resistance change layer is changed from a low resistance state to a high resistance state by applying an erase voltage pulse having a first polarity between the first electrode and the second electrode via the resistance portion. Change,
The resistance change layer is configured such that a write voltage pulse having a second polarity different from the first polarity is applied between the first electrode and the second electrode via the resistance unit. Changing from a high resistance state to a low resistance state,
The resistance unit has a first current value that flows through the resistance change layer when the resistance change layer completes a change from a low resistance state to a high resistance state by application of the erase voltage pulse, and the resistance change layer has the write voltage. When the change from the high resistance state to the low resistance state is completed by applying a pulse, the second current value flowing in the resistance change layer is suppressed to a value equal to or less than
Nonvolatile memory element. A method for driving a nonvolatile memory element, comprising:
The nonvolatile memory element is
A first electrode;
A second electrode;
A first resistance change layer formed between the first electrode and the second electrode and made of a first metal oxide; and an oxygen deficiency smaller than that of the first metal oxide. And a second resistance change layer composed of two metal oxides, and the resistance value reversibly changes according to a voltage pulse applied between the first electrode and the second electrode. A resistance change layer;
A first input / output terminal, a second input / output terminal, the first input / output terminal, and the second input, which are inserted into a path of a current flowing through the variable resistance layer and connected to the first electrode. A gate terminal for controlling conduction to and from the input / output terminal, and in the writing step, the second input / output terminal of the field effect transistor includes a field effect transistor that is a source terminal,
The driving method of the nonvolatile memory element is:
An erasing step of applying an erasing voltage pulse of a first polarity between the first electrode and the second electrode to change the resistance change layer from a low resistance state to a high resistance state;
A write voltage pulse having a second polarity different from the first polarity is applied between the first electrode and the second electrode in order to change the resistance change layer from a high resistance state to a low resistance state. Writing step to
A control step of suppressing, by the field effect transistor, a first current value that flows through the resistance change layer when the erasing step is completed to a second current value that flows through the resistance change layer when the write step is completed;
A method for driving a nonvolatile memory element including: Applying a voltage Vw to the gate terminal of the field effect transistor in the writing step;
A voltage Ve having an absolute value larger than the voltage Vw is applied to the gate terminal in the erasing step;
The method for driving a nonvolatile memory element according to claim 14.

Images